cpuidle-tegra30.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. /*
  2. * CPU idle driver for Tegra CPUs
  3. *
  4. * Copyright (c) 2010-2012, NVIDIA Corporation.
  5. * Copyright (c) 2011 Google, Inc.
  6. * Author: Colin Cross <ccross@android.com>
  7. * Gary King <gking@nvidia.com>
  8. *
  9. * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/cpuidle.h>
  24. #include <linux/cpu_pm.h>
  25. #include <linux/clockchips.h>
  26. #include <linux/clk/tegra.h>
  27. #include <asm/cpuidle.h>
  28. #include <asm/proc-fns.h>
  29. #include <asm/suspend.h>
  30. #include <asm/smp_plat.h>
  31. #include "pm.h"
  32. #include "sleep.h"
  33. #ifdef CONFIG_PM_SLEEP
  34. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  35. struct cpuidle_driver *drv,
  36. int index);
  37. #endif
  38. static struct cpuidle_driver tegra_idle_driver = {
  39. .name = "tegra_idle",
  40. .owner = THIS_MODULE,
  41. .en_core_tk_irqen = 1,
  42. #ifdef CONFIG_PM_SLEEP
  43. .state_count = 2,
  44. #else
  45. .state_count = 1,
  46. #endif
  47. .states = {
  48. [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
  49. #ifdef CONFIG_PM_SLEEP
  50. [1] = {
  51. .enter = tegra30_idle_lp2,
  52. .exit_latency = 2000,
  53. .target_residency = 2200,
  54. .power_usage = 0,
  55. .flags = CPUIDLE_FLAG_TIME_VALID,
  56. .name = "powered-down",
  57. .desc = "CPU power gated",
  58. },
  59. #endif
  60. },
  61. };
  62. static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
  63. #ifdef CONFIG_PM_SLEEP
  64. static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
  65. struct cpuidle_driver *drv,
  66. int index)
  67. {
  68. /* All CPUs entering LP2 is not working.
  69. * Don't let CPU0 enter LP2 when any secondary CPU is online.
  70. */
  71. if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
  72. cpu_do_idle();
  73. return false;
  74. }
  75. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  76. tegra_idle_lp2_last();
  77. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  78. return true;
  79. }
  80. #ifdef CONFIG_SMP
  81. static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  82. struct cpuidle_driver *drv,
  83. int index)
  84. {
  85. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  86. smp_wmb();
  87. cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
  88. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  89. return true;
  90. }
  91. #else
  92. static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  93. struct cpuidle_driver *drv,
  94. int index)
  95. {
  96. return true;
  97. }
  98. #endif
  99. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  100. struct cpuidle_driver *drv,
  101. int index)
  102. {
  103. u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
  104. bool entered_lp2 = false;
  105. bool last_cpu;
  106. local_fiq_disable();
  107. last_cpu = tegra_set_cpu_in_lp2(cpu);
  108. cpu_pm_enter();
  109. if (cpu == 0) {
  110. if (last_cpu)
  111. entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
  112. index);
  113. else
  114. cpu_do_idle();
  115. } else {
  116. entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
  117. }
  118. cpu_pm_exit();
  119. tegra_clear_cpu_in_lp2(cpu);
  120. local_fiq_enable();
  121. smp_rmb();
  122. return (entered_lp2) ? index : 0;
  123. }
  124. #endif
  125. int __init tegra30_cpuidle_init(void)
  126. {
  127. int ret;
  128. unsigned int cpu;
  129. struct cpuidle_device *dev;
  130. struct cpuidle_driver *drv = &tegra_idle_driver;
  131. #ifdef CONFIG_PM_SLEEP
  132. tegra_tear_down_cpu = tegra30_tear_down_cpu;
  133. #endif
  134. ret = cpuidle_register_driver(&tegra_idle_driver);
  135. if (ret) {
  136. pr_err("CPUidle driver registration failed\n");
  137. return ret;
  138. }
  139. for_each_possible_cpu(cpu) {
  140. dev = &per_cpu(tegra_idle_device, cpu);
  141. dev->cpu = cpu;
  142. dev->state_count = drv->state_count;
  143. ret = cpuidle_register_device(dev);
  144. if (ret) {
  145. pr_err("CPU%u: CPUidle device registration failed\n",
  146. cpu);
  147. return ret;
  148. }
  149. }
  150. return 0;
  151. }