hw-me.c 8.4 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2003-2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/mei.h>
  18. #include "mei_dev.h"
  19. #include "hw-me.h"
  20. /**
  21. * mei_reg_read - Reads 32bit data from the mei device
  22. *
  23. * @dev: the device structure
  24. * @offset: offset from which to read the data
  25. *
  26. * returns register value (u32)
  27. */
  28. static inline u32 mei_reg_read(const struct mei_device *dev,
  29. unsigned long offset)
  30. {
  31. return ioread32(dev->mem_addr + offset);
  32. }
  33. /**
  34. * mei_reg_write - Writes 32bit data to the mei device
  35. *
  36. * @dev: the device structure
  37. * @offset: offset from which to write the data
  38. * @value: register value to write (u32)
  39. */
  40. static inline void mei_reg_write(const struct mei_device *dev,
  41. unsigned long offset, u32 value)
  42. {
  43. iowrite32(value, dev->mem_addr + offset);
  44. }
  45. /**
  46. * mei_mecbrw_read - Reads 32bit data from ME circular buffer
  47. * read window register
  48. *
  49. * @dev: the device structure
  50. *
  51. * returns ME_CB_RW register value (u32)
  52. */
  53. u32 mei_mecbrw_read(const struct mei_device *dev)
  54. {
  55. return mei_reg_read(dev, ME_CB_RW);
  56. }
  57. /**
  58. * mei_mecsr_read - Reads 32bit data from the ME CSR
  59. *
  60. * @dev: the device structure
  61. *
  62. * returns ME_CSR_HA register value (u32)
  63. */
  64. u32 mei_mecsr_read(const struct mei_device *dev)
  65. {
  66. return mei_reg_read(dev, ME_CSR_HA);
  67. }
  68. /**
  69. * mei_hcsr_read - Reads 32bit data from the host CSR
  70. *
  71. * @dev: the device structure
  72. *
  73. * returns H_CSR register value (u32)
  74. */
  75. u32 mei_hcsr_read(const struct mei_device *dev)
  76. {
  77. return mei_reg_read(dev, H_CSR);
  78. }
  79. /**
  80. * mei_hcsr_set - writes H_CSR register to the mei device,
  81. * and ignores the H_IS bit for it is write-one-to-zero.
  82. *
  83. * @dev: the device structure
  84. */
  85. void mei_hcsr_set(struct mei_device *dev)
  86. {
  87. if ((dev->host_hw_state & H_IS) == H_IS)
  88. dev->host_hw_state &= ~H_IS;
  89. mei_reg_write(dev, H_CSR, dev->host_hw_state);
  90. dev->host_hw_state = mei_hcsr_read(dev);
  91. }
  92. /**
  93. * mei_clear_interrupts - clear and stop interrupts
  94. *
  95. * @dev: the device structure
  96. */
  97. void mei_clear_interrupts(struct mei_device *dev)
  98. {
  99. u32 hcsr = mei_hcsr_read(dev);
  100. if ((hcsr & H_IS) == H_IS)
  101. mei_reg_write(dev, H_CSR, hcsr);
  102. }
  103. /**
  104. * mei_enable_interrupts - enables mei device interrupts
  105. *
  106. * @dev: the device structure
  107. */
  108. void mei_enable_interrupts(struct mei_device *dev)
  109. {
  110. u32 hcsr = mei_hcsr_read(dev);
  111. hcsr |= H_IE;
  112. hcsr &= ~H_IS;
  113. mei_reg_write(dev, H_CSR, hcsr);
  114. }
  115. /**
  116. * mei_disable_interrupts - disables mei device interrupts
  117. *
  118. * @dev: the device structure
  119. */
  120. void mei_disable_interrupts(struct mei_device *dev)
  121. {
  122. u32 hcsr = mei_hcsr_read(dev);
  123. hcsr &= ~H_IE;
  124. hcsr &= ~H_IS;
  125. mei_reg_write(dev, H_CSR, hcsr);
  126. }
  127. /**
  128. * mei_hw_reset - resets fw via mei csr register.
  129. *
  130. * @dev: the device structure
  131. * @interrupts_enabled: if interrupt should be enabled after reset.
  132. */
  133. void mei_hw_reset(struct mei_device *dev, bool intr_enable)
  134. {
  135. u32 hcsr = mei_hcsr_read(dev);
  136. dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
  137. hcsr |= (H_RST | H_IG);
  138. if (intr_enable)
  139. hcsr |= H_IE;
  140. else
  141. hcsr &= ~H_IE;
  142. hcsr &= ~H_IS;
  143. mei_reg_write(dev, H_CSR, hcsr);
  144. hcsr = mei_hcsr_read(dev);
  145. hcsr &= ~H_RST;
  146. hcsr |= H_IG;
  147. hcsr &= ~H_IS;
  148. mei_reg_write(dev, H_CSR, hcsr);
  149. hcsr = mei_hcsr_read(dev);
  150. dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
  151. }
  152. /**
  153. * mei_host_set_ready - enable device
  154. *
  155. * @dev - mei device
  156. * returns bool
  157. */
  158. void mei_host_set_ready(struct mei_device *dev)
  159. {
  160. dev->host_hw_state |= H_IE | H_IG | H_RDY;
  161. mei_hcsr_set(dev);
  162. }
  163. /**
  164. * mei_host_is_ready - check whether the host has turned ready
  165. *
  166. * @dev - mei device
  167. * returns bool
  168. */
  169. bool mei_host_is_ready(struct mei_device *dev)
  170. {
  171. return (dev->host_hw_state & H_RDY) == H_RDY;
  172. }
  173. /**
  174. * mei_me_is_ready - check whether the me has turned ready
  175. *
  176. * @dev - mei device
  177. * returns bool
  178. */
  179. bool mei_me_is_ready(struct mei_device *dev)
  180. {
  181. return (dev->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
  182. }
  183. /**
  184. * mei_interrupt_quick_handler - The ISR of the MEI device
  185. *
  186. * @irq: The irq number
  187. * @dev_id: pointer to the device structure
  188. *
  189. * returns irqreturn_t
  190. */
  191. irqreturn_t mei_interrupt_quick_handler(int irq, void *dev_id)
  192. {
  193. struct mei_device *dev = (struct mei_device *) dev_id;
  194. u32 csr_reg = mei_hcsr_read(dev);
  195. if ((csr_reg & H_IS) != H_IS)
  196. return IRQ_NONE;
  197. /* clear H_IS bit in H_CSR */
  198. mei_reg_write(dev, H_CSR, csr_reg);
  199. return IRQ_WAKE_THREAD;
  200. }
  201. /**
  202. * mei_hbuf_filled_slots - gets number of device filled buffer slots
  203. *
  204. * @device: the device structure
  205. *
  206. * returns number of filled slots
  207. */
  208. static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
  209. {
  210. char read_ptr, write_ptr;
  211. dev->host_hw_state = mei_hcsr_read(dev);
  212. read_ptr = (char) ((dev->host_hw_state & H_CBRP) >> 8);
  213. write_ptr = (char) ((dev->host_hw_state & H_CBWP) >> 16);
  214. return (unsigned char) (write_ptr - read_ptr);
  215. }
  216. /**
  217. * mei_hbuf_is_empty - checks if host buffer is empty.
  218. *
  219. * @dev: the device structure
  220. *
  221. * returns true if empty, false - otherwise.
  222. */
  223. bool mei_hbuf_is_empty(struct mei_device *dev)
  224. {
  225. return mei_hbuf_filled_slots(dev) == 0;
  226. }
  227. /**
  228. * mei_hbuf_empty_slots - counts write empty slots.
  229. *
  230. * @dev: the device structure
  231. *
  232. * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
  233. */
  234. int mei_hbuf_empty_slots(struct mei_device *dev)
  235. {
  236. unsigned char filled_slots, empty_slots;
  237. filled_slots = mei_hbuf_filled_slots(dev);
  238. empty_slots = dev->hbuf_depth - filled_slots;
  239. /* check for overflow */
  240. if (filled_slots > dev->hbuf_depth)
  241. return -EOVERFLOW;
  242. return empty_slots;
  243. }
  244. /**
  245. * mei_write_message - writes a message to mei device.
  246. *
  247. * @dev: the device structure
  248. * @hader: mei HECI header of message
  249. * @buf: message payload will be written
  250. *
  251. * This function returns -EIO if write has failed
  252. */
  253. int mei_write_message(struct mei_device *dev, struct mei_msg_hdr *header,
  254. unsigned char *buf)
  255. {
  256. unsigned long rem, dw_cnt;
  257. unsigned long length = header->length;
  258. u32 *reg_buf = (u32 *)buf;
  259. int i;
  260. int empty_slots;
  261. dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
  262. empty_slots = mei_hbuf_empty_slots(dev);
  263. dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
  264. dw_cnt = mei_data2slots(length);
  265. if (empty_slots < 0 || dw_cnt > empty_slots)
  266. return -EIO;
  267. mei_reg_write(dev, H_CB_WW, *((u32 *) header));
  268. for (i = 0; i < length / 4; i++)
  269. mei_reg_write(dev, H_CB_WW, reg_buf[i]);
  270. rem = length & 0x3;
  271. if (rem > 0) {
  272. u32 reg = 0;
  273. memcpy(&reg, &buf[length - rem], rem);
  274. mei_reg_write(dev, H_CB_WW, reg);
  275. }
  276. dev->host_hw_state = mei_hcsr_read(dev);
  277. dev->host_hw_state |= H_IG;
  278. mei_hcsr_set(dev);
  279. dev->me_hw_state = mei_mecsr_read(dev);
  280. if (!mei_me_is_ready(dev))
  281. return -EIO;
  282. return 0;
  283. }
  284. /**
  285. * mei_count_full_read_slots - counts read full slots.
  286. *
  287. * @dev: the device structure
  288. *
  289. * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
  290. */
  291. int mei_count_full_read_slots(struct mei_device *dev)
  292. {
  293. char read_ptr, write_ptr;
  294. unsigned char buffer_depth, filled_slots;
  295. dev->me_hw_state = mei_mecsr_read(dev);
  296. buffer_depth = (unsigned char)((dev->me_hw_state & ME_CBD_HRA) >> 24);
  297. read_ptr = (char) ((dev->me_hw_state & ME_CBRP_HRA) >> 8);
  298. write_ptr = (char) ((dev->me_hw_state & ME_CBWP_HRA) >> 16);
  299. filled_slots = (unsigned char) (write_ptr - read_ptr);
  300. /* check for overflow */
  301. if (filled_slots > buffer_depth)
  302. return -EOVERFLOW;
  303. dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
  304. return (int)filled_slots;
  305. }
  306. /**
  307. * mei_read_slots - reads a message from mei device.
  308. *
  309. * @dev: the device structure
  310. * @buffer: message buffer will be written
  311. * @buffer_length: message size will be read
  312. */
  313. void mei_read_slots(struct mei_device *dev, unsigned char *buffer,
  314. unsigned long buffer_length)
  315. {
  316. u32 *reg_buf = (u32 *)buffer;
  317. for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
  318. *reg_buf++ = mei_mecbrw_read(dev);
  319. if (buffer_length > 0) {
  320. u32 reg = mei_mecbrw_read(dev);
  321. memcpy(reg_buf, &reg, buffer_length);
  322. }
  323. dev->host_hw_state |= H_IG;
  324. mei_hcsr_set(dev);
  325. }