isp1760-hcd.c 54 KB

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  1. /*
  2. * Driver for the NXP ISP1760 chip
  3. *
  4. * However, the code might contain some bugs. What doesn't work for sure is:
  5. * - ISO
  6. * - OTG
  7. e The interrupt line is configured as active low, level.
  8. *
  9. * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/list.h>
  16. #include <linux/usb.h>
  17. #include <linux/debugfs.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/io.h>
  20. #include <asm/unaligned.h>
  21. #include "../core/hcd.h"
  22. #include "isp1760-hcd.h"
  23. static struct kmem_cache *qtd_cachep;
  24. static struct kmem_cache *qh_cachep;
  25. struct isp1760_hcd {
  26. u32 hcs_params;
  27. spinlock_t lock;
  28. struct inter_packet_info atl_ints[32];
  29. struct inter_packet_info int_ints[32];
  30. struct memory_chunk memory_pool[BLOCKS];
  31. /* periodic schedule support */
  32. #define DEFAULT_I_TDPS 1024
  33. unsigned periodic_size;
  34. unsigned i_thresh;
  35. unsigned long reset_done;
  36. unsigned long next_statechange;
  37. unsigned int devflags;
  38. };
  39. static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  40. {
  41. return (struct isp1760_hcd *) (hcd->hcd_priv);
  42. }
  43. static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
  44. {
  45. return container_of((void *) priv, struct usb_hcd, hcd_priv);
  46. }
  47. /* Section 2.2 Host Controller Capability Registers */
  48. #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
  49. #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
  50. #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
  51. #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
  52. #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
  53. #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
  54. #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
  55. /* Section 2.3 Host Controller Operational Registers */
  56. #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
  57. #define CMD_RESET (1<<1) /* reset HC not bus */
  58. #define CMD_RUN (1<<0) /* start/stop HC */
  59. #define STS_PCD (1<<2) /* port change detect */
  60. #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
  61. #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
  62. #define PORT_POWER (1<<12) /* true: has power (see PPC) */
  63. #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
  64. #define PORT_RESET (1<<8) /* reset port */
  65. #define PORT_SUSPEND (1<<7) /* suspend port */
  66. #define PORT_RESUME (1<<6) /* resume it */
  67. #define PORT_PE (1<<2) /* port enable */
  68. #define PORT_CSC (1<<1) /* connect status change */
  69. #define PORT_CONNECT (1<<0) /* device connected */
  70. #define PORT_RWC_BITS (PORT_CSC)
  71. struct isp1760_qtd {
  72. struct isp1760_qtd *hw_next;
  73. u8 packet_type;
  74. u8 toggle;
  75. void *data_buffer;
  76. /* the rest is HCD-private */
  77. struct list_head qtd_list;
  78. struct urb *urb;
  79. size_t length;
  80. /* isp special*/
  81. u32 status;
  82. #define URB_COMPLETE_NOTIFY (1 << 0)
  83. #define URB_ENQUEUED (1 << 1)
  84. #define URB_TYPE_ATL (1 << 2)
  85. #define URB_TYPE_INT (1 << 3)
  86. };
  87. struct isp1760_qh {
  88. /* first part defined by EHCI spec */
  89. struct list_head qtd_list;
  90. struct isp1760_hcd *priv;
  91. /* periodic schedule info */
  92. unsigned short period; /* polling interval */
  93. struct usb_device *dev;
  94. u32 toggle;
  95. u32 ping;
  96. };
  97. #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED)
  98. static unsigned int isp1760_readl(__u32 __iomem *regs)
  99. {
  100. return readl(regs);
  101. }
  102. static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
  103. {
  104. writel(val, regs);
  105. }
  106. /*
  107. * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
  108. * doesn't quite work because some people have to enforce 32-bit access
  109. */
  110. static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
  111. __u32 __iomem *dst, u32 offset, u32 len)
  112. {
  113. struct usb_hcd *hcd = priv_to_hcd(priv);
  114. u32 val;
  115. u8 *buff8;
  116. if (!src) {
  117. printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
  118. return;
  119. }
  120. isp1760_writel(offset, hcd->regs + HC_MEMORY_REG);
  121. /* XXX
  122. * 90nsec delay, the spec says something how this could be avoided.
  123. */
  124. mdelay(1);
  125. while (len >= 4) {
  126. *src = __raw_readl(dst);
  127. len -= 4;
  128. src++;
  129. dst++;
  130. }
  131. if (!len)
  132. return;
  133. /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
  134. * allocated.
  135. */
  136. val = isp1760_readl(dst);
  137. buff8 = (u8 *)src;
  138. while (len) {
  139. *buff8 = val;
  140. val >>= 8;
  141. len--;
  142. buff8++;
  143. }
  144. }
  145. static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
  146. __u32 __iomem *dst, u32 len)
  147. {
  148. while (len >= 4) {
  149. __raw_writel(*src, dst);
  150. len -= 4;
  151. src++;
  152. dst++;
  153. }
  154. if (!len)
  155. return;
  156. /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
  157. * extra bytes should not be read by the HW
  158. */
  159. __raw_writel(*src, dst);
  160. }
  161. /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
  162. static void init_memory(struct isp1760_hcd *priv)
  163. {
  164. int i;
  165. u32 payload;
  166. payload = 0x1000;
  167. for (i = 0; i < BLOCK_1_NUM; i++) {
  168. priv->memory_pool[i].start = payload;
  169. priv->memory_pool[i].size = BLOCK_1_SIZE;
  170. priv->memory_pool[i].free = 1;
  171. payload += priv->memory_pool[i].size;
  172. }
  173. for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
  174. priv->memory_pool[i].start = payload;
  175. priv->memory_pool[i].size = BLOCK_2_SIZE;
  176. priv->memory_pool[i].free = 1;
  177. payload += priv->memory_pool[i].size;
  178. }
  179. for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
  180. priv->memory_pool[i].start = payload;
  181. priv->memory_pool[i].size = BLOCK_3_SIZE;
  182. priv->memory_pool[i].free = 1;
  183. payload += priv->memory_pool[i].size;
  184. }
  185. BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
  186. }
  187. static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
  188. {
  189. int i;
  190. if (!size)
  191. return ISP1760_NULL_POINTER;
  192. for (i = 0; i < BLOCKS; i++) {
  193. if (priv->memory_pool[i].size >= size &&
  194. priv->memory_pool[i].free) {
  195. priv->memory_pool[i].free = 0;
  196. return priv->memory_pool[i].start;
  197. }
  198. }
  199. printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
  200. size);
  201. printk(KERN_ERR "Current memory map:\n");
  202. for (i = 0; i < BLOCKS; i++) {
  203. printk(KERN_ERR "Pool %2d size %4d status: %d\n",
  204. i, priv->memory_pool[i].size,
  205. priv->memory_pool[i].free);
  206. }
  207. /* XXX maybe -ENOMEM could be possible */
  208. BUG();
  209. return 0;
  210. }
  211. static void free_mem(struct isp1760_hcd *priv, u32 mem)
  212. {
  213. int i;
  214. if (mem == ISP1760_NULL_POINTER)
  215. return;
  216. for (i = 0; i < BLOCKS; i++) {
  217. if (priv->memory_pool[i].start == mem) {
  218. BUG_ON(priv->memory_pool[i].free);
  219. priv->memory_pool[i].free = 1;
  220. return ;
  221. }
  222. }
  223. printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
  224. mem);
  225. BUG();
  226. }
  227. static void isp1760_init_regs(struct usb_hcd *hcd)
  228. {
  229. isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
  230. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  231. HC_ATL_PTD_SKIPMAP_REG);
  232. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  233. HC_INT_PTD_SKIPMAP_REG);
  234. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  235. HC_ISO_PTD_SKIPMAP_REG);
  236. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  237. HC_ATL_PTD_DONEMAP_REG);
  238. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  239. HC_INT_PTD_DONEMAP_REG);
  240. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  241. HC_ISO_PTD_DONEMAP_REG);
  242. }
  243. static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
  244. u32 mask, u32 done, int usec)
  245. {
  246. u32 result;
  247. do {
  248. result = isp1760_readl(ptr);
  249. if (result == ~0)
  250. return -ENODEV;
  251. result &= mask;
  252. if (result == done)
  253. return 0;
  254. udelay(1);
  255. usec--;
  256. } while (usec > 0);
  257. return -ETIMEDOUT;
  258. }
  259. /* reset a non-running (STS_HALT == 1) controller */
  260. static int ehci_reset(struct isp1760_hcd *priv)
  261. {
  262. int retval;
  263. struct usb_hcd *hcd = priv_to_hcd(priv);
  264. u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
  265. command |= CMD_RESET;
  266. isp1760_writel(command, hcd->regs + HC_USBCMD);
  267. hcd->state = HC_STATE_HALT;
  268. priv->next_statechange = jiffies;
  269. retval = handshake(priv, hcd->regs + HC_USBCMD,
  270. CMD_RESET, 0, 250 * 1000);
  271. return retval;
  272. }
  273. static void qh_destroy(struct isp1760_qh *qh)
  274. {
  275. BUG_ON(!list_empty(&qh->qtd_list));
  276. kmem_cache_free(qh_cachep, qh);
  277. }
  278. static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
  279. gfp_t flags)
  280. {
  281. struct isp1760_qh *qh;
  282. qh = kmem_cache_zalloc(qh_cachep, flags);
  283. if (!qh)
  284. return qh;
  285. INIT_LIST_HEAD(&qh->qtd_list);
  286. qh->priv = priv;
  287. return qh;
  288. }
  289. /* magic numbers that can affect system performance */
  290. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  291. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  292. #define EHCI_TUNE_RL_TT 0
  293. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  294. #define EHCI_TUNE_MULT_TT 1
  295. #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
  296. /* one-time init, only for memory state */
  297. static int priv_init(struct usb_hcd *hcd)
  298. {
  299. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  300. u32 hcc_params;
  301. spin_lock_init(&priv->lock);
  302. /*
  303. * hw default: 1K periodic list heads, one per frame.
  304. * periodic_size can shrink by USBCMD update if hcc_params allows.
  305. */
  306. priv->periodic_size = DEFAULT_I_TDPS;
  307. /* controllers may cache some of the periodic schedule ... */
  308. hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
  309. /* full frame cache */
  310. if (HCC_ISOC_CACHE(hcc_params))
  311. priv->i_thresh = 8;
  312. else /* N microframes cached */
  313. priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  314. return 0;
  315. }
  316. static int isp1760_hc_setup(struct usb_hcd *hcd)
  317. {
  318. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  319. int result;
  320. u32 scratch, hwmode;
  321. /* Setup HW Mode Control: This assumes a level active-low interrupt */
  322. hwmode = HW_DATA_BUS_32BIT;
  323. if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
  324. hwmode &= ~HW_DATA_BUS_32BIT;
  325. if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
  326. hwmode |= HW_ANA_DIGI_OC;
  327. if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
  328. hwmode |= HW_DACK_POL_HIGH;
  329. if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
  330. hwmode |= HW_DREQ_POL_HIGH;
  331. /*
  332. * We have to set this first in case we're in 16-bit mode.
  333. * Write it twice to ensure correct upper bits if switching
  334. * to 16-bit mode.
  335. */
  336. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  337. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  338. isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
  339. /* Change bus pattern */
  340. scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  341. scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
  342. if (scratch != 0xdeadbabe) {
  343. printk(KERN_ERR "ISP1760: Scratch test failed.\n");
  344. return -ENODEV;
  345. }
  346. /* pre reset */
  347. isp1760_init_regs(hcd);
  348. /* reset */
  349. isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
  350. mdelay(100);
  351. isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
  352. mdelay(100);
  353. result = ehci_reset(priv);
  354. if (result)
  355. return result;
  356. /* Step 11 passed */
  357. isp1760_info(priv, "bus width: %d, oc: %s\n",
  358. (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
  359. 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
  360. "analog" : "digital");
  361. /* ATL reset */
  362. isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
  363. mdelay(10);
  364. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  365. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
  366. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
  367. /*
  368. * PORT 1 Control register of the ISP1760 is the OTG control
  369. * register on ISP1761.
  370. */
  371. if (!(priv->devflags & ISP1760_FLAG_ISP1761) &&
  372. !(priv->devflags & ISP1760_FLAG_PORT1_DIS)) {
  373. isp1760_writel(PORT1_POWER | PORT1_INIT2,
  374. hcd->regs + HC_PORT1_CTRL);
  375. mdelay(10);
  376. }
  377. priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
  378. return priv_init(hcd);
  379. }
  380. static void isp1760_init_maps(struct usb_hcd *hcd)
  381. {
  382. /*set last maps, for iso its only 1, else 32 tds bitmap*/
  383. isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
  384. isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
  385. isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
  386. }
  387. static void isp1760_enable_interrupts(struct usb_hcd *hcd)
  388. {
  389. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
  390. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  391. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
  392. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  393. isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
  394. isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
  395. /* step 23 passed */
  396. }
  397. static int isp1760_run(struct usb_hcd *hcd)
  398. {
  399. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  400. int retval;
  401. u32 temp;
  402. u32 command;
  403. u32 chipid;
  404. hcd->uses_new_polling = 1;
  405. hcd->poll_rh = 0;
  406. hcd->state = HC_STATE_RUNNING;
  407. isp1760_enable_interrupts(hcd);
  408. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  409. isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  410. command = isp1760_readl(hcd->regs + HC_USBCMD);
  411. command &= ~(CMD_LRESET|CMD_RESET);
  412. command |= CMD_RUN;
  413. isp1760_writel(command, hcd->regs + HC_USBCMD);
  414. retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
  415. 250 * 1000);
  416. if (retval)
  417. return retval;
  418. /*
  419. * XXX
  420. * Spec says to write FLAG_CF as last config action, priv code grabs
  421. * the semaphore while doing so.
  422. */
  423. down_write(&ehci_cf_port_reset_rwsem);
  424. isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
  425. retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
  426. 250 * 1000);
  427. up_write(&ehci_cf_port_reset_rwsem);
  428. if (retval)
  429. return retval;
  430. chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  431. isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
  432. chipid >> 16);
  433. /* PTD Register Init Part 2, Step 28 */
  434. /* enable INTs */
  435. isp1760_init_maps(hcd);
  436. /* GRR this is run-once init(), being done every time the HC starts.
  437. * So long as they're part of class devices, we can't do it init()
  438. * since the class device isn't created that early.
  439. */
  440. return 0;
  441. }
  442. static u32 base_to_chip(u32 base)
  443. {
  444. return ((base - 0x400) >> 3);
  445. }
  446. static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  447. struct isp1760_qtd *qtd, struct urb *urb,
  448. u32 payload, struct ptd *ptd)
  449. {
  450. u32 dw0;
  451. u32 dw1;
  452. u32 dw2;
  453. u32 dw3;
  454. u32 maxpacket;
  455. u32 multi;
  456. u32 pid_code;
  457. u32 rl = RL_COUNTER;
  458. u32 nak = NAK_COUNTER;
  459. /* according to 3.6.2, max packet len can not be > 0x400 */
  460. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  461. multi = 1 + ((maxpacket >> 11) & 0x3);
  462. maxpacket &= 0x7ff;
  463. /* DW0 */
  464. dw0 = PTD_VALID;
  465. dw0 |= PTD_LENGTH(qtd->length);
  466. dw0 |= PTD_MAXPACKET(maxpacket);
  467. dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
  468. dw1 = usb_pipeendpoint(urb->pipe) >> 1;
  469. /* DW1 */
  470. dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
  471. pid_code = qtd->packet_type;
  472. dw1 |= PTD_PID_TOKEN(pid_code);
  473. if (usb_pipebulk(urb->pipe))
  474. dw1 |= PTD_TRANS_BULK;
  475. else if (usb_pipeint(urb->pipe))
  476. dw1 |= PTD_TRANS_INT;
  477. if (urb->dev->speed != USB_SPEED_HIGH) {
  478. /* split transaction */
  479. dw1 |= PTD_TRANS_SPLIT;
  480. if (urb->dev->speed == USB_SPEED_LOW)
  481. dw1 |= PTD_SE_USB_LOSPEED;
  482. dw1 |= PTD_PORT_NUM(urb->dev->ttport);
  483. dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
  484. /* SE bit for Split INT transfers */
  485. if (usb_pipeint(urb->pipe) &&
  486. (urb->dev->speed == USB_SPEED_LOW))
  487. dw1 |= 2 << 16;
  488. dw3 = 0;
  489. rl = 0;
  490. nak = 0;
  491. } else {
  492. dw0 |= PTD_MULTI(multi);
  493. if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
  494. dw3 = qh->ping;
  495. else
  496. dw3 = 0;
  497. }
  498. /* DW2 */
  499. dw2 = 0;
  500. dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
  501. dw2 |= PTD_RL_CNT(rl);
  502. dw3 |= PTD_NAC_CNT(nak);
  503. /* DW3 */
  504. if (usb_pipecontrol(urb->pipe))
  505. dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
  506. else
  507. dw3 |= qh->toggle;
  508. dw3 |= PTD_ACTIVE;
  509. /* Cerr */
  510. dw3 |= PTD_CERR(ERR_COUNTER);
  511. memset(ptd, 0, sizeof(*ptd));
  512. ptd->dw0 = cpu_to_le32(dw0);
  513. ptd->dw1 = cpu_to_le32(dw1);
  514. ptd->dw2 = cpu_to_le32(dw2);
  515. ptd->dw3 = cpu_to_le32(dw3);
  516. }
  517. static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  518. struct isp1760_qtd *qtd, struct urb *urb,
  519. u32 payload, struct ptd *ptd)
  520. {
  521. u32 maxpacket;
  522. u32 multi;
  523. u32 numberofusofs;
  524. u32 i;
  525. u32 usofmask, usof;
  526. u32 period;
  527. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  528. multi = 1 + ((maxpacket >> 11) & 0x3);
  529. maxpacket &= 0x7ff;
  530. /* length of the data per uframe */
  531. maxpacket = multi * maxpacket;
  532. numberofusofs = urb->transfer_buffer_length / maxpacket;
  533. if (urb->transfer_buffer_length % maxpacket)
  534. numberofusofs += 1;
  535. usofmask = 1;
  536. usof = 0;
  537. for (i = 0; i < numberofusofs; i++) {
  538. usof |= usofmask;
  539. usofmask <<= 1;
  540. }
  541. if (urb->dev->speed != USB_SPEED_HIGH) {
  542. /* split */
  543. ptd->dw5 = __constant_cpu_to_le32(0x1c);
  544. if (qh->period >= 32)
  545. period = qh->period / 2;
  546. else
  547. period = qh->period;
  548. } else {
  549. if (qh->period >= 8)
  550. period = qh->period/8;
  551. else
  552. period = qh->period;
  553. if (period >= 32)
  554. period = 16;
  555. if (qh->period >= 8) {
  556. /* millisecond period */
  557. period = (period << 3);
  558. } else {
  559. /* usof based tranmsfers */
  560. /* minimum 4 usofs */
  561. usof = 0x11;
  562. }
  563. }
  564. ptd->dw2 |= cpu_to_le32(period);
  565. ptd->dw4 = cpu_to_le32(usof);
  566. }
  567. static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  568. struct isp1760_qtd *qtd, struct urb *urb,
  569. u32 payload, struct ptd *ptd)
  570. {
  571. transform_into_atl(priv, qh, qtd, urb, payload, ptd);
  572. transform_add_int(priv, qh, qtd, urb, payload, ptd);
  573. }
  574. static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
  575. u32 token)
  576. {
  577. int count;
  578. qtd->data_buffer = databuffer;
  579. qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
  580. qtd->toggle = GET_DATA_TOGGLE(token);
  581. if (len > HC_ATL_PL_SIZE)
  582. count = HC_ATL_PL_SIZE;
  583. else
  584. count = len;
  585. qtd->length = count;
  586. return count;
  587. }
  588. static int check_error(struct ptd *ptd)
  589. {
  590. int error = 0;
  591. u32 dw3;
  592. dw3 = le32_to_cpu(ptd->dw3);
  593. if (dw3 & DW3_HALT_BIT)
  594. error = -EPIPE;
  595. if (dw3 & DW3_ERROR_BIT) {
  596. printk(KERN_ERR "error bit is set in DW3\n");
  597. error = -EPIPE;
  598. }
  599. if (dw3 & DW3_QTD_ACTIVE) {
  600. printk(KERN_ERR "transfer active bit is set DW3\n");
  601. printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
  602. (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
  603. }
  604. return error;
  605. }
  606. static void check_int_err_status(u32 dw4)
  607. {
  608. u32 i;
  609. dw4 >>= 8;
  610. for (i = 0; i < 8; i++) {
  611. switch (dw4 & 0x7) {
  612. case INT_UNDERRUN:
  613. printk(KERN_ERR "ERROR: under run , %d\n", i);
  614. break;
  615. case INT_EXACT:
  616. printk(KERN_ERR "ERROR: transaction error, %d\n", i);
  617. break;
  618. case INT_BABBLE:
  619. printk(KERN_ERR "ERROR: babble error, %d\n", i);
  620. break;
  621. }
  622. dw4 >>= 3;
  623. }
  624. }
  625. static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
  626. u32 payload)
  627. {
  628. u32 token;
  629. struct usb_hcd *hcd = priv_to_hcd(priv);
  630. token = qtd->packet_type;
  631. if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
  632. switch (token) {
  633. case IN_PID:
  634. break;
  635. case OUT_PID:
  636. case SETUP_PID:
  637. priv_write_copy(priv, qtd->data_buffer,
  638. hcd->regs + payload,
  639. qtd->length);
  640. }
  641. }
  642. }
  643. static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
  644. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  645. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  646. {
  647. struct ptd ptd;
  648. struct usb_hcd *hcd = priv_to_hcd(priv);
  649. transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
  650. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
  651. enqueue_one_qtd(qtd, priv, payload);
  652. priv->atl_ints[slot].urb = urb;
  653. priv->atl_ints[slot].qh = qh;
  654. priv->atl_ints[slot].qtd = qtd;
  655. priv->atl_ints[slot].data_buffer = qtd->data_buffer;
  656. priv->atl_ints[slot].payload = payload;
  657. qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
  658. qtd->status |= slot << 16;
  659. }
  660. static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
  661. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  662. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  663. {
  664. struct ptd ptd;
  665. struct usb_hcd *hcd = priv_to_hcd(priv);
  666. transform_into_int(priv, qh, qtd, urb, payload, &ptd);
  667. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
  668. enqueue_one_qtd(qtd, priv, payload);
  669. priv->int_ints[slot].urb = urb;
  670. priv->int_ints[slot].qh = qh;
  671. priv->int_ints[slot].qtd = qtd;
  672. priv->int_ints[slot].data_buffer = qtd->data_buffer;
  673. priv->int_ints[slot].payload = payload;
  674. qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
  675. qtd->status |= slot << 16;
  676. }
  677. static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  678. struct isp1760_qtd *qtd)
  679. {
  680. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  681. u32 skip_map, or_map;
  682. u32 queue_entry;
  683. u32 slot;
  684. u32 atl_regs, payload;
  685. u32 buffstatus;
  686. skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  687. BUG_ON(!skip_map);
  688. slot = __ffs(skip_map);
  689. queue_entry = 1 << slot;
  690. atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
  691. payload = alloc_mem(priv, qtd->length);
  692. enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
  693. or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  694. or_map |= queue_entry;
  695. isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  696. skip_map &= ~queue_entry;
  697. isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  698. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  699. buffstatus |= ATL_BUFFER;
  700. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  701. }
  702. static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  703. struct isp1760_qtd *qtd)
  704. {
  705. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  706. u32 skip_map, or_map;
  707. u32 queue_entry;
  708. u32 slot;
  709. u32 int_regs, payload;
  710. u32 buffstatus;
  711. skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  712. BUG_ON(!skip_map);
  713. slot = __ffs(skip_map);
  714. queue_entry = 1 << slot;
  715. int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
  716. payload = alloc_mem(priv, qtd->length);
  717. enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
  718. or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  719. or_map |= queue_entry;
  720. isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  721. skip_map &= ~queue_entry;
  722. isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  723. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  724. buffstatus |= INT_BUFFER;
  725. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  726. }
  727. static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
  728. __releases(priv->lock)
  729. __acquires(priv->lock)
  730. {
  731. if (!urb->unlinked) {
  732. if (status == -EINPROGRESS)
  733. status = 0;
  734. }
  735. /* complete() can reenter this HCD */
  736. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  737. spin_unlock(&priv->lock);
  738. usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
  739. spin_lock(&priv->lock);
  740. }
  741. static void isp1760_qtd_free(struct isp1760_qtd *qtd)
  742. {
  743. kmem_cache_free(qtd_cachep, qtd);
  744. }
  745. static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
  746. {
  747. struct isp1760_qtd *tmp_qtd;
  748. tmp_qtd = qtd->hw_next;
  749. list_del(&qtd->qtd_list);
  750. isp1760_qtd_free(qtd);
  751. return tmp_qtd;
  752. }
  753. /*
  754. * Remove this QTD from the QH list and free its memory. If this QTD
  755. * isn't the last one than remove also his successor(s).
  756. * Returns the QTD which is part of an new URB and should be enqueued.
  757. */
  758. static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
  759. {
  760. struct isp1760_qtd *tmp_qtd;
  761. int last_one;
  762. do {
  763. tmp_qtd = qtd->hw_next;
  764. last_one = qtd->status & URB_COMPLETE_NOTIFY;
  765. list_del(&qtd->qtd_list);
  766. isp1760_qtd_free(qtd);
  767. qtd = tmp_qtd;
  768. } while (!last_one && qtd);
  769. return qtd;
  770. }
  771. static void do_atl_int(struct usb_hcd *usb_hcd)
  772. {
  773. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  774. u32 done_map, skip_map;
  775. struct ptd ptd;
  776. struct urb *urb = NULL;
  777. u32 atl_regs_base;
  778. u32 atl_regs;
  779. u32 queue_entry;
  780. u32 payload;
  781. u32 length;
  782. u32 or_map;
  783. u32 status = -EINVAL;
  784. int error;
  785. struct isp1760_qtd *qtd;
  786. struct isp1760_qh *qh;
  787. u32 rl;
  788. u32 nakcount;
  789. done_map = isp1760_readl(usb_hcd->regs +
  790. HC_ATL_PTD_DONEMAP_REG);
  791. skip_map = isp1760_readl(usb_hcd->regs +
  792. HC_ATL_PTD_SKIPMAP_REG);
  793. or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  794. or_map &= ~done_map;
  795. isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  796. atl_regs_base = ATL_REGS_OFFSET;
  797. while (done_map) {
  798. u32 dw1;
  799. u32 dw2;
  800. u32 dw3;
  801. status = 0;
  802. queue_entry = __ffs(done_map);
  803. done_map &= ~(1 << queue_entry);
  804. skip_map |= 1 << queue_entry;
  805. atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
  806. urb = priv->atl_ints[queue_entry].urb;
  807. qtd = priv->atl_ints[queue_entry].qtd;
  808. qh = priv->atl_ints[queue_entry].qh;
  809. payload = priv->atl_ints[queue_entry].payload;
  810. if (!qh) {
  811. printk(KERN_ERR "qh is 0\n");
  812. continue;
  813. }
  814. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs,
  815. atl_regs, sizeof(ptd));
  816. dw1 = le32_to_cpu(ptd.dw1);
  817. dw2 = le32_to_cpu(ptd.dw2);
  818. dw3 = le32_to_cpu(ptd.dw3);
  819. rl = (dw2 >> 25) & 0x0f;
  820. nakcount = (dw3 >> 19) & 0xf;
  821. /* Transfer Error, *but* active and no HALT -> reload */
  822. if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
  823. !(dw3 & DW3_HALT_BIT)) {
  824. /* according to ppriv code, we have to
  825. * reload this one if trasfered bytes != requested bytes
  826. * else act like everything went smooth..
  827. * XXX This just doesn't feel right and hasn't
  828. * triggered so far.
  829. */
  830. length = PTD_XFERRED_LENGTH(dw3);
  831. printk(KERN_ERR "Should reload now.... transfered %d "
  832. "of %zu\n", length, qtd->length);
  833. BUG();
  834. }
  835. if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
  836. u32 buffstatus;
  837. /* XXX
  838. * NAKs are handled in HW by the chip. Usually if the
  839. * device is not able to send data fast enough.
  840. * This did not trigger for a long time now.
  841. */
  842. printk(KERN_ERR "Reloading ptd %p/%p... qh %p readed: "
  843. "%d of %zu done: %08x cur: %08x\n", qtd,
  844. urb, qh, PTD_XFERRED_LENGTH(dw3),
  845. qtd->length, done_map,
  846. (1 << queue_entry));
  847. /* RL counter = ERR counter */
  848. dw3 &= ~(0xf << 19);
  849. dw3 |= rl << 19;
  850. dw3 &= ~(3 << (55 - 32));
  851. dw3 |= ERR_COUNTER << (55 - 32);
  852. /*
  853. * It is not needed to write skip map back because it
  854. * is unchanged. Just make sure that this entry is
  855. * unskipped once it gets written to the HW.
  856. */
  857. skip_map &= ~(1 << queue_entry);
  858. or_map = isp1760_readl(usb_hcd->regs +
  859. HC_ATL_IRQ_MASK_OR_REG);
  860. or_map |= 1 << queue_entry;
  861. isp1760_writel(or_map, usb_hcd->regs +
  862. HC_ATL_IRQ_MASK_OR_REG);
  863. ptd.dw3 = cpu_to_le32(dw3);
  864. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  865. atl_regs, sizeof(ptd));
  866. ptd.dw0 |= __constant_cpu_to_le32(PTD_VALID);
  867. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  868. atl_regs, sizeof(ptd));
  869. buffstatus = isp1760_readl(usb_hcd->regs +
  870. HC_BUFFER_STATUS_REG);
  871. buffstatus |= ATL_BUFFER;
  872. isp1760_writel(buffstatus, usb_hcd->regs +
  873. HC_BUFFER_STATUS_REG);
  874. continue;
  875. }
  876. error = check_error(&ptd);
  877. if (error) {
  878. status = error;
  879. priv->atl_ints[queue_entry].qh->toggle = 0;
  880. priv->atl_ints[queue_entry].qh->ping = 0;
  881. urb->status = -EPIPE;
  882. #if 0
  883. printk(KERN_ERR "Error in %s().\n", __func__);
  884. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  885. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  886. "%08x dw7: %08x\n",
  887. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  888. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  889. #endif
  890. } else {
  891. if (usb_pipetype(urb->pipe) == PIPE_BULK) {
  892. priv->atl_ints[queue_entry].qh->toggle = dw3 &
  893. (1 << 25);
  894. priv->atl_ints[queue_entry].qh->ping = dw3 &
  895. (1 << 26);
  896. }
  897. }
  898. length = PTD_XFERRED_LENGTH(dw3);
  899. if (length) {
  900. switch (DW1_GET_PID(dw1)) {
  901. case IN_PID:
  902. priv_read_copy(priv,
  903. priv->atl_ints[queue_entry].data_buffer,
  904. usb_hcd->regs + payload, payload,
  905. length);
  906. case OUT_PID:
  907. urb->actual_length += length;
  908. case SETUP_PID:
  909. break;
  910. }
  911. }
  912. priv->atl_ints[queue_entry].data_buffer = NULL;
  913. priv->atl_ints[queue_entry].urb = NULL;
  914. priv->atl_ints[queue_entry].qtd = NULL;
  915. priv->atl_ints[queue_entry].qh = NULL;
  916. free_mem(priv, payload);
  917. isp1760_writel(skip_map, usb_hcd->regs +
  918. HC_ATL_PTD_SKIPMAP_REG);
  919. if (urb->status == -EPIPE) {
  920. /* HALT was received */
  921. qtd = clean_up_qtdlist(qtd);
  922. isp1760_urb_done(priv, urb, urb->status);
  923. } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
  924. /* short BULK received */
  925. printk(KERN_ERR "short bulk, %d instead %zu\n", length,
  926. qtd->length);
  927. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  928. urb->status = -EREMOTEIO;
  929. printk(KERN_ERR "not okey\n");
  930. }
  931. if (urb->status == -EINPROGRESS)
  932. urb->status = 0;
  933. qtd = clean_up_qtdlist(qtd);
  934. isp1760_urb_done(priv, urb, urb->status);
  935. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  936. /* that was the last qtd of that URB */
  937. if (urb->status == -EINPROGRESS)
  938. urb->status = 0;
  939. qtd = clean_this_qtd(qtd);
  940. isp1760_urb_done(priv, urb, urb->status);
  941. } else {
  942. /* next QTD of this URB */
  943. qtd = clean_this_qtd(qtd);
  944. BUG_ON(!qtd);
  945. }
  946. if (qtd)
  947. enqueue_an_ATL_packet(usb_hcd, qh, qtd);
  948. skip_map = isp1760_readl(usb_hcd->regs +
  949. HC_ATL_PTD_SKIPMAP_REG);
  950. }
  951. }
  952. static void do_intl_int(struct usb_hcd *usb_hcd)
  953. {
  954. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  955. u32 done_map, skip_map;
  956. struct ptd ptd;
  957. struct urb *urb = NULL;
  958. u32 int_regs;
  959. u32 int_regs_base;
  960. u32 payload;
  961. u32 length;
  962. u32 or_map;
  963. int error;
  964. u32 queue_entry;
  965. struct isp1760_qtd *qtd;
  966. struct isp1760_qh *qh;
  967. done_map = isp1760_readl(usb_hcd->regs +
  968. HC_INT_PTD_DONEMAP_REG);
  969. skip_map = isp1760_readl(usb_hcd->regs +
  970. HC_INT_PTD_SKIPMAP_REG);
  971. or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  972. or_map &= ~done_map;
  973. isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  974. int_regs_base = INT_REGS_OFFSET;
  975. while (done_map) {
  976. u32 dw1;
  977. u32 dw3;
  978. queue_entry = __ffs(done_map);
  979. done_map &= ~(1 << queue_entry);
  980. skip_map |= 1 << queue_entry;
  981. int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
  982. urb = priv->int_ints[queue_entry].urb;
  983. qtd = priv->int_ints[queue_entry].qtd;
  984. qh = priv->int_ints[queue_entry].qh;
  985. payload = priv->int_ints[queue_entry].payload;
  986. if (!qh) {
  987. printk(KERN_ERR "(INT) qh is 0\n");
  988. continue;
  989. }
  990. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs,
  991. int_regs, sizeof(ptd));
  992. dw1 = le32_to_cpu(ptd.dw1);
  993. dw3 = le32_to_cpu(ptd.dw3);
  994. check_int_err_status(le32_to_cpu(ptd.dw4));
  995. error = check_error(&ptd);
  996. if (error) {
  997. #if 0
  998. printk(KERN_ERR "Error in %s().\n", __func__);
  999. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  1000. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  1001. "%08x dw7: %08x\n",
  1002. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  1003. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  1004. #endif
  1005. urb->status = -EPIPE;
  1006. priv->int_ints[queue_entry].qh->toggle = 0;
  1007. priv->int_ints[queue_entry].qh->ping = 0;
  1008. } else {
  1009. priv->int_ints[queue_entry].qh->toggle =
  1010. dw3 & (1 << 25);
  1011. priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
  1012. }
  1013. if (urb->dev->speed != USB_SPEED_HIGH)
  1014. length = PTD_XFERRED_LENGTH_LO(dw3);
  1015. else
  1016. length = PTD_XFERRED_LENGTH(dw3);
  1017. if (length) {
  1018. switch (DW1_GET_PID(dw1)) {
  1019. case IN_PID:
  1020. priv_read_copy(priv,
  1021. priv->int_ints[queue_entry].data_buffer,
  1022. usb_hcd->regs + payload , payload,
  1023. length);
  1024. case OUT_PID:
  1025. urb->actual_length += length;
  1026. case SETUP_PID:
  1027. break;
  1028. }
  1029. }
  1030. priv->int_ints[queue_entry].data_buffer = NULL;
  1031. priv->int_ints[queue_entry].urb = NULL;
  1032. priv->int_ints[queue_entry].qtd = NULL;
  1033. priv->int_ints[queue_entry].qh = NULL;
  1034. isp1760_writel(skip_map, usb_hcd->regs +
  1035. HC_INT_PTD_SKIPMAP_REG);
  1036. free_mem(priv, payload);
  1037. if (urb->status == -EPIPE) {
  1038. /* HALT received */
  1039. qtd = clean_up_qtdlist(qtd);
  1040. isp1760_urb_done(priv, urb, urb->status);
  1041. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  1042. if (urb->status == -EINPROGRESS)
  1043. urb->status = 0;
  1044. qtd = clean_this_qtd(qtd);
  1045. isp1760_urb_done(priv, urb, urb->status);
  1046. } else {
  1047. /* next QTD of this URB */
  1048. qtd = clean_this_qtd(qtd);
  1049. BUG_ON(!qtd);
  1050. }
  1051. if (qtd)
  1052. enqueue_an_INT_packet(usb_hcd, qh, qtd);
  1053. skip_map = isp1760_readl(usb_hcd->regs +
  1054. HC_INT_PTD_SKIPMAP_REG);
  1055. }
  1056. }
  1057. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  1058. static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
  1059. gfp_t flags)
  1060. {
  1061. struct isp1760_qh *qh;
  1062. int is_input, type;
  1063. qh = isp1760_qh_alloc(priv, flags);
  1064. if (!qh)
  1065. return qh;
  1066. /*
  1067. * init endpoint/device data for this QH
  1068. */
  1069. is_input = usb_pipein(urb->pipe);
  1070. type = usb_pipetype(urb->pipe);
  1071. if (type == PIPE_INTERRUPT) {
  1072. if (urb->dev->speed == USB_SPEED_HIGH) {
  1073. qh->period = urb->interval >> 3;
  1074. if (qh->period == 0 && urb->interval != 1) {
  1075. /* NOTE interval 2 or 4 uframes could work.
  1076. * But interval 1 scheduling is simpler, and
  1077. * includes high bandwidth.
  1078. */
  1079. printk(KERN_ERR "intr period %d uframes, NYET!",
  1080. urb->interval);
  1081. qh_destroy(qh);
  1082. return NULL;
  1083. }
  1084. } else {
  1085. qh->period = urb->interval;
  1086. }
  1087. }
  1088. /* support for tt scheduling, and access to toggles */
  1089. qh->dev = urb->dev;
  1090. if (!usb_pipecontrol(urb->pipe))
  1091. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
  1092. 1);
  1093. return qh;
  1094. }
  1095. /*
  1096. * For control/bulk/interrupt, return QH with these TDs appended.
  1097. * Allocates and initializes the QH if necessary.
  1098. * Returns null if it can't allocate a QH it needs to.
  1099. * If the QH has TDs (urbs) already, that's great.
  1100. */
  1101. static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
  1102. struct urb *urb, struct list_head *qtd_list, int epnum,
  1103. void **ptr)
  1104. {
  1105. struct isp1760_qh *qh;
  1106. struct isp1760_qtd *qtd;
  1107. struct isp1760_qtd *prev_qtd;
  1108. qh = (struct isp1760_qh *)*ptr;
  1109. if (!qh) {
  1110. /* can't sleep here, we have priv->lock... */
  1111. qh = qh_make(priv, urb, GFP_ATOMIC);
  1112. if (!qh)
  1113. return qh;
  1114. *ptr = qh;
  1115. }
  1116. qtd = list_entry(qtd_list->next, struct isp1760_qtd,
  1117. qtd_list);
  1118. if (!list_empty(&qh->qtd_list))
  1119. prev_qtd = list_entry(qh->qtd_list.prev,
  1120. struct isp1760_qtd, qtd_list);
  1121. else
  1122. prev_qtd = NULL;
  1123. list_splice(qtd_list, qh->qtd_list.prev);
  1124. if (prev_qtd) {
  1125. BUG_ON(prev_qtd->hw_next);
  1126. prev_qtd->hw_next = qtd;
  1127. }
  1128. urb->hcpriv = qh;
  1129. return qh;
  1130. }
  1131. static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
  1132. struct list_head *qtd_list)
  1133. {
  1134. struct list_head *entry, *temp;
  1135. list_for_each_safe(entry, temp, qtd_list) {
  1136. struct isp1760_qtd *qtd;
  1137. qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
  1138. list_del(&qtd->qtd_list);
  1139. isp1760_qtd_free(qtd);
  1140. }
  1141. }
  1142. static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
  1143. struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
  1144. {
  1145. struct isp1760_qtd *qtd;
  1146. int epnum;
  1147. unsigned long flags;
  1148. struct isp1760_qh *qh = NULL;
  1149. int rc;
  1150. int qh_busy;
  1151. qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
  1152. epnum = urb->ep->desc.bEndpointAddress;
  1153. spin_lock_irqsave(&priv->lock, flags);
  1154. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
  1155. rc = -ESHUTDOWN;
  1156. goto done;
  1157. }
  1158. rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
  1159. if (rc)
  1160. goto done;
  1161. qh = urb->ep->hcpriv;
  1162. if (qh)
  1163. qh_busy = !list_empty(&qh->qtd_list);
  1164. else
  1165. qh_busy = 0;
  1166. qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1167. if (!qh) {
  1168. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  1169. rc = -ENOMEM;
  1170. goto done;
  1171. }
  1172. if (!qh_busy)
  1173. p(priv_to_hcd(priv), qh, qtd);
  1174. done:
  1175. spin_unlock_irqrestore(&priv->lock, flags);
  1176. if (!qh)
  1177. qtd_list_free(priv, urb, qtd_list);
  1178. return rc;
  1179. }
  1180. static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
  1181. gfp_t flags)
  1182. {
  1183. struct isp1760_qtd *qtd;
  1184. qtd = kmem_cache_zalloc(qtd_cachep, flags);
  1185. if (qtd)
  1186. INIT_LIST_HEAD(&qtd->qtd_list);
  1187. return qtd;
  1188. }
  1189. /*
  1190. * create a list of filled qtds for this URB; won't link into qh.
  1191. */
  1192. static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
  1193. struct urb *urb, struct list_head *head, gfp_t flags)
  1194. {
  1195. struct isp1760_qtd *qtd, *qtd_prev;
  1196. void *buf;
  1197. int len, maxpacket;
  1198. int is_input;
  1199. u32 token;
  1200. /*
  1201. * URBs map to sequences of QTDs: one logical transaction
  1202. */
  1203. qtd = isp1760_qtd_alloc(priv, flags);
  1204. if (!qtd)
  1205. return NULL;
  1206. list_add_tail(&qtd->qtd_list, head);
  1207. qtd->urb = urb;
  1208. urb->status = -EINPROGRESS;
  1209. token = 0;
  1210. /* for split transactions, SplitXState initialized to zero */
  1211. len = urb->transfer_buffer_length;
  1212. is_input = usb_pipein(urb->pipe);
  1213. if (usb_pipecontrol(urb->pipe)) {
  1214. /* SETUP pid */
  1215. qtd_fill(qtd, urb->setup_packet,
  1216. sizeof(struct usb_ctrlrequest),
  1217. token | SETUP_PID);
  1218. /* ... and always at least one more pid */
  1219. token ^= DATA_TOGGLE;
  1220. qtd_prev = qtd;
  1221. qtd = isp1760_qtd_alloc(priv, flags);
  1222. if (!qtd)
  1223. goto cleanup;
  1224. qtd->urb = urb;
  1225. qtd_prev->hw_next = qtd;
  1226. list_add_tail(&qtd->qtd_list, head);
  1227. /* for zero length DATA stages, STATUS is always IN */
  1228. if (len == 0)
  1229. token |= IN_PID;
  1230. }
  1231. /*
  1232. * data transfer stage: buffer setup
  1233. */
  1234. buf = urb->transfer_buffer;
  1235. if (is_input)
  1236. token |= IN_PID;
  1237. else
  1238. token |= OUT_PID;
  1239. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1240. /*
  1241. * buffer gets wrapped in one or more qtds;
  1242. * last one may be "short" (including zero len)
  1243. * and may serve as a control status ack
  1244. */
  1245. for (;;) {
  1246. int this_qtd_len;
  1247. if (!buf && len) {
  1248. /* XXX This looks like usb storage / SCSI bug */
  1249. printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
  1250. (long unsigned)urb->transfer_dma, len);
  1251. WARN_ON(1);
  1252. }
  1253. this_qtd_len = qtd_fill(qtd, buf, len, token);
  1254. len -= this_qtd_len;
  1255. buf += this_qtd_len;
  1256. /* qh makes control packets use qtd toggle; maybe switch it */
  1257. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1258. token ^= DATA_TOGGLE;
  1259. if (len <= 0)
  1260. break;
  1261. qtd_prev = qtd;
  1262. qtd = isp1760_qtd_alloc(priv, flags);
  1263. if (!qtd)
  1264. goto cleanup;
  1265. qtd->urb = urb;
  1266. qtd_prev->hw_next = qtd;
  1267. list_add_tail(&qtd->qtd_list, head);
  1268. }
  1269. /*
  1270. * control requests may need a terminating data "status" ack;
  1271. * bulk ones may need a terminating short packet (zero length).
  1272. */
  1273. if (urb->transfer_buffer_length != 0) {
  1274. int one_more = 0;
  1275. if (usb_pipecontrol(urb->pipe)) {
  1276. one_more = 1;
  1277. /* "in" <--> "out" */
  1278. token ^= IN_PID;
  1279. /* force DATA1 */
  1280. token |= DATA_TOGGLE;
  1281. } else if (usb_pipebulk(urb->pipe)
  1282. && (urb->transfer_flags & URB_ZERO_PACKET)
  1283. && !(urb->transfer_buffer_length % maxpacket)) {
  1284. one_more = 1;
  1285. }
  1286. if (one_more) {
  1287. qtd_prev = qtd;
  1288. qtd = isp1760_qtd_alloc(priv, flags);
  1289. if (!qtd)
  1290. goto cleanup;
  1291. qtd->urb = urb;
  1292. qtd_prev->hw_next = qtd;
  1293. list_add_tail(&qtd->qtd_list, head);
  1294. /* never any data in such packets */
  1295. qtd_fill(qtd, NULL, 0, token);
  1296. }
  1297. }
  1298. qtd->status = URB_COMPLETE_NOTIFY;
  1299. return head;
  1300. cleanup:
  1301. qtd_list_free(priv, urb, head);
  1302. return NULL;
  1303. }
  1304. static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  1305. gfp_t mem_flags)
  1306. {
  1307. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1308. struct list_head qtd_list;
  1309. packet_enqueue *pe;
  1310. INIT_LIST_HEAD(&qtd_list);
  1311. switch (usb_pipetype(urb->pipe)) {
  1312. case PIPE_CONTROL:
  1313. case PIPE_BULK:
  1314. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1315. return -ENOMEM;
  1316. pe = enqueue_an_ATL_packet;
  1317. break;
  1318. case PIPE_INTERRUPT:
  1319. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1320. return -ENOMEM;
  1321. pe = enqueue_an_INT_packet;
  1322. break;
  1323. case PIPE_ISOCHRONOUS:
  1324. printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
  1325. default:
  1326. return -EPIPE;
  1327. }
  1328. isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
  1329. return 0;
  1330. }
  1331. static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
  1332. int status)
  1333. {
  1334. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1335. struct inter_packet_info *ints;
  1336. u32 i;
  1337. u32 reg_base, or_reg, skip_reg;
  1338. unsigned long flags;
  1339. struct ptd ptd;
  1340. switch (usb_pipetype(urb->pipe)) {
  1341. case PIPE_ISOCHRONOUS:
  1342. return -EPIPE;
  1343. break;
  1344. case PIPE_INTERRUPT:
  1345. ints = priv->int_ints;
  1346. reg_base = INT_REGS_OFFSET;
  1347. or_reg = HC_INT_IRQ_MASK_OR_REG;
  1348. skip_reg = HC_INT_PTD_SKIPMAP_REG;
  1349. break;
  1350. default:
  1351. ints = priv->atl_ints;
  1352. reg_base = ATL_REGS_OFFSET;
  1353. or_reg = HC_ATL_IRQ_MASK_OR_REG;
  1354. skip_reg = HC_ATL_PTD_SKIPMAP_REG;
  1355. break;
  1356. }
  1357. memset(&ptd, 0, sizeof(ptd));
  1358. spin_lock_irqsave(&priv->lock, flags);
  1359. for (i = 0; i < 32; i++) {
  1360. if (ints->urb == urb) {
  1361. u32 skip_map;
  1362. u32 or_map;
  1363. struct isp1760_qtd *qtd;
  1364. skip_map = isp1760_readl(hcd->regs + skip_reg);
  1365. skip_map |= 1 << i;
  1366. isp1760_writel(skip_map, hcd->regs + skip_reg);
  1367. or_map = isp1760_readl(hcd->regs + or_reg);
  1368. or_map &= ~(1 << i);
  1369. isp1760_writel(or_map, hcd->regs + or_reg);
  1370. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
  1371. + i * sizeof(ptd), sizeof(ptd));
  1372. qtd = ints->qtd;
  1373. clean_up_qtdlist(qtd);
  1374. free_mem(priv, ints->payload);
  1375. ints->urb = NULL;
  1376. ints->qh = NULL;
  1377. ints->qtd = NULL;
  1378. ints->data_buffer = NULL;
  1379. ints->payload = 0;
  1380. isp1760_urb_done(priv, urb, status);
  1381. break;
  1382. }
  1383. ints++;
  1384. }
  1385. spin_unlock_irqrestore(&priv->lock, flags);
  1386. return 0;
  1387. }
  1388. static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
  1389. {
  1390. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1391. u32 imask;
  1392. irqreturn_t irqret = IRQ_NONE;
  1393. spin_lock(&priv->lock);
  1394. if (!(usb_hcd->state & HC_STATE_RUNNING))
  1395. goto leave;
  1396. imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
  1397. if (unlikely(!imask))
  1398. goto leave;
  1399. isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
  1400. if (imask & HC_ATL_INT)
  1401. do_atl_int(usb_hcd);
  1402. if (imask & HC_INTL_INT)
  1403. do_intl_int(usb_hcd);
  1404. irqret = IRQ_HANDLED;
  1405. leave:
  1406. spin_unlock(&priv->lock);
  1407. return irqret;
  1408. }
  1409. static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
  1410. {
  1411. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1412. u32 temp, status = 0;
  1413. u32 mask;
  1414. int retval = 1;
  1415. unsigned long flags;
  1416. /* if !USB_SUSPEND, root hub timers won't get shut down ... */
  1417. if (!HC_IS_RUNNING(hcd->state))
  1418. return 0;
  1419. /* init status to no-changes */
  1420. buf[0] = 0;
  1421. mask = PORT_CSC;
  1422. spin_lock_irqsave(&priv->lock, flags);
  1423. temp = isp1760_readl(hcd->regs + HC_PORTSC1);
  1424. if (temp & PORT_OWNER) {
  1425. if (temp & PORT_CSC) {
  1426. temp &= ~PORT_CSC;
  1427. isp1760_writel(temp, hcd->regs + HC_PORTSC1);
  1428. goto done;
  1429. }
  1430. }
  1431. /*
  1432. * Return status information even for ports with OWNER set.
  1433. * Otherwise khubd wouldn't see the disconnect event when a
  1434. * high-speed device is switched over to the companion
  1435. * controller by the user.
  1436. */
  1437. if ((temp & mask) != 0
  1438. || ((temp & PORT_RESUME) != 0
  1439. && time_after_eq(jiffies,
  1440. priv->reset_done))) {
  1441. buf [0] |= 1 << (0 + 1);
  1442. status = STS_PCD;
  1443. }
  1444. /* FIXME autosuspend idle root hubs */
  1445. done:
  1446. spin_unlock_irqrestore(&priv->lock, flags);
  1447. return status ? retval : 0;
  1448. }
  1449. static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
  1450. struct usb_hub_descriptor *desc)
  1451. {
  1452. int ports = HCS_N_PORTS(priv->hcs_params);
  1453. u16 temp;
  1454. desc->bDescriptorType = 0x29;
  1455. /* priv 1.0, 2.3.9 says 20ms max */
  1456. desc->bPwrOn2PwrGood = 10;
  1457. desc->bHubContrCurrent = 0;
  1458. desc->bNbrPorts = ports;
  1459. temp = 1 + (ports / 8);
  1460. desc->bDescLength = 7 + 2 * temp;
  1461. /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  1462. memset(&desc->bitmap[0], 0, temp);
  1463. memset(&desc->bitmap[temp], 0xff, temp);
  1464. /* per-port overcurrent reporting */
  1465. temp = 0x0008;
  1466. if (HCS_PPC(priv->hcs_params))
  1467. /* per-port power control */
  1468. temp |= 0x0001;
  1469. else
  1470. /* no power switching */
  1471. temp |= 0x0002;
  1472. desc->wHubCharacteristics = cpu_to_le16(temp);
  1473. }
  1474. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  1475. static int check_reset_complete(struct isp1760_hcd *priv, int index,
  1476. u32 __iomem *status_reg, int port_status)
  1477. {
  1478. if (!(port_status & PORT_CONNECT))
  1479. return port_status;
  1480. /* if reset finished and it's still not enabled -- handoff */
  1481. if (!(port_status & PORT_PE)) {
  1482. printk(KERN_ERR "port %d full speed --> companion\n",
  1483. index + 1);
  1484. port_status |= PORT_OWNER;
  1485. port_status &= ~PORT_RWC_BITS;
  1486. isp1760_writel(port_status, status_reg);
  1487. } else
  1488. printk(KERN_ERR "port %d high speed\n", index + 1);
  1489. return port_status;
  1490. }
  1491. static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
  1492. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  1493. {
  1494. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1495. int ports = HCS_N_PORTS(priv->hcs_params);
  1496. u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
  1497. u32 temp, status;
  1498. unsigned long flags;
  1499. int retval = 0;
  1500. unsigned selector;
  1501. /*
  1502. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  1503. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  1504. * (track current state ourselves) ... blink for diagnostics,
  1505. * power, "this is the one", etc. EHCI spec supports this.
  1506. */
  1507. spin_lock_irqsave(&priv->lock, flags);
  1508. switch (typeReq) {
  1509. case ClearHubFeature:
  1510. switch (wValue) {
  1511. case C_HUB_LOCAL_POWER:
  1512. case C_HUB_OVER_CURRENT:
  1513. /* no hub-wide feature/status flags */
  1514. break;
  1515. default:
  1516. goto error;
  1517. }
  1518. break;
  1519. case ClearPortFeature:
  1520. if (!wIndex || wIndex > ports)
  1521. goto error;
  1522. wIndex--;
  1523. temp = isp1760_readl(status_reg);
  1524. /*
  1525. * Even if OWNER is set, so the port is owned by the
  1526. * companion controller, khubd needs to be able to clear
  1527. * the port-change status bits (especially
  1528. * USB_PORT_FEAT_C_CONNECTION).
  1529. */
  1530. switch (wValue) {
  1531. case USB_PORT_FEAT_ENABLE:
  1532. isp1760_writel(temp & ~PORT_PE, status_reg);
  1533. break;
  1534. case USB_PORT_FEAT_C_ENABLE:
  1535. /* XXX error? */
  1536. break;
  1537. case USB_PORT_FEAT_SUSPEND:
  1538. if (temp & PORT_RESET)
  1539. goto error;
  1540. if (temp & PORT_SUSPEND) {
  1541. if ((temp & PORT_PE) == 0)
  1542. goto error;
  1543. /* resume signaling for 20 msec */
  1544. temp &= ~(PORT_RWC_BITS);
  1545. isp1760_writel(temp | PORT_RESUME,
  1546. status_reg);
  1547. priv->reset_done = jiffies +
  1548. msecs_to_jiffies(20);
  1549. }
  1550. break;
  1551. case USB_PORT_FEAT_C_SUSPEND:
  1552. /* we auto-clear this feature */
  1553. break;
  1554. case USB_PORT_FEAT_POWER:
  1555. if (HCS_PPC(priv->hcs_params))
  1556. isp1760_writel(temp & ~PORT_POWER, status_reg);
  1557. break;
  1558. case USB_PORT_FEAT_C_CONNECTION:
  1559. isp1760_writel(temp | PORT_CSC,
  1560. status_reg);
  1561. break;
  1562. case USB_PORT_FEAT_C_OVER_CURRENT:
  1563. /* XXX error ?*/
  1564. break;
  1565. case USB_PORT_FEAT_C_RESET:
  1566. /* GetPortStatus clears reset */
  1567. break;
  1568. default:
  1569. goto error;
  1570. }
  1571. isp1760_readl(hcd->regs + HC_USBCMD);
  1572. break;
  1573. case GetHubDescriptor:
  1574. isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
  1575. buf);
  1576. break;
  1577. case GetHubStatus:
  1578. /* no hub-wide feature/status flags */
  1579. memset(buf, 0, 4);
  1580. break;
  1581. case GetPortStatus:
  1582. if (!wIndex || wIndex > ports)
  1583. goto error;
  1584. wIndex--;
  1585. status = 0;
  1586. temp = isp1760_readl(status_reg);
  1587. /* wPortChange bits */
  1588. if (temp & PORT_CSC)
  1589. status |= 1 << USB_PORT_FEAT_C_CONNECTION;
  1590. /* whoever resumes must GetPortStatus to complete it!! */
  1591. if (temp & PORT_RESUME) {
  1592. printk(KERN_ERR "Port resume should be skipped.\n");
  1593. /* Remote Wakeup received? */
  1594. if (!priv->reset_done) {
  1595. /* resume signaling for 20 msec */
  1596. priv->reset_done = jiffies
  1597. + msecs_to_jiffies(20);
  1598. /* check the port again */
  1599. mod_timer(&priv_to_hcd(priv)->rh_timer,
  1600. priv->reset_done);
  1601. }
  1602. /* resume completed? */
  1603. else if (time_after_eq(jiffies,
  1604. priv->reset_done)) {
  1605. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  1606. priv->reset_done = 0;
  1607. /* stop resume signaling */
  1608. temp = isp1760_readl(status_reg);
  1609. isp1760_writel(
  1610. temp & ~(PORT_RWC_BITS | PORT_RESUME),
  1611. status_reg);
  1612. retval = handshake(priv, status_reg,
  1613. PORT_RESUME, 0, 2000 /* 2msec */);
  1614. if (retval != 0) {
  1615. isp1760_err(priv,
  1616. "port %d resume error %d\n",
  1617. wIndex + 1, retval);
  1618. goto error;
  1619. }
  1620. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  1621. }
  1622. }
  1623. /* whoever resets must GetPortStatus to complete it!! */
  1624. if ((temp & PORT_RESET)
  1625. && time_after_eq(jiffies,
  1626. priv->reset_done)) {
  1627. status |= 1 << USB_PORT_FEAT_C_RESET;
  1628. priv->reset_done = 0;
  1629. /* force reset to complete */
  1630. isp1760_writel(temp & ~PORT_RESET,
  1631. status_reg);
  1632. /* REVISIT: some hardware needs 550+ usec to clear
  1633. * this bit; seems too long to spin routinely...
  1634. */
  1635. retval = handshake(priv, status_reg,
  1636. PORT_RESET, 0, 750);
  1637. if (retval != 0) {
  1638. isp1760_err(priv, "port %d reset error %d\n",
  1639. wIndex + 1, retval);
  1640. goto error;
  1641. }
  1642. /* see what we found out */
  1643. temp = check_reset_complete(priv, wIndex, status_reg,
  1644. isp1760_readl(status_reg));
  1645. }
  1646. /*
  1647. * Even if OWNER is set, there's no harm letting khubd
  1648. * see the wPortStatus values (they should all be 0 except
  1649. * for PORT_POWER anyway).
  1650. */
  1651. if (temp & PORT_OWNER)
  1652. printk(KERN_ERR "Warning: PORT_OWNER is set\n");
  1653. if (temp & PORT_CONNECT) {
  1654. status |= 1 << USB_PORT_FEAT_CONNECTION;
  1655. /* status may be from integrated TT */
  1656. status |= ehci_port_speed(priv, temp);
  1657. }
  1658. if (temp & PORT_PE)
  1659. status |= 1 << USB_PORT_FEAT_ENABLE;
  1660. if (temp & (PORT_SUSPEND|PORT_RESUME))
  1661. status |= 1 << USB_PORT_FEAT_SUSPEND;
  1662. if (temp & PORT_RESET)
  1663. status |= 1 << USB_PORT_FEAT_RESET;
  1664. if (temp & PORT_POWER)
  1665. status |= 1 << USB_PORT_FEAT_POWER;
  1666. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  1667. break;
  1668. case SetHubFeature:
  1669. switch (wValue) {
  1670. case C_HUB_LOCAL_POWER:
  1671. case C_HUB_OVER_CURRENT:
  1672. /* no hub-wide feature/status flags */
  1673. break;
  1674. default:
  1675. goto error;
  1676. }
  1677. break;
  1678. case SetPortFeature:
  1679. selector = wIndex >> 8;
  1680. wIndex &= 0xff;
  1681. if (!wIndex || wIndex > ports)
  1682. goto error;
  1683. wIndex--;
  1684. temp = isp1760_readl(status_reg);
  1685. if (temp & PORT_OWNER)
  1686. break;
  1687. /* temp &= ~PORT_RWC_BITS; */
  1688. switch (wValue) {
  1689. case USB_PORT_FEAT_ENABLE:
  1690. isp1760_writel(temp | PORT_PE, status_reg);
  1691. break;
  1692. case USB_PORT_FEAT_SUSPEND:
  1693. if ((temp & PORT_PE) == 0
  1694. || (temp & PORT_RESET) != 0)
  1695. goto error;
  1696. isp1760_writel(temp | PORT_SUSPEND, status_reg);
  1697. break;
  1698. case USB_PORT_FEAT_POWER:
  1699. if (HCS_PPC(priv->hcs_params))
  1700. isp1760_writel(temp | PORT_POWER,
  1701. status_reg);
  1702. break;
  1703. case USB_PORT_FEAT_RESET:
  1704. if (temp & PORT_RESUME)
  1705. goto error;
  1706. /* line status bits may report this as low speed,
  1707. * which can be fine if this root hub has a
  1708. * transaction translator built in.
  1709. */
  1710. if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
  1711. && PORT_USB11(temp)) {
  1712. temp |= PORT_OWNER;
  1713. } else {
  1714. temp |= PORT_RESET;
  1715. temp &= ~PORT_PE;
  1716. /*
  1717. * caller must wait, then call GetPortStatus
  1718. * usb 2.0 spec says 50 ms resets on root
  1719. */
  1720. priv->reset_done = jiffies +
  1721. msecs_to_jiffies(50);
  1722. }
  1723. isp1760_writel(temp, status_reg);
  1724. break;
  1725. default:
  1726. goto error;
  1727. }
  1728. isp1760_readl(hcd->regs + HC_USBCMD);
  1729. break;
  1730. default:
  1731. error:
  1732. /* "stall" on error */
  1733. retval = -EPIPE;
  1734. }
  1735. spin_unlock_irqrestore(&priv->lock, flags);
  1736. return retval;
  1737. }
  1738. static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
  1739. struct usb_host_endpoint *ep)
  1740. {
  1741. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1742. struct isp1760_qh *qh;
  1743. struct isp1760_qtd *qtd;
  1744. unsigned long flags;
  1745. spin_lock_irqsave(&priv->lock, flags);
  1746. qh = ep->hcpriv;
  1747. if (!qh)
  1748. goto out;
  1749. ep->hcpriv = NULL;
  1750. do {
  1751. /* more than entry might get removed */
  1752. if (list_empty(&qh->qtd_list))
  1753. break;
  1754. qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
  1755. qtd_list);
  1756. if (qtd->status & URB_ENQUEUED) {
  1757. spin_unlock_irqrestore(&priv->lock, flags);
  1758. isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
  1759. spin_lock_irqsave(&priv->lock, flags);
  1760. } else {
  1761. struct urb *urb;
  1762. urb = qtd->urb;
  1763. clean_up_qtdlist(qtd);
  1764. isp1760_urb_done(priv, urb, -ECONNRESET);
  1765. }
  1766. } while (1);
  1767. qh_destroy(qh);
  1768. /* remove requests and leak them.
  1769. * ATL are pretty fast done, INT could take a while...
  1770. * The latter shoule be removed
  1771. */
  1772. out:
  1773. spin_unlock_irqrestore(&priv->lock, flags);
  1774. }
  1775. static int isp1760_get_frame(struct usb_hcd *hcd)
  1776. {
  1777. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1778. u32 fr;
  1779. fr = isp1760_readl(hcd->regs + HC_FRINDEX);
  1780. return (fr >> 3) % priv->periodic_size;
  1781. }
  1782. static void isp1760_stop(struct usb_hcd *hcd)
  1783. {
  1784. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1785. u32 temp;
  1786. isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
  1787. NULL, 0);
  1788. mdelay(20);
  1789. spin_lock_irq(&priv->lock);
  1790. ehci_reset(priv);
  1791. /* Disable IRQ */
  1792. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1793. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1794. spin_unlock_irq(&priv->lock);
  1795. isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
  1796. }
  1797. static void isp1760_shutdown(struct usb_hcd *hcd)
  1798. {
  1799. u32 command, temp;
  1800. isp1760_stop(hcd);
  1801. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1802. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1803. command = isp1760_readl(hcd->regs + HC_USBCMD);
  1804. command &= ~CMD_RUN;
  1805. isp1760_writel(command, hcd->regs + HC_USBCMD);
  1806. }
  1807. static const struct hc_driver isp1760_hc_driver = {
  1808. .description = "isp1760-hcd",
  1809. .product_desc = "NXP ISP1760 USB Host Controller",
  1810. .hcd_priv_size = sizeof(struct isp1760_hcd),
  1811. .irq = isp1760_irq,
  1812. .flags = HCD_MEMORY | HCD_USB2,
  1813. .reset = isp1760_hc_setup,
  1814. .start = isp1760_run,
  1815. .stop = isp1760_stop,
  1816. .shutdown = isp1760_shutdown,
  1817. .urb_enqueue = isp1760_urb_enqueue,
  1818. .urb_dequeue = isp1760_urb_dequeue,
  1819. .endpoint_disable = isp1760_endpoint_disable,
  1820. .get_frame_number = isp1760_get_frame,
  1821. .hub_status_data = isp1760_hub_status_data,
  1822. .hub_control = isp1760_hub_control,
  1823. };
  1824. int __init init_kmem_once(void)
  1825. {
  1826. qtd_cachep = kmem_cache_create("isp1760_qtd",
  1827. sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
  1828. SLAB_MEM_SPREAD, NULL);
  1829. if (!qtd_cachep)
  1830. return -ENOMEM;
  1831. qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
  1832. 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
  1833. if (!qh_cachep) {
  1834. kmem_cache_destroy(qtd_cachep);
  1835. return -ENOMEM;
  1836. }
  1837. return 0;
  1838. }
  1839. void deinit_kmem_cache(void)
  1840. {
  1841. kmem_cache_destroy(qtd_cachep);
  1842. kmem_cache_destroy(qh_cachep);
  1843. }
  1844. struct usb_hcd *isp1760_register(u64 res_start, u64 res_len, int irq,
  1845. u64 irqflags, struct device *dev, const char *busname,
  1846. unsigned int devflags)
  1847. {
  1848. struct usb_hcd *hcd;
  1849. struct isp1760_hcd *priv;
  1850. int ret;
  1851. if (usb_disabled())
  1852. return ERR_PTR(-ENODEV);
  1853. /* prevent usb-core allocating DMA pages */
  1854. dev->dma_mask = NULL;
  1855. hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
  1856. if (!hcd)
  1857. return ERR_PTR(-ENOMEM);
  1858. priv = hcd_to_priv(hcd);
  1859. priv->devflags = devflags;
  1860. init_memory(priv);
  1861. hcd->regs = ioremap(res_start, res_len);
  1862. if (!hcd->regs) {
  1863. ret = -EIO;
  1864. goto err_put;
  1865. }
  1866. hcd->irq = irq;
  1867. hcd->rsrc_start = res_start;
  1868. hcd->rsrc_len = res_len;
  1869. ret = usb_add_hcd(hcd, irq, irqflags);
  1870. if (ret)
  1871. goto err_unmap;
  1872. return hcd;
  1873. err_unmap:
  1874. iounmap(hcd->regs);
  1875. err_put:
  1876. usb_put_hcd(hcd);
  1877. return ERR_PTR(ret);
  1878. }
  1879. MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
  1880. MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
  1881. MODULE_LICENSE("GPL v2");