s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/smp_lock.h>
  31. #include <linux/errno.h>
  32. #include <linux/init.h>
  33. #include <linux/timer.h>
  34. #include <linux/list.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/version.h>
  38. #include <linux/clk.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/usb.h>
  42. #include <linux/usb/gadget.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include <mach/irqs.h>
  49. #include <mach/hardware.h>
  50. #include <mach/regs-gpio.h>
  51. #include <asm/plat-s3c24xx/regs-udc.h>
  52. #include <asm/plat-s3c24xx/udc.h>
  53. #include "s3c2410_udc.h"
  54. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  55. #define DRIVER_VERSION "29 Apr 2007"
  56. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  57. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  58. static const char gadget_name[] = "s3c2410_udc";
  59. static const char driver_desc[] = DRIVER_DESC;
  60. static struct s3c2410_udc *the_controller;
  61. static struct clk *udc_clock;
  62. static struct clk *usb_bus_clock;
  63. static void __iomem *base_addr;
  64. static u64 rsrc_start;
  65. static u64 rsrc_len;
  66. static struct dentry *s3c2410_udc_debugfs_root;
  67. static inline u32 udc_read(u32 reg)
  68. {
  69. return readb(base_addr + reg);
  70. }
  71. static inline void udc_write(u32 value, u32 reg)
  72. {
  73. writeb(value, base_addr + reg);
  74. }
  75. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  76. {
  77. writeb(value, base + reg);
  78. }
  79. static struct s3c2410_udc_mach_info *udc_info;
  80. /*************************** DEBUG FUNCTION ***************************/
  81. #define DEBUG_NORMAL 1
  82. #define DEBUG_VERBOSE 2
  83. #ifdef CONFIG_USB_S3C2410_DEBUG
  84. #define USB_S3C2410_DEBUG_LEVEL 0
  85. static uint32_t s3c2410_ticks = 0;
  86. static int dprintk(int level, const char *fmt, ...)
  87. {
  88. static char printk_buf[1024];
  89. static long prevticks;
  90. static int invocation;
  91. va_list args;
  92. int len;
  93. if (level > USB_S3C2410_DEBUG_LEVEL)
  94. return 0;
  95. if (s3c2410_ticks != prevticks) {
  96. prevticks = s3c2410_ticks;
  97. invocation = 0;
  98. }
  99. len = scnprintf(printk_buf,
  100. sizeof(printk_buf), "%1lu.%02d USB: ",
  101. prevticks, invocation++);
  102. va_start(args, fmt);
  103. len = vscnprintf(printk_buf+len,
  104. sizeof(printk_buf)-len, fmt, args);
  105. va_end(args);
  106. return printk(KERN_DEBUG "%s", printk_buf);
  107. }
  108. #else
  109. static int dprintk(int level, const char *fmt, ...)
  110. {
  111. return 0;
  112. }
  113. #endif
  114. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  115. {
  116. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  117. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  118. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  119. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  120. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  121. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  122. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  123. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  124. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  125. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  126. udc_write(0, S3C2410_UDC_INDEX_REG);
  127. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  128. udc_write(1, S3C2410_UDC_INDEX_REG);
  129. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  130. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  131. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  132. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  133. udc_write(2, S3C2410_UDC_INDEX_REG);
  134. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  135. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  136. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  137. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  138. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  139. "PWR_REG : 0x%04X\n"
  140. "EP_INT_REG : 0x%04X\n"
  141. "USB_INT_REG : 0x%04X\n"
  142. "EP_INT_EN_REG : 0x%04X\n"
  143. "USB_INT_EN_REG : 0x%04X\n"
  144. "EP0_CSR : 0x%04X\n"
  145. "EP1_I_CSR1 : 0x%04X\n"
  146. "EP1_I_CSR2 : 0x%04X\n"
  147. "EP1_O_CSR1 : 0x%04X\n"
  148. "EP1_O_CSR2 : 0x%04X\n"
  149. "EP2_I_CSR1 : 0x%04X\n"
  150. "EP2_I_CSR2 : 0x%04X\n"
  151. "EP2_O_CSR1 : 0x%04X\n"
  152. "EP2_O_CSR2 : 0x%04X\n",
  153. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  154. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  155. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  156. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  157. );
  158. return 0;
  159. }
  160. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  161. struct file *file)
  162. {
  163. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  164. }
  165. static const struct file_operations s3c2410_udc_debugfs_fops = {
  166. .open = s3c2410_udc_debugfs_fops_open,
  167. .read = seq_read,
  168. .llseek = seq_lseek,
  169. .release = single_release,
  170. .owner = THIS_MODULE,
  171. };
  172. /* io macros */
  173. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  174. {
  175. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  176. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  177. S3C2410_UDC_EP0_CSR_REG);
  178. }
  179. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  180. {
  181. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  182. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  183. }
  184. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  185. {
  186. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  187. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  188. }
  189. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  190. {
  191. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  192. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  193. }
  194. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  195. {
  196. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  197. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  198. }
  199. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  200. {
  201. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  202. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  203. }
  204. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  205. {
  206. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  207. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  208. | S3C2410_UDC_EP0_CSR_DE),
  209. S3C2410_UDC_EP0_CSR_REG);
  210. }
  211. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  212. {
  213. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  214. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  215. | S3C2410_UDC_EP0_CSR_SSE),
  216. S3C2410_UDC_EP0_CSR_REG);
  217. }
  218. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  219. {
  220. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  221. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  222. | S3C2410_UDC_EP0_CSR_DE),
  223. S3C2410_UDC_EP0_CSR_REG);
  224. }
  225. /*------------------------- I/O ----------------------------------*/
  226. /*
  227. * s3c2410_udc_done
  228. */
  229. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  230. struct s3c2410_request *req, int status)
  231. {
  232. unsigned halted = ep->halted;
  233. list_del_init(&req->queue);
  234. if (likely (req->req.status == -EINPROGRESS))
  235. req->req.status = status;
  236. else
  237. status = req->req.status;
  238. ep->halted = 1;
  239. req->req.complete(&ep->ep, &req->req);
  240. ep->halted = halted;
  241. }
  242. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  243. struct s3c2410_ep *ep, int status)
  244. {
  245. /* Sanity check */
  246. if (&ep->queue == NULL)
  247. return;
  248. while (!list_empty (&ep->queue)) {
  249. struct s3c2410_request *req;
  250. req = list_entry (ep->queue.next, struct s3c2410_request,
  251. queue);
  252. s3c2410_udc_done(ep, req, status);
  253. }
  254. }
  255. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  256. {
  257. unsigned i;
  258. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  259. * fifos, and pending transactions mustn't be continued in any case.
  260. */
  261. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  262. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  263. }
  264. static inline int s3c2410_udc_fifo_count_out(void)
  265. {
  266. int tmp;
  267. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  268. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  269. return tmp;
  270. }
  271. /*
  272. * s3c2410_udc_write_packet
  273. */
  274. static inline int s3c2410_udc_write_packet(int fifo,
  275. struct s3c2410_request *req,
  276. unsigned max)
  277. {
  278. unsigned len = min(req->req.length - req->req.actual, max);
  279. u8 *buf = req->req.buf + req->req.actual;
  280. prefetch(buf);
  281. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  282. req->req.actual, req->req.length, len, req->req.actual + len);
  283. req->req.actual += len;
  284. udelay(5);
  285. writesb(base_addr + fifo, buf, len);
  286. return len;
  287. }
  288. /*
  289. * s3c2410_udc_write_fifo
  290. *
  291. * return: 0 = still running, 1 = completed, negative = errno
  292. */
  293. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  294. struct s3c2410_request *req)
  295. {
  296. unsigned count;
  297. int is_last;
  298. u32 idx;
  299. int fifo_reg;
  300. u32 ep_csr;
  301. idx = ep->bEndpointAddress & 0x7F;
  302. switch (idx) {
  303. default:
  304. idx = 0;
  305. case 0:
  306. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  307. break;
  308. case 1:
  309. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  310. break;
  311. case 2:
  312. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  313. break;
  314. case 3:
  315. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  316. break;
  317. case 4:
  318. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  319. break;
  320. }
  321. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  322. /* last packet is often short (sometimes a zlp) */
  323. if (count != ep->ep.maxpacket)
  324. is_last = 1;
  325. else if (req->req.length != req->req.actual || req->req.zero)
  326. is_last = 0;
  327. else
  328. is_last = 2;
  329. /* Only ep0 debug messages are interesting */
  330. if (idx == 0)
  331. dprintk(DEBUG_NORMAL,
  332. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  333. idx, count, req->req.actual, req->req.length,
  334. is_last, req->req.zero);
  335. if (is_last) {
  336. /* The order is important. It prevents sending 2 packets
  337. * at the same time */
  338. if (idx == 0) {
  339. /* Reset signal => no need to say 'data sent' */
  340. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  341. & S3C2410_UDC_USBINT_RESET))
  342. s3c2410_udc_set_ep0_de_in(base_addr);
  343. ep->dev->ep0state=EP0_IDLE;
  344. } else {
  345. udc_write(idx, S3C2410_UDC_INDEX_REG);
  346. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  347. udc_write(idx, S3C2410_UDC_INDEX_REG);
  348. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  349. S3C2410_UDC_IN_CSR1_REG);
  350. }
  351. s3c2410_udc_done(ep, req, 0);
  352. is_last = 1;
  353. } else {
  354. if (idx == 0) {
  355. /* Reset signal => no need to say 'data sent' */
  356. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  357. & S3C2410_UDC_USBINT_RESET))
  358. s3c2410_udc_set_ep0_ipr(base_addr);
  359. } else {
  360. udc_write(idx, S3C2410_UDC_INDEX_REG);
  361. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  362. udc_write(idx, S3C2410_UDC_INDEX_REG);
  363. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  364. S3C2410_UDC_IN_CSR1_REG);
  365. }
  366. }
  367. return is_last;
  368. }
  369. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  370. struct s3c2410_request *req, unsigned avail)
  371. {
  372. unsigned len;
  373. len = min(req->req.length - req->req.actual, avail);
  374. req->req.actual += len;
  375. readsb(fifo + base_addr, buf, len);
  376. return len;
  377. }
  378. /*
  379. * return: 0 = still running, 1 = queue empty, negative = errno
  380. */
  381. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  382. struct s3c2410_request *req)
  383. {
  384. u8 *buf;
  385. u32 ep_csr;
  386. unsigned bufferspace;
  387. int is_last=1;
  388. unsigned avail;
  389. int fifo_count = 0;
  390. u32 idx;
  391. int fifo_reg;
  392. idx = ep->bEndpointAddress & 0x7F;
  393. switch (idx) {
  394. default:
  395. idx = 0;
  396. case 0:
  397. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  398. break;
  399. case 1:
  400. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  401. break;
  402. case 2:
  403. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  404. break;
  405. case 3:
  406. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  407. break;
  408. case 4:
  409. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  410. break;
  411. }
  412. if (!req->req.length)
  413. return 1;
  414. buf = req->req.buf + req->req.actual;
  415. bufferspace = req->req.length - req->req.actual;
  416. if (!bufferspace) {
  417. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  418. return -1;
  419. }
  420. udc_write(idx, S3C2410_UDC_INDEX_REG);
  421. fifo_count = s3c2410_udc_fifo_count_out();
  422. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  423. if (fifo_count > ep->ep.maxpacket)
  424. avail = ep->ep.maxpacket;
  425. else
  426. avail = fifo_count;
  427. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  428. /* checking this with ep0 is not accurate as we already
  429. * read a control request
  430. **/
  431. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  432. is_last = 1;
  433. /* overflowed this request? flush extra data */
  434. if (fifo_count != avail)
  435. req->req.status = -EOVERFLOW;
  436. } else {
  437. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  438. }
  439. udc_write(idx, S3C2410_UDC_INDEX_REG);
  440. fifo_count = s3c2410_udc_fifo_count_out();
  441. /* Only ep0 debug messages are interesting */
  442. if (idx == 0)
  443. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  444. __func__, fifo_count,is_last);
  445. if (is_last) {
  446. if (idx == 0) {
  447. s3c2410_udc_set_ep0_de_out(base_addr);
  448. ep->dev->ep0state = EP0_IDLE;
  449. } else {
  450. udc_write(idx, S3C2410_UDC_INDEX_REG);
  451. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  452. udc_write(idx, S3C2410_UDC_INDEX_REG);
  453. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  454. S3C2410_UDC_OUT_CSR1_REG);
  455. }
  456. s3c2410_udc_done(ep, req, 0);
  457. } else {
  458. if (idx == 0) {
  459. s3c2410_udc_clear_ep0_opr(base_addr);
  460. } else {
  461. udc_write(idx, S3C2410_UDC_INDEX_REG);
  462. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  463. udc_write(idx, S3C2410_UDC_INDEX_REG);
  464. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  465. S3C2410_UDC_OUT_CSR1_REG);
  466. }
  467. }
  468. return is_last;
  469. }
  470. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  471. {
  472. unsigned char *outbuf = (unsigned char*)crq;
  473. int bytes_read = 0;
  474. udc_write(0, S3C2410_UDC_INDEX_REG);
  475. bytes_read = s3c2410_udc_fifo_count_out();
  476. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  477. if (bytes_read > sizeof(struct usb_ctrlrequest))
  478. bytes_read = sizeof(struct usb_ctrlrequest);
  479. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  480. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  481. bytes_read, crq->bRequest, crq->bRequestType,
  482. crq->wValue, crq->wIndex, crq->wLength);
  483. return bytes_read;
  484. }
  485. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  486. struct usb_ctrlrequest *crq)
  487. {
  488. u16 status = 0;
  489. u8 ep_num = crq->wIndex & 0x7F;
  490. u8 is_in = crq->wIndex & USB_DIR_IN;
  491. switch (crq->bRequestType & USB_RECIP_MASK) {
  492. case USB_RECIP_INTERFACE:
  493. break;
  494. case USB_RECIP_DEVICE:
  495. status = dev->devstatus;
  496. break;
  497. case USB_RECIP_ENDPOINT:
  498. if (ep_num > 4 || crq->wLength > 2)
  499. return 1;
  500. if (ep_num == 0) {
  501. udc_write(0, S3C2410_UDC_INDEX_REG);
  502. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  503. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  504. } else {
  505. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  506. if (is_in) {
  507. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  508. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  509. } else {
  510. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  511. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  512. }
  513. }
  514. status = status ? 1 : 0;
  515. break;
  516. default:
  517. return 1;
  518. }
  519. /* Seems to be needed to get it working. ouch :( */
  520. udelay(5);
  521. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  522. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  523. s3c2410_udc_set_ep0_de_in(base_addr);
  524. return 0;
  525. }
  526. /*------------------------- usb state machine -------------------------------*/
  527. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  528. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  529. struct s3c2410_ep *ep,
  530. struct usb_ctrlrequest *crq,
  531. u32 ep0csr)
  532. {
  533. int len, ret, tmp;
  534. /* start control request? */
  535. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  536. return;
  537. s3c2410_udc_nuke(dev, ep, -EPROTO);
  538. len = s3c2410_udc_read_fifo_crq(crq);
  539. if (len != sizeof(*crq)) {
  540. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  541. " wanted %d bytes got %d. Stalling out...\n",
  542. sizeof(*crq), len);
  543. s3c2410_udc_set_ep0_ss(base_addr);
  544. return;
  545. }
  546. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  547. crq->bRequest, crq->bRequestType, crq->wLength);
  548. /* cope with automagic for some standard requests. */
  549. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  550. == USB_TYPE_STANDARD;
  551. dev->req_config = 0;
  552. dev->req_pending = 1;
  553. switch (crq->bRequest) {
  554. case USB_REQ_SET_CONFIGURATION:
  555. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  556. if (crq->bRequestType == USB_RECIP_DEVICE) {
  557. dev->req_config = 1;
  558. s3c2410_udc_set_ep0_de_out(base_addr);
  559. }
  560. break;
  561. case USB_REQ_SET_INTERFACE:
  562. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  563. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  564. dev->req_config = 1;
  565. s3c2410_udc_set_ep0_de_out(base_addr);
  566. }
  567. break;
  568. case USB_REQ_SET_ADDRESS:
  569. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  570. if (crq->bRequestType == USB_RECIP_DEVICE) {
  571. tmp = crq->wValue & 0x7F;
  572. dev->address = tmp;
  573. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  574. S3C2410_UDC_FUNC_ADDR_REG);
  575. s3c2410_udc_set_ep0_de_out(base_addr);
  576. return;
  577. }
  578. break;
  579. case USB_REQ_GET_STATUS:
  580. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  581. s3c2410_udc_clear_ep0_opr(base_addr);
  582. if (dev->req_std) {
  583. if (!s3c2410_udc_get_status(dev, crq)) {
  584. return;
  585. }
  586. }
  587. break;
  588. case USB_REQ_CLEAR_FEATURE:
  589. s3c2410_udc_clear_ep0_opr(base_addr);
  590. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  591. break;
  592. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  593. break;
  594. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  595. s3c2410_udc_set_ep0_de_out(base_addr);
  596. return;
  597. case USB_REQ_SET_FEATURE:
  598. s3c2410_udc_clear_ep0_opr(base_addr);
  599. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  600. break;
  601. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  602. break;
  603. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  604. s3c2410_udc_set_ep0_de_out(base_addr);
  605. return;
  606. default:
  607. s3c2410_udc_clear_ep0_opr(base_addr);
  608. break;
  609. }
  610. if (crq->bRequestType & USB_DIR_IN)
  611. dev->ep0state = EP0_IN_DATA_PHASE;
  612. else
  613. dev->ep0state = EP0_OUT_DATA_PHASE;
  614. ret = dev->driver->setup(&dev->gadget, crq);
  615. if (ret < 0) {
  616. if (dev->req_config) {
  617. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  618. crq->bRequest, ret);
  619. return;
  620. }
  621. if (ret == -EOPNOTSUPP)
  622. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  623. else
  624. dprintk(DEBUG_NORMAL,
  625. "dev->driver->setup failed. (%d)\n", ret);
  626. udelay(5);
  627. s3c2410_udc_set_ep0_ss(base_addr);
  628. s3c2410_udc_set_ep0_de_out(base_addr);
  629. dev->ep0state = EP0_IDLE;
  630. /* deferred i/o == no response yet */
  631. } else if (dev->req_pending) {
  632. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  633. dev->req_pending=0;
  634. }
  635. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  636. }
  637. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  638. {
  639. u32 ep0csr;
  640. struct s3c2410_ep *ep = &dev->ep[0];
  641. struct s3c2410_request *req;
  642. struct usb_ctrlrequest crq;
  643. if (list_empty(&ep->queue))
  644. req = NULL;
  645. else
  646. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  647. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  648. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  649. udc_write(0, S3C2410_UDC_INDEX_REG);
  650. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  651. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  652. ep0csr, ep0states[dev->ep0state]);
  653. /* clear stall status */
  654. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  655. s3c2410_udc_nuke(dev, ep, -EPIPE);
  656. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  657. s3c2410_udc_clear_ep0_sst(base_addr);
  658. dev->ep0state = EP0_IDLE;
  659. return;
  660. }
  661. /* clear setup end */
  662. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  663. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  664. s3c2410_udc_nuke(dev, ep, 0);
  665. s3c2410_udc_clear_ep0_se(base_addr);
  666. dev->ep0state = EP0_IDLE;
  667. }
  668. switch (dev->ep0state) {
  669. case EP0_IDLE:
  670. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  671. break;
  672. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  673. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  674. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  675. s3c2410_udc_write_fifo(ep, req);
  676. }
  677. break;
  678. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  679. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  680. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  681. s3c2410_udc_read_fifo(ep,req);
  682. }
  683. break;
  684. case EP0_END_XFER:
  685. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  686. dev->ep0state = EP0_IDLE;
  687. break;
  688. case EP0_STALL:
  689. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  690. dev->ep0state = EP0_IDLE;
  691. break;
  692. }
  693. }
  694. /*
  695. * handle_ep - Manage I/O endpoints
  696. */
  697. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  698. {
  699. struct s3c2410_request *req;
  700. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  701. u32 ep_csr1;
  702. u32 idx;
  703. if (likely (!list_empty(&ep->queue)))
  704. req = list_entry(ep->queue.next,
  705. struct s3c2410_request, queue);
  706. else
  707. req = NULL;
  708. idx = ep->bEndpointAddress & 0x7F;
  709. if (is_in) {
  710. udc_write(idx, S3C2410_UDC_INDEX_REG);
  711. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  712. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  713. idx, ep_csr1, req ? 1 : 0);
  714. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  715. dprintk(DEBUG_VERBOSE, "st\n");
  716. udc_write(idx, S3C2410_UDC_INDEX_REG);
  717. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  718. S3C2410_UDC_IN_CSR1_REG);
  719. return;
  720. }
  721. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  722. s3c2410_udc_write_fifo(ep,req);
  723. }
  724. } else {
  725. udc_write(idx, S3C2410_UDC_INDEX_REG);
  726. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  727. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  728. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  729. udc_write(idx, S3C2410_UDC_INDEX_REG);
  730. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  731. S3C2410_UDC_OUT_CSR1_REG);
  732. return;
  733. }
  734. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  735. s3c2410_udc_read_fifo(ep,req);
  736. }
  737. }
  738. }
  739. #include <mach/regs-irq.h>
  740. /*
  741. * s3c2410_udc_irq - interrupt handler
  742. */
  743. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  744. {
  745. struct s3c2410_udc *dev = _dev;
  746. int usb_status;
  747. int usbd_status;
  748. int pwr_reg;
  749. int ep0csr;
  750. int i;
  751. u32 idx;
  752. unsigned long flags;
  753. spin_lock_irqsave(&dev->lock, flags);
  754. /* Driver connected ? */
  755. if (!dev->driver) {
  756. /* Clear interrupts */
  757. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  758. S3C2410_UDC_USB_INT_REG);
  759. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  760. S3C2410_UDC_EP_INT_REG);
  761. }
  762. /* Save index */
  763. idx = udc_read(S3C2410_UDC_INDEX_REG);
  764. /* Read status registers */
  765. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  766. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  767. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  768. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  769. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  770. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  771. usb_status, usbd_status, pwr_reg, ep0csr);
  772. /*
  773. * Now, handle interrupts. There's two types :
  774. * - Reset, Resume, Suspend coming -> usb_int_reg
  775. * - EP -> ep_int_reg
  776. */
  777. /* RESET */
  778. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  779. /* two kind of reset :
  780. * - reset start -> pwr reg = 8
  781. * - reset end -> pwr reg = 0
  782. **/
  783. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  784. ep0csr, pwr_reg);
  785. dev->gadget.speed = USB_SPEED_UNKNOWN;
  786. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  787. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  788. S3C2410_UDC_MAXP_REG);
  789. dev->address = 0;
  790. dev->ep0state = EP0_IDLE;
  791. dev->gadget.speed = USB_SPEED_FULL;
  792. /* clear interrupt */
  793. udc_write(S3C2410_UDC_USBINT_RESET,
  794. S3C2410_UDC_USB_INT_REG);
  795. udc_write(idx, S3C2410_UDC_INDEX_REG);
  796. spin_unlock_irqrestore(&dev->lock, flags);
  797. return IRQ_HANDLED;
  798. }
  799. /* RESUME */
  800. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  801. dprintk(DEBUG_NORMAL, "USB resume\n");
  802. /* clear interrupt */
  803. udc_write(S3C2410_UDC_USBINT_RESUME,
  804. S3C2410_UDC_USB_INT_REG);
  805. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  806. && dev->driver
  807. && dev->driver->resume)
  808. dev->driver->resume(&dev->gadget);
  809. }
  810. /* SUSPEND */
  811. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  812. dprintk(DEBUG_NORMAL, "USB suspend\n");
  813. /* clear interrupt */
  814. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  815. S3C2410_UDC_USB_INT_REG);
  816. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  817. && dev->driver
  818. && dev->driver->suspend)
  819. dev->driver->suspend(&dev->gadget);
  820. dev->ep0state = EP0_IDLE;
  821. }
  822. /* EP */
  823. /* control traffic */
  824. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  825. * generate an interrupt
  826. */
  827. if (usbd_status & S3C2410_UDC_INT_EP0) {
  828. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  829. /* Clear the interrupt bit by setting it to 1 */
  830. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  831. s3c2410_udc_handle_ep0(dev);
  832. }
  833. /* endpoint data transfers */
  834. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  835. u32 tmp = 1 << i;
  836. if (usbd_status & tmp) {
  837. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  838. /* Clear the interrupt bit by setting it to 1 */
  839. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  840. s3c2410_udc_handle_ep(&dev->ep[i]);
  841. }
  842. }
  843. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  844. /* Restore old index */
  845. udc_write(idx, S3C2410_UDC_INDEX_REG);
  846. spin_unlock_irqrestore(&dev->lock, flags);
  847. return IRQ_HANDLED;
  848. }
  849. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  850. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  851. {
  852. return container_of(ep, struct s3c2410_ep, ep);
  853. }
  854. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  855. {
  856. return container_of(gadget, struct s3c2410_udc, gadget);
  857. }
  858. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  859. {
  860. return container_of(req, struct s3c2410_request, req);
  861. }
  862. /*
  863. * s3c2410_udc_ep_enable
  864. */
  865. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  866. const struct usb_endpoint_descriptor *desc)
  867. {
  868. struct s3c2410_udc *dev;
  869. struct s3c2410_ep *ep;
  870. u32 max, tmp;
  871. unsigned long flags;
  872. u32 csr1,csr2;
  873. u32 int_en_reg;
  874. ep = to_s3c2410_ep(_ep);
  875. if (!_ep || !desc || ep->desc
  876. || _ep->name == ep0name
  877. || desc->bDescriptorType != USB_DT_ENDPOINT)
  878. return -EINVAL;
  879. dev = ep->dev;
  880. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  881. return -ESHUTDOWN;
  882. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  883. local_irq_save (flags);
  884. _ep->maxpacket = max & 0x7ff;
  885. ep->desc = desc;
  886. ep->halted = 0;
  887. ep->bEndpointAddress = desc->bEndpointAddress;
  888. /* set max packet */
  889. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  890. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  891. /* set type, direction, address; reset fifo counters */
  892. if (desc->bEndpointAddress & USB_DIR_IN) {
  893. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  894. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  895. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  896. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  897. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  898. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  899. } else {
  900. /* don't flush in fifo or it will cause endpoint interrupt */
  901. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  902. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  903. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  904. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  905. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  906. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  907. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  908. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  909. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  910. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  911. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  912. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  913. }
  914. /* enable irqs */
  915. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  916. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  917. /* print some debug message */
  918. tmp = desc->bEndpointAddress;
  919. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  920. _ep->name,ep->num, tmp,
  921. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  922. local_irq_restore (flags);
  923. s3c2410_udc_set_halt(_ep, 0);
  924. return 0;
  925. }
  926. /*
  927. * s3c2410_udc_ep_disable
  928. */
  929. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  930. {
  931. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  932. unsigned long flags;
  933. u32 int_en_reg;
  934. if (!_ep || !ep->desc) {
  935. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  936. _ep ? ep->ep.name : NULL);
  937. return -EINVAL;
  938. }
  939. local_irq_save(flags);
  940. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  941. ep->desc = NULL;
  942. ep->halted = 1;
  943. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  944. /* disable irqs */
  945. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  946. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  947. local_irq_restore(flags);
  948. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  949. return 0;
  950. }
  951. /*
  952. * s3c2410_udc_alloc_request
  953. */
  954. static struct usb_request *
  955. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  956. {
  957. struct s3c2410_request *req;
  958. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  959. if (!_ep)
  960. return NULL;
  961. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  962. if (!req)
  963. return NULL;
  964. INIT_LIST_HEAD (&req->queue);
  965. return &req->req;
  966. }
  967. /*
  968. * s3c2410_udc_free_request
  969. */
  970. static void
  971. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  972. {
  973. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  974. struct s3c2410_request *req = to_s3c2410_req(_req);
  975. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  976. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  977. return;
  978. WARN_ON (!list_empty (&req->queue));
  979. kfree(req);
  980. }
  981. /*
  982. * s3c2410_udc_queue
  983. */
  984. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  985. gfp_t gfp_flags)
  986. {
  987. struct s3c2410_request *req = to_s3c2410_req(_req);
  988. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  989. struct s3c2410_udc *dev;
  990. u32 ep_csr = 0;
  991. int fifo_count = 0;
  992. unsigned long flags;
  993. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  994. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  995. return -EINVAL;
  996. }
  997. dev = ep->dev;
  998. if (unlikely (!dev->driver
  999. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  1000. return -ESHUTDOWN;
  1001. }
  1002. local_irq_save (flags);
  1003. if (unlikely(!_req || !_req->complete
  1004. || !_req->buf || !list_empty(&req->queue))) {
  1005. if (!_req)
  1006. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1007. else {
  1008. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1009. __func__, !_req->complete,!_req->buf,
  1010. !list_empty(&req->queue));
  1011. }
  1012. local_irq_restore(flags);
  1013. return -EINVAL;
  1014. }
  1015. _req->status = -EINPROGRESS;
  1016. _req->actual = 0;
  1017. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1018. __func__, ep->bEndpointAddress, _req->length);
  1019. if (ep->bEndpointAddress) {
  1020. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1021. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1022. ? S3C2410_UDC_IN_CSR1_REG
  1023. : S3C2410_UDC_OUT_CSR1_REG);
  1024. fifo_count = s3c2410_udc_fifo_count_out();
  1025. } else {
  1026. udc_write(0, S3C2410_UDC_INDEX_REG);
  1027. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1028. fifo_count = s3c2410_udc_fifo_count_out();
  1029. }
  1030. /* kickstart this i/o queue? */
  1031. if (list_empty(&ep->queue) && !ep->halted) {
  1032. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1033. switch (dev->ep0state) {
  1034. case EP0_IN_DATA_PHASE:
  1035. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1036. && s3c2410_udc_write_fifo(ep,
  1037. req)) {
  1038. dev->ep0state = EP0_IDLE;
  1039. req = NULL;
  1040. }
  1041. break;
  1042. case EP0_OUT_DATA_PHASE:
  1043. if ((!_req->length)
  1044. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1045. && s3c2410_udc_read_fifo(ep,
  1046. req))) {
  1047. dev->ep0state = EP0_IDLE;
  1048. req = NULL;
  1049. }
  1050. break;
  1051. default:
  1052. local_irq_restore(flags);
  1053. return -EL2HLT;
  1054. }
  1055. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1056. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1057. && s3c2410_udc_write_fifo(ep, req)) {
  1058. req = NULL;
  1059. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1060. && fifo_count
  1061. && s3c2410_udc_read_fifo(ep, req)) {
  1062. req = NULL;
  1063. }
  1064. }
  1065. /* pio or dma irq handler advances the queue. */
  1066. if (likely (req != 0))
  1067. list_add_tail(&req->queue, &ep->queue);
  1068. local_irq_restore(flags);
  1069. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1070. return 0;
  1071. }
  1072. /*
  1073. * s3c2410_udc_dequeue
  1074. */
  1075. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1076. {
  1077. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1078. struct s3c2410_udc *udc;
  1079. int retval = -EINVAL;
  1080. unsigned long flags;
  1081. struct s3c2410_request *req = NULL;
  1082. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1083. if (!the_controller->driver)
  1084. return -ESHUTDOWN;
  1085. if (!_ep || !_req)
  1086. return retval;
  1087. udc = to_s3c2410_udc(ep->gadget);
  1088. local_irq_save (flags);
  1089. list_for_each_entry (req, &ep->queue, queue) {
  1090. if (&req->req == _req) {
  1091. list_del_init (&req->queue);
  1092. _req->status = -ECONNRESET;
  1093. retval = 0;
  1094. break;
  1095. }
  1096. }
  1097. if (retval == 0) {
  1098. dprintk(DEBUG_VERBOSE,
  1099. "dequeued req %p from %s, len %d buf %p\n",
  1100. req, _ep->name, _req->length, _req->buf);
  1101. s3c2410_udc_done(ep, req, -ECONNRESET);
  1102. }
  1103. local_irq_restore (flags);
  1104. return retval;
  1105. }
  1106. /*
  1107. * s3c2410_udc_set_halt
  1108. */
  1109. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1110. {
  1111. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1112. u32 ep_csr = 0;
  1113. unsigned long flags;
  1114. u32 idx;
  1115. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1116. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1117. return -EINVAL;
  1118. }
  1119. local_irq_save (flags);
  1120. idx = ep->bEndpointAddress & 0x7F;
  1121. if (idx == 0) {
  1122. s3c2410_udc_set_ep0_ss(base_addr);
  1123. s3c2410_udc_set_ep0_de_out(base_addr);
  1124. } else {
  1125. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1126. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1127. ? S3C2410_UDC_IN_CSR1_REG
  1128. : S3C2410_UDC_OUT_CSR1_REG);
  1129. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1130. if (value)
  1131. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1132. S3C2410_UDC_IN_CSR1_REG);
  1133. else {
  1134. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1135. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1136. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1137. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1138. }
  1139. } else {
  1140. if (value)
  1141. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1142. S3C2410_UDC_OUT_CSR1_REG);
  1143. else {
  1144. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1145. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1146. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1147. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1148. }
  1149. }
  1150. }
  1151. ep->halted = value ? 1 : 0;
  1152. local_irq_restore (flags);
  1153. return 0;
  1154. }
  1155. static const struct usb_ep_ops s3c2410_ep_ops = {
  1156. .enable = s3c2410_udc_ep_enable,
  1157. .disable = s3c2410_udc_ep_disable,
  1158. .alloc_request = s3c2410_udc_alloc_request,
  1159. .free_request = s3c2410_udc_free_request,
  1160. .queue = s3c2410_udc_queue,
  1161. .dequeue = s3c2410_udc_dequeue,
  1162. .set_halt = s3c2410_udc_set_halt,
  1163. };
  1164. /*------------------------- usb_gadget_ops ----------------------------------*/
  1165. /*
  1166. * s3c2410_udc_get_frame
  1167. */
  1168. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1169. {
  1170. int tmp;
  1171. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1172. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1173. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1174. return tmp;
  1175. }
  1176. /*
  1177. * s3c2410_udc_wakeup
  1178. */
  1179. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1180. {
  1181. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1182. return 0;
  1183. }
  1184. /*
  1185. * s3c2410_udc_set_selfpowered
  1186. */
  1187. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1188. {
  1189. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1190. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1191. if (value)
  1192. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1193. else
  1194. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1195. return 0;
  1196. }
  1197. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1198. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1199. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1200. {
  1201. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1202. if (udc_info && udc_info->udc_command) {
  1203. if (is_on)
  1204. s3c2410_udc_enable(udc);
  1205. else {
  1206. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1207. if (udc->driver && udc->driver->disconnect)
  1208. udc->driver->disconnect(&udc->gadget);
  1209. }
  1210. s3c2410_udc_disable(udc);
  1211. }
  1212. }
  1213. else
  1214. return -EOPNOTSUPP;
  1215. return 0;
  1216. }
  1217. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1218. {
  1219. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1220. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1221. udc->vbus = (is_active != 0);
  1222. s3c2410_udc_set_pullup(udc, is_active);
  1223. return 0;
  1224. }
  1225. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1226. {
  1227. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1228. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1229. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1230. return 0;
  1231. }
  1232. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1233. {
  1234. struct s3c2410_udc *dev = _dev;
  1235. unsigned int value;
  1236. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1237. /* some cpus cannot read from an line configured to IRQ! */
  1238. s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_INPUT);
  1239. value = s3c2410_gpio_getpin(udc_info->vbus_pin);
  1240. s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_SFN2);
  1241. if (udc_info->vbus_pin_inverted)
  1242. value = !value;
  1243. if (value != dev->vbus)
  1244. s3c2410_udc_vbus_session(&dev->gadget, value);
  1245. return IRQ_HANDLED;
  1246. }
  1247. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1248. {
  1249. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1250. if (udc_info && udc_info->vbus_draw) {
  1251. udc_info->vbus_draw(ma);
  1252. return 0;
  1253. }
  1254. return -ENOTSUPP;
  1255. }
  1256. static const struct usb_gadget_ops s3c2410_ops = {
  1257. .get_frame = s3c2410_udc_get_frame,
  1258. .wakeup = s3c2410_udc_wakeup,
  1259. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1260. .pullup = s3c2410_udc_pullup,
  1261. .vbus_session = s3c2410_udc_vbus_session,
  1262. .vbus_draw = s3c2410_vbus_draw,
  1263. };
  1264. /*------------------------- gadget driver handling---------------------------*/
  1265. /*
  1266. * s3c2410_udc_disable
  1267. */
  1268. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1269. {
  1270. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1271. /* Disable all interrupts */
  1272. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1273. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1274. /* Clear the interrupt registers */
  1275. udc_write(S3C2410_UDC_USBINT_RESET
  1276. | S3C2410_UDC_USBINT_RESUME
  1277. | S3C2410_UDC_USBINT_SUSPEND,
  1278. S3C2410_UDC_USB_INT_REG);
  1279. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1280. /* Good bye, cruel world */
  1281. if (udc_info && udc_info->udc_command)
  1282. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1283. /* Set speed to unknown */
  1284. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1285. }
  1286. /*
  1287. * s3c2410_udc_reinit
  1288. */
  1289. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1290. {
  1291. u32 i;
  1292. /* device/ep0 records init */
  1293. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1294. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1295. dev->ep0state = EP0_IDLE;
  1296. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1297. struct s3c2410_ep *ep = &dev->ep[i];
  1298. if (i != 0)
  1299. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1300. ep->dev = dev;
  1301. ep->desc = NULL;
  1302. ep->halted = 0;
  1303. INIT_LIST_HEAD (&ep->queue);
  1304. }
  1305. }
  1306. /*
  1307. * s3c2410_udc_enable
  1308. */
  1309. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1310. {
  1311. int i;
  1312. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1313. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1314. dev->gadget.speed = USB_SPEED_FULL;
  1315. /* Set MAXP for all endpoints */
  1316. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1317. udc_write(i, S3C2410_UDC_INDEX_REG);
  1318. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1319. S3C2410_UDC_MAXP_REG);
  1320. }
  1321. /* Set default power state */
  1322. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1323. /* Enable reset and suspend interrupt interrupts */
  1324. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1325. S3C2410_UDC_USB_INT_EN_REG);
  1326. /* Enable ep0 interrupt */
  1327. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1328. /* time to say "hello, world" */
  1329. if (udc_info && udc_info->udc_command)
  1330. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1331. }
  1332. /*
  1333. * usb_gadget_register_driver
  1334. */
  1335. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1336. {
  1337. struct s3c2410_udc *udc = the_controller;
  1338. int retval;
  1339. dprintk(DEBUG_NORMAL, "usb_gadget_register_driver() '%s'\n",
  1340. driver->driver.name);
  1341. /* Sanity checks */
  1342. if (!udc)
  1343. return -ENODEV;
  1344. if (udc->driver)
  1345. return -EBUSY;
  1346. if (!driver->bind || !driver->setup
  1347. || driver->speed != USB_SPEED_FULL) {
  1348. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1349. driver->bind, driver->setup, driver->speed);
  1350. return -EINVAL;
  1351. }
  1352. #if defined(MODULE)
  1353. if (!driver->unbind) {
  1354. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1355. return -EINVAL;
  1356. }
  1357. #endif
  1358. /* Hook the driver */
  1359. udc->driver = driver;
  1360. udc->gadget.dev.driver = &driver->driver;
  1361. /* Bind the driver */
  1362. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1363. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1364. goto register_error;
  1365. }
  1366. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1367. driver->driver.name);
  1368. if ((retval = driver->bind (&udc->gadget)) != 0) {
  1369. device_del(&udc->gadget.dev);
  1370. goto register_error;
  1371. }
  1372. /* Enable udc */
  1373. s3c2410_udc_enable(udc);
  1374. return 0;
  1375. register_error:
  1376. udc->driver = NULL;
  1377. udc->gadget.dev.driver = NULL;
  1378. return retval;
  1379. }
  1380. /*
  1381. * usb_gadget_unregister_driver
  1382. */
  1383. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1384. {
  1385. struct s3c2410_udc *udc = the_controller;
  1386. if (!udc)
  1387. return -ENODEV;
  1388. if (!driver || driver != udc->driver || !driver->unbind)
  1389. return -EINVAL;
  1390. dprintk(DEBUG_NORMAL,"usb_gadget_register_driver() '%s'\n",
  1391. driver->driver.name);
  1392. if (driver->disconnect)
  1393. driver->disconnect(&udc->gadget);
  1394. device_del(&udc->gadget.dev);
  1395. udc->driver = NULL;
  1396. /* Disable udc */
  1397. s3c2410_udc_disable(udc);
  1398. return 0;
  1399. }
  1400. /*---------------------------------------------------------------------------*/
  1401. static struct s3c2410_udc memory = {
  1402. .gadget = {
  1403. .ops = &s3c2410_ops,
  1404. .ep0 = &memory.ep[0].ep,
  1405. .name = gadget_name,
  1406. .dev = {
  1407. .bus_id = "gadget",
  1408. },
  1409. },
  1410. /* control endpoint */
  1411. .ep[0] = {
  1412. .num = 0,
  1413. .ep = {
  1414. .name = ep0name,
  1415. .ops = &s3c2410_ep_ops,
  1416. .maxpacket = EP0_FIFO_SIZE,
  1417. },
  1418. .dev = &memory,
  1419. },
  1420. /* first group of endpoints */
  1421. .ep[1] = {
  1422. .num = 1,
  1423. .ep = {
  1424. .name = "ep1-bulk",
  1425. .ops = &s3c2410_ep_ops,
  1426. .maxpacket = EP_FIFO_SIZE,
  1427. },
  1428. .dev = &memory,
  1429. .fifo_size = EP_FIFO_SIZE,
  1430. .bEndpointAddress = 1,
  1431. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1432. },
  1433. .ep[2] = {
  1434. .num = 2,
  1435. .ep = {
  1436. .name = "ep2-bulk",
  1437. .ops = &s3c2410_ep_ops,
  1438. .maxpacket = EP_FIFO_SIZE,
  1439. },
  1440. .dev = &memory,
  1441. .fifo_size = EP_FIFO_SIZE,
  1442. .bEndpointAddress = 2,
  1443. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1444. },
  1445. .ep[3] = {
  1446. .num = 3,
  1447. .ep = {
  1448. .name = "ep3-bulk",
  1449. .ops = &s3c2410_ep_ops,
  1450. .maxpacket = EP_FIFO_SIZE,
  1451. },
  1452. .dev = &memory,
  1453. .fifo_size = EP_FIFO_SIZE,
  1454. .bEndpointAddress = 3,
  1455. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1456. },
  1457. .ep[4] = {
  1458. .num = 4,
  1459. .ep = {
  1460. .name = "ep4-bulk",
  1461. .ops = &s3c2410_ep_ops,
  1462. .maxpacket = EP_FIFO_SIZE,
  1463. },
  1464. .dev = &memory,
  1465. .fifo_size = EP_FIFO_SIZE,
  1466. .bEndpointAddress = 4,
  1467. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1468. }
  1469. };
  1470. /*
  1471. * probe - binds to the platform device
  1472. */
  1473. static int s3c2410_udc_probe(struct platform_device *pdev)
  1474. {
  1475. struct s3c2410_udc *udc = &memory;
  1476. struct device *dev = &pdev->dev;
  1477. int retval;
  1478. unsigned int irq;
  1479. dev_dbg(dev, "%s()\n", __func__);
  1480. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1481. if (IS_ERR(usb_bus_clock)) {
  1482. dev_err(dev, "failed to get usb bus clock source\n");
  1483. return PTR_ERR(usb_bus_clock);
  1484. }
  1485. clk_enable(usb_bus_clock);
  1486. udc_clock = clk_get(NULL, "usb-device");
  1487. if (IS_ERR(udc_clock)) {
  1488. dev_err(dev, "failed to get udc clock source\n");
  1489. return PTR_ERR(udc_clock);
  1490. }
  1491. clk_enable(udc_clock);
  1492. mdelay(10);
  1493. dev_dbg(dev, "got and enabled clocks\n");
  1494. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1495. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1496. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1497. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1498. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1499. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1500. }
  1501. spin_lock_init (&udc->lock);
  1502. udc_info = pdev->dev.platform_data;
  1503. rsrc_start = S3C2410_PA_USBDEV;
  1504. rsrc_len = S3C24XX_SZ_USBDEV;
  1505. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1506. return -EBUSY;
  1507. base_addr = ioremap(rsrc_start, rsrc_len);
  1508. if (!base_addr) {
  1509. retval = -ENOMEM;
  1510. goto err_mem;
  1511. }
  1512. device_initialize(&udc->gadget.dev);
  1513. udc->gadget.dev.parent = &pdev->dev;
  1514. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1515. the_controller = udc;
  1516. platform_set_drvdata(pdev, udc);
  1517. s3c2410_udc_disable(udc);
  1518. s3c2410_udc_reinit(udc);
  1519. /* irq setup after old hardware state is cleaned up */
  1520. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1521. IRQF_DISABLED, gadget_name, udc);
  1522. if (retval != 0) {
  1523. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1524. retval = -EBUSY;
  1525. goto err_map;
  1526. }
  1527. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1528. if (udc_info && udc_info->vbus_pin > 0) {
  1529. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1530. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1531. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1532. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1533. gadget_name, udc);
  1534. if (retval != 0) {
  1535. dev_err(dev, "can't get vbus irq %i, err %d\n",
  1536. irq, retval);
  1537. retval = -EBUSY;
  1538. goto err_int;
  1539. }
  1540. dev_dbg(dev, "got irq %i\n", irq);
  1541. } else {
  1542. udc->vbus = 1;
  1543. }
  1544. if (s3c2410_udc_debugfs_root) {
  1545. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1546. s3c2410_udc_debugfs_root,
  1547. udc, &s3c2410_udc_debugfs_fops);
  1548. if (IS_ERR(udc->regs_info)) {
  1549. dev_warn(dev, "debugfs file creation failed %ld\n",
  1550. PTR_ERR(udc->regs_info));
  1551. udc->regs_info = NULL;
  1552. }
  1553. }
  1554. dev_dbg(dev, "probe ok\n");
  1555. return 0;
  1556. err_int:
  1557. free_irq(IRQ_USBD, udc);
  1558. err_map:
  1559. iounmap(base_addr);
  1560. err_mem:
  1561. release_mem_region(rsrc_start, rsrc_len);
  1562. return retval;
  1563. }
  1564. /*
  1565. * s3c2410_udc_remove
  1566. */
  1567. static int s3c2410_udc_remove(struct platform_device *pdev)
  1568. {
  1569. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1570. unsigned int irq;
  1571. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1572. if (udc->driver)
  1573. return -EBUSY;
  1574. debugfs_remove(udc->regs_info);
  1575. if (udc_info && udc_info->vbus_pin > 0) {
  1576. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1577. free_irq(irq, udc);
  1578. }
  1579. free_irq(IRQ_USBD, udc);
  1580. iounmap(base_addr);
  1581. release_mem_region(rsrc_start, rsrc_len);
  1582. platform_set_drvdata(pdev, NULL);
  1583. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1584. clk_disable(udc_clock);
  1585. clk_put(udc_clock);
  1586. udc_clock = NULL;
  1587. }
  1588. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1589. clk_disable(usb_bus_clock);
  1590. clk_put(usb_bus_clock);
  1591. usb_bus_clock = NULL;
  1592. }
  1593. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1594. return 0;
  1595. }
  1596. #ifdef CONFIG_PM
  1597. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1598. {
  1599. if (udc_info && udc_info->udc_command)
  1600. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1601. return 0;
  1602. }
  1603. static int s3c2410_udc_resume(struct platform_device *pdev)
  1604. {
  1605. if (udc_info && udc_info->udc_command)
  1606. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1607. return 0;
  1608. }
  1609. #else
  1610. #define s3c2410_udc_suspend NULL
  1611. #define s3c2410_udc_resume NULL
  1612. #endif
  1613. static struct platform_driver udc_driver_2410 = {
  1614. .driver = {
  1615. .name = "s3c2410-usbgadget",
  1616. .owner = THIS_MODULE,
  1617. },
  1618. .probe = s3c2410_udc_probe,
  1619. .remove = s3c2410_udc_remove,
  1620. .suspend = s3c2410_udc_suspend,
  1621. .resume = s3c2410_udc_resume,
  1622. };
  1623. static struct platform_driver udc_driver_2440 = {
  1624. .driver = {
  1625. .name = "s3c2440-usbgadget",
  1626. .owner = THIS_MODULE,
  1627. },
  1628. .probe = s3c2410_udc_probe,
  1629. .remove = s3c2410_udc_remove,
  1630. .suspend = s3c2410_udc_suspend,
  1631. .resume = s3c2410_udc_resume,
  1632. };
  1633. static int __init udc_init(void)
  1634. {
  1635. int retval;
  1636. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1637. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1638. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1639. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1640. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1641. s3c2410_udc_debugfs_root = NULL;
  1642. }
  1643. retval = platform_driver_register(&udc_driver_2410);
  1644. if (retval)
  1645. goto err;
  1646. retval = platform_driver_register(&udc_driver_2440);
  1647. if (retval)
  1648. goto err;
  1649. return 0;
  1650. err:
  1651. debugfs_remove(s3c2410_udc_debugfs_root);
  1652. return retval;
  1653. }
  1654. static void __exit udc_exit(void)
  1655. {
  1656. platform_driver_unregister(&udc_driver_2410);
  1657. platform_driver_unregister(&udc_driver_2440);
  1658. debugfs_remove(s3c2410_udc_debugfs_root);
  1659. }
  1660. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1661. EXPORT_SYMBOL(usb_gadget_register_driver);
  1662. module_init(udc_init);
  1663. module_exit(udc_exit);
  1664. MODULE_AUTHOR(DRIVER_AUTHOR);
  1665. MODULE_DESCRIPTION(DRIVER_DESC);
  1666. MODULE_VERSION(DRIVER_VERSION);
  1667. MODULE_LICENSE("GPL");
  1668. MODULE_ALIAS("platform:s3c2410-usbgadget");
  1669. MODULE_ALIAS("platform:s3c2440-usbgadget");