armada-370-xp.dtsi 2.9 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. * Ben Dooks <ben.dooks@codethink.co.uk>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * This file contains the definitions that are common to the Armada
  16. * 370 and Armada XP SoC.
  17. */
  18. /include/ "skeleton.dtsi"
  19. / {
  20. model = "Marvell Armada 370 and XP SoC";
  21. compatible = "marvell,armada-370-xp";
  22. cpus {
  23. cpu@0 {
  24. compatible = "marvell,sheeva-v7";
  25. };
  26. };
  27. mpic: interrupt-controller@d0020000 {
  28. compatible = "marvell,mpic";
  29. #interrupt-cells = <1>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. interrupt-controller;
  33. };
  34. coherency-fabric@d0020200 {
  35. compatible = "marvell,coherency-fabric";
  36. reg = <0xd0020200 0xb0>;
  37. };
  38. soc {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. compatible = "simple-bus";
  42. interrupt-parent = <&mpic>;
  43. ranges;
  44. serial@d0012000 {
  45. compatible = "ns16550";
  46. reg = <0xd0012000 0x100>;
  47. reg-shift = <2>;
  48. interrupts = <41>;
  49. status = "disabled";
  50. };
  51. serial@d0012100 {
  52. compatible = "ns16550";
  53. reg = <0xd0012100 0x100>;
  54. reg-shift = <2>;
  55. interrupts = <42>;
  56. status = "disabled";
  57. };
  58. timer@d0020300 {
  59. compatible = "marvell,armada-370-xp-timer";
  60. reg = <0xd0020300 0x30>;
  61. interrupts = <37>, <38>, <39>, <40>;
  62. clocks = <&coreclk 2>;
  63. };
  64. addr-decoding@d0020000 {
  65. compatible = "marvell,armada-addr-decoding-controller";
  66. reg = <0xd0020000 0x258>;
  67. };
  68. sata@d00a0000 {
  69. compatible = "marvell,orion-sata";
  70. reg = <0xd00a0000 0x2400>;
  71. interrupts = <55>;
  72. clocks = <&gateclk 15>, <&gateclk 30>;
  73. clock-names = "0", "1";
  74. status = "disabled";
  75. };
  76. mdio {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. compatible = "marvell,orion-mdio";
  80. reg = <0xd0072004 0x4>;
  81. };
  82. ethernet@d0070000 {
  83. compatible = "marvell,armada-370-neta";
  84. reg = <0xd0070000 0x2500>;
  85. interrupts = <8>;
  86. clocks = <&gateclk 4>;
  87. status = "disabled";
  88. };
  89. ethernet@d0074000 {
  90. compatible = "marvell,armada-370-neta";
  91. reg = <0xd0074000 0x2500>;
  92. interrupts = <10>;
  93. clocks = <&gateclk 3>;
  94. status = "disabled";
  95. };
  96. i2c0: i2c@d0011000 {
  97. compatible = "marvell,mv64xxx-i2c";
  98. reg = <0xd0011000 0x20>;
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. interrupts = <31>;
  102. timeout-ms = <1000>;
  103. clocks = <&coreclk 0>;
  104. status = "disabled";
  105. };
  106. i2c1: i2c@d0011100 {
  107. compatible = "marvell,mv64xxx-i2c";
  108. reg = <0xd0011100 0x20>;
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. interrupts = <32>;
  112. timeout-ms = <1000>;
  113. clocks = <&coreclk 0>;
  114. status = "disabled";
  115. };
  116. };
  117. };