radeon_drv.c 20 KB

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  1. /**
  2. * \file radeon_drv.c
  3. * ATI Radeon driver
  4. *
  5. * \author Gareth Hughes <gareth@valinux.com>
  6. */
  7. /*
  8. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  9. * All Rights Reserved.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice (including the next
  19. * paragraph) shall be included in all copies or substantial portions of the
  20. * Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  28. * OTHER DEALINGS IN THE SOFTWARE.
  29. */
  30. #include <drm/drmP.h>
  31. #include <drm/radeon_drm.h>
  32. #include "radeon_drv.h"
  33. #include <drm/drm_pciids.h>
  34. #include <linux/console.h>
  35. #include <linux/module.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/vga_switcheroo.h>
  38. #include "drm_crtc_helper.h"
  39. /*
  40. * KMS wrapper.
  41. * - 2.0.0 - initial interface
  42. * - 2.1.0 - add square tiling interface
  43. * - 2.2.0 - add r6xx/r7xx const buffer support
  44. * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  45. * - 2.4.0 - add crtc id query
  46. * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
  47. * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
  48. * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
  49. * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
  50. * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  51. * 2.10.0 - fusion 2D tiling
  52. * 2.11.0 - backend map, initial compute support for the CS checker
  53. * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  54. * 2.13.0 - virtual memory support, streamout
  55. * 2.14.0 - add evergreen tiling informations
  56. * 2.15.0 - add max_pipes query
  57. * 2.16.0 - fix evergreen 2D tiled surface calculation
  58. * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  59. * 2.18.0 - r600-eg: allow "invalid" DB formats
  60. * 2.19.0 - r600-eg: MSAA textures
  61. * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  62. * 2.21.0 - r600-r700: FMASK and CMASK
  63. * 2.22.0 - r600 only: RESOLVE_BOX allowed
  64. * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
  65. * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
  66. * 2.25.0 - eg+: new info request for num SE and num SH
  67. * 2.26.0 - r600-eg: fix htile size computation
  68. * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
  69. * 2.28.0 - r600-eg: Add MEM_WRITE packet support
  70. * 2.29.0 - R500 FP16 color clear registers
  71. * 2.30.0 - fix for FMASK texturing
  72. * 2.31.0 - Add fastfb support for rs690
  73. * 2.32.0 - new info request for rings working
  74. * 2.33.0 - Add SI tiling mode array query
  75. * 2.34.0 - Add CIK tiling mode array query
  76. */
  77. #define KMS_DRIVER_MAJOR 2
  78. #define KMS_DRIVER_MINOR 34
  79. #define KMS_DRIVER_PATCHLEVEL 0
  80. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
  81. int radeon_driver_unload_kms(struct drm_device *dev);
  82. void radeon_driver_lastclose_kms(struct drm_device *dev);
  83. int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
  84. void radeon_driver_postclose_kms(struct drm_device *dev,
  85. struct drm_file *file_priv);
  86. void radeon_driver_preclose_kms(struct drm_device *dev,
  87. struct drm_file *file_priv);
  88. int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
  89. int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
  90. u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
  91. int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
  92. void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
  93. int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
  94. int *max_error,
  95. struct timeval *vblank_time,
  96. unsigned flags);
  97. void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
  98. int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
  99. void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
  100. irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
  101. void radeon_gem_object_free(struct drm_gem_object *obj);
  102. int radeon_gem_object_open(struct drm_gem_object *obj,
  103. struct drm_file *file_priv);
  104. void radeon_gem_object_close(struct drm_gem_object *obj,
  105. struct drm_file *file_priv);
  106. extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
  107. int *vpos, int *hpos);
  108. extern const struct drm_ioctl_desc radeon_ioctls_kms[];
  109. extern int radeon_max_kms_ioctl;
  110. int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
  111. int radeon_mode_dumb_mmap(struct drm_file *filp,
  112. struct drm_device *dev,
  113. uint32_t handle, uint64_t *offset_p);
  114. int radeon_mode_dumb_create(struct drm_file *file_priv,
  115. struct drm_device *dev,
  116. struct drm_mode_create_dumb *args);
  117. struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
  118. struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
  119. size_t size,
  120. struct sg_table *sg);
  121. int radeon_gem_prime_pin(struct drm_gem_object *obj);
  122. void radeon_gem_prime_unpin(struct drm_gem_object *obj);
  123. void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
  124. void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  125. extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
  126. unsigned long arg);
  127. #if defined(CONFIG_DEBUG_FS)
  128. int radeon_debugfs_init(struct drm_minor *minor);
  129. void radeon_debugfs_cleanup(struct drm_minor *minor);
  130. #endif
  131. /* atpx handler */
  132. #if defined(CONFIG_VGA_SWITCHEROO)
  133. void radeon_register_atpx_handler(void);
  134. void radeon_unregister_atpx_handler(void);
  135. bool radeon_is_px(void);
  136. #else
  137. static inline void radeon_register_atpx_handler(void) {}
  138. static inline void radeon_unregister_atpx_handler(void) {}
  139. static inline bool radeon_is_px(void) { return false; }
  140. #endif
  141. int radeon_no_wb;
  142. int radeon_modeset = -1;
  143. int radeon_dynclks = -1;
  144. int radeon_r4xx_atom = 0;
  145. int radeon_agpmode = 0;
  146. int radeon_vram_limit = 0;
  147. int radeon_gart_size = -1; /* auto */
  148. int radeon_benchmarking = 0;
  149. int radeon_testing = 0;
  150. int radeon_connector_table = 0;
  151. int radeon_tv = 1;
  152. int radeon_audio = 1;
  153. int radeon_disp_priority = 0;
  154. int radeon_hw_i2c = 0;
  155. int radeon_pcie_gen2 = -1;
  156. int radeon_msi = -1;
  157. int radeon_lockup_timeout = 10000;
  158. int radeon_fastfb = 0;
  159. int radeon_dpm = -1;
  160. int radeon_aspm = -1;
  161. int radeon_runtime_pm = -1;
  162. MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
  163. module_param_named(no_wb, radeon_no_wb, int, 0444);
  164. MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
  165. module_param_named(modeset, radeon_modeset, int, 0400);
  166. MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
  167. module_param_named(dynclks, radeon_dynclks, int, 0444);
  168. MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
  169. module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
  170. MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
  171. module_param_named(vramlimit, radeon_vram_limit, int, 0600);
  172. MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
  173. module_param_named(agpmode, radeon_agpmode, int, 0444);
  174. MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
  175. module_param_named(gartsize, radeon_gart_size, int, 0600);
  176. MODULE_PARM_DESC(benchmark, "Run benchmark");
  177. module_param_named(benchmark, radeon_benchmarking, int, 0444);
  178. MODULE_PARM_DESC(test, "Run tests");
  179. module_param_named(test, radeon_testing, int, 0444);
  180. MODULE_PARM_DESC(connector_table, "Force connector table");
  181. module_param_named(connector_table, radeon_connector_table, int, 0444);
  182. MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
  183. module_param_named(tv, radeon_tv, int, 0444);
  184. MODULE_PARM_DESC(audio, "Audio enable (1 = enable)");
  185. module_param_named(audio, radeon_audio, int, 0444);
  186. MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
  187. module_param_named(disp_priority, radeon_disp_priority, int, 0444);
  188. MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
  189. module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
  190. MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
  191. module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
  192. MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
  193. module_param_named(msi, radeon_msi, int, 0444);
  194. MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
  195. module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
  196. MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
  197. module_param_named(fastfb, radeon_fastfb, int, 0444);
  198. MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
  199. module_param_named(dpm, radeon_dpm, int, 0444);
  200. MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
  201. module_param_named(aspm, radeon_aspm, int, 0444);
  202. MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
  203. module_param_named(runpm, radeon_runtime_pm, int, 0444);
  204. static struct pci_device_id pciidlist[] = {
  205. radeon_PCI_IDS
  206. };
  207. MODULE_DEVICE_TABLE(pci, pciidlist);
  208. #ifdef CONFIG_DRM_RADEON_UMS
  209. static int radeon_suspend(struct drm_device *dev, pm_message_t state)
  210. {
  211. drm_radeon_private_t *dev_priv = dev->dev_private;
  212. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  213. return 0;
  214. /* Disable *all* interrupts */
  215. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  216. RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
  217. RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
  218. return 0;
  219. }
  220. static int radeon_resume(struct drm_device *dev)
  221. {
  222. drm_radeon_private_t *dev_priv = dev->dev_private;
  223. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  224. return 0;
  225. /* Restore interrupt registers */
  226. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  227. RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  228. RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  229. return 0;
  230. }
  231. static const struct file_operations radeon_driver_old_fops = {
  232. .owner = THIS_MODULE,
  233. .open = drm_open,
  234. .release = drm_release,
  235. .unlocked_ioctl = drm_ioctl,
  236. .mmap = drm_mmap,
  237. .poll = drm_poll,
  238. .read = drm_read,
  239. #ifdef CONFIG_COMPAT
  240. .compat_ioctl = radeon_compat_ioctl,
  241. #endif
  242. .llseek = noop_llseek,
  243. };
  244. static struct drm_driver driver_old = {
  245. .driver_features =
  246. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  247. DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
  248. .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
  249. .load = radeon_driver_load,
  250. .firstopen = radeon_driver_firstopen,
  251. .open = radeon_driver_open,
  252. .preclose = radeon_driver_preclose,
  253. .postclose = radeon_driver_postclose,
  254. .lastclose = radeon_driver_lastclose,
  255. .unload = radeon_driver_unload,
  256. .suspend = radeon_suspend,
  257. .resume = radeon_resume,
  258. .get_vblank_counter = radeon_get_vblank_counter,
  259. .enable_vblank = radeon_enable_vblank,
  260. .disable_vblank = radeon_disable_vblank,
  261. .master_create = radeon_master_create,
  262. .master_destroy = radeon_master_destroy,
  263. .irq_preinstall = radeon_driver_irq_preinstall,
  264. .irq_postinstall = radeon_driver_irq_postinstall,
  265. .irq_uninstall = radeon_driver_irq_uninstall,
  266. .irq_handler = radeon_driver_irq_handler,
  267. .ioctls = radeon_ioctls,
  268. .dma_ioctl = radeon_cp_buffers,
  269. .fops = &radeon_driver_old_fops,
  270. .name = DRIVER_NAME,
  271. .desc = DRIVER_DESC,
  272. .date = DRIVER_DATE,
  273. .major = DRIVER_MAJOR,
  274. .minor = DRIVER_MINOR,
  275. .patchlevel = DRIVER_PATCHLEVEL,
  276. };
  277. #endif
  278. static struct drm_driver kms_driver;
  279. static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
  280. {
  281. struct apertures_struct *ap;
  282. bool primary = false;
  283. ap = alloc_apertures(1);
  284. if (!ap)
  285. return -ENOMEM;
  286. ap->ranges[0].base = pci_resource_start(pdev, 0);
  287. ap->ranges[0].size = pci_resource_len(pdev, 0);
  288. #ifdef CONFIG_X86
  289. primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  290. #endif
  291. remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
  292. kfree(ap);
  293. return 0;
  294. }
  295. static int radeon_pci_probe(struct pci_dev *pdev,
  296. const struct pci_device_id *ent)
  297. {
  298. int ret;
  299. /* Get rid of things like offb */
  300. ret = radeon_kick_out_firmware_fb(pdev);
  301. if (ret)
  302. return ret;
  303. return drm_get_pci_dev(pdev, ent, &kms_driver);
  304. }
  305. static void
  306. radeon_pci_remove(struct pci_dev *pdev)
  307. {
  308. struct drm_device *dev = pci_get_drvdata(pdev);
  309. drm_put_dev(dev);
  310. }
  311. static int radeon_pmops_suspend(struct device *dev)
  312. {
  313. struct pci_dev *pdev = to_pci_dev(dev);
  314. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  315. return radeon_suspend_kms(drm_dev, true, true);
  316. }
  317. static int radeon_pmops_resume(struct device *dev)
  318. {
  319. struct pci_dev *pdev = to_pci_dev(dev);
  320. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  321. return radeon_resume_kms(drm_dev, true, true);
  322. }
  323. static int radeon_pmops_freeze(struct device *dev)
  324. {
  325. struct pci_dev *pdev = to_pci_dev(dev);
  326. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  327. return radeon_suspend_kms(drm_dev, false, true);
  328. }
  329. static int radeon_pmops_thaw(struct device *dev)
  330. {
  331. struct pci_dev *pdev = to_pci_dev(dev);
  332. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  333. return radeon_resume_kms(drm_dev, false, true);
  334. }
  335. static int radeon_pmops_runtime_suspend(struct device *dev)
  336. {
  337. struct pci_dev *pdev = to_pci_dev(dev);
  338. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  339. int ret;
  340. if (radeon_runtime_pm == 0)
  341. return -EINVAL;
  342. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  343. drm_kms_helper_poll_disable(drm_dev);
  344. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  345. ret = radeon_suspend_kms(drm_dev, false, false);
  346. pci_save_state(pdev);
  347. pci_disable_device(pdev);
  348. pci_set_power_state(pdev, PCI_D3cold);
  349. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  350. return 0;
  351. }
  352. static int radeon_pmops_runtime_resume(struct device *dev)
  353. {
  354. struct pci_dev *pdev = to_pci_dev(dev);
  355. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  356. int ret;
  357. if (radeon_runtime_pm == 0)
  358. return -EINVAL;
  359. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  360. pci_set_power_state(pdev, PCI_D0);
  361. pci_restore_state(pdev);
  362. ret = pci_enable_device(pdev);
  363. if (ret)
  364. return ret;
  365. pci_set_master(pdev);
  366. ret = radeon_resume_kms(drm_dev, false, false);
  367. drm_kms_helper_poll_enable(drm_dev);
  368. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  369. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  370. return 0;
  371. }
  372. static int radeon_pmops_runtime_idle(struct device *dev)
  373. {
  374. struct pci_dev *pdev = to_pci_dev(dev);
  375. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  376. struct drm_crtc *crtc;
  377. if (radeon_runtime_pm == 0)
  378. return -EBUSY;
  379. /* are we PX enabled? */
  380. if (radeon_runtime_pm == -1 && !radeon_is_px()) {
  381. DRM_DEBUG_DRIVER("failing to power off - not px\n");
  382. return -EBUSY;
  383. }
  384. list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
  385. if (crtc->enabled) {
  386. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  387. return -EBUSY;
  388. }
  389. }
  390. pm_runtime_mark_last_busy(dev);
  391. pm_runtime_autosuspend(dev);
  392. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  393. return 1;
  394. }
  395. long radeon_drm_ioctl(struct file *filp,
  396. unsigned int cmd, unsigned long arg)
  397. {
  398. struct drm_file *file_priv = filp->private_data;
  399. struct drm_device *dev;
  400. long ret;
  401. dev = file_priv->minor->dev;
  402. ret = pm_runtime_get_sync(dev->dev);
  403. if (ret < 0)
  404. return ret;
  405. ret = drm_ioctl(filp, cmd, arg);
  406. pm_runtime_mark_last_busy(dev->dev);
  407. pm_runtime_put_autosuspend(dev->dev);
  408. return ret;
  409. }
  410. static const struct dev_pm_ops radeon_pm_ops = {
  411. .suspend = radeon_pmops_suspend,
  412. .resume = radeon_pmops_resume,
  413. .freeze = radeon_pmops_freeze,
  414. .thaw = radeon_pmops_thaw,
  415. .poweroff = radeon_pmops_freeze,
  416. .restore = radeon_pmops_resume,
  417. .runtime_suspend = radeon_pmops_runtime_suspend,
  418. .runtime_resume = radeon_pmops_runtime_resume,
  419. .runtime_idle = radeon_pmops_runtime_idle,
  420. };
  421. static const struct file_operations radeon_driver_kms_fops = {
  422. .owner = THIS_MODULE,
  423. .open = drm_open,
  424. .release = drm_release,
  425. .unlocked_ioctl = radeon_drm_ioctl,
  426. .mmap = radeon_mmap,
  427. .poll = drm_poll,
  428. .read = drm_read,
  429. #ifdef CONFIG_COMPAT
  430. .compat_ioctl = radeon_kms_compat_ioctl,
  431. #endif
  432. };
  433. static struct drm_driver kms_driver = {
  434. .driver_features =
  435. DRIVER_USE_AGP |
  436. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  437. DRIVER_PRIME | DRIVER_RENDER,
  438. .dev_priv_size = 0,
  439. .load = radeon_driver_load_kms,
  440. .open = radeon_driver_open_kms,
  441. .preclose = radeon_driver_preclose_kms,
  442. .postclose = radeon_driver_postclose_kms,
  443. .lastclose = radeon_driver_lastclose_kms,
  444. .unload = radeon_driver_unload_kms,
  445. .get_vblank_counter = radeon_get_vblank_counter_kms,
  446. .enable_vblank = radeon_enable_vblank_kms,
  447. .disable_vblank = radeon_disable_vblank_kms,
  448. .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
  449. .get_scanout_position = radeon_get_crtc_scanoutpos,
  450. #if defined(CONFIG_DEBUG_FS)
  451. .debugfs_init = radeon_debugfs_init,
  452. .debugfs_cleanup = radeon_debugfs_cleanup,
  453. #endif
  454. .irq_preinstall = radeon_driver_irq_preinstall_kms,
  455. .irq_postinstall = radeon_driver_irq_postinstall_kms,
  456. .irq_uninstall = radeon_driver_irq_uninstall_kms,
  457. .irq_handler = radeon_driver_irq_handler_kms,
  458. .ioctls = radeon_ioctls_kms,
  459. .gem_free_object = radeon_gem_object_free,
  460. .gem_open_object = radeon_gem_object_open,
  461. .gem_close_object = radeon_gem_object_close,
  462. .dumb_create = radeon_mode_dumb_create,
  463. .dumb_map_offset = radeon_mode_dumb_mmap,
  464. .dumb_destroy = drm_gem_dumb_destroy,
  465. .fops = &radeon_driver_kms_fops,
  466. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  467. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  468. .gem_prime_export = drm_gem_prime_export,
  469. .gem_prime_import = drm_gem_prime_import,
  470. .gem_prime_pin = radeon_gem_prime_pin,
  471. .gem_prime_unpin = radeon_gem_prime_unpin,
  472. .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
  473. .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
  474. .gem_prime_vmap = radeon_gem_prime_vmap,
  475. .gem_prime_vunmap = radeon_gem_prime_vunmap,
  476. .name = DRIVER_NAME,
  477. .desc = DRIVER_DESC,
  478. .date = DRIVER_DATE,
  479. .major = KMS_DRIVER_MAJOR,
  480. .minor = KMS_DRIVER_MINOR,
  481. .patchlevel = KMS_DRIVER_PATCHLEVEL,
  482. };
  483. static struct drm_driver *driver;
  484. static struct pci_driver *pdriver;
  485. #ifdef CONFIG_DRM_RADEON_UMS
  486. static struct pci_driver radeon_pci_driver = {
  487. .name = DRIVER_NAME,
  488. .id_table = pciidlist,
  489. };
  490. #endif
  491. static struct pci_driver radeon_kms_pci_driver = {
  492. .name = DRIVER_NAME,
  493. .id_table = pciidlist,
  494. .probe = radeon_pci_probe,
  495. .remove = radeon_pci_remove,
  496. .driver.pm = &radeon_pm_ops,
  497. };
  498. static int __init radeon_init(void)
  499. {
  500. #ifdef CONFIG_VGA_CONSOLE
  501. if (vgacon_text_force() && radeon_modeset == -1) {
  502. DRM_INFO("VGACON disable radeon kernel modesetting.\n");
  503. radeon_modeset = 0;
  504. }
  505. #endif
  506. /* set to modesetting by default if not nomodeset */
  507. if (radeon_modeset == -1)
  508. radeon_modeset = 1;
  509. if (radeon_modeset == 1) {
  510. DRM_INFO("radeon kernel modesetting enabled.\n");
  511. driver = &kms_driver;
  512. pdriver = &radeon_kms_pci_driver;
  513. driver->driver_features |= DRIVER_MODESET;
  514. driver->num_ioctls = radeon_max_kms_ioctl;
  515. radeon_register_atpx_handler();
  516. } else {
  517. #ifdef CONFIG_DRM_RADEON_UMS
  518. DRM_INFO("radeon userspace modesetting enabled.\n");
  519. driver = &driver_old;
  520. pdriver = &radeon_pci_driver;
  521. driver->driver_features &= ~DRIVER_MODESET;
  522. driver->num_ioctls = radeon_max_ioctl;
  523. #else
  524. DRM_ERROR("No UMS support in radeon module!\n");
  525. return -EINVAL;
  526. #endif
  527. }
  528. /* let modprobe override vga console setting */
  529. return drm_pci_init(driver, pdriver);
  530. }
  531. static void __exit radeon_exit(void)
  532. {
  533. drm_pci_exit(driver, pdriver);
  534. radeon_unregister_atpx_handler();
  535. }
  536. module_init(radeon_init);
  537. module_exit(radeon_exit);
  538. MODULE_AUTHOR(DRIVER_AUTHOR);
  539. MODULE_DESCRIPTION(DRIVER_DESC);
  540. MODULE_LICENSE("GPL and additional rights");