gdth.c 180 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: Command priority
  87. * buffer: phys. DMA sense buffer
  88. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  89. * buffers_residual: Timeout value
  90. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  91. * Message: Additional info (gdth_do_cmd()), DMA direction
  92. * have_data_in: Flag for gdth_wait_completion()
  93. * sent_command: Opcode special command
  94. * phase: Service/parameter/return code special command
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #ifdef GDTH_RTC
  116. #include <linux/mc146818rtc.h>
  117. #endif
  118. #include <linux/reboot.h>
  119. #include <asm/dma.h>
  120. #include <asm/system.h>
  121. #include <asm/io.h>
  122. #include <asm/uaccess.h>
  123. #include <linux/spinlock.h>
  124. #include <linux/blkdev.h>
  125. #include "scsi.h"
  126. #include <scsi/scsi_host.h>
  127. #include "gdth.h"
  128. static void gdth_delay(int milliseconds);
  129. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  130. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  131. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  132. int gdth_from_wait, int* pIndex);
  133. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  134. Scsi_Cmnd *scp);
  135. static int gdth_async_event(gdth_ha_str *ha);
  136. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  137. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  138. static void gdth_next(gdth_ha_str *ha);
  139. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  140. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  141. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  142. ushort idx, gdth_evt_data *evt);
  143. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  144. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  145. gdth_evt_str *estr);
  146. static void gdth_clear_events(void);
  147. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  148. char *buffer,ushort count);
  149. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  150. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  151. static void gdth_enable_int(gdth_ha_str *ha);
  152. static unchar gdth_get_status(gdth_ha_str *ha, int irq);
  153. static int gdth_test_busy(gdth_ha_str *ha);
  154. static int gdth_get_cmd_index(gdth_ha_str *ha);
  155. static void gdth_release_event(gdth_ha_str *ha);
  156. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  157. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  158. ulong32 p1, ulong64 p2,ulong64 p3);
  159. static int gdth_search_drives(gdth_ha_str *ha);
  160. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  161. static const char *gdth_ctr_name(gdth_ha_str *ha);
  162. static int gdth_open(struct inode *inode, struct file *filep);
  163. static int gdth_close(struct inode *inode, struct file *filep);
  164. static int gdth_ioctl(struct inode *inode, struct file *filep,
  165. unsigned int cmd, unsigned long arg);
  166. static void gdth_flush(gdth_ha_str *ha);
  167. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  168. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  169. static void gdth_scsi_done(struct scsi_cmnd *scp);
  170. #ifdef CONFIG_ISA
  171. static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
  172. #endif
  173. #ifdef CONFIG_EISA
  174. static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
  175. #endif
  176. #ifdef CONFIG_PCI
  177. static int gdth_pci_probe_one(struct scsi_host_template *, gdth_pci_str *, int);
  178. #endif
  179. #ifdef DEBUG_GDTH
  180. static unchar DebugState = DEBUG_GDTH;
  181. #ifdef __SERIAL__
  182. #define MAX_SERBUF 160
  183. static void ser_init(void);
  184. static void ser_puts(char *str);
  185. static void ser_putc(char c);
  186. static int ser_printk(const char *fmt, ...);
  187. static char strbuf[MAX_SERBUF+1];
  188. #ifdef __COM2__
  189. #define COM_BASE 0x2f8
  190. #else
  191. #define COM_BASE 0x3f8
  192. #endif
  193. static void ser_init()
  194. {
  195. unsigned port=COM_BASE;
  196. outb(0x80,port+3);
  197. outb(0,port+1);
  198. /* 19200 Baud, if 9600: outb(12,port) */
  199. outb(6, port);
  200. outb(3,port+3);
  201. outb(0,port+1);
  202. /*
  203. ser_putc('I');
  204. ser_putc(' ');
  205. */
  206. }
  207. static void ser_puts(char *str)
  208. {
  209. char *ptr;
  210. ser_init();
  211. for (ptr=str;*ptr;++ptr)
  212. ser_putc(*ptr);
  213. }
  214. static void ser_putc(char c)
  215. {
  216. unsigned port=COM_BASE;
  217. while ((inb(port+5) & 0x20)==0);
  218. outb(c,port);
  219. if (c==0x0a)
  220. {
  221. while ((inb(port+5) & 0x20)==0);
  222. outb(0x0d,port);
  223. }
  224. }
  225. static int ser_printk(const char *fmt, ...)
  226. {
  227. va_list args;
  228. int i;
  229. va_start(args,fmt);
  230. i = vsprintf(strbuf,fmt,args);
  231. ser_puts(strbuf);
  232. va_end(args);
  233. return i;
  234. }
  235. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  236. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  237. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  238. #else /* !__SERIAL__ */
  239. #define TRACE(a) {if (DebugState==1) {printk a;}}
  240. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  241. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  242. #endif
  243. #else /* !DEBUG */
  244. #define TRACE(a)
  245. #define TRACE2(a)
  246. #define TRACE3(a)
  247. #endif
  248. #ifdef GDTH_STATISTICS
  249. static ulong32 max_rq=0, max_index=0, max_sg=0;
  250. #ifdef INT_COAL
  251. static ulong32 max_int_coal=0;
  252. #endif
  253. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  254. static struct timer_list gdth_timer;
  255. #endif
  256. #define PTR2USHORT(a) (ushort)(ulong)(a)
  257. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  258. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  259. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  260. #ifdef CONFIG_ISA
  261. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  262. #endif
  263. #ifdef CONFIG_EISA
  264. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  265. #endif
  266. static unchar gdth_polling; /* polling if TRUE */
  267. static int gdth_ctr_count = 0; /* controller count */
  268. static int gdth_ctr_released = 0; /* gdth_release() */
  269. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  270. static unchar gdth_write_through = FALSE; /* write through */
  271. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  272. static int elastidx;
  273. static int eoldidx;
  274. static int major;
  275. #define DIN 1 /* IN data direction */
  276. #define DOU 2 /* OUT data direction */
  277. #define DNO DIN /* no data transfer */
  278. #define DUN DIN /* unknown data direction */
  279. static unchar gdth_direction_tab[0x100] = {
  280. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  281. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  282. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  283. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  284. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  290. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  291. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  292. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  293. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  294. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  295. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  296. };
  297. /* LILO and modprobe/insmod parameters */
  298. /* IRQ list for GDT3000/3020 EISA controllers */
  299. static int irq[MAXHA] __initdata =
  300. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  301. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  302. /* disable driver flag */
  303. static int disable __initdata = 0;
  304. /* reserve flag */
  305. static int reserve_mode = 1;
  306. /* reserve list */
  307. static int reserve_list[MAX_RES_ARGS] =
  308. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  309. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  310. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  311. /* scan order for PCI controllers */
  312. static int reverse_scan = 0;
  313. /* virtual channel for the host drives */
  314. static int hdr_channel = 0;
  315. /* max. IDs per channel */
  316. static int max_ids = MAXID;
  317. /* rescan all IDs */
  318. static int rescan = 0;
  319. /* shared access */
  320. static int shared_access = 1;
  321. /* enable support for EISA and ISA controllers */
  322. static int probe_eisa_isa = 0;
  323. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  324. static int force_dma32 = 0;
  325. /* parameters for modprobe/insmod */
  326. module_param_array(irq, int, NULL, 0);
  327. module_param(disable, int, 0);
  328. module_param(reserve_mode, int, 0);
  329. module_param_array(reserve_list, int, NULL, 0);
  330. module_param(reverse_scan, int, 0);
  331. module_param(hdr_channel, int, 0);
  332. module_param(max_ids, int, 0);
  333. module_param(rescan, int, 0);
  334. module_param(shared_access, int, 0);
  335. module_param(probe_eisa_isa, int, 0);
  336. module_param(force_dma32, int, 0);
  337. MODULE_AUTHOR("Achim Leubner");
  338. MODULE_LICENSE("GPL");
  339. /* ioctl interface */
  340. static const struct file_operations gdth_fops = {
  341. .ioctl = gdth_ioctl,
  342. .open = gdth_open,
  343. .release = gdth_close,
  344. };
  345. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  346. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  347. #include "gdth_proc.h"
  348. #include "gdth_proc.c"
  349. /* notifier block to get a notify on system shutdown/halt/reboot */
  350. static struct notifier_block gdth_notifier = {
  351. gdth_halt, NULL, 0
  352. };
  353. static int notifier_disabled = 0;
  354. static void gdth_delay(int milliseconds)
  355. {
  356. if (milliseconds == 0) {
  357. udelay(1);
  358. } else {
  359. mdelay(milliseconds);
  360. }
  361. }
  362. static void gdth_scsi_done(struct scsi_cmnd *scp)
  363. {
  364. TRACE2(("gdth_scsi_done()\n"));
  365. if (IS_GDTH_INTERNAL_CMD(scp))
  366. complete((struct completion *)scp->request);
  367. else
  368. scp->scsi_done(scp);
  369. }
  370. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  371. int timeout, u32 *info)
  372. {
  373. Scsi_Cmnd *scp;
  374. DECLARE_COMPLETION_ONSTACK(wait);
  375. int rval;
  376. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  377. if (!scp)
  378. return -ENOMEM;
  379. scp->device = sdev;
  380. /* use request field to save the ptr. to completion struct. */
  381. scp->request = (struct request *)&wait;
  382. scp->timeout_per_command = timeout*HZ;
  383. scp->request_buffer = gdtcmd;
  384. scp->cmd_len = 12;
  385. memcpy(scp->cmnd, cmnd, 12);
  386. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  387. scp->underflow = GDTH_MAGIC;
  388. gdth_queuecommand(scp, NULL);
  389. wait_for_completion(&wait);
  390. rval = scp->SCp.Status;
  391. if (info)
  392. *info = scp->SCp.Message;
  393. kfree(scp);
  394. return rval;
  395. }
  396. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  397. int timeout, u32 *info)
  398. {
  399. struct scsi_device *sdev = scsi_get_host_dev(shost);
  400. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  401. scsi_free_host_dev(sdev);
  402. return rval;
  403. }
  404. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  405. {
  406. *cyls = size /HEADS/SECS;
  407. if (*cyls <= MAXCYLS) {
  408. *heads = HEADS;
  409. *secs = SECS;
  410. } else { /* too high for 64*32 */
  411. *cyls = size /MEDHEADS/MEDSECS;
  412. if (*cyls <= MAXCYLS) {
  413. *heads = MEDHEADS;
  414. *secs = MEDSECS;
  415. } else { /* too high for 127*63 */
  416. *cyls = size /BIGHEADS/BIGSECS;
  417. *heads = BIGHEADS;
  418. *secs = BIGSECS;
  419. }
  420. }
  421. }
  422. /* controller search and initialization functions */
  423. #ifdef CONFIG_EISA
  424. static int __init gdth_search_eisa(ushort eisa_adr)
  425. {
  426. ulong32 id;
  427. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  428. id = inl(eisa_adr+ID0REG);
  429. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  430. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  431. return 0; /* not EISA configured */
  432. return 1;
  433. }
  434. if (id == GDT3_ID) /* GDT3000 */
  435. return 1;
  436. return 0;
  437. }
  438. #endif /* CONFIG_EISA */
  439. #ifdef CONFIG_ISA
  440. static int __init gdth_search_isa(ulong32 bios_adr)
  441. {
  442. void __iomem *addr;
  443. ulong32 id;
  444. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  445. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  446. id = readl(addr);
  447. iounmap(addr);
  448. if (id == GDT2_ID) /* GDT2000 */
  449. return 1;
  450. }
  451. return 0;
  452. }
  453. #endif /* CONFIG_ISA */
  454. #ifdef CONFIG_PCI
  455. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  456. ushort vendor, ushort dev);
  457. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  458. {
  459. ushort device, cnt;
  460. TRACE(("gdth_search_pci()\n"));
  461. cnt = 0;
  462. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  463. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  464. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  465. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  466. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  467. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  468. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  469. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  470. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  471. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  472. PCI_DEVICE_ID_INTEL_SRC);
  473. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  474. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  475. return cnt;
  476. }
  477. /* Vortex only makes RAID controllers.
  478. * We do not really want to specify all 550 ids here, so wildcard match.
  479. */
  480. static struct pci_device_id gdthtable[] __maybe_unused = {
  481. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  482. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  483. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  484. {0}
  485. };
  486. MODULE_DEVICE_TABLE(pci,gdthtable);
  487. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  488. ushort vendor, ushort device)
  489. {
  490. ulong base0, base1, base2;
  491. struct pci_dev *pdev;
  492. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  493. *cnt, vendor, device));
  494. pdev = NULL;
  495. while ((pdev = pci_find_device(vendor, device, pdev))
  496. != NULL) {
  497. if (pci_enable_device(pdev))
  498. continue;
  499. if (*cnt >= MAXHA)
  500. return;
  501. /* GDT PCI controller found, resources are already in pdev */
  502. pcistr[*cnt].pdev = pdev;
  503. pcistr[*cnt].irq = pdev->irq;
  504. base0 = pci_resource_flags(pdev, 0);
  505. base1 = pci_resource_flags(pdev, 1);
  506. base2 = pci_resource_flags(pdev, 2);
  507. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  508. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  509. if (!(base0 & IORESOURCE_MEM))
  510. continue;
  511. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  512. } else { /* GDT6110, GDT6120, .. */
  513. if (!(base0 & IORESOURCE_MEM) ||
  514. !(base2 & IORESOURCE_MEM) ||
  515. !(base1 & IORESOURCE_IO))
  516. continue;
  517. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  518. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  519. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  520. }
  521. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  522. pcistr[*cnt].pdev->bus->number,
  523. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  524. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  525. (*cnt)++;
  526. }
  527. }
  528. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  529. {
  530. gdth_pci_str temp;
  531. int i, changed;
  532. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  533. if (cnt == 0)
  534. return;
  535. do {
  536. changed = FALSE;
  537. for (i = 0; i < cnt-1; ++i) {
  538. if (!reverse_scan) {
  539. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  540. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  541. PCI_SLOT(pcistr[i].pdev->devfn) >
  542. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  543. temp = pcistr[i];
  544. pcistr[i] = pcistr[i+1];
  545. pcistr[i+1] = temp;
  546. changed = TRUE;
  547. }
  548. } else {
  549. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  550. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  551. PCI_SLOT(pcistr[i].pdev->devfn) <
  552. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  553. temp = pcistr[i];
  554. pcistr[i] = pcistr[i+1];
  555. pcistr[i+1] = temp;
  556. changed = TRUE;
  557. }
  558. }
  559. }
  560. } while (changed);
  561. }
  562. #endif /* CONFIG_PCI */
  563. #ifdef CONFIG_EISA
  564. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  565. {
  566. ulong32 retries,id;
  567. unchar prot_ver,eisacf,i,irq_found;
  568. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  569. /* disable board interrupts, deinitialize services */
  570. outb(0xff,eisa_adr+EDOORREG);
  571. outb(0x00,eisa_adr+EDENABREG);
  572. outb(0x00,eisa_adr+EINTENABREG);
  573. outb(0xff,eisa_adr+LDOORREG);
  574. retries = INIT_RETRIES;
  575. gdth_delay(20);
  576. while (inb(eisa_adr+EDOORREG) != 0xff) {
  577. if (--retries == 0) {
  578. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  579. return 0;
  580. }
  581. gdth_delay(1);
  582. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  583. }
  584. prot_ver = inb(eisa_adr+MAILBOXREG);
  585. outb(0xff,eisa_adr+EDOORREG);
  586. if (prot_ver != PROTOCOL_VERSION) {
  587. printk("GDT-EISA: Illegal protocol version\n");
  588. return 0;
  589. }
  590. ha->bmic = eisa_adr;
  591. ha->brd_phys = (ulong32)eisa_adr >> 12;
  592. outl(0,eisa_adr+MAILBOXREG);
  593. outl(0,eisa_adr+MAILBOXREG+4);
  594. outl(0,eisa_adr+MAILBOXREG+8);
  595. outl(0,eisa_adr+MAILBOXREG+12);
  596. /* detect IRQ */
  597. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  598. ha->oem_id = OEM_ID_ICP;
  599. ha->type = GDT_EISA;
  600. ha->stype = id;
  601. outl(1,eisa_adr+MAILBOXREG+8);
  602. outb(0xfe,eisa_adr+LDOORREG);
  603. retries = INIT_RETRIES;
  604. gdth_delay(20);
  605. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  606. if (--retries == 0) {
  607. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  608. return 0;
  609. }
  610. gdth_delay(1);
  611. }
  612. ha->irq = inb(eisa_adr+MAILBOXREG);
  613. outb(0xff,eisa_adr+EDOORREG);
  614. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  615. /* check the result */
  616. if (ha->irq == 0) {
  617. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  618. for (i = 0, irq_found = FALSE;
  619. i < MAXHA && irq[i] != 0xff; ++i) {
  620. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  621. irq_found = TRUE;
  622. break;
  623. }
  624. }
  625. if (irq_found) {
  626. ha->irq = irq[i];
  627. irq[i] = 0;
  628. printk("GDT-EISA: Can not detect controller IRQ,\n");
  629. printk("Use IRQ setting from command line (IRQ = %d)\n",
  630. ha->irq);
  631. } else {
  632. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  633. printk("the controller BIOS or use command line parameters\n");
  634. return 0;
  635. }
  636. }
  637. } else {
  638. eisacf = inb(eisa_adr+EISAREG) & 7;
  639. if (eisacf > 4) /* level triggered */
  640. eisacf -= 4;
  641. ha->irq = gdth_irq_tab[eisacf];
  642. ha->oem_id = OEM_ID_ICP;
  643. ha->type = GDT_EISA;
  644. ha->stype = id;
  645. }
  646. ha->dma64_support = 0;
  647. return 1;
  648. }
  649. #endif /* CONFIG_EISA */
  650. #ifdef CONFIG_ISA
  651. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  652. {
  653. register gdt2_dpram_str __iomem *dp2_ptr;
  654. int i;
  655. unchar irq_drq,prot_ver;
  656. ulong32 retries;
  657. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  658. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  659. if (ha->brd == NULL) {
  660. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  661. return 0;
  662. }
  663. dp2_ptr = ha->brd;
  664. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  665. /* reset interface area */
  666. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  667. if (readl(&dp2_ptr->u) != 0) {
  668. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  669. iounmap(ha->brd);
  670. return 0;
  671. }
  672. /* disable board interrupts, read DRQ and IRQ */
  673. writeb(0xff, &dp2_ptr->io.irqdel);
  674. writeb(0x00, &dp2_ptr->io.irqen);
  675. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  676. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  677. irq_drq = readb(&dp2_ptr->io.rq);
  678. for (i=0; i<3; ++i) {
  679. if ((irq_drq & 1)==0)
  680. break;
  681. irq_drq >>= 1;
  682. }
  683. ha->drq = gdth_drq_tab[i];
  684. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  685. for (i=1; i<5; ++i) {
  686. if ((irq_drq & 1)==0)
  687. break;
  688. irq_drq >>= 1;
  689. }
  690. ha->irq = gdth_irq_tab[i];
  691. /* deinitialize services */
  692. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  693. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  694. writeb(0, &dp2_ptr->io.event);
  695. retries = INIT_RETRIES;
  696. gdth_delay(20);
  697. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  698. if (--retries == 0) {
  699. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  700. iounmap(ha->brd);
  701. return 0;
  702. }
  703. gdth_delay(1);
  704. }
  705. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  706. writeb(0, &dp2_ptr->u.ic.Status);
  707. writeb(0xff, &dp2_ptr->io.irqdel);
  708. if (prot_ver != PROTOCOL_VERSION) {
  709. printk("GDT-ISA: Illegal protocol version\n");
  710. iounmap(ha->brd);
  711. return 0;
  712. }
  713. ha->oem_id = OEM_ID_ICP;
  714. ha->type = GDT_ISA;
  715. ha->ic_all_size = sizeof(dp2_ptr->u);
  716. ha->stype= GDT2_ID;
  717. ha->brd_phys = bios_adr >> 4;
  718. /* special request to controller BIOS */
  719. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  720. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  721. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  722. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  723. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  724. writeb(0, &dp2_ptr->io.event);
  725. retries = INIT_RETRIES;
  726. gdth_delay(20);
  727. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  728. if (--retries == 0) {
  729. printk("GDT-ISA: Initialization error\n");
  730. iounmap(ha->brd);
  731. return 0;
  732. }
  733. gdth_delay(1);
  734. }
  735. writeb(0, &dp2_ptr->u.ic.Status);
  736. writeb(0xff, &dp2_ptr->io.irqdel);
  737. ha->dma64_support = 0;
  738. return 1;
  739. }
  740. #endif /* CONFIG_ISA */
  741. #ifdef CONFIG_PCI
  742. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  743. {
  744. register gdt6_dpram_str __iomem *dp6_ptr;
  745. register gdt6c_dpram_str __iomem *dp6c_ptr;
  746. register gdt6m_dpram_str __iomem *dp6m_ptr;
  747. ulong32 retries;
  748. unchar prot_ver;
  749. ushort command;
  750. int i, found = FALSE;
  751. TRACE(("gdth_init_pci()\n"));
  752. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  753. ha->oem_id = OEM_ID_INTEL;
  754. else
  755. ha->oem_id = OEM_ID_ICP;
  756. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  757. ha->stype = (ulong32)pcistr->pdev->device;
  758. ha->irq = pcistr->irq;
  759. ha->pdev = pcistr->pdev;
  760. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  761. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  762. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  763. if (ha->brd == NULL) {
  764. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  765. return 0;
  766. }
  767. /* check and reset interface area */
  768. dp6_ptr = ha->brd;
  769. writel(DPMEM_MAGIC, &dp6_ptr->u);
  770. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  771. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  772. pcistr->dpmem);
  773. found = FALSE;
  774. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  775. iounmap(ha->brd);
  776. ha->brd = ioremap(i, sizeof(ushort));
  777. if (ha->brd == NULL) {
  778. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  779. return 0;
  780. }
  781. if (readw(ha->brd) != 0xffff) {
  782. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  783. continue;
  784. }
  785. iounmap(ha->brd);
  786. pci_write_config_dword(pcistr->pdev,
  787. PCI_BASE_ADDRESS_0, i);
  788. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  789. if (ha->brd == NULL) {
  790. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  791. return 0;
  792. }
  793. dp6_ptr = ha->brd;
  794. writel(DPMEM_MAGIC, &dp6_ptr->u);
  795. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  796. printk("GDT-PCI: Use free address at 0x%x\n", i);
  797. found = TRUE;
  798. break;
  799. }
  800. }
  801. if (!found) {
  802. printk("GDT-PCI: No free address found!\n");
  803. iounmap(ha->brd);
  804. return 0;
  805. }
  806. }
  807. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  808. if (readl(&dp6_ptr->u) != 0) {
  809. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  810. iounmap(ha->brd);
  811. return 0;
  812. }
  813. /* disable board interrupts, deinit services */
  814. writeb(0xff, &dp6_ptr->io.irqdel);
  815. writeb(0x00, &dp6_ptr->io.irqen);
  816. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  817. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  818. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  819. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  820. writeb(0, &dp6_ptr->io.event);
  821. retries = INIT_RETRIES;
  822. gdth_delay(20);
  823. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  824. if (--retries == 0) {
  825. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  826. iounmap(ha->brd);
  827. return 0;
  828. }
  829. gdth_delay(1);
  830. }
  831. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  832. writeb(0, &dp6_ptr->u.ic.S_Status);
  833. writeb(0xff, &dp6_ptr->io.irqdel);
  834. if (prot_ver != PROTOCOL_VERSION) {
  835. printk("GDT-PCI: Illegal protocol version\n");
  836. iounmap(ha->brd);
  837. return 0;
  838. }
  839. ha->type = GDT_PCI;
  840. ha->ic_all_size = sizeof(dp6_ptr->u);
  841. /* special command to controller BIOS */
  842. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  843. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  844. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  845. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  846. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  847. writeb(0, &dp6_ptr->io.event);
  848. retries = INIT_RETRIES;
  849. gdth_delay(20);
  850. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  851. if (--retries == 0) {
  852. printk("GDT-PCI: Initialization error\n");
  853. iounmap(ha->brd);
  854. return 0;
  855. }
  856. gdth_delay(1);
  857. }
  858. writeb(0, &dp6_ptr->u.ic.S_Status);
  859. writeb(0xff, &dp6_ptr->io.irqdel);
  860. ha->dma64_support = 0;
  861. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  862. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  863. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  864. pcistr->dpmem,ha->irq));
  865. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  866. if (ha->brd == NULL) {
  867. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  868. iounmap(ha->brd);
  869. return 0;
  870. }
  871. /* check and reset interface area */
  872. dp6c_ptr = ha->brd;
  873. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  874. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  875. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  876. pcistr->dpmem);
  877. found = FALSE;
  878. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  879. iounmap(ha->brd);
  880. ha->brd = ioremap(i, sizeof(ushort));
  881. if (ha->brd == NULL) {
  882. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  883. return 0;
  884. }
  885. if (readw(ha->brd) != 0xffff) {
  886. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  887. continue;
  888. }
  889. iounmap(ha->brd);
  890. pci_write_config_dword(pcistr->pdev,
  891. PCI_BASE_ADDRESS_2, i);
  892. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  893. if (ha->brd == NULL) {
  894. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  895. return 0;
  896. }
  897. dp6c_ptr = ha->brd;
  898. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  899. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  900. printk("GDT-PCI: Use free address at 0x%x\n", i);
  901. found = TRUE;
  902. break;
  903. }
  904. }
  905. if (!found) {
  906. printk("GDT-PCI: No free address found!\n");
  907. iounmap(ha->brd);
  908. return 0;
  909. }
  910. }
  911. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  912. if (readl(&dp6c_ptr->u) != 0) {
  913. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  914. iounmap(ha->brd);
  915. return 0;
  916. }
  917. /* disable board interrupts, deinit services */
  918. outb(0x00,PTR2USHORT(&ha->plx->control1));
  919. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  920. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  921. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  922. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  923. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  924. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  925. retries = INIT_RETRIES;
  926. gdth_delay(20);
  927. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  928. if (--retries == 0) {
  929. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  930. iounmap(ha->brd);
  931. return 0;
  932. }
  933. gdth_delay(1);
  934. }
  935. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  936. writeb(0, &dp6c_ptr->u.ic.Status);
  937. if (prot_ver != PROTOCOL_VERSION) {
  938. printk("GDT-PCI: Illegal protocol version\n");
  939. iounmap(ha->brd);
  940. return 0;
  941. }
  942. ha->type = GDT_PCINEW;
  943. ha->ic_all_size = sizeof(dp6c_ptr->u);
  944. /* special command to controller BIOS */
  945. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  946. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  947. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  948. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  949. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  950. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  951. retries = INIT_RETRIES;
  952. gdth_delay(20);
  953. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  954. if (--retries == 0) {
  955. printk("GDT-PCI: Initialization error\n");
  956. iounmap(ha->brd);
  957. return 0;
  958. }
  959. gdth_delay(1);
  960. }
  961. writeb(0, &dp6c_ptr->u.ic.S_Status);
  962. ha->dma64_support = 0;
  963. } else { /* MPR */
  964. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  965. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  966. if (ha->brd == NULL) {
  967. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  968. return 0;
  969. }
  970. /* manipulate config. space to enable DPMEM, start RP controller */
  971. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  972. command |= 6;
  973. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  974. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  975. pci_resource_start(pcistr->pdev, 8) = 0UL;
  976. i = 0xFEFF0001UL;
  977. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  978. gdth_delay(1);
  979. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  980. pci_resource_start(pcistr->pdev, 8));
  981. dp6m_ptr = ha->brd;
  982. /* Ensure that it is safe to access the non HW portions of DPMEM.
  983. * Aditional check needed for Xscale based RAID controllers */
  984. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  985. gdth_delay(1);
  986. /* check and reset interface area */
  987. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  988. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  989. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  990. pcistr->dpmem);
  991. found = FALSE;
  992. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  993. iounmap(ha->brd);
  994. ha->brd = ioremap(i, sizeof(ushort));
  995. if (ha->brd == NULL) {
  996. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  997. return 0;
  998. }
  999. if (readw(ha->brd) != 0xffff) {
  1000. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1001. continue;
  1002. }
  1003. iounmap(ha->brd);
  1004. pci_write_config_dword(pcistr->pdev,
  1005. PCI_BASE_ADDRESS_0, i);
  1006. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1007. if (ha->brd == NULL) {
  1008. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1009. return 0;
  1010. }
  1011. dp6m_ptr = ha->brd;
  1012. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1013. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1014. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1015. found = TRUE;
  1016. break;
  1017. }
  1018. }
  1019. if (!found) {
  1020. printk("GDT-PCI: No free address found!\n");
  1021. iounmap(ha->brd);
  1022. return 0;
  1023. }
  1024. }
  1025. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1026. /* disable board interrupts, deinit services */
  1027. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1028. &dp6m_ptr->i960r.edoor_en_reg);
  1029. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1030. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1031. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1032. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1033. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1034. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1035. retries = INIT_RETRIES;
  1036. gdth_delay(20);
  1037. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1038. if (--retries == 0) {
  1039. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1040. iounmap(ha->brd);
  1041. return 0;
  1042. }
  1043. gdth_delay(1);
  1044. }
  1045. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1046. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1047. if (prot_ver != PROTOCOL_VERSION) {
  1048. printk("GDT-PCI: Illegal protocol version\n");
  1049. iounmap(ha->brd);
  1050. return 0;
  1051. }
  1052. ha->type = GDT_PCIMPR;
  1053. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1054. /* special command to controller BIOS */
  1055. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1056. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1057. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1058. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1059. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1060. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1061. retries = INIT_RETRIES;
  1062. gdth_delay(20);
  1063. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1064. if (--retries == 0) {
  1065. printk("GDT-PCI: Initialization error\n");
  1066. iounmap(ha->brd);
  1067. return 0;
  1068. }
  1069. gdth_delay(1);
  1070. }
  1071. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1072. /* read FW version to detect 64-bit DMA support */
  1073. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1074. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1075. retries = INIT_RETRIES;
  1076. gdth_delay(20);
  1077. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1078. if (--retries == 0) {
  1079. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1080. iounmap(ha->brd);
  1081. return 0;
  1082. }
  1083. gdth_delay(1);
  1084. }
  1085. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1086. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1087. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1088. ha->dma64_support = 0;
  1089. else
  1090. ha->dma64_support = 1;
  1091. }
  1092. return 1;
  1093. }
  1094. #endif /* CONFIG_PCI */
  1095. /* controller protocol functions */
  1096. static void __init gdth_enable_int(gdth_ha_str *ha)
  1097. {
  1098. ulong flags;
  1099. gdt2_dpram_str __iomem *dp2_ptr;
  1100. gdt6_dpram_str __iomem *dp6_ptr;
  1101. gdt6m_dpram_str __iomem *dp6m_ptr;
  1102. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1103. spin_lock_irqsave(&ha->smp_lock, flags);
  1104. if (ha->type == GDT_EISA) {
  1105. outb(0xff, ha->bmic + EDOORREG);
  1106. outb(0xff, ha->bmic + EDENABREG);
  1107. outb(0x01, ha->bmic + EINTENABREG);
  1108. } else if (ha->type == GDT_ISA) {
  1109. dp2_ptr = ha->brd;
  1110. writeb(1, &dp2_ptr->io.irqdel);
  1111. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1112. writeb(1, &dp2_ptr->io.irqen);
  1113. } else if (ha->type == GDT_PCI) {
  1114. dp6_ptr = ha->brd;
  1115. writeb(1, &dp6_ptr->io.irqdel);
  1116. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1117. writeb(1, &dp6_ptr->io.irqen);
  1118. } else if (ha->type == GDT_PCINEW) {
  1119. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1120. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1121. } else if (ha->type == GDT_PCIMPR) {
  1122. dp6m_ptr = ha->brd;
  1123. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1124. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1125. &dp6m_ptr->i960r.edoor_en_reg);
  1126. }
  1127. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1128. }
  1129. /* return IStatus if interrupt was from this card else 0 */
  1130. static unchar gdth_get_status(gdth_ha_str *ha, int irq)
  1131. {
  1132. unchar IStatus = 0;
  1133. TRACE(("gdth_get_status() irq %d ctr_count %d\n", irq, gdth_ctr_count));
  1134. if (ha->irq != (unchar)irq) /* check IRQ */
  1135. return false;
  1136. if (ha->type == GDT_EISA)
  1137. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1138. else if (ha->type == GDT_ISA)
  1139. IStatus =
  1140. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1141. else if (ha->type == GDT_PCI)
  1142. IStatus =
  1143. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1144. else if (ha->type == GDT_PCINEW)
  1145. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1146. else if (ha->type == GDT_PCIMPR)
  1147. IStatus =
  1148. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1149. return IStatus;
  1150. }
  1151. static int gdth_test_busy(gdth_ha_str *ha)
  1152. {
  1153. register int gdtsema0 = 0;
  1154. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1155. if (ha->type == GDT_EISA)
  1156. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1157. else if (ha->type == GDT_ISA)
  1158. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1159. else if (ha->type == GDT_PCI)
  1160. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1161. else if (ha->type == GDT_PCINEW)
  1162. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1163. else if (ha->type == GDT_PCIMPR)
  1164. gdtsema0 =
  1165. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1166. return (gdtsema0 & 1);
  1167. }
  1168. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1169. {
  1170. int i;
  1171. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1172. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1173. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1174. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1175. ha->cmd_tab[i].service = ha->pccb->Service;
  1176. ha->pccb->CommandIndex = (ulong32)i+2;
  1177. return (i+2);
  1178. }
  1179. }
  1180. return 0;
  1181. }
  1182. static void gdth_set_sema0(gdth_ha_str *ha)
  1183. {
  1184. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1185. if (ha->type == GDT_EISA) {
  1186. outb(1, ha->bmic + SEMA0REG);
  1187. } else if (ha->type == GDT_ISA) {
  1188. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1189. } else if (ha->type == GDT_PCI) {
  1190. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1191. } else if (ha->type == GDT_PCINEW) {
  1192. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1193. } else if (ha->type == GDT_PCIMPR) {
  1194. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1195. }
  1196. }
  1197. static void gdth_copy_command(gdth_ha_str *ha)
  1198. {
  1199. register gdth_cmd_str *cmd_ptr;
  1200. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1201. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1202. gdt6_dpram_str __iomem *dp6_ptr;
  1203. gdt2_dpram_str __iomem *dp2_ptr;
  1204. ushort cp_count,dp_offset,cmd_no;
  1205. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1206. cp_count = ha->cmd_len;
  1207. dp_offset= ha->cmd_offs_dpmem;
  1208. cmd_no = ha->cmd_cnt;
  1209. cmd_ptr = ha->pccb;
  1210. ++ha->cmd_cnt;
  1211. if (ha->type == GDT_EISA)
  1212. return; /* no DPMEM, no copy */
  1213. /* set cpcount dword aligned */
  1214. if (cp_count & 3)
  1215. cp_count += (4 - (cp_count & 3));
  1216. ha->cmd_offs_dpmem += cp_count;
  1217. /* set offset and service, copy command to DPMEM */
  1218. if (ha->type == GDT_ISA) {
  1219. dp2_ptr = ha->brd;
  1220. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1221. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1222. writew((ushort)cmd_ptr->Service,
  1223. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1224. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1225. } else if (ha->type == GDT_PCI) {
  1226. dp6_ptr = ha->brd;
  1227. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1228. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1229. writew((ushort)cmd_ptr->Service,
  1230. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1231. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1232. } else if (ha->type == GDT_PCINEW) {
  1233. dp6c_ptr = ha->brd;
  1234. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1235. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1236. writew((ushort)cmd_ptr->Service,
  1237. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1238. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1239. } else if (ha->type == GDT_PCIMPR) {
  1240. dp6m_ptr = ha->brd;
  1241. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1242. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1243. writew((ushort)cmd_ptr->Service,
  1244. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1245. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1246. }
  1247. }
  1248. static void gdth_release_event(gdth_ha_str *ha)
  1249. {
  1250. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1251. #ifdef GDTH_STATISTICS
  1252. {
  1253. ulong32 i,j;
  1254. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1255. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1256. ++i;
  1257. }
  1258. if (max_index < i) {
  1259. max_index = i;
  1260. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1261. }
  1262. }
  1263. #endif
  1264. if (ha->pccb->OpCode == GDT_INIT)
  1265. ha->pccb->Service |= 0x80;
  1266. if (ha->type == GDT_EISA) {
  1267. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1268. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1269. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1270. } else if (ha->type == GDT_ISA) {
  1271. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1272. } else if (ha->type == GDT_PCI) {
  1273. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1274. } else if (ha->type == GDT_PCINEW) {
  1275. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1276. } else if (ha->type == GDT_PCIMPR) {
  1277. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1278. }
  1279. }
  1280. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1281. {
  1282. int answer_found = FALSE;
  1283. int wait_index = 0;
  1284. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1285. if (index == 0)
  1286. return 1; /* no wait required */
  1287. do {
  1288. __gdth_interrupt(ha, (int)ha->irq, true, &wait_index);
  1289. if (wait_index == index) {
  1290. answer_found = TRUE;
  1291. break;
  1292. }
  1293. gdth_delay(1);
  1294. } while (--time);
  1295. while (gdth_test_busy(ha))
  1296. gdth_delay(0);
  1297. return (answer_found);
  1298. }
  1299. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1300. ulong32 p1, ulong64 p2, ulong64 p3)
  1301. {
  1302. register gdth_cmd_str *cmd_ptr;
  1303. int retries,index;
  1304. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1305. cmd_ptr = ha->pccb;
  1306. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1307. /* make command */
  1308. for (retries = INIT_RETRIES;;) {
  1309. cmd_ptr->Service = service;
  1310. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1311. if (!(index=gdth_get_cmd_index(ha))) {
  1312. TRACE(("GDT: No free command index found\n"));
  1313. return 0;
  1314. }
  1315. gdth_set_sema0(ha);
  1316. cmd_ptr->OpCode = opcode;
  1317. cmd_ptr->BoardNode = LOCALBOARD;
  1318. if (service == CACHESERVICE) {
  1319. if (opcode == GDT_IOCTL) {
  1320. cmd_ptr->u.ioctl.subfunc = p1;
  1321. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1322. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1323. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1324. } else {
  1325. if (ha->cache_feat & GDT_64BIT) {
  1326. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1327. cmd_ptr->u.cache64.BlockNo = p2;
  1328. } else {
  1329. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1330. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1331. }
  1332. }
  1333. } else if (service == SCSIRAWSERVICE) {
  1334. if (ha->raw_feat & GDT_64BIT) {
  1335. cmd_ptr->u.raw64.direction = p1;
  1336. cmd_ptr->u.raw64.bus = (unchar)p2;
  1337. cmd_ptr->u.raw64.target = (unchar)p3;
  1338. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1339. } else {
  1340. cmd_ptr->u.raw.direction = p1;
  1341. cmd_ptr->u.raw.bus = (unchar)p2;
  1342. cmd_ptr->u.raw.target = (unchar)p3;
  1343. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1344. }
  1345. } else if (service == SCREENSERVICE) {
  1346. if (opcode == GDT_REALTIME) {
  1347. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1348. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1349. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1350. }
  1351. }
  1352. ha->cmd_len = sizeof(gdth_cmd_str);
  1353. ha->cmd_offs_dpmem = 0;
  1354. ha->cmd_cnt = 0;
  1355. gdth_copy_command(ha);
  1356. gdth_release_event(ha);
  1357. gdth_delay(20);
  1358. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1359. printk("GDT: Initialization error (timeout service %d)\n",service);
  1360. return 0;
  1361. }
  1362. if (ha->status != S_BSY || --retries == 0)
  1363. break;
  1364. gdth_delay(1);
  1365. }
  1366. return (ha->status != S_OK ? 0:1);
  1367. }
  1368. /* search for devices */
  1369. static int __init gdth_search_drives(gdth_ha_str *ha)
  1370. {
  1371. ushort cdev_cnt, i;
  1372. int ok;
  1373. ulong32 bus_no, drv_cnt, drv_no, j;
  1374. gdth_getch_str *chn;
  1375. gdth_drlist_str *drl;
  1376. gdth_iochan_str *ioc;
  1377. gdth_raw_iochan_str *iocr;
  1378. gdth_arcdl_str *alst;
  1379. gdth_alist_str *alst2;
  1380. gdth_oem_str_ioctl *oemstr;
  1381. #ifdef INT_COAL
  1382. gdth_perf_modes *pmod;
  1383. #endif
  1384. #ifdef GDTH_RTC
  1385. unchar rtc[12];
  1386. ulong flags;
  1387. #endif
  1388. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1389. ok = 0;
  1390. /* initialize controller services, at first: screen service */
  1391. ha->screen_feat = 0;
  1392. if (!force_dma32) {
  1393. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1394. if (ok)
  1395. ha->screen_feat = GDT_64BIT;
  1396. }
  1397. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1398. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1399. if (!ok) {
  1400. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1401. ha->hanum, ha->status);
  1402. return 0;
  1403. }
  1404. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1405. #ifdef GDTH_RTC
  1406. /* read realtime clock info, send to controller */
  1407. /* 1. wait for the falling edge of update flag */
  1408. spin_lock_irqsave(&rtc_lock, flags);
  1409. for (j = 0; j < 1000000; ++j)
  1410. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1411. break;
  1412. for (j = 0; j < 1000000; ++j)
  1413. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1414. break;
  1415. /* 2. read info */
  1416. do {
  1417. for (j = 0; j < 12; ++j)
  1418. rtc[j] = CMOS_READ(j);
  1419. } while (rtc[0] != CMOS_READ(0));
  1420. spin_unlock_irqrestore(&rtc_lock, flags);
  1421. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1422. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1423. /* 3. send to controller firmware */
  1424. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1425. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1426. #endif
  1427. /* unfreeze all IOs */
  1428. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1429. /* initialize cache service */
  1430. ha->cache_feat = 0;
  1431. if (!force_dma32) {
  1432. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1433. 0, 0);
  1434. if (ok)
  1435. ha->cache_feat = GDT_64BIT;
  1436. }
  1437. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1438. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1439. if (!ok) {
  1440. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1441. ha->hanum, ha->status);
  1442. return 0;
  1443. }
  1444. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1445. cdev_cnt = (ushort)ha->info;
  1446. ha->fw_vers = ha->service;
  1447. #ifdef INT_COAL
  1448. if (ha->type == GDT_PCIMPR) {
  1449. /* set perf. modes */
  1450. pmod = (gdth_perf_modes *)ha->pscratch;
  1451. pmod->version = 1;
  1452. pmod->st_mode = 1; /* enable one status buffer */
  1453. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1454. pmod->st_buff_indx1 = COALINDEX;
  1455. pmod->st_buff_addr2 = 0;
  1456. pmod->st_buff_u_addr2 = 0;
  1457. pmod->st_buff_indx2 = 0;
  1458. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1459. pmod->cmd_mode = 0; // disable all cmd buffers
  1460. pmod->cmd_buff_addr1 = 0;
  1461. pmod->cmd_buff_u_addr1 = 0;
  1462. pmod->cmd_buff_indx1 = 0;
  1463. pmod->cmd_buff_addr2 = 0;
  1464. pmod->cmd_buff_u_addr2 = 0;
  1465. pmod->cmd_buff_indx2 = 0;
  1466. pmod->cmd_buff_size = 0;
  1467. pmod->reserved1 = 0;
  1468. pmod->reserved2 = 0;
  1469. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1470. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1471. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1472. }
  1473. }
  1474. #endif
  1475. /* detect number of buses - try new IOCTL */
  1476. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1477. iocr->hdr.version = 0xffffffff;
  1478. iocr->hdr.list_entries = MAXBUS;
  1479. iocr->hdr.first_chan = 0;
  1480. iocr->hdr.last_chan = MAXBUS-1;
  1481. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1482. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1483. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1484. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1485. ha->bus_cnt = iocr->hdr.chan_count;
  1486. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1487. if (iocr->list[bus_no].proc_id < MAXID)
  1488. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1489. else
  1490. ha->bus_id[bus_no] = 0xff;
  1491. }
  1492. } else {
  1493. /* old method */
  1494. chn = (gdth_getch_str *)ha->pscratch;
  1495. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1496. chn->channel_no = bus_no;
  1497. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1498. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1499. IO_CHANNEL | INVALID_CHANNEL,
  1500. sizeof(gdth_getch_str))) {
  1501. if (bus_no == 0) {
  1502. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1503. ha->hanum, ha->status);
  1504. return 0;
  1505. }
  1506. break;
  1507. }
  1508. if (chn->siop_id < MAXID)
  1509. ha->bus_id[bus_no] = chn->siop_id;
  1510. else
  1511. ha->bus_id[bus_no] = 0xff;
  1512. }
  1513. ha->bus_cnt = (unchar)bus_no;
  1514. }
  1515. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1516. /* read cache configuration */
  1517. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1518. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1519. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1520. ha->hanum, ha->status);
  1521. return 0;
  1522. }
  1523. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1524. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1525. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1526. ha->cpar.write_back,ha->cpar.block_size));
  1527. /* read board info and features */
  1528. ha->more_proc = FALSE;
  1529. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1530. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1531. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1532. sizeof(gdth_binfo_str));
  1533. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1534. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1535. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1536. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1537. ha->more_proc = TRUE;
  1538. }
  1539. } else {
  1540. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1541. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1542. }
  1543. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1544. /* read more informations */
  1545. if (ha->more_proc) {
  1546. /* physical drives, channel addresses */
  1547. ioc = (gdth_iochan_str *)ha->pscratch;
  1548. ioc->hdr.version = 0xffffffff;
  1549. ioc->hdr.list_entries = MAXBUS;
  1550. ioc->hdr.first_chan = 0;
  1551. ioc->hdr.last_chan = MAXBUS-1;
  1552. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1553. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1554. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1555. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1556. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1557. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1558. }
  1559. } else {
  1560. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1561. ha->raw[bus_no].address = IO_CHANNEL;
  1562. ha->raw[bus_no].local_no = bus_no;
  1563. }
  1564. }
  1565. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1566. chn = (gdth_getch_str *)ha->pscratch;
  1567. chn->channel_no = ha->raw[bus_no].local_no;
  1568. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1569. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1570. ha->raw[bus_no].address | INVALID_CHANNEL,
  1571. sizeof(gdth_getch_str))) {
  1572. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1573. TRACE2(("Channel %d: %d phys. drives\n",
  1574. bus_no,chn->drive_cnt));
  1575. }
  1576. if (ha->raw[bus_no].pdev_cnt > 0) {
  1577. drl = (gdth_drlist_str *)ha->pscratch;
  1578. drl->sc_no = ha->raw[bus_no].local_no;
  1579. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1580. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1581. SCSI_DR_LIST | L_CTRL_PATTERN,
  1582. ha->raw[bus_no].address | INVALID_CHANNEL,
  1583. sizeof(gdth_drlist_str))) {
  1584. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1585. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1586. } else {
  1587. ha->raw[bus_no].pdev_cnt = 0;
  1588. }
  1589. }
  1590. }
  1591. /* logical drives */
  1592. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1593. INVALID_CHANNEL,sizeof(ulong32))) {
  1594. drv_cnt = *(ulong32 *)ha->pscratch;
  1595. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1596. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1597. for (j = 0; j < drv_cnt; ++j) {
  1598. drv_no = ((ulong32 *)ha->pscratch)[j];
  1599. if (drv_no < MAX_LDRIVES) {
  1600. ha->hdr[drv_no].is_logdrv = TRUE;
  1601. TRACE2(("Drive %d is log. drive\n",drv_no));
  1602. }
  1603. }
  1604. }
  1605. alst = (gdth_arcdl_str *)ha->pscratch;
  1606. alst->entries_avail = MAX_LDRIVES;
  1607. alst->first_entry = 0;
  1608. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1609. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1610. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1611. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1612. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1613. for (j = 0; j < alst->entries_init; ++j) {
  1614. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1615. ha->hdr[j].is_master = alst->list[j].is_master;
  1616. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1617. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1618. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1619. }
  1620. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1621. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1622. 0, 35 * sizeof(gdth_alist_str))) {
  1623. for (j = 0; j < 35; ++j) {
  1624. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1625. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1626. ha->hdr[j].is_master = alst2->is_master;
  1627. ha->hdr[j].is_parity = alst2->is_parity;
  1628. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1629. ha->hdr[j].master_no = alst2->cd_handle;
  1630. }
  1631. }
  1632. }
  1633. }
  1634. /* initialize raw service */
  1635. ha->raw_feat = 0;
  1636. if (!force_dma32) {
  1637. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1638. if (ok)
  1639. ha->raw_feat = GDT_64BIT;
  1640. }
  1641. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1642. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1643. if (!ok) {
  1644. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1645. ha->hanum, ha->status);
  1646. return 0;
  1647. }
  1648. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1649. /* set/get features raw service (scatter/gather) */
  1650. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1651. 0, 0)) {
  1652. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1653. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1654. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1655. ha->info));
  1656. ha->raw_feat |= (ushort)ha->info;
  1657. }
  1658. }
  1659. /* set/get features cache service (equal to raw service) */
  1660. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1661. SCATTER_GATHER,0)) {
  1662. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1663. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1664. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1665. ha->info));
  1666. ha->cache_feat |= (ushort)ha->info;
  1667. }
  1668. }
  1669. /* reserve drives for raw service */
  1670. if (reserve_mode != 0) {
  1671. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1672. reserve_mode == 1 ? 1 : 3, 0, 0);
  1673. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1674. ha->status));
  1675. }
  1676. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1677. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1678. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1679. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1680. reserve_list[i], reserve_list[i+1],
  1681. reserve_list[i+2], reserve_list[i+3]));
  1682. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1683. reserve_list[i+1], reserve_list[i+2] |
  1684. (reserve_list[i+3] << 8))) {
  1685. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1686. ha->hanum, ha->status);
  1687. }
  1688. }
  1689. }
  1690. /* Determine OEM string using IOCTL */
  1691. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1692. oemstr->params.ctl_version = 0x01;
  1693. oemstr->params.buffer_size = sizeof(oemstr->text);
  1694. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1695. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1696. sizeof(gdth_oem_str_ioctl))) {
  1697. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1698. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1699. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1700. /* Save the Host Drive inquiry data */
  1701. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1702. sizeof(ha->oem_name));
  1703. } else {
  1704. /* Old method, based on PCI ID */
  1705. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1706. printk("GDT-HA %d: Name: %s\n",
  1707. ha->hanum, ha->binfo.type_string);
  1708. if (ha->oem_id == OEM_ID_INTEL)
  1709. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1710. else
  1711. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1712. }
  1713. /* scanning for host drives */
  1714. for (i = 0; i < cdev_cnt; ++i)
  1715. gdth_analyse_hdrive(ha, i);
  1716. TRACE(("gdth_search_drives() OK\n"));
  1717. return 1;
  1718. }
  1719. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1720. {
  1721. ulong32 drv_cyls;
  1722. int drv_hds, drv_secs;
  1723. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1724. if (hdrive >= MAX_HDRIVES)
  1725. return 0;
  1726. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1727. return 0;
  1728. ha->hdr[hdrive].present = TRUE;
  1729. ha->hdr[hdrive].size = ha->info;
  1730. /* evaluate mapping (sectors per head, heads per cylinder) */
  1731. ha->hdr[hdrive].size &= ~SECS32;
  1732. if (ha->info2 == 0) {
  1733. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1734. } else {
  1735. drv_hds = ha->info2 & 0xff;
  1736. drv_secs = (ha->info2 >> 8) & 0xff;
  1737. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1738. }
  1739. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1740. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1741. /* round size */
  1742. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1743. if (ha->cache_feat & GDT_64BIT) {
  1744. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1745. && ha->info2 != 0) {
  1746. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1747. }
  1748. }
  1749. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1750. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1751. /* get informations about device */
  1752. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1753. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1754. hdrive,ha->info));
  1755. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1756. }
  1757. /* cluster info */
  1758. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1759. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1760. hdrive,ha->info));
  1761. if (!shared_access)
  1762. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1763. }
  1764. /* R/W attributes */
  1765. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1766. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1767. hdrive,ha->info));
  1768. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1769. }
  1770. return 1;
  1771. }
  1772. /* command queueing/sending functions */
  1773. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1774. {
  1775. register Scsi_Cmnd *pscp;
  1776. register Scsi_Cmnd *nscp;
  1777. ulong flags;
  1778. unchar b, t;
  1779. TRACE(("gdth_putq() priority %d\n",priority));
  1780. spin_lock_irqsave(&ha->smp_lock, flags);
  1781. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  1782. scp->SCp.this_residual = (int)priority;
  1783. b = scp->device->channel;
  1784. t = scp->device->id;
  1785. if (priority >= DEFAULT_PRI) {
  1786. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1787. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1788. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1789. scp->SCp.buffers_residual = gdth_update_timeout(scp, 0);
  1790. }
  1791. }
  1792. }
  1793. if (ha->req_first==NULL) {
  1794. ha->req_first = scp; /* queue was empty */
  1795. scp->SCp.ptr = NULL;
  1796. } else { /* queue not empty */
  1797. pscp = ha->req_first;
  1798. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1799. /* priority: 0-highest,..,0xff-lowest */
  1800. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  1801. pscp = nscp;
  1802. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1803. }
  1804. pscp->SCp.ptr = (char *)scp;
  1805. scp->SCp.ptr = (char *)nscp;
  1806. }
  1807. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1808. #ifdef GDTH_STATISTICS
  1809. flags = 0;
  1810. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1811. ++flags;
  1812. if (max_rq < flags) {
  1813. max_rq = flags;
  1814. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1815. }
  1816. #endif
  1817. }
  1818. static void gdth_next(gdth_ha_str *ha)
  1819. {
  1820. register Scsi_Cmnd *pscp;
  1821. register Scsi_Cmnd *nscp;
  1822. unchar b, t, l, firsttime;
  1823. unchar this_cmd, next_cmd;
  1824. ulong flags = 0;
  1825. int cmd_index;
  1826. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1827. if (!gdth_polling)
  1828. spin_lock_irqsave(&ha->smp_lock, flags);
  1829. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1830. this_cmd = firsttime = TRUE;
  1831. next_cmd = gdth_polling ? FALSE:TRUE;
  1832. cmd_index = 0;
  1833. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1834. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1835. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1836. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1837. b = nscp->device->channel;
  1838. t = nscp->device->id;
  1839. l = nscp->device->lun;
  1840. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  1841. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1842. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1843. continue;
  1844. }
  1845. } else
  1846. b = t = l = 0;
  1847. if (firsttime) {
  1848. if (gdth_test_busy(ha)) { /* controller busy ? */
  1849. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1850. if (!gdth_polling) {
  1851. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1852. return;
  1853. }
  1854. while (gdth_test_busy(ha))
  1855. gdth_delay(1);
  1856. }
  1857. firsttime = FALSE;
  1858. }
  1859. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1860. if (nscp->SCp.phase == -1) {
  1861. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  1862. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1863. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1864. b, t, l));
  1865. /* TEST_UNIT_READY -> set scan mode */
  1866. if ((ha->scan_mode & 0x0f) == 0) {
  1867. if (b == 0 && t == 0 && l == 0) {
  1868. ha->scan_mode |= 1;
  1869. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1870. }
  1871. } else if ((ha->scan_mode & 0x0f) == 1) {
  1872. if (b == 0 && ((t == 0 && l == 1) ||
  1873. (t == 1 && l == 0))) {
  1874. nscp->SCp.sent_command = GDT_SCAN_START;
  1875. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1876. | SCSIRAWSERVICE;
  1877. ha->scan_mode = 0x12;
  1878. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1879. ha->scan_mode));
  1880. } else {
  1881. ha->scan_mode &= 0x10;
  1882. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1883. }
  1884. } else if (ha->scan_mode == 0x12) {
  1885. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1886. nscp->SCp.phase = SCSIRAWSERVICE;
  1887. nscp->SCp.sent_command = GDT_SCAN_END;
  1888. ha->scan_mode &= 0x10;
  1889. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1890. ha->scan_mode));
  1891. }
  1892. }
  1893. }
  1894. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1895. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1896. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1897. /* always GDT_CLUST_INFO! */
  1898. nscp->SCp.sent_command = GDT_CLUST_INFO;
  1899. }
  1900. }
  1901. }
  1902. if (nscp->SCp.sent_command != -1) {
  1903. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  1904. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1905. this_cmd = FALSE;
  1906. next_cmd = FALSE;
  1907. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  1908. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1909. this_cmd = FALSE;
  1910. next_cmd = FALSE;
  1911. } else {
  1912. memset((char*)nscp->sense_buffer,0,16);
  1913. nscp->sense_buffer[0] = 0x70;
  1914. nscp->sense_buffer[2] = NOT_READY;
  1915. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1916. if (!nscp->SCp.have_data_in)
  1917. nscp->SCp.have_data_in++;
  1918. else
  1919. gdth_scsi_done(nscp);
  1920. }
  1921. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  1922. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1923. this_cmd = FALSE;
  1924. next_cmd = FALSE;
  1925. } else if (b != ha->virt_bus) {
  1926. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1927. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1928. this_cmd = FALSE;
  1929. else
  1930. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1931. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1932. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1933. nscp->cmnd[0], b, t, l));
  1934. nscp->result = DID_BAD_TARGET << 16;
  1935. if (!nscp->SCp.have_data_in)
  1936. nscp->SCp.have_data_in++;
  1937. else
  1938. gdth_scsi_done(nscp);
  1939. } else {
  1940. switch (nscp->cmnd[0]) {
  1941. case TEST_UNIT_READY:
  1942. case INQUIRY:
  1943. case REQUEST_SENSE:
  1944. case READ_CAPACITY:
  1945. case VERIFY:
  1946. case START_STOP:
  1947. case MODE_SENSE:
  1948. case SERVICE_ACTION_IN:
  1949. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1950. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1951. nscp->cmnd[4],nscp->cmnd[5]));
  1952. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1953. /* return UNIT_ATTENTION */
  1954. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1955. nscp->cmnd[0], t));
  1956. ha->hdr[t].media_changed = FALSE;
  1957. memset((char*)nscp->sense_buffer,0,16);
  1958. nscp->sense_buffer[0] = 0x70;
  1959. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1960. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1961. if (!nscp->SCp.have_data_in)
  1962. nscp->SCp.have_data_in++;
  1963. else
  1964. gdth_scsi_done(nscp);
  1965. } else if (gdth_internal_cache_cmd(ha, nscp))
  1966. gdth_scsi_done(nscp);
  1967. break;
  1968. case ALLOW_MEDIUM_REMOVAL:
  1969. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1970. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1971. nscp->cmnd[4],nscp->cmnd[5]));
  1972. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1973. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1974. nscp->result = DID_OK << 16;
  1975. nscp->sense_buffer[0] = 0;
  1976. if (!nscp->SCp.have_data_in)
  1977. nscp->SCp.have_data_in++;
  1978. else
  1979. gdth_scsi_done(nscp);
  1980. } else {
  1981. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1982. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1983. nscp->cmnd[4],nscp->cmnd[3]));
  1984. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1985. this_cmd = FALSE;
  1986. }
  1987. break;
  1988. case RESERVE:
  1989. case RELEASE:
  1990. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1991. "RESERVE" : "RELEASE"));
  1992. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1993. this_cmd = FALSE;
  1994. break;
  1995. case READ_6:
  1996. case WRITE_6:
  1997. case READ_10:
  1998. case WRITE_10:
  1999. case READ_16:
  2000. case WRITE_16:
  2001. if (ha->hdr[t].media_changed) {
  2002. /* return UNIT_ATTENTION */
  2003. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2004. nscp->cmnd[0], t));
  2005. ha->hdr[t].media_changed = FALSE;
  2006. memset((char*)nscp->sense_buffer,0,16);
  2007. nscp->sense_buffer[0] = 0x70;
  2008. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2009. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2010. if (!nscp->SCp.have_data_in)
  2011. nscp->SCp.have_data_in++;
  2012. else
  2013. gdth_scsi_done(nscp);
  2014. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2015. this_cmd = FALSE;
  2016. break;
  2017. default:
  2018. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2019. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2020. nscp->cmnd[4],nscp->cmnd[5]));
  2021. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2022. ha->hanum, nscp->cmnd[0]);
  2023. nscp->result = DID_ABORT << 16;
  2024. if (!nscp->SCp.have_data_in)
  2025. nscp->SCp.have_data_in++;
  2026. else
  2027. gdth_scsi_done(nscp);
  2028. break;
  2029. }
  2030. }
  2031. if (!this_cmd)
  2032. break;
  2033. if (nscp == ha->req_first)
  2034. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2035. else
  2036. pscp->SCp.ptr = nscp->SCp.ptr;
  2037. if (!next_cmd)
  2038. break;
  2039. }
  2040. if (ha->cmd_cnt > 0) {
  2041. gdth_release_event(ha);
  2042. }
  2043. if (!gdth_polling)
  2044. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2045. if (gdth_polling && ha->cmd_cnt > 0) {
  2046. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2047. printk("GDT-HA %d: Command %d timed out !\n",
  2048. ha->hanum, cmd_index);
  2049. }
  2050. }
  2051. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2052. char *buffer,ushort count)
  2053. {
  2054. ushort cpcount,i;
  2055. ushort cpsum,cpnow;
  2056. struct scatterlist *sl;
  2057. char *address;
  2058. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2059. if (scp->use_sg) {
  2060. sl = (struct scatterlist *)scp->request_buffer;
  2061. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2062. unsigned long flags;
  2063. cpnow = (ushort)sl->length;
  2064. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2065. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2066. if (cpsum+cpnow > cpcount)
  2067. cpnow = cpcount - cpsum;
  2068. cpsum += cpnow;
  2069. if (!sl->page) {
  2070. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2071. ha->hanum);
  2072. return;
  2073. }
  2074. local_irq_save(flags);
  2075. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2076. memcpy(address,buffer,cpnow);
  2077. flush_dcache_page(sl->page);
  2078. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2079. local_irq_restore(flags);
  2080. if (cpsum == cpcount)
  2081. break;
  2082. buffer += cpnow;
  2083. }
  2084. } else {
  2085. TRACE(("copy_internal() count %d\n",cpcount));
  2086. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2087. }
  2088. }
  2089. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2090. {
  2091. unchar t;
  2092. gdth_inq_data inq;
  2093. gdth_rdcap_data rdc;
  2094. gdth_sense_data sd;
  2095. gdth_modep_data mpd;
  2096. t = scp->device->id;
  2097. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2098. scp->cmnd[0],t));
  2099. scp->result = DID_OK << 16;
  2100. scp->sense_buffer[0] = 0;
  2101. switch (scp->cmnd[0]) {
  2102. case TEST_UNIT_READY:
  2103. case VERIFY:
  2104. case START_STOP:
  2105. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2106. break;
  2107. case INQUIRY:
  2108. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2109. t,ha->hdr[t].devtype));
  2110. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2111. /* you can here set all disks to removable, if you want to do
  2112. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2113. inq.modif_rmb = 0x00;
  2114. if ((ha->hdr[t].devtype & 1) ||
  2115. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2116. inq.modif_rmb = 0x80;
  2117. inq.version = 2;
  2118. inq.resp_aenc = 2;
  2119. inq.add_length= 32;
  2120. strcpy(inq.vendor,ha->oem_name);
  2121. sprintf(inq.product,"Host Drive #%02d",t);
  2122. strcpy(inq.revision," ");
  2123. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2124. break;
  2125. case REQUEST_SENSE:
  2126. TRACE2(("Request sense hdrive %d\n",t));
  2127. sd.errorcode = 0x70;
  2128. sd.segno = 0x00;
  2129. sd.key = NO_SENSE;
  2130. sd.info = 0;
  2131. sd.add_length= 0;
  2132. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2133. break;
  2134. case MODE_SENSE:
  2135. TRACE2(("Mode sense hdrive %d\n",t));
  2136. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2137. mpd.hd.data_length = sizeof(gdth_modep_data);
  2138. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2139. mpd.hd.bd_length = sizeof(mpd.bd);
  2140. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2141. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2142. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2143. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2144. break;
  2145. case READ_CAPACITY:
  2146. TRACE2(("Read capacity hdrive %d\n",t));
  2147. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2148. rdc.last_block_no = 0xffffffff;
  2149. else
  2150. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2151. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2152. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2153. break;
  2154. case SERVICE_ACTION_IN:
  2155. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2156. (ha->cache_feat & GDT_64BIT)) {
  2157. gdth_rdcap16_data rdc16;
  2158. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2159. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2160. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2161. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2162. sizeof(gdth_rdcap16_data));
  2163. } else {
  2164. scp->result = DID_ABORT << 16;
  2165. }
  2166. break;
  2167. default:
  2168. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2169. break;
  2170. }
  2171. if (!scp->SCp.have_data_in)
  2172. scp->SCp.have_data_in++;
  2173. else
  2174. return 1;
  2175. return 0;
  2176. }
  2177. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2178. {
  2179. register gdth_cmd_str *cmdp;
  2180. struct scatterlist *sl;
  2181. ulong32 cnt, blockcnt;
  2182. ulong64 no, blockno;
  2183. dma_addr_t phys_addr;
  2184. int i, cmd_index, read_write, sgcnt, mode64;
  2185. struct page *page;
  2186. ulong offset;
  2187. cmdp = ha->pccb;
  2188. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2189. scp->cmnd[0],scp->cmd_len,hdrive));
  2190. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2191. return 0;
  2192. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2193. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2194. not required, should not occur due to error return on
  2195. READ_CAPACITY_16 */
  2196. cmdp->Service = CACHESERVICE;
  2197. cmdp->RequestBuffer = scp;
  2198. /* search free command index */
  2199. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2200. TRACE(("GDT: No free command index found\n"));
  2201. return 0;
  2202. }
  2203. /* if it's the first command, set command semaphore */
  2204. if (ha->cmd_cnt == 0)
  2205. gdth_set_sema0(ha);
  2206. /* fill command */
  2207. read_write = 0;
  2208. if (scp->SCp.sent_command != -1)
  2209. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2210. else if (scp->cmnd[0] == RESERVE)
  2211. cmdp->OpCode = GDT_RESERVE_DRV;
  2212. else if (scp->cmnd[0] == RELEASE)
  2213. cmdp->OpCode = GDT_RELEASE_DRV;
  2214. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2215. if (scp->cmnd[4] & 1) /* prevent ? */
  2216. cmdp->OpCode = GDT_MOUNT;
  2217. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2218. cmdp->OpCode = GDT_UNMOUNT;
  2219. else
  2220. cmdp->OpCode = GDT_FLUSH;
  2221. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2222. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2223. ) {
  2224. read_write = 1;
  2225. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2226. (ha->cache_feat & GDT_WR_THROUGH)))
  2227. cmdp->OpCode = GDT_WRITE_THR;
  2228. else
  2229. cmdp->OpCode = GDT_WRITE;
  2230. } else {
  2231. read_write = 2;
  2232. cmdp->OpCode = GDT_READ;
  2233. }
  2234. cmdp->BoardNode = LOCALBOARD;
  2235. if (mode64) {
  2236. cmdp->u.cache64.DeviceNo = hdrive;
  2237. cmdp->u.cache64.BlockNo = 1;
  2238. cmdp->u.cache64.sg_canz = 0;
  2239. } else {
  2240. cmdp->u.cache.DeviceNo = hdrive;
  2241. cmdp->u.cache.BlockNo = 1;
  2242. cmdp->u.cache.sg_canz = 0;
  2243. }
  2244. if (read_write) {
  2245. if (scp->cmd_len == 16) {
  2246. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2247. blockno = be64_to_cpu(no);
  2248. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2249. blockcnt = be32_to_cpu(cnt);
  2250. } else if (scp->cmd_len == 10) {
  2251. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2252. blockno = be32_to_cpu(no);
  2253. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2254. blockcnt = be16_to_cpu(cnt);
  2255. } else {
  2256. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2257. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2258. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2259. }
  2260. if (mode64) {
  2261. cmdp->u.cache64.BlockNo = blockno;
  2262. cmdp->u.cache64.BlockCnt = blockcnt;
  2263. } else {
  2264. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2265. cmdp->u.cache.BlockCnt = blockcnt;
  2266. }
  2267. if (scp->use_sg) {
  2268. sl = (struct scatterlist *)scp->request_buffer;
  2269. sgcnt = scp->use_sg;
  2270. scp->SCp.Status = GDTH_MAP_SG;
  2271. scp->SCp.Message = (read_write == 1 ?
  2272. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2273. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2274. if (mode64) {
  2275. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2276. cmdp->u.cache64.sg_canz = sgcnt;
  2277. for (i=0; i<sgcnt; ++i,++sl) {
  2278. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2279. #ifdef GDTH_DMA_STATISTICS
  2280. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2281. ha->dma64_cnt++;
  2282. else
  2283. ha->dma32_cnt++;
  2284. #endif
  2285. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2286. }
  2287. } else {
  2288. cmdp->u.cache.DestAddr= 0xffffffff;
  2289. cmdp->u.cache.sg_canz = sgcnt;
  2290. for (i=0; i<sgcnt; ++i,++sl) {
  2291. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2292. #ifdef GDTH_DMA_STATISTICS
  2293. ha->dma32_cnt++;
  2294. #endif
  2295. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2296. }
  2297. }
  2298. #ifdef GDTH_STATISTICS
  2299. if (max_sg < (ulong32)sgcnt) {
  2300. max_sg = (ulong32)sgcnt;
  2301. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2302. }
  2303. #endif
  2304. } else if (scp->request_bufflen) {
  2305. scp->SCp.Status = GDTH_MAP_SINGLE;
  2306. scp->SCp.Message = (read_write == 1 ?
  2307. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2308. page = virt_to_page(scp->request_buffer);
  2309. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2310. phys_addr = pci_map_page(ha->pdev,page,offset,
  2311. scp->request_bufflen,scp->SCp.Message);
  2312. scp->SCp.dma_handle = phys_addr;
  2313. if (mode64) {
  2314. if (ha->cache_feat & SCATTER_GATHER) {
  2315. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2316. cmdp->u.cache64.sg_canz = 1;
  2317. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2318. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2319. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2320. } else {
  2321. cmdp->u.cache64.DestAddr = phys_addr;
  2322. cmdp->u.cache64.sg_canz= 0;
  2323. }
  2324. } else {
  2325. if (ha->cache_feat & SCATTER_GATHER) {
  2326. cmdp->u.cache.DestAddr = 0xffffffff;
  2327. cmdp->u.cache.sg_canz = 1;
  2328. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2329. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2330. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2331. } else {
  2332. cmdp->u.cache.DestAddr = phys_addr;
  2333. cmdp->u.cache.sg_canz= 0;
  2334. }
  2335. }
  2336. }
  2337. }
  2338. /* evaluate command size, check space */
  2339. if (mode64) {
  2340. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2341. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2342. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2343. cmdp->u.cache64.sg_lst[0].sg_len));
  2344. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2345. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2346. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2347. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2348. } else {
  2349. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2350. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2351. cmdp->u.cache.sg_lst[0].sg_ptr,
  2352. cmdp->u.cache.sg_lst[0].sg_len));
  2353. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2354. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2355. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2356. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2357. }
  2358. if (ha->cmd_len & 3)
  2359. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2360. if (ha->cmd_cnt > 0) {
  2361. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2362. ha->ic_all_size) {
  2363. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2364. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2365. return 0;
  2366. }
  2367. }
  2368. /* copy command */
  2369. gdth_copy_command(ha);
  2370. return cmd_index;
  2371. }
  2372. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2373. {
  2374. register gdth_cmd_str *cmdp;
  2375. struct scatterlist *sl;
  2376. ushort i;
  2377. dma_addr_t phys_addr, sense_paddr;
  2378. int cmd_index, sgcnt, mode64;
  2379. unchar t,l;
  2380. struct page *page;
  2381. ulong offset;
  2382. t = scp->device->id;
  2383. l = scp->device->lun;
  2384. cmdp = ha->pccb;
  2385. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2386. scp->cmnd[0],b,t,l));
  2387. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2388. return 0;
  2389. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2390. cmdp->Service = SCSIRAWSERVICE;
  2391. cmdp->RequestBuffer = scp;
  2392. /* search free command index */
  2393. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2394. TRACE(("GDT: No free command index found\n"));
  2395. return 0;
  2396. }
  2397. /* if it's the first command, set command semaphore */
  2398. if (ha->cmd_cnt == 0)
  2399. gdth_set_sema0(ha);
  2400. /* fill command */
  2401. if (scp->SCp.sent_command != -1) {
  2402. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2403. cmdp->BoardNode = LOCALBOARD;
  2404. if (mode64) {
  2405. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2406. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2407. cmdp->OpCode, cmdp->u.raw64.direction));
  2408. /* evaluate command size */
  2409. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2410. } else {
  2411. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2412. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2413. cmdp->OpCode, cmdp->u.raw.direction));
  2414. /* evaluate command size */
  2415. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2416. }
  2417. } else {
  2418. page = virt_to_page(scp->sense_buffer);
  2419. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2420. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2421. 16,PCI_DMA_FROMDEVICE);
  2422. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2423. /* high part, if 64bit */
  2424. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2425. cmdp->OpCode = GDT_WRITE; /* always */
  2426. cmdp->BoardNode = LOCALBOARD;
  2427. if (mode64) {
  2428. cmdp->u.raw64.reserved = 0;
  2429. cmdp->u.raw64.mdisc_time = 0;
  2430. cmdp->u.raw64.mcon_time = 0;
  2431. cmdp->u.raw64.clen = scp->cmd_len;
  2432. cmdp->u.raw64.target = t;
  2433. cmdp->u.raw64.lun = l;
  2434. cmdp->u.raw64.bus = b;
  2435. cmdp->u.raw64.priority = 0;
  2436. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2437. cmdp->u.raw64.sense_len = 16;
  2438. cmdp->u.raw64.sense_data = sense_paddr;
  2439. cmdp->u.raw64.direction =
  2440. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2441. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2442. cmdp->u.raw64.sg_ranz = 0;
  2443. } else {
  2444. cmdp->u.raw.reserved = 0;
  2445. cmdp->u.raw.mdisc_time = 0;
  2446. cmdp->u.raw.mcon_time = 0;
  2447. cmdp->u.raw.clen = scp->cmd_len;
  2448. cmdp->u.raw.target = t;
  2449. cmdp->u.raw.lun = l;
  2450. cmdp->u.raw.bus = b;
  2451. cmdp->u.raw.priority = 0;
  2452. cmdp->u.raw.link_p = 0;
  2453. cmdp->u.raw.sdlen = scp->request_bufflen;
  2454. cmdp->u.raw.sense_len = 16;
  2455. cmdp->u.raw.sense_data = sense_paddr;
  2456. cmdp->u.raw.direction =
  2457. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2458. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2459. cmdp->u.raw.sg_ranz = 0;
  2460. }
  2461. if (scp->use_sg) {
  2462. sl = (struct scatterlist *)scp->request_buffer;
  2463. sgcnt = scp->use_sg;
  2464. scp->SCp.Status = GDTH_MAP_SG;
  2465. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2466. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2467. if (mode64) {
  2468. cmdp->u.raw64.sdata = (ulong64)-1;
  2469. cmdp->u.raw64.sg_ranz = sgcnt;
  2470. for (i=0; i<sgcnt; ++i,++sl) {
  2471. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2472. #ifdef GDTH_DMA_STATISTICS
  2473. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2474. ha->dma64_cnt++;
  2475. else
  2476. ha->dma32_cnt++;
  2477. #endif
  2478. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2479. }
  2480. } else {
  2481. cmdp->u.raw.sdata = 0xffffffff;
  2482. cmdp->u.raw.sg_ranz = sgcnt;
  2483. for (i=0; i<sgcnt; ++i,++sl) {
  2484. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2485. #ifdef GDTH_DMA_STATISTICS
  2486. ha->dma32_cnt++;
  2487. #endif
  2488. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2489. }
  2490. }
  2491. #ifdef GDTH_STATISTICS
  2492. if (max_sg < sgcnt) {
  2493. max_sg = sgcnt;
  2494. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2495. }
  2496. #endif
  2497. } else if (scp->request_bufflen) {
  2498. scp->SCp.Status = GDTH_MAP_SINGLE;
  2499. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2500. page = virt_to_page(scp->request_buffer);
  2501. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2502. phys_addr = pci_map_page(ha->pdev,page,offset,
  2503. scp->request_bufflen,scp->SCp.Message);
  2504. scp->SCp.dma_handle = phys_addr;
  2505. if (mode64) {
  2506. if (ha->raw_feat & SCATTER_GATHER) {
  2507. cmdp->u.raw64.sdata = (ulong64)-1;
  2508. cmdp->u.raw64.sg_ranz= 1;
  2509. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2510. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2511. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2512. } else {
  2513. cmdp->u.raw64.sdata = phys_addr;
  2514. cmdp->u.raw64.sg_ranz= 0;
  2515. }
  2516. } else {
  2517. if (ha->raw_feat & SCATTER_GATHER) {
  2518. cmdp->u.raw.sdata = 0xffffffff;
  2519. cmdp->u.raw.sg_ranz= 1;
  2520. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2521. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2522. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2523. } else {
  2524. cmdp->u.raw.sdata = phys_addr;
  2525. cmdp->u.raw.sg_ranz= 0;
  2526. }
  2527. }
  2528. }
  2529. if (mode64) {
  2530. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2531. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2532. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2533. cmdp->u.raw64.sg_lst[0].sg_len));
  2534. /* evaluate command size */
  2535. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2536. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2537. } else {
  2538. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2539. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2540. cmdp->u.raw.sg_lst[0].sg_ptr,
  2541. cmdp->u.raw.sg_lst[0].sg_len));
  2542. /* evaluate command size */
  2543. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2544. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2545. }
  2546. }
  2547. /* check space */
  2548. if (ha->cmd_len & 3)
  2549. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2550. if (ha->cmd_cnt > 0) {
  2551. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2552. ha->ic_all_size) {
  2553. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2554. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2555. return 0;
  2556. }
  2557. }
  2558. /* copy command */
  2559. gdth_copy_command(ha);
  2560. return cmd_index;
  2561. }
  2562. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2563. {
  2564. register gdth_cmd_str *cmdp;
  2565. int cmd_index;
  2566. cmdp= ha->pccb;
  2567. TRACE2(("gdth_special_cmd(): "));
  2568. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2569. return 0;
  2570. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2571. cmdp->RequestBuffer = scp;
  2572. /* search free command index */
  2573. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2574. TRACE(("GDT: No free command index found\n"));
  2575. return 0;
  2576. }
  2577. /* if it's the first command, set command semaphore */
  2578. if (ha->cmd_cnt == 0)
  2579. gdth_set_sema0(ha);
  2580. /* evaluate command size, check space */
  2581. if (cmdp->OpCode == GDT_IOCTL) {
  2582. TRACE2(("IOCTL\n"));
  2583. ha->cmd_len =
  2584. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2585. } else if (cmdp->Service == CACHESERVICE) {
  2586. TRACE2(("cache command %d\n",cmdp->OpCode));
  2587. if (ha->cache_feat & GDT_64BIT)
  2588. ha->cmd_len =
  2589. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2590. else
  2591. ha->cmd_len =
  2592. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2593. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2594. TRACE2(("raw command %d\n",cmdp->OpCode));
  2595. if (ha->raw_feat & GDT_64BIT)
  2596. ha->cmd_len =
  2597. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2598. else
  2599. ha->cmd_len =
  2600. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2601. }
  2602. if (ha->cmd_len & 3)
  2603. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2604. if (ha->cmd_cnt > 0) {
  2605. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2606. ha->ic_all_size) {
  2607. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2608. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2609. return 0;
  2610. }
  2611. }
  2612. /* copy command */
  2613. gdth_copy_command(ha);
  2614. return cmd_index;
  2615. }
  2616. /* Controller event handling functions */
  2617. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2618. ushort idx, gdth_evt_data *evt)
  2619. {
  2620. gdth_evt_str *e;
  2621. struct timeval tv;
  2622. /* no GDTH_LOCK_HA() ! */
  2623. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2624. if (source == 0) /* no source -> no event */
  2625. return NULL;
  2626. if (ebuffer[elastidx].event_source == source &&
  2627. ebuffer[elastidx].event_idx == idx &&
  2628. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2629. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2630. (char *)&evt->eu, evt->size)) ||
  2631. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2632. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2633. (char *)&evt->event_string)))) {
  2634. e = &ebuffer[elastidx];
  2635. do_gettimeofday(&tv);
  2636. e->last_stamp = tv.tv_sec;
  2637. ++e->same_count;
  2638. } else {
  2639. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2640. ++elastidx;
  2641. if (elastidx == MAX_EVENTS)
  2642. elastidx = 0;
  2643. if (elastidx == eoldidx) { /* reached mark ? */
  2644. ++eoldidx;
  2645. if (eoldidx == MAX_EVENTS)
  2646. eoldidx = 0;
  2647. }
  2648. }
  2649. e = &ebuffer[elastidx];
  2650. e->event_source = source;
  2651. e->event_idx = idx;
  2652. do_gettimeofday(&tv);
  2653. e->first_stamp = e->last_stamp = tv.tv_sec;
  2654. e->same_count = 1;
  2655. e->event_data = *evt;
  2656. e->application = 0;
  2657. }
  2658. return e;
  2659. }
  2660. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2661. {
  2662. gdth_evt_str *e;
  2663. int eindex;
  2664. ulong flags;
  2665. TRACE2(("gdth_read_event() handle %d\n", handle));
  2666. spin_lock_irqsave(&ha->smp_lock, flags);
  2667. if (handle == -1)
  2668. eindex = eoldidx;
  2669. else
  2670. eindex = handle;
  2671. estr->event_source = 0;
  2672. if (eindex >= MAX_EVENTS) {
  2673. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2674. return eindex;
  2675. }
  2676. e = &ebuffer[eindex];
  2677. if (e->event_source != 0) {
  2678. if (eindex != elastidx) {
  2679. if (++eindex == MAX_EVENTS)
  2680. eindex = 0;
  2681. } else {
  2682. eindex = -1;
  2683. }
  2684. memcpy(estr, e, sizeof(gdth_evt_str));
  2685. }
  2686. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2687. return eindex;
  2688. }
  2689. static void gdth_readapp_event(gdth_ha_str *ha,
  2690. unchar application, gdth_evt_str *estr)
  2691. {
  2692. gdth_evt_str *e;
  2693. int eindex;
  2694. ulong flags;
  2695. unchar found = FALSE;
  2696. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2697. spin_lock_irqsave(&ha->smp_lock, flags);
  2698. eindex = eoldidx;
  2699. for (;;) {
  2700. e = &ebuffer[eindex];
  2701. if (e->event_source == 0)
  2702. break;
  2703. if ((e->application & application) == 0) {
  2704. e->application |= application;
  2705. found = TRUE;
  2706. break;
  2707. }
  2708. if (eindex == elastidx)
  2709. break;
  2710. if (++eindex == MAX_EVENTS)
  2711. eindex = 0;
  2712. }
  2713. if (found)
  2714. memcpy(estr, e, sizeof(gdth_evt_str));
  2715. else
  2716. estr->event_source = 0;
  2717. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2718. }
  2719. static void gdth_clear_events(void)
  2720. {
  2721. TRACE(("gdth_clear_events()"));
  2722. eoldidx = elastidx = 0;
  2723. ebuffer[0].event_source = 0;
  2724. }
  2725. /* SCSI interface functions */
  2726. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  2727. int gdth_from_wait, int* pIndex)
  2728. {
  2729. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2730. gdt6_dpram_str __iomem *dp6_ptr;
  2731. gdt2_dpram_str __iomem *dp2_ptr;
  2732. Scsi_Cmnd *scp;
  2733. int rval, i;
  2734. unchar IStatus;
  2735. ushort Service;
  2736. ulong flags = 0;
  2737. #ifdef INT_COAL
  2738. int coalesced = FALSE;
  2739. int next = FALSE;
  2740. gdth_coal_status *pcs = NULL;
  2741. int act_int_coal = 0;
  2742. #endif
  2743. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  2744. /* if polling and not from gdth_wait() -> return */
  2745. if (gdth_polling) {
  2746. if (!gdth_from_wait) {
  2747. return IRQ_HANDLED;
  2748. }
  2749. }
  2750. if (!gdth_polling)
  2751. spin_lock_irqsave(&ha->smp_lock, flags);
  2752. /* search controller */
  2753. if (0 == (IStatus = gdth_get_status(ha, irq))) {
  2754. /* spurious interrupt */
  2755. if (!gdth_polling)
  2756. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2757. return IRQ_HANDLED;
  2758. }
  2759. #ifdef GDTH_STATISTICS
  2760. ++act_ints;
  2761. #endif
  2762. #ifdef INT_COAL
  2763. /* See if the fw is returning coalesced status */
  2764. if (IStatus == COALINDEX) {
  2765. /* Coalesced status. Setup the initial status
  2766. buffer pointer and flags */
  2767. pcs = ha->coal_stat;
  2768. coalesced = TRUE;
  2769. next = TRUE;
  2770. }
  2771. do {
  2772. if (coalesced) {
  2773. /* For coalesced requests all status
  2774. information is found in the status buffer */
  2775. IStatus = (unchar)(pcs->status & 0xff);
  2776. }
  2777. #endif
  2778. if (ha->type == GDT_EISA) {
  2779. if (IStatus & 0x80) { /* error flag */
  2780. IStatus &= ~0x80;
  2781. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2782. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2783. } else /* no error */
  2784. ha->status = S_OK;
  2785. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2786. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2787. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2788. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2789. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2790. } else if (ha->type == GDT_ISA) {
  2791. dp2_ptr = ha->brd;
  2792. if (IStatus & 0x80) { /* error flag */
  2793. IStatus &= ~0x80;
  2794. ha->status = readw(&dp2_ptr->u.ic.Status);
  2795. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2796. } else /* no error */
  2797. ha->status = S_OK;
  2798. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2799. ha->service = readw(&dp2_ptr->u.ic.Service);
  2800. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2801. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2802. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2803. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2804. } else if (ha->type == GDT_PCI) {
  2805. dp6_ptr = ha->brd;
  2806. if (IStatus & 0x80) { /* error flag */
  2807. IStatus &= ~0x80;
  2808. ha->status = readw(&dp6_ptr->u.ic.Status);
  2809. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2810. } else /* no error */
  2811. ha->status = S_OK;
  2812. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2813. ha->service = readw(&dp6_ptr->u.ic.Service);
  2814. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2815. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2816. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2817. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2818. } else if (ha->type == GDT_PCINEW) {
  2819. if (IStatus & 0x80) { /* error flag */
  2820. IStatus &= ~0x80;
  2821. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2822. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2823. } else
  2824. ha->status = S_OK;
  2825. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2826. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2827. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2828. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2829. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2830. } else if (ha->type == GDT_PCIMPR) {
  2831. dp6m_ptr = ha->brd;
  2832. if (IStatus & 0x80) { /* error flag */
  2833. IStatus &= ~0x80;
  2834. #ifdef INT_COAL
  2835. if (coalesced)
  2836. ha->status = pcs->ext_status & 0xffff;
  2837. else
  2838. #endif
  2839. ha->status = readw(&dp6m_ptr->i960r.status);
  2840. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2841. } else /* no error */
  2842. ha->status = S_OK;
  2843. #ifdef INT_COAL
  2844. /* get information */
  2845. if (coalesced) {
  2846. ha->info = pcs->info0;
  2847. ha->info2 = pcs->info1;
  2848. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2849. } else
  2850. #endif
  2851. {
  2852. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2853. ha->service = readw(&dp6m_ptr->i960r.service);
  2854. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2855. }
  2856. /* event string */
  2857. if (IStatus == ASYNCINDEX) {
  2858. if (ha->service != SCREENSERVICE &&
  2859. (ha->fw_vers & 0xff) >= 0x1a) {
  2860. ha->dvr.severity = readb
  2861. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2862. for (i = 0; i < 256; ++i) {
  2863. ha->dvr.event_string[i] = readb
  2864. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2865. if (ha->dvr.event_string[i] == 0)
  2866. break;
  2867. }
  2868. }
  2869. }
  2870. #ifdef INT_COAL
  2871. /* Make sure that non coalesced interrupts get cleared
  2872. before being handled by gdth_async_event/gdth_sync_event */
  2873. if (!coalesced)
  2874. #endif
  2875. {
  2876. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2877. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2878. }
  2879. } else {
  2880. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2881. if (!gdth_polling)
  2882. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2883. return IRQ_HANDLED;
  2884. }
  2885. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2886. IStatus,ha->status,ha->info));
  2887. if (gdth_from_wait) {
  2888. *pIndex = (int)IStatus;
  2889. }
  2890. if (IStatus == ASYNCINDEX) {
  2891. TRACE2(("gdth_interrupt() async. event\n"));
  2892. gdth_async_event(ha);
  2893. if (!gdth_polling)
  2894. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2895. gdth_next(ha);
  2896. return IRQ_HANDLED;
  2897. }
  2898. if (IStatus == SPEZINDEX) {
  2899. TRACE2(("Service unknown or not initialized !\n"));
  2900. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2901. ha->dvr.eu.driver.ionode = ha->hanum;
  2902. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2903. if (!gdth_polling)
  2904. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2905. return IRQ_HANDLED;
  2906. }
  2907. scp = ha->cmd_tab[IStatus-2].cmnd;
  2908. Service = ha->cmd_tab[IStatus-2].service;
  2909. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2910. if (scp == UNUSED_CMND) {
  2911. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2912. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2913. ha->dvr.eu.driver.ionode = ha->hanum;
  2914. ha->dvr.eu.driver.index = IStatus;
  2915. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2916. if (!gdth_polling)
  2917. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2918. return IRQ_HANDLED;
  2919. }
  2920. if (scp == INTERNAL_CMND) {
  2921. TRACE(("gdth_interrupt() answer to internal command\n"));
  2922. if (!gdth_polling)
  2923. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2924. return IRQ_HANDLED;
  2925. }
  2926. TRACE(("gdth_interrupt() sync. status\n"));
  2927. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2928. if (!gdth_polling)
  2929. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2930. if (rval == 2) {
  2931. gdth_putq(ha, scp,scp->SCp.this_residual);
  2932. } else if (rval == 1) {
  2933. gdth_scsi_done(scp);
  2934. }
  2935. #ifdef INT_COAL
  2936. if (coalesced) {
  2937. /* go to the next status in the status buffer */
  2938. ++pcs;
  2939. #ifdef GDTH_STATISTICS
  2940. ++act_int_coal;
  2941. if (act_int_coal > max_int_coal) {
  2942. max_int_coal = act_int_coal;
  2943. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2944. }
  2945. #endif
  2946. /* see if there is another status */
  2947. if (pcs->status == 0)
  2948. /* Stop the coalesce loop */
  2949. next = FALSE;
  2950. }
  2951. } while (next);
  2952. /* coalescing only for new GDT_PCIMPR controllers available */
  2953. if (ha->type == GDT_PCIMPR && coalesced) {
  2954. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2955. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2956. }
  2957. #endif
  2958. gdth_next(ha);
  2959. return IRQ_HANDLED;
  2960. }
  2961. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2962. {
  2963. gdth_ha_str *ha = (gdth_ha_str *)dev_id;
  2964. return __gdth_interrupt(ha, irq, false, NULL);
  2965. }
  2966. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2967. Scsi_Cmnd *scp)
  2968. {
  2969. gdth_msg_str *msg;
  2970. gdth_cmd_str *cmdp;
  2971. unchar b, t;
  2972. cmdp = ha->pccb;
  2973. TRACE(("gdth_sync_event() serv %d status %d\n",
  2974. service,ha->status));
  2975. if (service == SCREENSERVICE) {
  2976. msg = ha->pmsg;
  2977. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2978. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2979. if (msg->msg_len > MSGLEN+1)
  2980. msg->msg_len = MSGLEN+1;
  2981. if (msg->msg_len)
  2982. if (!(msg->msg_answer && msg->msg_ext)) {
  2983. msg->msg_text[msg->msg_len] = '\0';
  2984. printk("%s",msg->msg_text);
  2985. }
  2986. if (msg->msg_ext && !msg->msg_answer) {
  2987. while (gdth_test_busy(ha))
  2988. gdth_delay(0);
  2989. cmdp->Service = SCREENSERVICE;
  2990. cmdp->RequestBuffer = SCREEN_CMND;
  2991. gdth_get_cmd_index(ha);
  2992. gdth_set_sema0(ha);
  2993. cmdp->OpCode = GDT_READ;
  2994. cmdp->BoardNode = LOCALBOARD;
  2995. cmdp->u.screen.reserved = 0;
  2996. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2997. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2998. ha->cmd_offs_dpmem = 0;
  2999. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3000. + sizeof(ulong64);
  3001. ha->cmd_cnt = 0;
  3002. gdth_copy_command(ha);
  3003. gdth_release_event(ha);
  3004. return 0;
  3005. }
  3006. if (msg->msg_answer && msg->msg_alen) {
  3007. /* default answers (getchar() not possible) */
  3008. if (msg->msg_alen == 1) {
  3009. msg->msg_alen = 0;
  3010. msg->msg_len = 1;
  3011. msg->msg_text[0] = 0;
  3012. } else {
  3013. msg->msg_alen -= 2;
  3014. msg->msg_len = 2;
  3015. msg->msg_text[0] = 1;
  3016. msg->msg_text[1] = 0;
  3017. }
  3018. msg->msg_ext = 0;
  3019. msg->msg_answer = 0;
  3020. while (gdth_test_busy(ha))
  3021. gdth_delay(0);
  3022. cmdp->Service = SCREENSERVICE;
  3023. cmdp->RequestBuffer = SCREEN_CMND;
  3024. gdth_get_cmd_index(ha);
  3025. gdth_set_sema0(ha);
  3026. cmdp->OpCode = GDT_WRITE;
  3027. cmdp->BoardNode = LOCALBOARD;
  3028. cmdp->u.screen.reserved = 0;
  3029. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3030. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3031. ha->cmd_offs_dpmem = 0;
  3032. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3033. + sizeof(ulong64);
  3034. ha->cmd_cnt = 0;
  3035. gdth_copy_command(ha);
  3036. gdth_release_event(ha);
  3037. return 0;
  3038. }
  3039. printk("\n");
  3040. } else {
  3041. b = scp->device->channel;
  3042. t = scp->device->id;
  3043. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3044. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3045. }
  3046. /* cache or raw service */
  3047. if (ha->status == S_BSY) {
  3048. TRACE2(("Controller busy -> retry !\n"));
  3049. if (scp->SCp.sent_command == GDT_MOUNT)
  3050. scp->SCp.sent_command = GDT_CLUST_INFO;
  3051. /* retry */
  3052. return 2;
  3053. }
  3054. if (scp->SCp.Status == GDTH_MAP_SG)
  3055. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3056. scp->use_sg,scp->SCp.Message);
  3057. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3058. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3059. scp->request_bufflen,scp->SCp.Message);
  3060. if (scp->SCp.buffer) {
  3061. dma_addr_t addr;
  3062. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3063. if (scp->host_scribble)
  3064. addr += (dma_addr_t)
  3065. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3066. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3067. }
  3068. if (ha->status == S_OK) {
  3069. scp->SCp.Status = S_OK;
  3070. scp->SCp.Message = ha->info;
  3071. if (scp->SCp.sent_command != -1) {
  3072. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3073. scp->SCp.sent_command));
  3074. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3075. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3076. ha->hdr[t].cluster_type = (unchar)ha->info;
  3077. if (!(ha->hdr[t].cluster_type &
  3078. CLUSTER_MOUNTED)) {
  3079. /* NOT MOUNTED -> MOUNT */
  3080. scp->SCp.sent_command = GDT_MOUNT;
  3081. if (ha->hdr[t].cluster_type &
  3082. CLUSTER_RESERVED) {
  3083. /* cluster drive RESERVED (on the other node) */
  3084. scp->SCp.phase = -2; /* reservation conflict */
  3085. }
  3086. } else {
  3087. scp->SCp.sent_command = -1;
  3088. }
  3089. } else {
  3090. if (scp->SCp.sent_command == GDT_MOUNT) {
  3091. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3092. ha->hdr[t].media_changed = TRUE;
  3093. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3094. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3095. ha->hdr[t].media_changed = TRUE;
  3096. }
  3097. scp->SCp.sent_command = -1;
  3098. }
  3099. /* retry */
  3100. scp->SCp.this_residual = HIGH_PRI;
  3101. return 2;
  3102. } else {
  3103. /* RESERVE/RELEASE ? */
  3104. if (scp->cmnd[0] == RESERVE) {
  3105. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3106. } else if (scp->cmnd[0] == RELEASE) {
  3107. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3108. }
  3109. scp->result = DID_OK << 16;
  3110. scp->sense_buffer[0] = 0;
  3111. }
  3112. } else {
  3113. scp->SCp.Status = ha->status;
  3114. scp->SCp.Message = ha->info;
  3115. if (scp->SCp.sent_command != -1) {
  3116. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3117. scp->SCp.sent_command, ha->status));
  3118. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3119. scp->SCp.sent_command == GDT_SCAN_END) {
  3120. scp->SCp.sent_command = -1;
  3121. /* retry */
  3122. scp->SCp.this_residual = HIGH_PRI;
  3123. return 2;
  3124. }
  3125. memset((char*)scp->sense_buffer,0,16);
  3126. scp->sense_buffer[0] = 0x70;
  3127. scp->sense_buffer[2] = NOT_READY;
  3128. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3129. } else if (service == CACHESERVICE) {
  3130. if (ha->status == S_CACHE_UNKNOWN &&
  3131. (ha->hdr[t].cluster_type &
  3132. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3133. /* bus reset -> force GDT_CLUST_INFO */
  3134. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3135. }
  3136. memset((char*)scp->sense_buffer,0,16);
  3137. if (ha->status == (ushort)S_CACHE_RESERV) {
  3138. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3139. } else {
  3140. scp->sense_buffer[0] = 0x70;
  3141. scp->sense_buffer[2] = NOT_READY;
  3142. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3143. }
  3144. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3145. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3146. ha->dvr.eu.sync.ionode = ha->hanum;
  3147. ha->dvr.eu.sync.service = service;
  3148. ha->dvr.eu.sync.status = ha->status;
  3149. ha->dvr.eu.sync.info = ha->info;
  3150. ha->dvr.eu.sync.hostdrive = t;
  3151. if (ha->status >= 0x8000)
  3152. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3153. else
  3154. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3155. }
  3156. } else {
  3157. /* sense buffer filled from controller firmware (DMA) */
  3158. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3159. scp->result = DID_BAD_TARGET << 16;
  3160. } else {
  3161. scp->result = (DID_OK << 16) | ha->info;
  3162. }
  3163. }
  3164. }
  3165. if (!scp->SCp.have_data_in)
  3166. scp->SCp.have_data_in++;
  3167. else
  3168. return 1;
  3169. }
  3170. return 0;
  3171. }
  3172. static char *async_cache_tab[] = {
  3173. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3174. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3175. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3176. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3177. /* 2*/ "\005\000\002\006\004"
  3178. "GDT HA %u, Host Drive %lu not ready",
  3179. /* 3*/ "\005\000\002\006\004"
  3180. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3181. /* 4*/ "\005\000\002\006\004"
  3182. "GDT HA %u, mirror update on Host Drive %lu failed",
  3183. /* 5*/ "\005\000\002\006\004"
  3184. "GDT HA %u, Mirror Drive %lu failed",
  3185. /* 6*/ "\005\000\002\006\004"
  3186. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3187. /* 7*/ "\005\000\002\006\004"
  3188. "GDT HA %u, Host Drive %lu write protected",
  3189. /* 8*/ "\005\000\002\006\004"
  3190. "GDT HA %u, media changed in Host Drive %lu",
  3191. /* 9*/ "\005\000\002\006\004"
  3192. "GDT HA %u, Host Drive %lu is offline",
  3193. /*10*/ "\005\000\002\006\004"
  3194. "GDT HA %u, media change of Mirror Drive %lu",
  3195. /*11*/ "\005\000\002\006\004"
  3196. "GDT HA %u, Mirror Drive %lu is write protected",
  3197. /*12*/ "\005\000\002\006\004"
  3198. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3199. /*13*/ "\007\000\002\006\002\010\002"
  3200. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3201. /*14*/ "\005\000\002\006\002"
  3202. "GDT HA %u, Array Drive %u: FAIL state entered",
  3203. /*15*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Array Drive %u: error",
  3205. /*16*/ "\007\000\002\006\002\010\002"
  3206. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3207. /*17*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: parity build failed",
  3209. /*18*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3211. /*19*/ "\005\000\002\010\002"
  3212. "GDT HA %u, Test of Hot Fix %u failed",
  3213. /*20*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3215. /*21*/ "\005\000\002\006\002"
  3216. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3217. /*22*/ "\007\000\002\006\002\010\002"
  3218. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3219. /*23*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3221. /*24*/ "\005\000\002\010\002"
  3222. "GDT HA %u, mirror update on Cache Drive %u completed",
  3223. /*25*/ "\005\000\002\010\002"
  3224. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3225. /*26*/ "\005\000\002\006\002"
  3226. "GDT HA %u, Array Drive %u: drive rebuild started",
  3227. /*27*/ "\005\000\002\012\001"
  3228. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3229. /*28*/ "\005\000\002\012\001"
  3230. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3231. /*29*/ "\007\000\002\012\001\013\001"
  3232. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3233. /*30*/ "\007\000\002\012\001\013\001"
  3234. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3235. /*31*/ "\007\000\002\012\001\013\001"
  3236. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3237. /*32*/ "\007\000\002\012\001\013\001"
  3238. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3239. /*33*/ "\007\000\002\012\001\013\001"
  3240. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3241. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3242. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3243. /*35*/ "\007\000\002\012\001\013\001"
  3244. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3245. /*36*/ "\007\000\002\012\001\013\001"
  3246. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3247. /*37*/ "\007\000\002\012\001\006\004"
  3248. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3249. /*38*/ "\007\000\002\012\001\013\001"
  3250. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3251. /*39*/ "\007\000\002\012\001\013\001"
  3252. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3253. /*40*/ "\007\000\002\012\001\013\001"
  3254. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3255. /*41*/ "\007\000\002\012\001\013\001"
  3256. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3257. /*42*/ "\005\000\002\006\002"
  3258. "GDT HA %u, Array Drive %u: drive build started",
  3259. /*43*/ "\003\000\002"
  3260. "GDT HA %u, DRAM parity error detected",
  3261. /*44*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Mirror Drive %u: update started",
  3263. /*45*/ "\007\000\002\006\002\010\002"
  3264. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3265. /*46*/ "\005\000\002\006\002"
  3266. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3267. /*47*/ "\005\000\002\006\002"
  3268. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3269. /*48*/ "\005\000\002\006\002"
  3270. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3271. /*49*/ "\005\000\002\006\002"
  3272. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3273. /*50*/ "\007\000\002\012\001\013\001"
  3274. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3275. /*51*/ "\005\000\002\006\002"
  3276. "GDT HA %u, Array Drive %u: expand started",
  3277. /*52*/ "\005\000\002\006\002"
  3278. "GDT HA %u, Array Drive %u: expand finished successfully",
  3279. /*53*/ "\005\000\002\006\002"
  3280. "GDT HA %u, Array Drive %u: expand failed",
  3281. /*54*/ "\003\000\002"
  3282. "GDT HA %u, CPU temperature critical",
  3283. /*55*/ "\003\000\002"
  3284. "GDT HA %u, CPU temperature OK",
  3285. /*56*/ "\005\000\002\006\004"
  3286. "GDT HA %u, Host drive %lu created",
  3287. /*57*/ "\005\000\002\006\002"
  3288. "GDT HA %u, Array Drive %u: expand restarted",
  3289. /*58*/ "\005\000\002\006\002"
  3290. "GDT HA %u, Array Drive %u: expand stopped",
  3291. /*59*/ "\005\000\002\010\002"
  3292. "GDT HA %u, Mirror Drive %u: drive build quited",
  3293. /*60*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: parity build quited",
  3295. /*61*/ "\005\000\002\006\002"
  3296. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3297. /*62*/ "\005\000\002\006\002"
  3298. "GDT HA %u, Array Drive %u: parity verify started",
  3299. /*63*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: parity verify done",
  3301. /*64*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Array Drive %u: parity verify failed",
  3303. /*65*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Array Drive %u: parity error detected",
  3305. /*66*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Array Drive %u: parity verify quited",
  3307. /*67*/ "\005\000\002\006\002"
  3308. "GDT HA %u, Host Drive %u reserved",
  3309. /*68*/ "\005\000\002\006\002"
  3310. "GDT HA %u, Host Drive %u mounted and released",
  3311. /*69*/ "\005\000\002\006\002"
  3312. "GDT HA %u, Host Drive %u released",
  3313. /*70*/ "\003\000\002"
  3314. "GDT HA %u, DRAM error detected and corrected with ECC",
  3315. /*71*/ "\003\000\002"
  3316. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3317. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3318. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3319. /*73*/ "\005\000\002\006\002"
  3320. "GDT HA %u, Host drive %u resetted locally",
  3321. /*74*/ "\005\000\002\006\002"
  3322. "GDT HA %u, Host drive %u resetted remotely",
  3323. /*75*/ "\003\000\002"
  3324. "GDT HA %u, async. status 75 unknown",
  3325. };
  3326. static int gdth_async_event(gdth_ha_str *ha)
  3327. {
  3328. gdth_cmd_str *cmdp;
  3329. int cmd_index;
  3330. cmdp= ha->pccb;
  3331. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3332. ha->hanum, ha->service));
  3333. if (ha->service == SCREENSERVICE) {
  3334. if (ha->status == MSG_REQUEST) {
  3335. while (gdth_test_busy(ha))
  3336. gdth_delay(0);
  3337. cmdp->Service = SCREENSERVICE;
  3338. cmdp->RequestBuffer = SCREEN_CMND;
  3339. cmd_index = gdth_get_cmd_index(ha);
  3340. gdth_set_sema0(ha);
  3341. cmdp->OpCode = GDT_READ;
  3342. cmdp->BoardNode = LOCALBOARD;
  3343. cmdp->u.screen.reserved = 0;
  3344. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3345. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3346. ha->cmd_offs_dpmem = 0;
  3347. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3348. + sizeof(ulong64);
  3349. ha->cmd_cnt = 0;
  3350. gdth_copy_command(ha);
  3351. if (ha->type == GDT_EISA)
  3352. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3353. else if (ha->type == GDT_ISA)
  3354. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3355. else
  3356. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3357. (ushort)((ha->brd_phys>>3)&0x1f));
  3358. gdth_release_event(ha);
  3359. }
  3360. } else {
  3361. if (ha->type == GDT_PCIMPR &&
  3362. (ha->fw_vers & 0xff) >= 0x1a) {
  3363. ha->dvr.size = 0;
  3364. ha->dvr.eu.async.ionode = ha->hanum;
  3365. ha->dvr.eu.async.status = ha->status;
  3366. /* severity and event_string already set! */
  3367. } else {
  3368. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3369. ha->dvr.eu.async.ionode = ha->hanum;
  3370. ha->dvr.eu.async.service = ha->service;
  3371. ha->dvr.eu.async.status = ha->status;
  3372. ha->dvr.eu.async.info = ha->info;
  3373. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3374. }
  3375. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3376. gdth_log_event( &ha->dvr, NULL );
  3377. /* new host drive from expand? */
  3378. if (ha->service == CACHESERVICE && ha->status == 56) {
  3379. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3380. (ushort)ha->info));
  3381. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3382. }
  3383. }
  3384. return 1;
  3385. }
  3386. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3387. {
  3388. gdth_stackframe stack;
  3389. char *f = NULL;
  3390. int i,j;
  3391. TRACE2(("gdth_log_event()\n"));
  3392. if (dvr->size == 0) {
  3393. if (buffer == NULL) {
  3394. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3395. } else {
  3396. sprintf(buffer,"Adapter %d: %s\n",
  3397. dvr->eu.async.ionode,dvr->event_string);
  3398. }
  3399. } else if (dvr->eu.async.service == CACHESERVICE &&
  3400. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3401. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3402. dvr->eu.async.status));
  3403. f = async_cache_tab[dvr->eu.async.status];
  3404. /* i: parameter to push, j: stack element to fill */
  3405. for (j=0,i=1; i < f[0]; i+=2) {
  3406. switch (f[i+1]) {
  3407. case 4:
  3408. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3409. break;
  3410. case 2:
  3411. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3412. break;
  3413. case 1:
  3414. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3415. break;
  3416. default:
  3417. break;
  3418. }
  3419. }
  3420. if (buffer == NULL) {
  3421. printk(&f[(int)f[0]],stack);
  3422. printk("\n");
  3423. } else {
  3424. sprintf(buffer,&f[(int)f[0]],stack);
  3425. }
  3426. } else {
  3427. if (buffer == NULL) {
  3428. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3429. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3430. } else {
  3431. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3432. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3433. }
  3434. }
  3435. }
  3436. #ifdef GDTH_STATISTICS
  3437. static void gdth_timeout(ulong data)
  3438. {
  3439. ulong32 i;
  3440. Scsi_Cmnd *nscp;
  3441. gdth_ha_str *ha;
  3442. ulong flags;
  3443. ha = shost_priv(gdth_ctr_tab[0]);
  3444. spin_lock_irqsave(&ha->smp_lock, flags);
  3445. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3446. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3447. ++act_stats;
  3448. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3449. ++act_rq;
  3450. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3451. act_ints, act_ios, act_stats, act_rq));
  3452. act_ints = act_ios = 0;
  3453. gdth_timer.expires = jiffies + 30 * HZ;
  3454. add_timer(&gdth_timer);
  3455. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3456. }
  3457. #endif
  3458. static void __init internal_setup(char *str,int *ints)
  3459. {
  3460. int i, argc;
  3461. char *cur_str, *argv;
  3462. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3463. str ? str:"NULL", ints ? ints[0]:0));
  3464. /* read irq[] from ints[] */
  3465. if (ints) {
  3466. argc = ints[0];
  3467. if (argc > 0) {
  3468. if (argc > MAXHA)
  3469. argc = MAXHA;
  3470. for (i = 0; i < argc; ++i)
  3471. irq[i] = ints[i+1];
  3472. }
  3473. }
  3474. /* analyse string */
  3475. argv = str;
  3476. while (argv && (cur_str = strchr(argv, ':'))) {
  3477. int val = 0, c = *++cur_str;
  3478. if (c == 'n' || c == 'N')
  3479. val = 0;
  3480. else if (c == 'y' || c == 'Y')
  3481. val = 1;
  3482. else
  3483. val = (int)simple_strtoul(cur_str, NULL, 0);
  3484. if (!strncmp(argv, "disable:", 8))
  3485. disable = val;
  3486. else if (!strncmp(argv, "reserve_mode:", 13))
  3487. reserve_mode = val;
  3488. else if (!strncmp(argv, "reverse_scan:", 13))
  3489. reverse_scan = val;
  3490. else if (!strncmp(argv, "hdr_channel:", 12))
  3491. hdr_channel = val;
  3492. else if (!strncmp(argv, "max_ids:", 8))
  3493. max_ids = val;
  3494. else if (!strncmp(argv, "rescan:", 7))
  3495. rescan = val;
  3496. else if (!strncmp(argv, "shared_access:", 14))
  3497. shared_access = val;
  3498. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3499. probe_eisa_isa = val;
  3500. else if (!strncmp(argv, "reserve_list:", 13)) {
  3501. reserve_list[0] = val;
  3502. for (i = 1; i < MAX_RES_ARGS; i++) {
  3503. cur_str = strchr(cur_str, ',');
  3504. if (!cur_str)
  3505. break;
  3506. if (!isdigit((int)*++cur_str)) {
  3507. --cur_str;
  3508. break;
  3509. }
  3510. reserve_list[i] =
  3511. (int)simple_strtoul(cur_str, NULL, 0);
  3512. }
  3513. if (!cur_str)
  3514. break;
  3515. argv = ++cur_str;
  3516. continue;
  3517. }
  3518. if ((argv = strchr(argv, ',')))
  3519. ++argv;
  3520. }
  3521. }
  3522. int __init option_setup(char *str)
  3523. {
  3524. int ints[MAXHA];
  3525. char *cur = str;
  3526. int i = 1;
  3527. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3528. while (cur && isdigit(*cur) && i <= MAXHA) {
  3529. ints[i++] = simple_strtoul(cur, NULL, 0);
  3530. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3531. }
  3532. ints[0] = i - 1;
  3533. internal_setup(cur, ints);
  3534. return 1;
  3535. }
  3536. static int __init gdth_detect(struct scsi_host_template *shtp)
  3537. {
  3538. #ifdef DEBUG_GDTH
  3539. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3540. DebugState);
  3541. printk(" Destination of debugging information: ");
  3542. #ifdef __SERIAL__
  3543. #ifdef __COM2__
  3544. printk("Serial port COM2\n");
  3545. #else
  3546. printk("Serial port COM1\n");
  3547. #endif
  3548. #else
  3549. printk("Console\n");
  3550. #endif
  3551. gdth_delay(3000);
  3552. #endif
  3553. TRACE(("gdth_detect()\n"));
  3554. if (disable) {
  3555. printk("GDT-HA: Controller driver disabled from command line !\n");
  3556. return 0;
  3557. }
  3558. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3559. /* initializations */
  3560. gdth_polling = TRUE;
  3561. gdth_clear_events();
  3562. /* As default we do not probe for EISA or ISA controllers */
  3563. if (probe_eisa_isa) {
  3564. /* scanning for controllers, at first: ISA controller */
  3565. #ifdef CONFIG_ISA
  3566. ulong32 isa_bios;
  3567. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  3568. isa_bios += 0x8000UL) {
  3569. if (gdth_ctr_count >= MAXHA)
  3570. break;
  3571. gdth_isa_probe_one(shtp, isa_bios);
  3572. }
  3573. #endif
  3574. #ifdef CONFIG_EISA
  3575. {
  3576. ushort eisa_slot;
  3577. for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
  3578. if (gdth_ctr_count >= MAXHA)
  3579. break;
  3580. gdth_eisa_probe_one(shtp, eisa_slot);
  3581. }
  3582. }
  3583. #endif
  3584. }
  3585. #ifdef CONFIG_PCI
  3586. /* scanning for PCI controllers */
  3587. {
  3588. gdth_pci_str pcistr[MAXHA];
  3589. int cnt,ctr;
  3590. cnt = gdth_search_pci(pcistr);
  3591. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  3592. gdth_sort_pci(pcistr,cnt);
  3593. for (ctr = 0; ctr < cnt; ++ctr) {
  3594. if (gdth_ctr_count >= MAXHA)
  3595. break;
  3596. gdth_pci_probe_one(shtp, pcistr, ctr);
  3597. }
  3598. }
  3599. #endif /* CONFIG_PCI */
  3600. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  3601. if (gdth_ctr_count > 0) {
  3602. #ifdef GDTH_STATISTICS
  3603. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3604. init_timer(&gdth_timer);
  3605. gdth_timer.expires = jiffies + HZ;
  3606. gdth_timer.data = 0L;
  3607. gdth_timer.function = gdth_timeout;
  3608. add_timer(&gdth_timer);
  3609. #endif
  3610. major = register_chrdev(0,"gdth",&gdth_fops);
  3611. notifier_disabled = 0;
  3612. register_reboot_notifier(&gdth_notifier);
  3613. }
  3614. gdth_polling = FALSE;
  3615. return gdth_ctr_count;
  3616. }
  3617. static int gdth_release(struct Scsi_Host *shp)
  3618. {
  3619. gdth_ha_str *ha = shost_priv(shp);
  3620. TRACE2(("gdth_release()\n"));
  3621. if (ha->sdev) {
  3622. scsi_free_host_dev(ha->sdev);
  3623. ha->sdev = NULL;
  3624. }
  3625. gdth_flush(ha);
  3626. if (shp->irq) {
  3627. free_irq(shp->irq,ha);
  3628. }
  3629. #ifdef CONFIG_ISA
  3630. if (shp->dma_channel != 0xff) {
  3631. free_dma(shp->dma_channel);
  3632. }
  3633. #endif
  3634. #ifdef INT_COAL
  3635. if (ha->coal_stat)
  3636. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3637. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  3638. #endif
  3639. if (ha->pscratch)
  3640. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  3641. ha->pscratch, ha->scratch_phys);
  3642. if (ha->pmsg)
  3643. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  3644. ha->pmsg, ha->msg_phys);
  3645. if (ha->ccb_phys)
  3646. pci_unmap_single(ha->pdev,ha->ccb_phys,
  3647. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  3648. gdth_ctr_released++;
  3649. TRACE2(("gdth_release(): HA %d of %d\n",
  3650. gdth_ctr_released, gdth_ctr_count));
  3651. if (gdth_ctr_released == gdth_ctr_count) {
  3652. #ifdef GDTH_STATISTICS
  3653. del_timer(&gdth_timer);
  3654. #endif
  3655. unregister_chrdev(major,"gdth");
  3656. unregister_reboot_notifier(&gdth_notifier);
  3657. }
  3658. scsi_unregister(shp);
  3659. return 0;
  3660. }
  3661. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3662. {
  3663. TRACE2(("gdth_ctr_name()\n"));
  3664. if (ha->type == GDT_EISA) {
  3665. switch (ha->stype) {
  3666. case GDT3_ID:
  3667. return("GDT3000/3020");
  3668. case GDT3A_ID:
  3669. return("GDT3000A/3020A/3050A");
  3670. case GDT3B_ID:
  3671. return("GDT3000B/3010A");
  3672. }
  3673. } else if (ha->type == GDT_ISA) {
  3674. return("GDT2000/2020");
  3675. } else if (ha->type == GDT_PCI) {
  3676. switch (ha->pdev->device) {
  3677. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3678. return("GDT6000/6020/6050");
  3679. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3680. return("GDT6000B/6010");
  3681. }
  3682. }
  3683. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3684. return("");
  3685. }
  3686. static const char *gdth_info(struct Scsi_Host *shp)
  3687. {
  3688. gdth_ha_str *ha = shost_priv(shp);
  3689. TRACE2(("gdth_info()\n"));
  3690. return ((const char *)ha->binfo.type_string);
  3691. }
  3692. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3693. {
  3694. gdth_ha_str *ha = shost_priv(scp->device->host);
  3695. int i;
  3696. ulong flags;
  3697. Scsi_Cmnd *cmnd;
  3698. unchar b;
  3699. TRACE2(("gdth_eh_bus_reset()\n"));
  3700. b = scp->device->channel;
  3701. /* clear command tab */
  3702. spin_lock_irqsave(&ha->smp_lock, flags);
  3703. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3704. cmnd = ha->cmd_tab[i].cmnd;
  3705. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3706. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3707. }
  3708. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3709. if (b == ha->virt_bus) {
  3710. /* host drives */
  3711. for (i = 0; i < MAX_HDRIVES; ++i) {
  3712. if (ha->hdr[i].present) {
  3713. spin_lock_irqsave(&ha->smp_lock, flags);
  3714. gdth_polling = TRUE;
  3715. while (gdth_test_busy(ha))
  3716. gdth_delay(0);
  3717. if (gdth_internal_cmd(ha, CACHESERVICE,
  3718. GDT_CLUST_RESET, i, 0, 0))
  3719. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3720. gdth_polling = FALSE;
  3721. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3722. }
  3723. }
  3724. } else {
  3725. /* raw devices */
  3726. spin_lock_irqsave(&ha->smp_lock, flags);
  3727. for (i = 0; i < MAXID; ++i)
  3728. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3729. gdth_polling = TRUE;
  3730. while (gdth_test_busy(ha))
  3731. gdth_delay(0);
  3732. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3733. BUS_L2P(ha,b), 0, 0);
  3734. gdth_polling = FALSE;
  3735. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3736. }
  3737. return SUCCESS;
  3738. }
  3739. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3740. {
  3741. unchar b, t;
  3742. gdth_ha_str *ha = shost_priv(sdev->host);
  3743. struct scsi_device *sd;
  3744. unsigned capacity;
  3745. sd = sdev;
  3746. capacity = cap;
  3747. b = sd->channel;
  3748. t = sd->id;
  3749. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3750. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3751. /* raw device or host drive without mapping information */
  3752. TRACE2(("Evaluate mapping\n"));
  3753. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3754. } else {
  3755. ip[0] = ha->hdr[t].heads;
  3756. ip[1] = ha->hdr[t].secs;
  3757. ip[2] = capacity / ip[0] / ip[1];
  3758. }
  3759. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3760. ip[0],ip[1],ip[2]));
  3761. return 0;
  3762. }
  3763. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3764. void (*done)(struct scsi_cmnd *))
  3765. {
  3766. gdth_ha_str *ha = shost_priv(scp->device->host);
  3767. int priority;
  3768. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3769. scp->scsi_done = done;
  3770. scp->SCp.have_data_in = 1;
  3771. scp->SCp.phase = -1;
  3772. scp->SCp.sent_command = -1;
  3773. scp->SCp.Status = GDTH_MAP_NONE;
  3774. scp->SCp.buffer = (struct scatterlist *)NULL;
  3775. #ifdef GDTH_STATISTICS
  3776. ++act_ios;
  3777. #endif
  3778. priority = DEFAULT_PRI;
  3779. if (IS_GDTH_INTERNAL_CMD(scp))
  3780. priority = scp->SCp.this_residual;
  3781. else
  3782. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3783. gdth_putq(ha, scp, priority);
  3784. gdth_next(ha);
  3785. return 0;
  3786. }
  3787. static int gdth_open(struct inode *inode, struct file *filep)
  3788. {
  3789. gdth_ha_str *ha;
  3790. int i;
  3791. for (i = 0; i < gdth_ctr_count; i++) {
  3792. ha = shost_priv(gdth_ctr_tab[i]);
  3793. if (!ha->sdev)
  3794. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  3795. }
  3796. TRACE(("gdth_open()\n"));
  3797. return 0;
  3798. }
  3799. static int gdth_close(struct inode *inode, struct file *filep)
  3800. {
  3801. TRACE(("gdth_close()\n"));
  3802. return 0;
  3803. }
  3804. static int ioc_event(void __user *arg)
  3805. {
  3806. gdth_ioctl_event evt;
  3807. gdth_ha_str *ha;
  3808. ulong flags;
  3809. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  3810. evt.ionode >= gdth_ctr_count)
  3811. return -EFAULT;
  3812. ha = shost_priv(gdth_ctr_tab[evt.ionode]);
  3813. if (evt.erase == 0xff) {
  3814. if (evt.event.event_source == ES_TEST)
  3815. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3816. else if (evt.event.event_source == ES_DRIVER)
  3817. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3818. else if (evt.event.event_source == ES_SYNC)
  3819. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3820. else
  3821. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3822. spin_lock_irqsave(&ha->smp_lock, flags);
  3823. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3824. &evt.event.event_data);
  3825. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3826. } else if (evt.erase == 0xfe) {
  3827. gdth_clear_events();
  3828. } else if (evt.erase == 0) {
  3829. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3830. } else {
  3831. gdth_readapp_event(ha, evt.erase, &evt.event);
  3832. }
  3833. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3834. return -EFAULT;
  3835. return 0;
  3836. }
  3837. static int ioc_lockdrv(void __user *arg)
  3838. {
  3839. gdth_ioctl_lockdrv ldrv;
  3840. unchar i, j;
  3841. ulong flags;
  3842. gdth_ha_str *ha;
  3843. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  3844. ldrv.ionode >= gdth_ctr_count)
  3845. return -EFAULT;
  3846. ha = shost_priv(gdth_ctr_tab[ldrv.ionode]);
  3847. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3848. j = ldrv.drives[i];
  3849. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3850. continue;
  3851. if (ldrv.lock) {
  3852. spin_lock_irqsave(&ha->smp_lock, flags);
  3853. ha->hdr[j].lock = 1;
  3854. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3855. gdth_wait_completion(ha, ha->bus_cnt, j);
  3856. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3857. } else {
  3858. spin_lock_irqsave(&ha->smp_lock, flags);
  3859. ha->hdr[j].lock = 0;
  3860. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3861. gdth_start_timeout(ha, ha->bus_cnt, j);
  3862. gdth_next(ha);
  3863. }
  3864. }
  3865. return 0;
  3866. }
  3867. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3868. {
  3869. gdth_ioctl_reset res;
  3870. gdth_cmd_str cmd;
  3871. gdth_ha_str *ha;
  3872. int rval;
  3873. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3874. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  3875. return -EFAULT;
  3876. ha = shost_priv(gdth_ctr_tab[res.ionode]);
  3877. if (!ha->hdr[res.number].present)
  3878. return 0;
  3879. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3880. cmd.Service = CACHESERVICE;
  3881. cmd.OpCode = GDT_CLUST_RESET;
  3882. if (ha->cache_feat & GDT_64BIT)
  3883. cmd.u.cache64.DeviceNo = res.number;
  3884. else
  3885. cmd.u.cache.DeviceNo = res.number;
  3886. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3887. if (rval < 0)
  3888. return rval;
  3889. res.status = rval;
  3890. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3891. return -EFAULT;
  3892. return 0;
  3893. }
  3894. static int ioc_general(void __user *arg, char *cmnd)
  3895. {
  3896. gdth_ioctl_general gen;
  3897. char *buf = NULL;
  3898. ulong64 paddr;
  3899. gdth_ha_str *ha;
  3900. int rval;
  3901. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  3902. gen.ionode >= gdth_ctr_count)
  3903. return -EFAULT;
  3904. ha = shost_priv(gdth_ctr_tab[gen.ionode]);
  3905. if (gen.data_len + gen.sense_len != 0) {
  3906. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3907. FALSE, &paddr)))
  3908. return -EFAULT;
  3909. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3910. gen.data_len + gen.sense_len)) {
  3911. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3912. return -EFAULT;
  3913. }
  3914. if (gen.command.OpCode == GDT_IOCTL) {
  3915. gen.command.u.ioctl.p_param = paddr;
  3916. } else if (gen.command.Service == CACHESERVICE) {
  3917. if (ha->cache_feat & GDT_64BIT) {
  3918. /* copy elements from 32-bit IOCTL structure */
  3919. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3920. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3921. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3922. /* addresses */
  3923. if (ha->cache_feat & SCATTER_GATHER) {
  3924. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3925. gen.command.u.cache64.sg_canz = 1;
  3926. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3927. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3928. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3929. } else {
  3930. gen.command.u.cache64.DestAddr = paddr;
  3931. gen.command.u.cache64.sg_canz = 0;
  3932. }
  3933. } else {
  3934. if (ha->cache_feat & SCATTER_GATHER) {
  3935. gen.command.u.cache.DestAddr = 0xffffffff;
  3936. gen.command.u.cache.sg_canz = 1;
  3937. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3938. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3939. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3940. } else {
  3941. gen.command.u.cache.DestAddr = paddr;
  3942. gen.command.u.cache.sg_canz = 0;
  3943. }
  3944. }
  3945. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3946. if (ha->raw_feat & GDT_64BIT) {
  3947. /* copy elements from 32-bit IOCTL structure */
  3948. char cmd[16];
  3949. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3950. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3951. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3952. gen.command.u.raw64.target = gen.command.u.raw.target;
  3953. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3954. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3955. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3956. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3957. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3958. /* addresses */
  3959. if (ha->raw_feat & SCATTER_GATHER) {
  3960. gen.command.u.raw64.sdata = (ulong64)-1;
  3961. gen.command.u.raw64.sg_ranz = 1;
  3962. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3963. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3964. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3965. } else {
  3966. gen.command.u.raw64.sdata = paddr;
  3967. gen.command.u.raw64.sg_ranz = 0;
  3968. }
  3969. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3970. } else {
  3971. if (ha->raw_feat & SCATTER_GATHER) {
  3972. gen.command.u.raw.sdata = 0xffffffff;
  3973. gen.command.u.raw.sg_ranz = 1;
  3974. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3975. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3976. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3977. } else {
  3978. gen.command.u.raw.sdata = paddr;
  3979. gen.command.u.raw.sg_ranz = 0;
  3980. }
  3981. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3982. }
  3983. } else {
  3984. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3985. return -EFAULT;
  3986. }
  3987. }
  3988. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3989. if (rval < 0)
  3990. return rval;
  3991. gen.status = rval;
  3992. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3993. gen.data_len + gen.sense_len)) {
  3994. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3995. return -EFAULT;
  3996. }
  3997. if (copy_to_user(arg, &gen,
  3998. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3999. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  4000. return -EFAULT;
  4001. }
  4002. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  4003. return 0;
  4004. }
  4005. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4006. {
  4007. gdth_ioctl_rescan *rsc;
  4008. gdth_cmd_str *cmd;
  4009. gdth_ha_str *ha;
  4010. unchar i;
  4011. int rc = -ENOMEM;
  4012. u32 cluster_type = 0;
  4013. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4014. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4015. if (!rsc || !cmd)
  4016. goto free_fail;
  4017. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4018. rsc->ionode >= gdth_ctr_count) {
  4019. rc = -EFAULT;
  4020. goto free_fail;
  4021. }
  4022. ha = shost_priv(gdth_ctr_tab[rsc->ionode]);
  4023. memset(cmd, 0, sizeof(gdth_cmd_str));
  4024. for (i = 0; i < MAX_HDRIVES; ++i) {
  4025. if (!ha->hdr[i].present) {
  4026. rsc->hdr_list[i].bus = 0xff;
  4027. continue;
  4028. }
  4029. rsc->hdr_list[i].bus = ha->virt_bus;
  4030. rsc->hdr_list[i].target = i;
  4031. rsc->hdr_list[i].lun = 0;
  4032. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4033. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4034. cmd->Service = CACHESERVICE;
  4035. cmd->OpCode = GDT_CLUST_INFO;
  4036. if (ha->cache_feat & GDT_64BIT)
  4037. cmd->u.cache64.DeviceNo = i;
  4038. else
  4039. cmd->u.cache.DeviceNo = i;
  4040. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4041. rsc->hdr_list[i].cluster_type = cluster_type;
  4042. }
  4043. }
  4044. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4045. rc = -EFAULT;
  4046. else
  4047. rc = 0;
  4048. free_fail:
  4049. kfree(rsc);
  4050. kfree(cmd);
  4051. return rc;
  4052. }
  4053. static int ioc_rescan(void __user *arg, char *cmnd)
  4054. {
  4055. gdth_ioctl_rescan *rsc;
  4056. gdth_cmd_str *cmd;
  4057. ushort i, status, hdr_cnt;
  4058. ulong32 info;
  4059. int cyls, hds, secs;
  4060. int rc = -ENOMEM;
  4061. ulong flags;
  4062. gdth_ha_str *ha;
  4063. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4064. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4065. if (!cmd || !rsc)
  4066. goto free_fail;
  4067. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4068. rsc->ionode >= gdth_ctr_count) {
  4069. rc = -EFAULT;
  4070. goto free_fail;
  4071. }
  4072. ha = shost_priv(gdth_ctr_tab[rsc->ionode]);
  4073. memset(cmd, 0, sizeof(gdth_cmd_str));
  4074. if (rsc->flag == 0) {
  4075. /* old method: re-init. cache service */
  4076. cmd->Service = CACHESERVICE;
  4077. if (ha->cache_feat & GDT_64BIT) {
  4078. cmd->OpCode = GDT_X_INIT_HOST;
  4079. cmd->u.cache64.DeviceNo = LINUX_OS;
  4080. } else {
  4081. cmd->OpCode = GDT_INIT;
  4082. cmd->u.cache.DeviceNo = LINUX_OS;
  4083. }
  4084. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4085. i = 0;
  4086. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4087. } else {
  4088. i = rsc->hdr_no;
  4089. hdr_cnt = i + 1;
  4090. }
  4091. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4092. cmd->Service = CACHESERVICE;
  4093. cmd->OpCode = GDT_INFO;
  4094. if (ha->cache_feat & GDT_64BIT)
  4095. cmd->u.cache64.DeviceNo = i;
  4096. else
  4097. cmd->u.cache.DeviceNo = i;
  4098. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4099. spin_lock_irqsave(&ha->smp_lock, flags);
  4100. rsc->hdr_list[i].bus = ha->virt_bus;
  4101. rsc->hdr_list[i].target = i;
  4102. rsc->hdr_list[i].lun = 0;
  4103. if (status != S_OK) {
  4104. ha->hdr[i].present = FALSE;
  4105. } else {
  4106. ha->hdr[i].present = TRUE;
  4107. ha->hdr[i].size = info;
  4108. /* evaluate mapping */
  4109. ha->hdr[i].size &= ~SECS32;
  4110. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4111. ha->hdr[i].heads = hds;
  4112. ha->hdr[i].secs = secs;
  4113. /* round size */
  4114. ha->hdr[i].size = cyls * hds * secs;
  4115. }
  4116. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4117. if (status != S_OK)
  4118. continue;
  4119. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4120. /* but we need ha->info2, not yet stored in scp->SCp */
  4121. /* devtype, cluster info, R/W attribs */
  4122. cmd->Service = CACHESERVICE;
  4123. cmd->OpCode = GDT_DEVTYPE;
  4124. if (ha->cache_feat & GDT_64BIT)
  4125. cmd->u.cache64.DeviceNo = i;
  4126. else
  4127. cmd->u.cache.DeviceNo = i;
  4128. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4129. spin_lock_irqsave(&ha->smp_lock, flags);
  4130. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4131. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4132. cmd->Service = CACHESERVICE;
  4133. cmd->OpCode = GDT_CLUST_INFO;
  4134. if (ha->cache_feat & GDT_64BIT)
  4135. cmd->u.cache64.DeviceNo = i;
  4136. else
  4137. cmd->u.cache.DeviceNo = i;
  4138. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4139. spin_lock_irqsave(&ha->smp_lock, flags);
  4140. ha->hdr[i].cluster_type =
  4141. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4142. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4143. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4144. cmd->Service = CACHESERVICE;
  4145. cmd->OpCode = GDT_RW_ATTRIBS;
  4146. if (ha->cache_feat & GDT_64BIT)
  4147. cmd->u.cache64.DeviceNo = i;
  4148. else
  4149. cmd->u.cache.DeviceNo = i;
  4150. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4151. spin_lock_irqsave(&ha->smp_lock, flags);
  4152. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4153. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4154. }
  4155. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4156. rc = -EFAULT;
  4157. else
  4158. rc = 0;
  4159. free_fail:
  4160. kfree(rsc);
  4161. kfree(cmd);
  4162. return rc;
  4163. }
  4164. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4165. unsigned int cmd, unsigned long arg)
  4166. {
  4167. gdth_ha_str *ha;
  4168. Scsi_Cmnd *scp;
  4169. ulong flags;
  4170. char cmnd[MAX_COMMAND_SIZE];
  4171. void __user *argp = (void __user *)arg;
  4172. memset(cmnd, 0xff, 12);
  4173. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4174. switch (cmd) {
  4175. case GDTIOCTL_CTRCNT:
  4176. {
  4177. int cnt = gdth_ctr_count;
  4178. if (put_user(cnt, (int __user *)argp))
  4179. return -EFAULT;
  4180. break;
  4181. }
  4182. case GDTIOCTL_DRVERS:
  4183. {
  4184. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4185. if (put_user(ver, (int __user *)argp))
  4186. return -EFAULT;
  4187. break;
  4188. }
  4189. case GDTIOCTL_OSVERS:
  4190. {
  4191. gdth_ioctl_osvers osv;
  4192. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4193. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4194. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4195. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4196. return -EFAULT;
  4197. break;
  4198. }
  4199. case GDTIOCTL_CTRTYPE:
  4200. {
  4201. gdth_ioctl_ctrtype ctrt;
  4202. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4203. ctrt.ionode >= gdth_ctr_count)
  4204. return -EFAULT;
  4205. ha = shost_priv(gdth_ctr_tab[ctrt.ionode]);
  4206. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4207. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4208. } else {
  4209. if (ha->type != GDT_PCIMPR) {
  4210. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4211. } else {
  4212. ctrt.type =
  4213. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4214. if (ha->stype >= 0x300)
  4215. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4216. else
  4217. ctrt.ext_type = 0x6000 | ha->stype;
  4218. }
  4219. ctrt.device_id = ha->pdev->device;
  4220. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4221. }
  4222. ctrt.info = ha->brd_phys;
  4223. ctrt.oem_id = ha->oem_id;
  4224. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4225. return -EFAULT;
  4226. break;
  4227. }
  4228. case GDTIOCTL_GENERAL:
  4229. return ioc_general(argp, cmnd);
  4230. case GDTIOCTL_EVENT:
  4231. return ioc_event(argp);
  4232. case GDTIOCTL_LOCKDRV:
  4233. return ioc_lockdrv(argp);
  4234. case GDTIOCTL_LOCKCHN:
  4235. {
  4236. gdth_ioctl_lockchn lchn;
  4237. unchar i, j;
  4238. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4239. lchn.ionode >= gdth_ctr_count)
  4240. return -EFAULT;
  4241. ha = shost_priv(gdth_ctr_tab[lchn.ionode]);
  4242. i = lchn.channel;
  4243. if (i < ha->bus_cnt) {
  4244. if (lchn.lock) {
  4245. spin_lock_irqsave(&ha->smp_lock, flags);
  4246. ha->raw[i].lock = 1;
  4247. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4248. for (j = 0; j < ha->tid_cnt; ++j) {
  4249. gdth_wait_completion(ha, i, j);
  4250. gdth_stop_timeout(ha, i, j);
  4251. }
  4252. } else {
  4253. spin_lock_irqsave(&ha->smp_lock, flags);
  4254. ha->raw[i].lock = 0;
  4255. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4256. for (j = 0; j < ha->tid_cnt; ++j) {
  4257. gdth_start_timeout(ha, i, j);
  4258. gdth_next(ha);
  4259. }
  4260. }
  4261. }
  4262. break;
  4263. }
  4264. case GDTIOCTL_RESCAN:
  4265. return ioc_rescan(argp, cmnd);
  4266. case GDTIOCTL_HDRLIST:
  4267. return ioc_hdrlist(argp, cmnd);
  4268. case GDTIOCTL_RESET_BUS:
  4269. {
  4270. gdth_ioctl_reset res;
  4271. int rval;
  4272. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4273. res.ionode >= gdth_ctr_count)
  4274. return -EFAULT;
  4275. ha = shost_priv(gdth_ctr_tab[res.ionode]);
  4276. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4277. if (!scp)
  4278. return -ENOMEM;
  4279. scp->device = ha->sdev;
  4280. scp->cmd_len = 12;
  4281. scp->use_sg = 0;
  4282. scp->device->channel = res.number;
  4283. rval = gdth_eh_bus_reset(scp);
  4284. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4285. kfree(scp);
  4286. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4287. return -EFAULT;
  4288. break;
  4289. }
  4290. case GDTIOCTL_RESET_DRV:
  4291. return ioc_resetdrv(argp, cmnd);
  4292. default:
  4293. break;
  4294. }
  4295. return 0;
  4296. }
  4297. /* flush routine */
  4298. static void gdth_flush(gdth_ha_str *ha)
  4299. {
  4300. int i;
  4301. gdth_cmd_str gdtcmd;
  4302. char cmnd[MAX_COMMAND_SIZE];
  4303. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4304. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4305. for (i = 0; i < MAX_HDRIVES; ++i) {
  4306. if (ha->hdr[i].present) {
  4307. gdtcmd.BoardNode = LOCALBOARD;
  4308. gdtcmd.Service = CACHESERVICE;
  4309. gdtcmd.OpCode = GDT_FLUSH;
  4310. if (ha->cache_feat & GDT_64BIT) {
  4311. gdtcmd.u.cache64.DeviceNo = i;
  4312. gdtcmd.u.cache64.BlockNo = 1;
  4313. gdtcmd.u.cache64.sg_canz = 0;
  4314. } else {
  4315. gdtcmd.u.cache.DeviceNo = i;
  4316. gdtcmd.u.cache.BlockNo = 1;
  4317. gdtcmd.u.cache.sg_canz = 0;
  4318. }
  4319. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4320. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4321. }
  4322. }
  4323. }
  4324. /* shutdown routine */
  4325. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4326. {
  4327. int hanum;
  4328. #ifndef __alpha__
  4329. gdth_cmd_str gdtcmd;
  4330. char cmnd[MAX_COMMAND_SIZE];
  4331. #endif
  4332. if (notifier_disabled)
  4333. return NOTIFY_OK;
  4334. TRACE2(("gdth_halt() event %d\n",(int)event));
  4335. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4336. return NOTIFY_DONE;
  4337. notifier_disabled = 1;
  4338. printk("GDT-HA: Flushing all host drives .. ");
  4339. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  4340. gdth_ha_str *ha = shost_priv(gdth_ctr_tab[hanum]);
  4341. gdth_flush(ha);
  4342. #ifndef __alpha__
  4343. /* controller reset */
  4344. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4345. gdtcmd.BoardNode = LOCALBOARD;
  4346. gdtcmd.Service = CACHESERVICE;
  4347. gdtcmd.OpCode = GDT_RESET;
  4348. TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
  4349. gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
  4350. #endif
  4351. }
  4352. printk("Done.\n");
  4353. #ifdef GDTH_STATISTICS
  4354. del_timer(&gdth_timer);
  4355. #endif
  4356. return NOTIFY_OK;
  4357. }
  4358. /* configure lun */
  4359. static int gdth_slave_configure(struct scsi_device *sdev)
  4360. {
  4361. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4362. sdev->skip_ms_page_3f = 1;
  4363. sdev->skip_ms_page_8 = 1;
  4364. return 0;
  4365. }
  4366. static struct scsi_host_template driver_template = {
  4367. .name = "GDT SCSI Disk Array Controller",
  4368. .detect = gdth_detect,
  4369. .release = gdth_release,
  4370. .info = gdth_info,
  4371. .queuecommand = gdth_queuecommand,
  4372. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4373. .slave_configure = gdth_slave_configure,
  4374. .bios_param = gdth_bios_param,
  4375. .proc_info = gdth_proc_info,
  4376. .proc_name = "gdth",
  4377. .can_queue = GDTH_MAXCMDS,
  4378. .this_id = -1,
  4379. .sg_tablesize = GDTH_MAXSG,
  4380. .cmd_per_lun = GDTH_MAXC_P_L,
  4381. .unchecked_isa_dma = 1,
  4382. .use_clustering = ENABLE_CLUSTERING,
  4383. };
  4384. #ifdef CONFIG_ISA
  4385. static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
  4386. {
  4387. struct Scsi_Host *shp;
  4388. gdth_ha_str *ha;
  4389. dma_addr_t scratch_dma_handle = 0;
  4390. int error, hanum, i;
  4391. if (!gdth_search_isa(isa_bios))
  4392. return -ENXIO;
  4393. shp = scsi_register(shtp, sizeof(gdth_ha_str));
  4394. if (!shp)
  4395. return -ENOMEM;
  4396. ha = shost_priv(shp);
  4397. error = -ENODEV;
  4398. if (!gdth_init_isa(isa_bios,ha))
  4399. goto out_host_put;
  4400. /* controller found and initialized */
  4401. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4402. isa_bios, ha->irq, ha->drq);
  4403. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4404. if (error) {
  4405. printk("GDT-ISA: Unable to allocate IRQ\n");
  4406. goto out_host_put;
  4407. }
  4408. error = request_dma(ha->drq, "gdth");
  4409. if (error) {
  4410. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4411. goto out_free_irq;
  4412. }
  4413. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4414. enable_dma(ha->drq);
  4415. shp->unchecked_isa_dma = 1;
  4416. shp->irq = ha->irq;
  4417. shp->dma_channel = ha->drq;
  4418. hanum = gdth_ctr_count;
  4419. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4420. ha->hanum = (ushort)hanum;
  4421. ha->shost = shp;
  4422. ha->pccb = &ha->cmdext;
  4423. ha->ccb_phys = 0L;
  4424. ha->pdev = NULL;
  4425. error = -ENOMEM;
  4426. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4427. &scratch_dma_handle);
  4428. if (!ha->pscratch)
  4429. goto out_dec_counters;
  4430. ha->scratch_phys = scratch_dma_handle;
  4431. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4432. &scratch_dma_handle);
  4433. if (!ha->pmsg)
  4434. goto out_free_pscratch;
  4435. ha->msg_phys = scratch_dma_handle;
  4436. #ifdef INT_COAL
  4437. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4438. sizeof(gdth_coal_status) * MAXOFFSETS,
  4439. &scratch_dma_handle);
  4440. if (!ha->coal_stat)
  4441. goto out_free_pmsg;
  4442. ha->coal_stat_phys = scratch_dma_handle;
  4443. #endif
  4444. ha->scratch_busy = FALSE;
  4445. ha->req_first = NULL;
  4446. ha->tid_cnt = MAX_HDRIVES;
  4447. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4448. ha->tid_cnt = max_ids;
  4449. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4450. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4451. ha->scan_mode = rescan ? 0x10 : 0;
  4452. error = -ENODEV;
  4453. if (!gdth_search_drives(ha)) {
  4454. printk("GDT-ISA: Error during device scan\n");
  4455. goto out_free_coal_stat;
  4456. }
  4457. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4458. hdr_channel = ha->bus_cnt;
  4459. ha->virt_bus = hdr_channel;
  4460. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4461. shp->max_cmd_len = 16;
  4462. shp->max_id = ha->tid_cnt;
  4463. shp->max_lun = MAXLUN;
  4464. shp->max_channel = ha->bus_cnt;
  4465. spin_lock_init(&ha->smp_lock);
  4466. gdth_enable_int(ha);
  4467. return 0;
  4468. out_free_coal_stat:
  4469. #ifdef INT_COAL
  4470. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4471. ha->coal_stat, ha->coal_stat_phys);
  4472. out_free_pmsg:
  4473. #endif
  4474. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4475. ha->pmsg, ha->msg_phys);
  4476. out_free_pscratch:
  4477. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4478. ha->pscratch, ha->scratch_phys);
  4479. out_dec_counters:
  4480. gdth_ctr_count--;
  4481. out_free_irq:
  4482. free_irq(ha->irq, ha);
  4483. out_host_put:
  4484. scsi_unregister(shp);
  4485. return error;
  4486. }
  4487. #endif /* CONFIG_ISA */
  4488. #ifdef CONFIG_EISA
  4489. static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
  4490. ushort eisa_slot)
  4491. {
  4492. struct Scsi_Host *shp;
  4493. gdth_ha_str *ha;
  4494. dma_addr_t scratch_dma_handle = 0;
  4495. int error, hanum, i;
  4496. if (!gdth_search_eisa(eisa_slot))
  4497. return -ENXIO;
  4498. shp = scsi_register(shtp,sizeof(gdth_ha_str));
  4499. if (!shp)
  4500. return -ENOMEM;
  4501. ha = shost_priv(shp);
  4502. error = -ENODEV;
  4503. if (!gdth_init_eisa(eisa_slot,ha))
  4504. goto out_host_put;
  4505. /* controller found and initialized */
  4506. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4507. eisa_slot >> 12, ha->irq);
  4508. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4509. if (error) {
  4510. printk("GDT-EISA: Unable to allocate IRQ\n");
  4511. goto out_host_put;
  4512. }
  4513. shp->unchecked_isa_dma = 0;
  4514. shp->irq = ha->irq;
  4515. shp->dma_channel = 0xff;
  4516. hanum = gdth_ctr_count;
  4517. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4518. ha->hanum = (ushort)hanum;
  4519. ha->shost = shp;
  4520. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4521. ha->pccb = &ha->cmdext;
  4522. ha->ccb_phys = 0L;
  4523. error = -ENOMEM;
  4524. ha->pdev = NULL;
  4525. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4526. &scratch_dma_handle);
  4527. if (!ha->pscratch)
  4528. goto out_free_irq;
  4529. ha->scratch_phys = scratch_dma_handle;
  4530. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4531. &scratch_dma_handle);
  4532. if (!ha->pmsg)
  4533. goto out_free_pscratch;
  4534. ha->msg_phys = scratch_dma_handle;
  4535. #ifdef INT_COAL
  4536. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4537. sizeof(gdth_coal_status) * MAXOFFSETS,
  4538. &scratch_dma_handle);
  4539. if (!ha->coal_stat)
  4540. goto out_free_pmsg;
  4541. ha->coal_stat_phys = scratch_dma_handle;
  4542. #endif
  4543. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4544. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4545. if (!ha->ccb_phys)
  4546. goto out_free_coal_stat;
  4547. ha->scratch_busy = FALSE;
  4548. ha->req_first = NULL;
  4549. ha->tid_cnt = MAX_HDRIVES;
  4550. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4551. ha->tid_cnt = max_ids;
  4552. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4553. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4554. ha->scan_mode = rescan ? 0x10 : 0;
  4555. if (!gdth_search_drives(ha)) {
  4556. printk("GDT-EISA: Error during device scan\n");
  4557. error = -ENODEV;
  4558. goto out_free_ccb_phys;
  4559. }
  4560. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4561. hdr_channel = ha->bus_cnt;
  4562. ha->virt_bus = hdr_channel;
  4563. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4564. shp->max_cmd_len = 16;
  4565. shp->max_id = ha->tid_cnt;
  4566. shp->max_lun = MAXLUN;
  4567. shp->max_channel = ha->bus_cnt;
  4568. spin_lock_init(&ha->smp_lock);
  4569. gdth_enable_int(ha);
  4570. return 0;
  4571. out_free_ccb_phys:
  4572. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4573. PCI_DMA_BIDIRECTIONAL);
  4574. out_free_coal_stat:
  4575. #ifdef INT_COAL
  4576. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4577. ha->coal_stat, ha->coal_stat_phys);
  4578. out_free_pmsg:
  4579. #endif
  4580. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4581. ha->pmsg, ha->msg_phys);
  4582. out_free_pscratch:
  4583. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4584. ha->pscratch, ha->scratch_phys);
  4585. out_free_irq:
  4586. free_irq(ha->irq, ha);
  4587. gdth_ctr_count--;
  4588. out_host_put:
  4589. scsi_unregister(shp);
  4590. return error;
  4591. }
  4592. #endif /* CONFIG_EISA */
  4593. #ifdef CONFIG_PCI
  4594. static int gdth_pci_probe_one(struct scsi_host_template *shtp,
  4595. gdth_pci_str *pcistr, int ctr)
  4596. {
  4597. struct Scsi_Host *shp;
  4598. gdth_ha_str *ha;
  4599. dma_addr_t scratch_dma_handle = 0;
  4600. int error, hanum, i;
  4601. shp = scsi_register(shtp,sizeof(gdth_ha_str));
  4602. if (!shp)
  4603. return -ENOMEM;
  4604. ha = shost_priv(shp);
  4605. error = -ENODEV;
  4606. if (!gdth_init_pci(&pcistr[ctr],ha))
  4607. goto out_host_put;
  4608. /* controller found and initialized */
  4609. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4610. pcistr[ctr].pdev->bus->number,
  4611. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4612. ha->irq);
  4613. error = request_irq(ha->irq, gdth_interrupt,
  4614. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4615. if (error) {
  4616. printk("GDT-PCI: Unable to allocate IRQ\n");
  4617. goto out_host_put;
  4618. }
  4619. shp->unchecked_isa_dma = 0;
  4620. shp->irq = ha->irq;
  4621. shp->dma_channel = 0xff;
  4622. hanum = gdth_ctr_count;
  4623. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4624. ha->hanum = (ushort)hanum;
  4625. ha->shost = shp;
  4626. ha->pccb = &ha->cmdext;
  4627. ha->ccb_phys = 0L;
  4628. error = -ENOMEM;
  4629. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4630. &scratch_dma_handle);
  4631. if (!ha->pscratch)
  4632. goto out_free_irq;
  4633. ha->scratch_phys = scratch_dma_handle;
  4634. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4635. &scratch_dma_handle);
  4636. if (!ha->pmsg)
  4637. goto out_free_pscratch;
  4638. ha->msg_phys = scratch_dma_handle;
  4639. #ifdef INT_COAL
  4640. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4641. sizeof(gdth_coal_status) * MAXOFFSETS,
  4642. &scratch_dma_handle);
  4643. if (!ha->coal_stat)
  4644. goto out_free_pmsg;
  4645. ha->coal_stat_phys = scratch_dma_handle;
  4646. #endif
  4647. ha->scratch_busy = FALSE;
  4648. ha->req_first = NULL;
  4649. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4650. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4651. ha->tid_cnt = max_ids;
  4652. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4653. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4654. ha->scan_mode = rescan ? 0x10 : 0;
  4655. error = -ENODEV;
  4656. if (!gdth_search_drives(ha)) {
  4657. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4658. goto out_free_coal_stat;
  4659. }
  4660. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4661. hdr_channel = ha->bus_cnt;
  4662. ha->virt_bus = hdr_channel;
  4663. /* 64-bit DMA only supported from FW >= x.43 */
  4664. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4665. !ha->dma64_support) {
  4666. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4667. printk(KERN_WARNING "GDT-PCI %d: "
  4668. "Unable to set 32-bit DMA\n", ha->hanum);
  4669. goto out_free_coal_stat;
  4670. }
  4671. } else {
  4672. shp->max_cmd_len = 16;
  4673. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4674. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4675. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4676. printk(KERN_WARNING "GDT-PCI %d: "
  4677. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4678. goto out_free_coal_stat;
  4679. }
  4680. }
  4681. shp->max_id = ha->tid_cnt;
  4682. shp->max_lun = MAXLUN;
  4683. shp->max_channel = ha->bus_cnt;
  4684. spin_lock_init(&ha->smp_lock);
  4685. gdth_enable_int(ha);
  4686. return 0;
  4687. out_free_coal_stat:
  4688. #ifdef INT_COAL
  4689. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4690. ha->coal_stat, ha->coal_stat_phys);
  4691. out_free_pmsg:
  4692. #endif
  4693. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4694. ha->pmsg, ha->msg_phys);
  4695. out_free_pscratch:
  4696. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4697. ha->pscratch, ha->scratch_phys);
  4698. out_free_irq:
  4699. free_irq(ha->irq, ha);
  4700. gdth_ctr_count--;
  4701. out_host_put:
  4702. scsi_unregister(shp);
  4703. return error;
  4704. }
  4705. #endif /* CONFIG_PCI */
  4706. #include "scsi_module.c"
  4707. #ifndef MODULE
  4708. __setup("gdth=", option_setup);
  4709. #endif