netxen_nic_init.c 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  44. static void crb_addr_transform_setup(void)
  45. {
  46. crb_addr_transform(XDMA);
  47. crb_addr_transform(TIMR);
  48. crb_addr_transform(SRE);
  49. crb_addr_transform(SQN3);
  50. crb_addr_transform(SQN2);
  51. crb_addr_transform(SQN1);
  52. crb_addr_transform(SQN0);
  53. crb_addr_transform(SQS3);
  54. crb_addr_transform(SQS2);
  55. crb_addr_transform(SQS1);
  56. crb_addr_transform(SQS0);
  57. crb_addr_transform(RPMX7);
  58. crb_addr_transform(RPMX6);
  59. crb_addr_transform(RPMX5);
  60. crb_addr_transform(RPMX4);
  61. crb_addr_transform(RPMX3);
  62. crb_addr_transform(RPMX2);
  63. crb_addr_transform(RPMX1);
  64. crb_addr_transform(RPMX0);
  65. crb_addr_transform(ROMUSB);
  66. crb_addr_transform(SN);
  67. crb_addr_transform(QMN);
  68. crb_addr_transform(QMS);
  69. crb_addr_transform(PGNI);
  70. crb_addr_transform(PGND);
  71. crb_addr_transform(PGN3);
  72. crb_addr_transform(PGN2);
  73. crb_addr_transform(PGN1);
  74. crb_addr_transform(PGN0);
  75. crb_addr_transform(PGSI);
  76. crb_addr_transform(PGSD);
  77. crb_addr_transform(PGS3);
  78. crb_addr_transform(PGS2);
  79. crb_addr_transform(PGS1);
  80. crb_addr_transform(PGS0);
  81. crb_addr_transform(PS);
  82. crb_addr_transform(PH);
  83. crb_addr_transform(NIU);
  84. crb_addr_transform(I2Q);
  85. crb_addr_transform(EG);
  86. crb_addr_transform(MN);
  87. crb_addr_transform(MS);
  88. crb_addr_transform(CAS2);
  89. crb_addr_transform(CAS1);
  90. crb_addr_transform(CAS0);
  91. crb_addr_transform(CAM);
  92. crb_addr_transform(C2C1);
  93. crb_addr_transform(C2C0);
  94. crb_addr_transform(SMB);
  95. crb_addr_transform(OCM0);
  96. crb_addr_transform(I2C0);
  97. }
  98. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  99. {
  100. struct netxen_recv_context *recv_ctx;
  101. struct nx_host_rds_ring *rds_ring;
  102. struct netxen_rx_buffer *rx_buf;
  103. int i, ring;
  104. recv_ctx = &adapter->recv_ctx;
  105. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  106. rds_ring = &recv_ctx->rds_rings[ring];
  107. for (i = 0; i < rds_ring->num_desc; ++i) {
  108. rx_buf = &(rds_ring->rx_buf_arr[i]);
  109. if (rx_buf->state == NETXEN_BUFFER_FREE)
  110. continue;
  111. pci_unmap_single(adapter->pdev,
  112. rx_buf->dma,
  113. rds_ring->dma_size,
  114. PCI_DMA_FROMDEVICE);
  115. if (rx_buf->skb != NULL)
  116. dev_kfree_skb_any(rx_buf->skb);
  117. }
  118. }
  119. }
  120. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  121. {
  122. struct netxen_cmd_buffer *cmd_buf;
  123. struct netxen_skb_frag *buffrag;
  124. int i, j;
  125. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  126. cmd_buf = tx_ring->cmd_buf_arr;
  127. for (i = 0; i < tx_ring->num_desc; i++) {
  128. buffrag = cmd_buf->frag_array;
  129. if (buffrag->dma) {
  130. pci_unmap_single(adapter->pdev, buffrag->dma,
  131. buffrag->length, PCI_DMA_TODEVICE);
  132. buffrag->dma = 0ULL;
  133. }
  134. for (j = 0; j < cmd_buf->frag_count; j++) {
  135. buffrag++;
  136. if (buffrag->dma) {
  137. pci_unmap_page(adapter->pdev, buffrag->dma,
  138. buffrag->length,
  139. PCI_DMA_TODEVICE);
  140. buffrag->dma = 0ULL;
  141. }
  142. }
  143. if (cmd_buf->skb) {
  144. dev_kfree_skb_any(cmd_buf->skb);
  145. cmd_buf->skb = NULL;
  146. }
  147. cmd_buf++;
  148. }
  149. }
  150. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  151. {
  152. struct netxen_recv_context *recv_ctx;
  153. struct nx_host_rds_ring *rds_ring;
  154. struct nx_host_tx_ring *tx_ring;
  155. int ring;
  156. recv_ctx = &adapter->recv_ctx;
  157. if (recv_ctx->rds_rings == NULL)
  158. goto skip_rds;
  159. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  160. rds_ring = &recv_ctx->rds_rings[ring];
  161. vfree(rds_ring->rx_buf_arr);
  162. rds_ring->rx_buf_arr = NULL;
  163. }
  164. kfree(recv_ctx->rds_rings);
  165. skip_rds:
  166. if (adapter->tx_ring == NULL)
  167. return;
  168. tx_ring = adapter->tx_ring;
  169. vfree(tx_ring->cmd_buf_arr);
  170. kfree(tx_ring);
  171. adapter->tx_ring = NULL;
  172. }
  173. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  174. {
  175. struct netxen_recv_context *recv_ctx;
  176. struct nx_host_rds_ring *rds_ring;
  177. struct nx_host_sds_ring *sds_ring;
  178. struct nx_host_tx_ring *tx_ring;
  179. struct netxen_rx_buffer *rx_buf;
  180. int ring, i, size;
  181. struct netxen_cmd_buffer *cmd_buf_arr;
  182. struct net_device *netdev = adapter->netdev;
  183. struct pci_dev *pdev = adapter->pdev;
  184. size = sizeof(struct nx_host_tx_ring);
  185. tx_ring = kzalloc(size, GFP_KERNEL);
  186. if (tx_ring == NULL) {
  187. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  188. netdev->name);
  189. return -ENOMEM;
  190. }
  191. adapter->tx_ring = tx_ring;
  192. tx_ring->num_desc = adapter->num_txd;
  193. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  194. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  195. if (cmd_buf_arr == NULL) {
  196. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  197. netdev->name);
  198. return -ENOMEM;
  199. }
  200. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  201. tx_ring->cmd_buf_arr = cmd_buf_arr;
  202. recv_ctx = &adapter->recv_ctx;
  203. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  204. rds_ring = kzalloc(size, GFP_KERNEL);
  205. if (rds_ring == NULL) {
  206. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  207. netdev->name);
  208. return -ENOMEM;
  209. }
  210. recv_ctx->rds_rings = rds_ring;
  211. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  212. rds_ring = &recv_ctx->rds_rings[ring];
  213. switch (ring) {
  214. case RCV_RING_NORMAL:
  215. rds_ring->num_desc = adapter->num_rxd;
  216. if (adapter->ahw.cut_through) {
  217. rds_ring->dma_size =
  218. NX_CT_DEFAULT_RX_BUF_LEN;
  219. rds_ring->skb_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. } else {
  222. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  223. rds_ring->dma_size =
  224. NX_P3_RX_BUF_MAX_LEN;
  225. else
  226. rds_ring->dma_size =
  227. NX_P2_RX_BUF_MAX_LEN;
  228. rds_ring->skb_size =
  229. rds_ring->dma_size + NET_IP_ALIGN;
  230. }
  231. break;
  232. case RCV_RING_JUMBO:
  233. rds_ring->num_desc = adapter->num_jumbo_rxd;
  234. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  235. rds_ring->dma_size =
  236. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  237. else
  238. rds_ring->dma_size =
  239. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  240. if (adapter->capabilities & NX_CAP0_HW_LRO)
  241. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  242. rds_ring->skb_size =
  243. rds_ring->dma_size + NET_IP_ALIGN;
  244. break;
  245. case RCV_RING_LRO:
  246. rds_ring->num_desc = adapter->num_lro_rxd;
  247. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  248. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  249. break;
  250. }
  251. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  252. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL) {
  254. printk(KERN_ERR "%s: Failed to allocate "
  255. "rx buffer ring %d\n",
  256. netdev->name, ring);
  257. /* free whatever was already allocated */
  258. goto err_out;
  259. }
  260. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  261. INIT_LIST_HEAD(&rds_ring->free_list);
  262. /*
  263. * Now go through all of them, set reference handles
  264. * and put them in the queues.
  265. */
  266. rx_buf = rds_ring->rx_buf_arr;
  267. for (i = 0; i < rds_ring->num_desc; i++) {
  268. list_add_tail(&rx_buf->list,
  269. &rds_ring->free_list);
  270. rx_buf->ref_handle = i;
  271. rx_buf->state = NETXEN_BUFFER_FREE;
  272. rx_buf++;
  273. }
  274. spin_lock_init(&rds_ring->lock);
  275. }
  276. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  277. sds_ring = &recv_ctx->sds_rings[ring];
  278. sds_ring->irq = adapter->msix_entries[ring].vector;
  279. sds_ring->adapter = adapter;
  280. sds_ring->num_desc = adapter->num_rxd;
  281. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  282. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. /*
  290. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  291. * address to external PCI CRB address.
  292. */
  293. static u32 netxen_decode_crb_addr(u32 addr)
  294. {
  295. int i;
  296. u32 base_addr, offset, pci_base;
  297. crb_addr_transform_setup();
  298. pci_base = NETXEN_ADDR_ERROR;
  299. base_addr = addr & 0xfff00000;
  300. offset = addr & 0x000fffff;
  301. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  302. if (crb_addr_xform[i] == base_addr) {
  303. pci_base = i << 20;
  304. break;
  305. }
  306. }
  307. if (pci_base == NETXEN_ADDR_ERROR)
  308. return pci_base;
  309. else
  310. return (pci_base + offset);
  311. }
  312. #define NETXEN_MAX_ROM_WAIT_USEC 100
  313. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  314. {
  315. long timeout = 0;
  316. long done = 0;
  317. cond_resched();
  318. while (done == 0) {
  319. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  320. done &= 2;
  321. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  322. dev_err(&adapter->pdev->dev,
  323. "Timeout reached waiting for rom done");
  324. return -EIO;
  325. }
  326. udelay(1);
  327. }
  328. return 0;
  329. }
  330. static int do_rom_fast_read(struct netxen_adapter *adapter,
  331. int addr, int *valp)
  332. {
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  336. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  337. if (netxen_wait_rom_done(adapter)) {
  338. printk("Error waiting for rom done\n");
  339. return -EIO;
  340. }
  341. /* reset abyte_cnt and dummy_byte_cnt */
  342. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  343. udelay(10);
  344. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  345. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  346. return 0;
  347. }
  348. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  349. u8 *bytes, size_t size)
  350. {
  351. int addridx;
  352. int ret = 0;
  353. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  354. int v;
  355. ret = do_rom_fast_read(adapter, addridx, &v);
  356. if (ret != 0)
  357. break;
  358. *(__le32 *)bytes = cpu_to_le32(v);
  359. bytes += 4;
  360. }
  361. return ret;
  362. }
  363. int
  364. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  365. u8 *bytes, size_t size)
  366. {
  367. int ret;
  368. ret = netxen_rom_lock(adapter);
  369. if (ret < 0)
  370. return ret;
  371. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  372. netxen_rom_unlock(adapter);
  373. return ret;
  374. }
  375. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  376. {
  377. int ret;
  378. if (netxen_rom_lock(adapter) != 0)
  379. return -EIO;
  380. ret = do_rom_fast_read(adapter, addr, valp);
  381. netxen_rom_unlock(adapter);
  382. return ret;
  383. }
  384. #define NETXEN_BOARDTYPE 0x4008
  385. #define NETXEN_BOARDNUM 0x400c
  386. #define NETXEN_CHIPNUM 0x4010
  387. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  388. {
  389. int addr, val;
  390. int i, n, init_delay = 0;
  391. struct crb_addr_pair *buf;
  392. unsigned offset;
  393. u32 off;
  394. /* resetall */
  395. netxen_rom_lock(adapter);
  396. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  397. netxen_rom_unlock(adapter);
  398. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  399. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  400. (n != 0xcafecafe) ||
  401. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  402. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  403. "n: %08x\n", netxen_nic_driver_name, n);
  404. return -EIO;
  405. }
  406. offset = n & 0xffffU;
  407. n = (n >> 16) & 0xffffU;
  408. } else {
  409. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  410. !(n & 0x80000000)) {
  411. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  412. "n: %08x\n", netxen_nic_driver_name, n);
  413. return -EIO;
  414. }
  415. offset = 1;
  416. n &= ~0x80000000;
  417. }
  418. if (n >= 1024) {
  419. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  420. " initialized.\n", __func__, n);
  421. return -EIO;
  422. }
  423. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  424. if (buf == NULL) {
  425. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  426. netxen_nic_driver_name);
  427. return -ENOMEM;
  428. }
  429. for (i = 0; i < n; i++) {
  430. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  431. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  432. kfree(buf);
  433. return -EIO;
  434. }
  435. buf[i].addr = addr;
  436. buf[i].data = val;
  437. }
  438. for (i = 0; i < n; i++) {
  439. off = netxen_decode_crb_addr(buf[i].addr);
  440. if (off == NETXEN_ADDR_ERROR) {
  441. printk(KERN_ERR"CRB init value out of range %x\n",
  442. buf[i].addr);
  443. continue;
  444. }
  445. off += NETXEN_PCI_CRBSPACE;
  446. if (off & 1)
  447. continue;
  448. /* skipping cold reboot MAGIC */
  449. if (off == NETXEN_CAM_RAM(0x1fc))
  450. continue;
  451. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  452. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  453. continue;
  454. /* do not reset PCI */
  455. if (off == (ROMUSB_GLB + 0xbc))
  456. continue;
  457. if (off == (ROMUSB_GLB + 0xa8))
  458. continue;
  459. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  460. continue;
  461. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  462. continue;
  463. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  464. continue;
  465. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  466. continue;
  467. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  468. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  469. buf[i].data = 0x1020;
  470. /* skip the function enable register */
  471. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  472. continue;
  473. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  474. continue;
  475. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  476. continue;
  477. }
  478. init_delay = 1;
  479. /* After writing this register, HW needs time for CRB */
  480. /* to quiet down (else crb_window returns 0xffffffff) */
  481. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  482. init_delay = 1000;
  483. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  484. /* hold xdma in reset also */
  485. buf[i].data = NETXEN_NIC_XDMA_RESET;
  486. buf[i].data = 0x8000ff;
  487. }
  488. }
  489. NXWR32(adapter, off, buf[i].data);
  490. msleep(init_delay);
  491. }
  492. kfree(buf);
  493. /* disable_peg_cache_all */
  494. /* unreset_net_cache */
  495. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  496. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  497. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  498. }
  499. /* p2dn replyCount */
  500. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  501. /* disable_peg_cache 0 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  503. /* disable_peg_cache 1 */
  504. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  505. /* peg_clr_all */
  506. /* peg_clr 0 */
  507. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  509. /* peg_clr 1 */
  510. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  512. /* peg_clr 2 */
  513. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  515. /* peg_clr 3 */
  516. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  517. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  518. return 0;
  519. }
  520. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  521. {
  522. uint32_t i;
  523. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  524. __le32 entries = cpu_to_le32(directory->num_entries);
  525. for (i = 0; i < entries; i++) {
  526. __le32 offs = cpu_to_le32(directory->findex) +
  527. (i * cpu_to_le32(directory->entry_size));
  528. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  529. if (tab_type == section)
  530. return (struct uni_table_desc *) &unirom[offs];
  531. }
  532. return NULL;
  533. }
  534. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  535. static int
  536. netxen_nic_validate_header(struct netxen_adapter *adapter)
  537. {
  538. const u8 *unirom = adapter->fw->data;
  539. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  540. u32 fw_file_size = adapter->fw->size;
  541. u32 tab_size;
  542. __le32 entries;
  543. __le32 entry_size;
  544. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  545. return -EINVAL;
  546. entries = cpu_to_le32(directory->num_entries);
  547. entry_size = cpu_to_le32(directory->entry_size);
  548. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  549. if (fw_file_size < tab_size)
  550. return -EINVAL;
  551. return 0;
  552. }
  553. static int
  554. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  555. {
  556. struct uni_table_desc *tab_desc;
  557. struct uni_data_desc *descr;
  558. const u8 *unirom = adapter->fw->data;
  559. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  560. NX_UNI_BOOTLD_IDX_OFF));
  561. u32 offs;
  562. u32 tab_size;
  563. u32 data_size;
  564. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  565. if (!tab_desc)
  566. return -EINVAL;
  567. tab_size = cpu_to_le32(tab_desc->findex) +
  568. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  569. if (adapter->fw->size < tab_size)
  570. return -EINVAL;
  571. offs = cpu_to_le32(tab_desc->findex) +
  572. (cpu_to_le32(tab_desc->entry_size) * (idx));
  573. descr = (struct uni_data_desc *)&unirom[offs];
  574. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  575. if (adapter->fw->size < data_size)
  576. return -EINVAL;
  577. return 0;
  578. }
  579. static int
  580. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  581. {
  582. struct uni_table_desc *tab_desc;
  583. struct uni_data_desc *descr;
  584. const u8 *unirom = adapter->fw->data;
  585. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  586. NX_UNI_FIRMWARE_IDX_OFF));
  587. u32 offs;
  588. u32 tab_size;
  589. u32 data_size;
  590. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  591. if (!tab_desc)
  592. return -EINVAL;
  593. tab_size = cpu_to_le32(tab_desc->findex) +
  594. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  595. if (adapter->fw->size < tab_size)
  596. return -EINVAL;
  597. offs = cpu_to_le32(tab_desc->findex) +
  598. (cpu_to_le32(tab_desc->entry_size) * (idx));
  599. descr = (struct uni_data_desc *)&unirom[offs];
  600. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  601. if (adapter->fw->size < data_size)
  602. return -EINVAL;
  603. return 0;
  604. }
  605. static int
  606. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  607. {
  608. struct uni_table_desc *ptab_descr;
  609. const u8 *unirom = adapter->fw->data;
  610. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  611. 1 : netxen_p3_has_mn(adapter);
  612. __le32 entries;
  613. __le32 entry_size;
  614. u32 tab_size;
  615. u32 i;
  616. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  617. if (ptab_descr == NULL)
  618. return -EINVAL;
  619. entries = cpu_to_le32(ptab_descr->num_entries);
  620. entry_size = cpu_to_le32(ptab_descr->entry_size);
  621. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  622. if (adapter->fw->size < tab_size)
  623. return -EINVAL;
  624. nomn:
  625. for (i = 0; i < entries; i++) {
  626. __le32 flags, file_chiprev, offs;
  627. u8 chiprev = adapter->ahw.revision_id;
  628. uint32_t flagbit;
  629. offs = cpu_to_le32(ptab_descr->findex) +
  630. (i * cpu_to_le32(ptab_descr->entry_size));
  631. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  632. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  633. NX_UNI_CHIP_REV_OFF));
  634. flagbit = mn_present ? 1 : 2;
  635. if ((chiprev == file_chiprev) &&
  636. ((1ULL << flagbit) & flags)) {
  637. adapter->file_prd_off = offs;
  638. return 0;
  639. }
  640. }
  641. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  642. mn_present = 0;
  643. goto nomn;
  644. }
  645. return -EINVAL;
  646. }
  647. static int
  648. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  649. {
  650. if (netxen_nic_validate_header(adapter)) {
  651. dev_err(&adapter->pdev->dev,
  652. "unified image: header validation failed\n");
  653. return -EINVAL;
  654. }
  655. if (netxen_nic_validate_product_offs(adapter)) {
  656. dev_err(&adapter->pdev->dev,
  657. "unified image: product validation failed\n");
  658. return -EINVAL;
  659. }
  660. if (netxen_nic_validate_bootld(adapter)) {
  661. dev_err(&adapter->pdev->dev,
  662. "unified image: bootld validation failed\n");
  663. return -EINVAL;
  664. }
  665. if (netxen_nic_validate_fw(adapter)) {
  666. dev_err(&adapter->pdev->dev,
  667. "unified image: firmware validation failed\n");
  668. return -EINVAL;
  669. }
  670. return 0;
  671. }
  672. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  673. u32 section, u32 idx_offset)
  674. {
  675. const u8 *unirom = adapter->fw->data;
  676. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  677. idx_offset));
  678. struct uni_table_desc *tab_desc;
  679. __le32 offs;
  680. tab_desc = nx_get_table_desc(unirom, section);
  681. if (tab_desc == NULL)
  682. return NULL;
  683. offs = cpu_to_le32(tab_desc->findex) +
  684. (cpu_to_le32(tab_desc->entry_size) * idx);
  685. return (struct uni_data_desc *)&unirom[offs];
  686. }
  687. static u8 *
  688. nx_get_bootld_offs(struct netxen_adapter *adapter)
  689. {
  690. u32 offs = NETXEN_BOOTLD_START;
  691. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  692. offs = cpu_to_le32((nx_get_data_desc(adapter,
  693. NX_UNI_DIR_SECT_BOOTLD,
  694. NX_UNI_BOOTLD_IDX_OFF))->findex);
  695. return (u8 *)&adapter->fw->data[offs];
  696. }
  697. static u8 *
  698. nx_get_fw_offs(struct netxen_adapter *adapter)
  699. {
  700. u32 offs = NETXEN_IMAGE_START;
  701. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  702. offs = cpu_to_le32((nx_get_data_desc(adapter,
  703. NX_UNI_DIR_SECT_FW,
  704. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  705. return (u8 *)&adapter->fw->data[offs];
  706. }
  707. static __le32
  708. nx_get_fw_size(struct netxen_adapter *adapter)
  709. {
  710. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  711. return cpu_to_le32((nx_get_data_desc(adapter,
  712. NX_UNI_DIR_SECT_FW,
  713. NX_UNI_FIRMWARE_IDX_OFF))->size);
  714. else
  715. return cpu_to_le32(
  716. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  717. }
  718. static __le32
  719. nx_get_fw_version(struct netxen_adapter *adapter)
  720. {
  721. struct uni_data_desc *fw_data_desc;
  722. const struct firmware *fw = adapter->fw;
  723. __le32 major, minor, sub;
  724. const u8 *ver_str;
  725. int i, ret = 0;
  726. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  727. fw_data_desc = nx_get_data_desc(adapter,
  728. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  729. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  730. cpu_to_le32(fw_data_desc->size) - 17;
  731. for (i = 0; i < 12; i++) {
  732. if (!strncmp(&ver_str[i], "REV=", 4)) {
  733. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  734. &major, &minor, &sub);
  735. break;
  736. }
  737. }
  738. if (ret != 3)
  739. return 0;
  740. return major + (minor << 8) + (sub << 16);
  741. } else
  742. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  743. }
  744. static __le32
  745. nx_get_bios_version(struct netxen_adapter *adapter)
  746. {
  747. const struct firmware *fw = adapter->fw;
  748. __le32 bios_ver, prd_off = adapter->file_prd_off;
  749. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  750. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  751. + NX_UNI_BIOS_VERSION_OFF));
  752. return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) +
  753. (bios_ver >> 24);
  754. } else
  755. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  756. }
  757. int
  758. netxen_need_fw_reset(struct netxen_adapter *adapter)
  759. {
  760. u32 count, old_count;
  761. u32 val, version, major, minor, build;
  762. int i, timeout;
  763. u8 fw_type;
  764. /* NX2031 firmware doesn't support heartbit */
  765. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  766. return 1;
  767. if (adapter->need_fw_reset)
  768. return 1;
  769. /* last attempt had failed */
  770. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  771. return 1;
  772. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  773. for (i = 0; i < 10; i++) {
  774. timeout = msleep_interruptible(200);
  775. if (timeout) {
  776. NXWR32(adapter, CRB_CMDPEG_STATE,
  777. PHAN_INITIALIZE_FAILED);
  778. return -EINTR;
  779. }
  780. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  781. if (count != old_count)
  782. break;
  783. }
  784. /* firmware is dead */
  785. if (count == old_count)
  786. return 1;
  787. /* check if we have got newer or different file firmware */
  788. if (adapter->fw) {
  789. val = nx_get_fw_version(adapter);
  790. version = NETXEN_DECODE_VERSION(val);
  791. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  792. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  793. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  794. if (version > NETXEN_VERSION_CODE(major, minor, build))
  795. return 1;
  796. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  797. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  798. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  799. fw_type = (val & 0x4) ?
  800. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  801. if (adapter->fw_type != fw_type)
  802. return 1;
  803. }
  804. }
  805. return 0;
  806. }
  807. static char *fw_name[] = {
  808. NX_P2_MN_ROMIMAGE_NAME,
  809. NX_P3_CT_ROMIMAGE_NAME,
  810. NX_P3_MN_ROMIMAGE_NAME,
  811. NX_UNIFIED_ROMIMAGE_NAME,
  812. NX_FLASH_ROMIMAGE_NAME,
  813. };
  814. int
  815. netxen_load_firmware(struct netxen_adapter *adapter)
  816. {
  817. u64 *ptr64;
  818. u32 i, flashaddr, size;
  819. const struct firmware *fw = adapter->fw;
  820. struct pci_dev *pdev = adapter->pdev;
  821. dev_info(&pdev->dev, "loading firmware from %s\n",
  822. fw_name[adapter->fw_type]);
  823. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  824. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  825. if (fw) {
  826. __le64 data;
  827. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  828. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  829. flashaddr = NETXEN_BOOTLD_START;
  830. for (i = 0; i < size; i++) {
  831. data = cpu_to_le64(ptr64[i]);
  832. if (adapter->pci_mem_write(adapter, flashaddr, data))
  833. return -EIO;
  834. flashaddr += 8;
  835. }
  836. size = (__force u32)nx_get_fw_size(adapter) / 8;
  837. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  838. flashaddr = NETXEN_IMAGE_START;
  839. for (i = 0; i < size; i++) {
  840. data = cpu_to_le64(ptr64[i]);
  841. if (adapter->pci_mem_write(adapter,
  842. flashaddr, data))
  843. return -EIO;
  844. flashaddr += 8;
  845. }
  846. } else {
  847. u64 data;
  848. u32 hi, lo;
  849. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  850. flashaddr = NETXEN_BOOTLD_START;
  851. for (i = 0; i < size; i++) {
  852. if (netxen_rom_fast_read(adapter,
  853. flashaddr, (int *)&lo) != 0)
  854. return -EIO;
  855. if (netxen_rom_fast_read(adapter,
  856. flashaddr + 4, (int *)&hi) != 0)
  857. return -EIO;
  858. /* hi, lo are already in host endian byteorder */
  859. data = (((u64)hi << 32) | lo);
  860. if (adapter->pci_mem_write(adapter,
  861. flashaddr, data))
  862. return -EIO;
  863. flashaddr += 8;
  864. }
  865. }
  866. msleep(1);
  867. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  868. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  869. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  870. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  871. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  872. else {
  873. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  874. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  875. }
  876. return 0;
  877. }
  878. static int
  879. netxen_validate_firmware(struct netxen_adapter *adapter)
  880. {
  881. __le32 val;
  882. u32 ver, min_ver, bios;
  883. struct pci_dev *pdev = adapter->pdev;
  884. const struct firmware *fw = adapter->fw;
  885. u8 fw_type = adapter->fw_type;
  886. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  887. if (netxen_nic_validate_unified_romimage(adapter))
  888. return -EINVAL;
  889. } else {
  890. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  891. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  892. return -EINVAL;
  893. if (fw->size < NX_FW_MIN_SIZE)
  894. return -EINVAL;
  895. }
  896. val = nx_get_fw_version(adapter);
  897. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  898. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  899. else
  900. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  901. ver = NETXEN_DECODE_VERSION(val);
  902. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  903. dev_err(&pdev->dev,
  904. "%s: firmware version %d.%d.%d unsupported\n",
  905. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  906. return -EINVAL;
  907. }
  908. val = nx_get_bios_version(adapter);
  909. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  910. if ((__force u32)val != bios) {
  911. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  912. fw_name[fw_type]);
  913. return -EINVAL;
  914. }
  915. /* check if flashed firmware is newer */
  916. if (netxen_rom_fast_read(adapter,
  917. NX_FW_VERSION_OFFSET, (int *)&val))
  918. return -EIO;
  919. val = NETXEN_DECODE_VERSION(val);
  920. if (val > ver) {
  921. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  922. fw_name[fw_type]);
  923. return -EINVAL;
  924. }
  925. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  926. return 0;
  927. }
  928. static void
  929. nx_get_next_fwtype(struct netxen_adapter *adapter)
  930. {
  931. u8 fw_type;
  932. switch (adapter->fw_type) {
  933. case NX_UNKNOWN_ROMIMAGE:
  934. fw_type = NX_UNIFIED_ROMIMAGE;
  935. break;
  936. case NX_UNIFIED_ROMIMAGE:
  937. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  938. fw_type = NX_FLASH_ROMIMAGE;
  939. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  940. fw_type = NX_P2_MN_ROMIMAGE;
  941. else if (netxen_p3_has_mn(adapter))
  942. fw_type = NX_P3_MN_ROMIMAGE;
  943. else
  944. fw_type = NX_P3_CT_ROMIMAGE;
  945. break;
  946. case NX_P3_MN_ROMIMAGE:
  947. fw_type = NX_P3_CT_ROMIMAGE;
  948. break;
  949. case NX_P2_MN_ROMIMAGE:
  950. case NX_P3_CT_ROMIMAGE:
  951. default:
  952. fw_type = NX_FLASH_ROMIMAGE;
  953. break;
  954. }
  955. adapter->fw_type = fw_type;
  956. }
  957. static int
  958. netxen_p3_has_mn(struct netxen_adapter *adapter)
  959. {
  960. u32 capability, flashed_ver;
  961. capability = 0;
  962. /* NX2031 always had MN */
  963. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  964. return 1;
  965. netxen_rom_fast_read(adapter,
  966. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  967. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  968. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  969. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  970. if (capability & NX_PEG_TUNE_MN_PRESENT)
  971. return 1;
  972. }
  973. return 0;
  974. }
  975. void netxen_request_firmware(struct netxen_adapter *adapter)
  976. {
  977. struct pci_dev *pdev = adapter->pdev;
  978. int rc = 0;
  979. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  980. next:
  981. nx_get_next_fwtype(adapter);
  982. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  983. adapter->fw = NULL;
  984. } else {
  985. rc = request_firmware(&adapter->fw,
  986. fw_name[adapter->fw_type], &pdev->dev);
  987. if (rc != 0)
  988. goto next;
  989. rc = netxen_validate_firmware(adapter);
  990. if (rc != 0) {
  991. release_firmware(adapter->fw);
  992. msleep(1);
  993. goto next;
  994. }
  995. }
  996. }
  997. void
  998. netxen_release_firmware(struct netxen_adapter *adapter)
  999. {
  1000. if (adapter->fw)
  1001. release_firmware(adapter->fw);
  1002. adapter->fw = NULL;
  1003. }
  1004. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1005. {
  1006. u64 addr;
  1007. u32 hi, lo;
  1008. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1009. return 0;
  1010. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1011. NETXEN_HOST_DUMMY_DMA_SIZE,
  1012. &adapter->dummy_dma.phys_addr);
  1013. if (adapter->dummy_dma.addr == NULL) {
  1014. dev_err(&adapter->pdev->dev,
  1015. "ERROR: Could not allocate dummy DMA memory\n");
  1016. return -ENOMEM;
  1017. }
  1018. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1019. hi = (addr >> 32) & 0xffffffff;
  1020. lo = addr & 0xffffffff;
  1021. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1022. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1023. return 0;
  1024. }
  1025. /*
  1026. * NetXen DMA watchdog control:
  1027. *
  1028. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1029. * Bit 1 : disable_request => 1 req disable dma watchdog
  1030. * Bit 2 : enable_request => 1 req enable dma watchdog
  1031. * Bit 3-31 : unused
  1032. */
  1033. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1034. {
  1035. int i = 100;
  1036. u32 ctrl;
  1037. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1038. return;
  1039. if (!adapter->dummy_dma.addr)
  1040. return;
  1041. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1042. if ((ctrl & 0x1) != 0) {
  1043. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1044. while ((ctrl & 0x1) != 0) {
  1045. msleep(50);
  1046. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1047. if (--i == 0)
  1048. break;
  1049. };
  1050. }
  1051. if (i) {
  1052. pci_free_consistent(adapter->pdev,
  1053. NETXEN_HOST_DUMMY_DMA_SIZE,
  1054. adapter->dummy_dma.addr,
  1055. adapter->dummy_dma.phys_addr);
  1056. adapter->dummy_dma.addr = NULL;
  1057. } else
  1058. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1059. }
  1060. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1061. {
  1062. u32 val = 0;
  1063. int retries = 60;
  1064. if (pegtune_val)
  1065. return 0;
  1066. do {
  1067. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1068. switch (val) {
  1069. case PHAN_INITIALIZE_COMPLETE:
  1070. case PHAN_INITIALIZE_ACK:
  1071. return 0;
  1072. case PHAN_INITIALIZE_FAILED:
  1073. goto out_err;
  1074. default:
  1075. break;
  1076. }
  1077. msleep(500);
  1078. } while (--retries);
  1079. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1080. out_err:
  1081. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1082. return -EIO;
  1083. }
  1084. static int
  1085. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1086. {
  1087. u32 val = 0;
  1088. int retries = 2000;
  1089. do {
  1090. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1091. if (val == PHAN_PEG_RCV_INITIALIZED)
  1092. return 0;
  1093. msleep(10);
  1094. } while (--retries);
  1095. if (!retries) {
  1096. printk(KERN_ERR "Receive Peg initialization not "
  1097. "complete, state: 0x%x.\n", val);
  1098. return -EIO;
  1099. }
  1100. return 0;
  1101. }
  1102. int netxen_init_firmware(struct netxen_adapter *adapter)
  1103. {
  1104. int err;
  1105. err = netxen_receive_peg_ready(adapter);
  1106. if (err)
  1107. return err;
  1108. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1109. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1110. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1111. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1112. return err;
  1113. }
  1114. static void
  1115. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1116. {
  1117. u32 cable_OUI;
  1118. u16 cable_len;
  1119. u16 link_speed;
  1120. u8 link_status, module, duplex, autoneg;
  1121. struct net_device *netdev = adapter->netdev;
  1122. adapter->has_link_events = 1;
  1123. cable_OUI = msg->body[1] & 0xffffffff;
  1124. cable_len = (msg->body[1] >> 32) & 0xffff;
  1125. link_speed = (msg->body[1] >> 48) & 0xffff;
  1126. link_status = msg->body[2] & 0xff;
  1127. duplex = (msg->body[2] >> 16) & 0xff;
  1128. autoneg = (msg->body[2] >> 24) & 0xff;
  1129. module = (msg->body[2] >> 8) & 0xff;
  1130. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1131. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1132. netdev->name, cable_OUI, cable_len);
  1133. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1134. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1135. netdev->name, cable_len);
  1136. }
  1137. netxen_advert_link_change(adapter, link_status);
  1138. /* update link parameters */
  1139. if (duplex == LINKEVENT_FULL_DUPLEX)
  1140. adapter->link_duplex = DUPLEX_FULL;
  1141. else
  1142. adapter->link_duplex = DUPLEX_HALF;
  1143. adapter->module_type = module;
  1144. adapter->link_autoneg = autoneg;
  1145. adapter->link_speed = link_speed;
  1146. }
  1147. static void
  1148. netxen_handle_fw_message(int desc_cnt, int index,
  1149. struct nx_host_sds_ring *sds_ring)
  1150. {
  1151. nx_fw_msg_t msg;
  1152. struct status_desc *desc;
  1153. int i = 0, opcode;
  1154. while (desc_cnt > 0 && i < 8) {
  1155. desc = &sds_ring->desc_head[index];
  1156. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1157. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1158. index = get_next_index(index, sds_ring->num_desc);
  1159. desc_cnt--;
  1160. }
  1161. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1162. switch (opcode) {
  1163. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1164. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1165. break;
  1166. default:
  1167. break;
  1168. }
  1169. }
  1170. static int
  1171. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1172. struct nx_host_rds_ring *rds_ring,
  1173. struct netxen_rx_buffer *buffer)
  1174. {
  1175. struct sk_buff *skb;
  1176. dma_addr_t dma;
  1177. struct pci_dev *pdev = adapter->pdev;
  1178. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1179. if (!buffer->skb)
  1180. return 1;
  1181. skb = buffer->skb;
  1182. if (!adapter->ahw.cut_through)
  1183. skb_reserve(skb, 2);
  1184. dma = pci_map_single(pdev, skb->data,
  1185. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1186. if (pci_dma_mapping_error(pdev, dma)) {
  1187. dev_kfree_skb_any(skb);
  1188. buffer->skb = NULL;
  1189. return 1;
  1190. }
  1191. buffer->skb = skb;
  1192. buffer->dma = dma;
  1193. buffer->state = NETXEN_BUFFER_BUSY;
  1194. return 0;
  1195. }
  1196. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1197. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1198. {
  1199. struct netxen_rx_buffer *buffer;
  1200. struct sk_buff *skb;
  1201. buffer = &rds_ring->rx_buf_arr[index];
  1202. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1203. PCI_DMA_FROMDEVICE);
  1204. skb = buffer->skb;
  1205. if (!skb)
  1206. goto no_skb;
  1207. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1208. adapter->stats.csummed++;
  1209. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1210. } else
  1211. skb->ip_summed = CHECKSUM_NONE;
  1212. skb->dev = adapter->netdev;
  1213. buffer->skb = NULL;
  1214. no_skb:
  1215. buffer->state = NETXEN_BUFFER_FREE;
  1216. return skb;
  1217. }
  1218. static struct netxen_rx_buffer *
  1219. netxen_process_rcv(struct netxen_adapter *adapter,
  1220. struct nx_host_sds_ring *sds_ring,
  1221. int ring, u64 sts_data0)
  1222. {
  1223. struct net_device *netdev = adapter->netdev;
  1224. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1225. struct netxen_rx_buffer *buffer;
  1226. struct sk_buff *skb;
  1227. struct nx_host_rds_ring *rds_ring;
  1228. int index, length, cksum, pkt_offset;
  1229. if (unlikely(ring >= adapter->max_rds_rings))
  1230. return NULL;
  1231. rds_ring = &recv_ctx->rds_rings[ring];
  1232. index = netxen_get_sts_refhandle(sts_data0);
  1233. if (unlikely(index >= rds_ring->num_desc))
  1234. return NULL;
  1235. buffer = &rds_ring->rx_buf_arr[index];
  1236. length = netxen_get_sts_totallength(sts_data0);
  1237. cksum = netxen_get_sts_status(sts_data0);
  1238. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1239. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1240. if (!skb)
  1241. return buffer;
  1242. if (length > rds_ring->skb_size)
  1243. skb_put(skb, rds_ring->skb_size);
  1244. else
  1245. skb_put(skb, length);
  1246. if (pkt_offset)
  1247. skb_pull(skb, pkt_offset);
  1248. skb->truesize = skb->len + sizeof(struct sk_buff);
  1249. skb->protocol = eth_type_trans(skb, netdev);
  1250. napi_gro_receive(&sds_ring->napi, skb);
  1251. adapter->stats.rx_pkts++;
  1252. adapter->stats.rxbytes += length;
  1253. return buffer;
  1254. }
  1255. #define TCP_HDR_SIZE 20
  1256. #define TCP_TS_OPTION_SIZE 12
  1257. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1258. static struct netxen_rx_buffer *
  1259. netxen_process_lro(struct netxen_adapter *adapter,
  1260. struct nx_host_sds_ring *sds_ring,
  1261. int ring, u64 sts_data0, u64 sts_data1)
  1262. {
  1263. struct net_device *netdev = adapter->netdev;
  1264. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1265. struct netxen_rx_buffer *buffer;
  1266. struct sk_buff *skb;
  1267. struct nx_host_rds_ring *rds_ring;
  1268. struct iphdr *iph;
  1269. struct tcphdr *th;
  1270. bool push, timestamp;
  1271. int l2_hdr_offset, l4_hdr_offset;
  1272. int index;
  1273. u16 lro_length, length, data_offset;
  1274. u32 seq_number;
  1275. if (unlikely(ring > adapter->max_rds_rings))
  1276. return NULL;
  1277. rds_ring = &recv_ctx->rds_rings[ring];
  1278. index = netxen_get_lro_sts_refhandle(sts_data0);
  1279. if (unlikely(index > rds_ring->num_desc))
  1280. return NULL;
  1281. buffer = &rds_ring->rx_buf_arr[index];
  1282. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1283. lro_length = netxen_get_lro_sts_length(sts_data0);
  1284. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1285. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1286. push = netxen_get_lro_sts_push_flag(sts_data0);
  1287. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1288. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1289. if (!skb)
  1290. return buffer;
  1291. if (timestamp)
  1292. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1293. else
  1294. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1295. skb_put(skb, lro_length + data_offset);
  1296. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1297. skb_pull(skb, l2_hdr_offset);
  1298. skb->protocol = eth_type_trans(skb, netdev);
  1299. iph = (struct iphdr *)skb->data;
  1300. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1301. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1302. iph->tot_len = htons(length);
  1303. iph->check = 0;
  1304. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1305. th->psh = push;
  1306. th->seq = htonl(seq_number);
  1307. length = skb->len;
  1308. netif_receive_skb(skb);
  1309. adapter->stats.lro_pkts++;
  1310. adapter->stats.rxbytes += length;
  1311. return buffer;
  1312. }
  1313. #define netxen_merge_rx_buffers(list, head) \
  1314. do { list_splice_tail_init(list, head); } while (0);
  1315. int
  1316. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1317. {
  1318. struct netxen_adapter *adapter = sds_ring->adapter;
  1319. struct list_head *cur;
  1320. struct status_desc *desc;
  1321. struct netxen_rx_buffer *rxbuf;
  1322. u32 consumer = sds_ring->consumer;
  1323. int count = 0;
  1324. u64 sts_data0, sts_data1;
  1325. int opcode, ring = 0, desc_cnt;
  1326. while (count < max) {
  1327. desc = &sds_ring->desc_head[consumer];
  1328. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1329. if (!(sts_data0 & STATUS_OWNER_HOST))
  1330. break;
  1331. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1332. opcode = netxen_get_sts_opcode(sts_data0);
  1333. switch (opcode) {
  1334. case NETXEN_NIC_RXPKT_DESC:
  1335. case NETXEN_OLD_RXPKT_DESC:
  1336. case NETXEN_NIC_SYN_OFFLOAD:
  1337. ring = netxen_get_sts_type(sts_data0);
  1338. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1339. ring, sts_data0);
  1340. break;
  1341. case NETXEN_NIC_LRO_DESC:
  1342. ring = netxen_get_lro_sts_type(sts_data0);
  1343. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1344. rxbuf = netxen_process_lro(adapter, sds_ring,
  1345. ring, sts_data0, sts_data1);
  1346. break;
  1347. case NETXEN_NIC_RESPONSE_DESC:
  1348. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1349. default:
  1350. goto skip;
  1351. }
  1352. WARN_ON(desc_cnt > 1);
  1353. if (rxbuf)
  1354. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1355. skip:
  1356. for (; desc_cnt > 0; desc_cnt--) {
  1357. desc = &sds_ring->desc_head[consumer];
  1358. desc->status_desc_data[0] =
  1359. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1360. consumer = get_next_index(consumer, sds_ring->num_desc);
  1361. }
  1362. count++;
  1363. }
  1364. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1365. struct nx_host_rds_ring *rds_ring =
  1366. &adapter->recv_ctx.rds_rings[ring];
  1367. if (!list_empty(&sds_ring->free_list[ring])) {
  1368. list_for_each(cur, &sds_ring->free_list[ring]) {
  1369. rxbuf = list_entry(cur,
  1370. struct netxen_rx_buffer, list);
  1371. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1372. }
  1373. spin_lock(&rds_ring->lock);
  1374. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1375. &rds_ring->free_list);
  1376. spin_unlock(&rds_ring->lock);
  1377. }
  1378. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1379. }
  1380. if (count) {
  1381. sds_ring->consumer = consumer;
  1382. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1383. }
  1384. return count;
  1385. }
  1386. /* Process Command status ring */
  1387. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1388. {
  1389. u32 sw_consumer, hw_consumer;
  1390. int count = 0, i;
  1391. struct netxen_cmd_buffer *buffer;
  1392. struct pci_dev *pdev = adapter->pdev;
  1393. struct net_device *netdev = adapter->netdev;
  1394. struct netxen_skb_frag *frag;
  1395. int done = 0;
  1396. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1397. if (!spin_trylock(&adapter->tx_clean_lock))
  1398. return 1;
  1399. sw_consumer = tx_ring->sw_consumer;
  1400. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1401. while (sw_consumer != hw_consumer) {
  1402. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1403. if (buffer->skb) {
  1404. frag = &buffer->frag_array[0];
  1405. pci_unmap_single(pdev, frag->dma, frag->length,
  1406. PCI_DMA_TODEVICE);
  1407. frag->dma = 0ULL;
  1408. for (i = 1; i < buffer->frag_count; i++) {
  1409. frag++; /* Get the next frag */
  1410. pci_unmap_page(pdev, frag->dma, frag->length,
  1411. PCI_DMA_TODEVICE);
  1412. frag->dma = 0ULL;
  1413. }
  1414. adapter->stats.xmitfinished++;
  1415. dev_kfree_skb_any(buffer->skb);
  1416. buffer->skb = NULL;
  1417. }
  1418. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1419. if (++count >= MAX_STATUS_HANDLE)
  1420. break;
  1421. }
  1422. if (count && netif_running(netdev)) {
  1423. tx_ring->sw_consumer = sw_consumer;
  1424. smp_mb();
  1425. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1426. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1427. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1428. netif_wake_queue(netdev);
  1429. adapter->tx_timeo_cnt = 0;
  1430. }
  1431. __netif_tx_unlock(tx_ring->txq);
  1432. }
  1433. }
  1434. /*
  1435. * If everything is freed up to consumer then check if the ring is full
  1436. * If the ring is full then check if more needs to be freed and
  1437. * schedule the call back again.
  1438. *
  1439. * This happens when there are 2 CPUs. One could be freeing and the
  1440. * other filling it. If the ring is full when we get out of here and
  1441. * the card has already interrupted the host then the host can miss the
  1442. * interrupt.
  1443. *
  1444. * There is still a possible race condition and the host could miss an
  1445. * interrupt. The card has to take care of this.
  1446. */
  1447. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1448. done = (sw_consumer == hw_consumer);
  1449. spin_unlock(&adapter->tx_clean_lock);
  1450. return (done);
  1451. }
  1452. void
  1453. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1454. struct nx_host_rds_ring *rds_ring)
  1455. {
  1456. struct rcv_desc *pdesc;
  1457. struct netxen_rx_buffer *buffer;
  1458. int producer, count = 0;
  1459. netxen_ctx_msg msg = 0;
  1460. struct list_head *head;
  1461. producer = rds_ring->producer;
  1462. spin_lock(&rds_ring->lock);
  1463. head = &rds_ring->free_list;
  1464. while (!list_empty(head)) {
  1465. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1466. if (!buffer->skb) {
  1467. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1468. break;
  1469. }
  1470. count++;
  1471. list_del(&buffer->list);
  1472. /* make a rcv descriptor */
  1473. pdesc = &rds_ring->desc_head[producer];
  1474. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1475. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1476. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1477. producer = get_next_index(producer, rds_ring->num_desc);
  1478. }
  1479. spin_unlock(&rds_ring->lock);
  1480. if (count) {
  1481. rds_ring->producer = producer;
  1482. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1483. (producer-1) & (rds_ring->num_desc-1));
  1484. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1485. /*
  1486. * Write a doorbell msg to tell phanmon of change in
  1487. * receive ring producer
  1488. * Only for firmware version < 4.0.0
  1489. */
  1490. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1491. netxen_set_msg_privid(msg);
  1492. netxen_set_msg_count(msg,
  1493. ((producer - 1) &
  1494. (rds_ring->num_desc - 1)));
  1495. netxen_set_msg_ctxid(msg, adapter->portnum);
  1496. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1497. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1498. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1499. }
  1500. }
  1501. }
  1502. static void
  1503. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1504. struct nx_host_rds_ring *rds_ring)
  1505. {
  1506. struct rcv_desc *pdesc;
  1507. struct netxen_rx_buffer *buffer;
  1508. int producer, count = 0;
  1509. struct list_head *head;
  1510. producer = rds_ring->producer;
  1511. if (!spin_trylock(&rds_ring->lock))
  1512. return;
  1513. head = &rds_ring->free_list;
  1514. while (!list_empty(head)) {
  1515. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1516. if (!buffer->skb) {
  1517. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1518. break;
  1519. }
  1520. count++;
  1521. list_del(&buffer->list);
  1522. /* make a rcv descriptor */
  1523. pdesc = &rds_ring->desc_head[producer];
  1524. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1525. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1526. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1527. producer = get_next_index(producer, rds_ring->num_desc);
  1528. }
  1529. if (count) {
  1530. rds_ring->producer = producer;
  1531. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1532. (producer - 1) & (rds_ring->num_desc - 1));
  1533. }
  1534. spin_unlock(&rds_ring->lock);
  1535. }
  1536. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1537. {
  1538. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1539. return;
  1540. }