iwl-rx.c 37 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. unsigned long flags;
  126. u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
  127. u32 reg;
  128. int ret = 0;
  129. spin_lock_irqsave(&q->lock, flags);
  130. if (q->need_update == 0)
  131. goto exit_unlock;
  132. /* If power-saving is in use, make sure device is awake */
  133. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  134. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  135. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  136. IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n",
  137. reg);
  138. iwl_set_bit(priv, CSR_GP_CNTRL,
  139. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  140. goto exit_unlock;
  141. }
  142. q->write_actual = (q->write & ~0x7);
  143. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  144. /* Else device is assumed to be awake */
  145. } else {
  146. /* Device expects a multiple of 8 */
  147. q->write_actual = (q->write & ~0x7);
  148. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  149. }
  150. q->need_update = 0;
  151. exit_unlock:
  152. spin_unlock_irqrestore(&q->lock, flags);
  153. return ret;
  154. }
  155. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  156. /**
  157. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  158. */
  159. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  160. dma_addr_t dma_addr)
  161. {
  162. return cpu_to_le32((u32)(dma_addr >> 8));
  163. }
  164. /**
  165. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  166. *
  167. * If there are slots in the RX queue that need to be restocked,
  168. * and we have free pre-allocated buffers, fill the ranks as much
  169. * as we can, pulling from rx_free.
  170. *
  171. * This moves the 'write' index forward to catch up with 'processed', and
  172. * also updates the memory address in the firmware to reference the new
  173. * target buffer.
  174. */
  175. int iwl_rx_queue_restock(struct iwl_priv *priv)
  176. {
  177. struct iwl_rx_queue *rxq = &priv->rxq;
  178. struct list_head *element;
  179. struct iwl_rx_mem_buffer *rxb;
  180. unsigned long flags;
  181. int write;
  182. int ret = 0;
  183. spin_lock_irqsave(&rxq->lock, flags);
  184. write = rxq->write & ~0x7;
  185. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  186. /* Get next free Rx buffer, remove from free list */
  187. element = rxq->rx_free.next;
  188. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  189. list_del(element);
  190. /* Point to Rx buffer via next RBD in circular buffer */
  191. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma);
  192. rxq->queue[rxq->write] = rxb;
  193. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  194. rxq->free_count--;
  195. }
  196. spin_unlock_irqrestore(&rxq->lock, flags);
  197. /* If the pre-allocated buffer pool is dropping low, schedule to
  198. * refill it */
  199. if (rxq->free_count <= RX_LOW_WATERMARK)
  200. queue_work(priv->workqueue, &priv->rx_replenish);
  201. /* If we've added more space for the firmware to place data, tell it.
  202. * Increment device's write pointer in multiples of 8. */
  203. if (rxq->write_actual != (rxq->write & ~0x7)) {
  204. spin_lock_irqsave(&rxq->lock, flags);
  205. rxq->need_update = 1;
  206. spin_unlock_irqrestore(&rxq->lock, flags);
  207. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  208. }
  209. return ret;
  210. }
  211. EXPORT_SYMBOL(iwl_rx_queue_restock);
  212. /**
  213. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  214. *
  215. * When moving to rx_free an SKB is allocated for the slot.
  216. *
  217. * Also restock the Rx queue via iwl_rx_queue_restock.
  218. * This is called as a scheduled work item (except for during initialization)
  219. */
  220. void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  221. {
  222. struct iwl_rx_queue *rxq = &priv->rxq;
  223. struct list_head *element;
  224. struct iwl_rx_mem_buffer *rxb;
  225. struct page *page;
  226. unsigned long flags;
  227. gfp_t gfp_mask = priority;
  228. while (1) {
  229. spin_lock_irqsave(&rxq->lock, flags);
  230. if (list_empty(&rxq->rx_used)) {
  231. spin_unlock_irqrestore(&rxq->lock, flags);
  232. return;
  233. }
  234. spin_unlock_irqrestore(&rxq->lock, flags);
  235. if (rxq->free_count > RX_LOW_WATERMARK)
  236. gfp_mask |= __GFP_NOWARN;
  237. if (priv->hw_params.rx_page_order > 0)
  238. gfp_mask |= __GFP_COMP;
  239. /* Alloc a new receive buffer */
  240. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  241. if (!page) {
  242. if (net_ratelimit())
  243. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  244. "order: %d\n",
  245. priv->hw_params.rx_page_order);
  246. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  247. net_ratelimit())
  248. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  249. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  250. rxq->free_count);
  251. /* We don't reschedule replenish work here -- we will
  252. * call the restock method and if it still needs
  253. * more buffers it will schedule replenish */
  254. return;
  255. }
  256. spin_lock_irqsave(&rxq->lock, flags);
  257. if (list_empty(&rxq->rx_used)) {
  258. spin_unlock_irqrestore(&rxq->lock, flags);
  259. __free_pages(page, priv->hw_params.rx_page_order);
  260. return;
  261. }
  262. element = rxq->rx_used.next;
  263. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  264. list_del(element);
  265. spin_unlock_irqrestore(&rxq->lock, flags);
  266. rxb->page = page;
  267. /* Get physical address of the RB */
  268. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  269. PAGE_SIZE << priv->hw_params.rx_page_order,
  270. PCI_DMA_FROMDEVICE);
  271. /* dma address must be no more than 36 bits */
  272. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  273. /* and also 256 byte aligned! */
  274. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  275. spin_lock_irqsave(&rxq->lock, flags);
  276. list_add_tail(&rxb->list, &rxq->rx_free);
  277. rxq->free_count++;
  278. priv->alloc_rxb_page++;
  279. spin_unlock_irqrestore(&rxq->lock, flags);
  280. }
  281. }
  282. void iwl_rx_replenish(struct iwl_priv *priv)
  283. {
  284. unsigned long flags;
  285. iwl_rx_allocate(priv, GFP_KERNEL);
  286. spin_lock_irqsave(&priv->lock, flags);
  287. iwl_rx_queue_restock(priv);
  288. spin_unlock_irqrestore(&priv->lock, flags);
  289. }
  290. EXPORT_SYMBOL(iwl_rx_replenish);
  291. void iwl_rx_replenish_now(struct iwl_priv *priv)
  292. {
  293. iwl_rx_allocate(priv, GFP_ATOMIC);
  294. iwl_rx_queue_restock(priv);
  295. }
  296. EXPORT_SYMBOL(iwl_rx_replenish_now);
  297. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  298. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  299. * This free routine walks the list of POOL entries and if SKB is set to
  300. * non NULL it is unmapped and freed
  301. */
  302. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  303. {
  304. int i;
  305. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  306. if (rxq->pool[i].page != NULL) {
  307. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  308. PAGE_SIZE << priv->hw_params.rx_page_order,
  309. PCI_DMA_FROMDEVICE);
  310. __iwl_free_pages(priv, rxq->pool[i].page);
  311. rxq->pool[i].page = NULL;
  312. }
  313. }
  314. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  315. rxq->dma_addr);
  316. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  317. rxq->rb_stts, rxq->rb_stts_dma);
  318. rxq->bd = NULL;
  319. rxq->rb_stts = NULL;
  320. }
  321. EXPORT_SYMBOL(iwl_rx_queue_free);
  322. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  323. {
  324. struct iwl_rx_queue *rxq = &priv->rxq;
  325. struct pci_dev *dev = priv->pci_dev;
  326. int i;
  327. spin_lock_init(&rxq->lock);
  328. INIT_LIST_HEAD(&rxq->rx_free);
  329. INIT_LIST_HEAD(&rxq->rx_used);
  330. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  331. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  332. if (!rxq->bd)
  333. goto err_bd;
  334. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  335. &rxq->rb_stts_dma);
  336. if (!rxq->rb_stts)
  337. goto err_rb;
  338. /* Fill the rx_used queue with _all_ of the Rx buffers */
  339. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  340. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  341. /* Set us so that we have processed and used all buffers, but have
  342. * not restocked the Rx queue with fresh buffers */
  343. rxq->read = rxq->write = 0;
  344. rxq->write_actual = 0;
  345. rxq->free_count = 0;
  346. rxq->need_update = 0;
  347. return 0;
  348. err_rb:
  349. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  350. rxq->dma_addr);
  351. err_bd:
  352. return -ENOMEM;
  353. }
  354. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  355. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  356. {
  357. unsigned long flags;
  358. int i;
  359. spin_lock_irqsave(&rxq->lock, flags);
  360. INIT_LIST_HEAD(&rxq->rx_free);
  361. INIT_LIST_HEAD(&rxq->rx_used);
  362. /* Fill the rx_used queue with _all_ of the Rx buffers */
  363. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  364. /* In the reset function, these buffers may have been allocated
  365. * to an SKB, so we need to unmap and free potential storage */
  366. if (rxq->pool[i].page != NULL) {
  367. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  368. PAGE_SIZE << priv->hw_params.rx_page_order,
  369. PCI_DMA_FROMDEVICE);
  370. __iwl_free_pages(priv, rxq->pool[i].page);
  371. rxq->pool[i].page = NULL;
  372. }
  373. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  374. }
  375. /* Set us so that we have processed and used all buffers, but have
  376. * not restocked the Rx queue with fresh buffers */
  377. rxq->read = rxq->write = 0;
  378. rxq->write_actual = 0;
  379. rxq->free_count = 0;
  380. spin_unlock_irqrestore(&rxq->lock, flags);
  381. }
  382. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  383. {
  384. u32 rb_size;
  385. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  386. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  387. if (!priv->cfg->use_isr_legacy)
  388. rb_timeout = RX_RB_TIMEOUT;
  389. if (priv->cfg->mod_params->amsdu_size_8K)
  390. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  391. else
  392. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  393. /* Stop Rx DMA */
  394. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  395. /* Reset driver's Rx queue write index */
  396. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  397. /* Tell device where to find RBD circular buffer in DRAM */
  398. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  399. (u32)(rxq->dma_addr >> 8));
  400. /* Tell device where in DRAM to update its Rx status */
  401. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  402. rxq->rb_stts_dma >> 4);
  403. /* Enable Rx DMA
  404. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  405. * the credit mechanism in 5000 HW RX FIFO
  406. * Direct rx interrupts to hosts
  407. * Rx buffer size 4 or 8k
  408. * RB timeout 0x10
  409. * 256 RBDs
  410. */
  411. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  412. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  413. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  414. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  415. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  416. rb_size|
  417. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  418. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  419. /* Set interrupt coalescing timer to default (2048 usecs) */
  420. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  421. return 0;
  422. }
  423. int iwl_rxq_stop(struct iwl_priv *priv)
  424. {
  425. /* stop Rx DMA */
  426. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  427. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  428. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  429. return 0;
  430. }
  431. EXPORT_SYMBOL(iwl_rxq_stop);
  432. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  433. struct iwl_rx_mem_buffer *rxb)
  434. {
  435. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  436. struct iwl_missed_beacon_notif *missed_beacon;
  437. missed_beacon = &pkt->u.missed_beacon;
  438. if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
  439. priv->missed_beacon_threshold) {
  440. IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  441. le32_to_cpu(missed_beacon->consecutive_missed_beacons),
  442. le32_to_cpu(missed_beacon->total_missed_becons),
  443. le32_to_cpu(missed_beacon->num_recvd_beacons),
  444. le32_to_cpu(missed_beacon->num_expected_beacons));
  445. if (!test_bit(STATUS_SCANNING, &priv->status))
  446. iwl_init_sensitivity(priv);
  447. }
  448. }
  449. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  450. void iwl_rx_spectrum_measure_notif(struct iwl_priv *priv,
  451. struct iwl_rx_mem_buffer *rxb)
  452. {
  453. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  454. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  455. if (!report->state) {
  456. IWL_DEBUG_11H(priv,
  457. "Spectrum Measure Notification: Start\n");
  458. return;
  459. }
  460. memcpy(&priv->measure_report, report, sizeof(*report));
  461. priv->measurement_status |= MEASUREMENT_READY;
  462. }
  463. EXPORT_SYMBOL(iwl_rx_spectrum_measure_notif);
  464. /* Calculate noise level, based on measurements during network silence just
  465. * before arriving beacon. This measurement can be done only if we know
  466. * exactly when to expect beacons, therefore only when we're associated. */
  467. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  468. {
  469. struct statistics_rx_non_phy *rx_info
  470. = &(priv->statistics.rx.general);
  471. int num_active_rx = 0;
  472. int total_silence = 0;
  473. int bcn_silence_a =
  474. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  475. int bcn_silence_b =
  476. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  477. int bcn_silence_c =
  478. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  479. if (bcn_silence_a) {
  480. total_silence += bcn_silence_a;
  481. num_active_rx++;
  482. }
  483. if (bcn_silence_b) {
  484. total_silence += bcn_silence_b;
  485. num_active_rx++;
  486. }
  487. if (bcn_silence_c) {
  488. total_silence += bcn_silence_c;
  489. num_active_rx++;
  490. }
  491. /* Average among active antennas */
  492. if (num_active_rx)
  493. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  494. else
  495. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  496. IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
  497. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  498. priv->last_rx_noise);
  499. }
  500. #ifdef CONFIG_IWLWIFI_DEBUG
  501. /*
  502. * based on the assumption of all statistics counter are in DWORD
  503. * FIXME: This function is for debugging, do not deal with
  504. * the case of counters roll-over.
  505. */
  506. static void iwl_accumulative_statistics(struct iwl_priv *priv,
  507. __le32 *stats)
  508. {
  509. int i;
  510. __le32 *prev_stats;
  511. u32 *accum_stats;
  512. u32 *delta, *max_delta;
  513. prev_stats = (__le32 *)&priv->statistics;
  514. accum_stats = (u32 *)&priv->accum_statistics;
  515. delta = (u32 *)&priv->delta_statistics;
  516. max_delta = (u32 *)&priv->max_delta;
  517. for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics);
  518. i += sizeof(__le32), stats++, prev_stats++, delta++,
  519. max_delta++, accum_stats++) {
  520. if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
  521. *delta = (le32_to_cpu(*stats) -
  522. le32_to_cpu(*prev_stats));
  523. *accum_stats += *delta;
  524. if (*delta > *max_delta)
  525. *max_delta = *delta;
  526. }
  527. }
  528. /* reset accumulative statistics for "no-counter" type statistics */
  529. priv->accum_statistics.general.temperature =
  530. priv->statistics.general.temperature;
  531. priv->accum_statistics.general.temperature_m =
  532. priv->statistics.general.temperature_m;
  533. priv->accum_statistics.general.ttl_timestamp =
  534. priv->statistics.general.ttl_timestamp;
  535. priv->accum_statistics.tx.tx_power.ant_a =
  536. priv->statistics.tx.tx_power.ant_a;
  537. priv->accum_statistics.tx.tx_power.ant_b =
  538. priv->statistics.tx.tx_power.ant_b;
  539. priv->accum_statistics.tx.tx_power.ant_c =
  540. priv->statistics.tx.tx_power.ant_c;
  541. }
  542. #endif
  543. #define REG_RECALIB_PERIOD (60)
  544. #define PLCP_MSG "plcp_err exceeded %u, %u, %u, %u, %u, %d, %u mSecs\n"
  545. void iwl_rx_statistics(struct iwl_priv *priv,
  546. struct iwl_rx_mem_buffer *rxb)
  547. {
  548. int change;
  549. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  550. int combined_plcp_delta;
  551. unsigned int plcp_msec;
  552. unsigned long plcp_received_jiffies;
  553. IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
  554. (int)sizeof(priv->statistics),
  555. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  556. change = ((priv->statistics.general.temperature !=
  557. pkt->u.stats.general.temperature) ||
  558. ((priv->statistics.flag &
  559. STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
  560. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
  561. #ifdef CONFIG_IWLWIFI_DEBUG
  562. iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
  563. #endif
  564. /*
  565. * check for plcp_err and trigger radio reset if it exceeds
  566. * the plcp error threshold plcp_delta.
  567. */
  568. plcp_received_jiffies = jiffies;
  569. plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
  570. (long) priv->plcp_jiffies);
  571. priv->plcp_jiffies = plcp_received_jiffies;
  572. /*
  573. * check to make sure plcp_msec is not 0 to prevent division
  574. * by zero.
  575. */
  576. if (plcp_msec) {
  577. combined_plcp_delta =
  578. (le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err) -
  579. le32_to_cpu(priv->statistics.rx.ofdm.plcp_err)) +
  580. (le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err) -
  581. le32_to_cpu(priv->statistics.rx.ofdm_ht.plcp_err));
  582. if ((combined_plcp_delta > 0) &&
  583. ((combined_plcp_delta * 100) / plcp_msec) >
  584. priv->cfg->plcp_delta_threshold) {
  585. /*
  586. * if plcp_err exceed the threshold, the following
  587. * data is printed in csv format:
  588. * Text: plcp_err exceeded %d,
  589. * Received ofdm.plcp_err,
  590. * Current ofdm.plcp_err,
  591. * Received ofdm_ht.plcp_err,
  592. * Current ofdm_ht.plcp_err,
  593. * combined_plcp_delta,
  594. * plcp_msec
  595. */
  596. IWL_DEBUG_RADIO(priv, PLCP_MSG,
  597. priv->cfg->plcp_delta_threshold,
  598. le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err),
  599. le32_to_cpu(priv->statistics.rx.ofdm.plcp_err),
  600. le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err),
  601. le32_to_cpu(
  602. priv->statistics.rx.ofdm_ht.plcp_err),
  603. combined_plcp_delta, plcp_msec);
  604. /*
  605. * Reset the RF radio due to the high plcp
  606. * error rate
  607. */
  608. iwl_force_rf_reset(priv);
  609. }
  610. }
  611. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  612. set_bit(STATUS_STATISTICS, &priv->status);
  613. /* Reschedule the statistics timer to occur in
  614. * REG_RECALIB_PERIOD seconds to ensure we get a
  615. * thermal update even if the uCode doesn't give
  616. * us one */
  617. mod_timer(&priv->statistics_periodic, jiffies +
  618. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  619. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  620. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  621. iwl_rx_calc_noise(priv);
  622. queue_work(priv->workqueue, &priv->run_time_calib_work);
  623. }
  624. if (priv->cfg->ops->lib->temp_ops.temperature && change)
  625. priv->cfg->ops->lib->temp_ops.temperature(priv);
  626. }
  627. EXPORT_SYMBOL(iwl_rx_statistics);
  628. void iwl_reply_statistics(struct iwl_priv *priv,
  629. struct iwl_rx_mem_buffer *rxb)
  630. {
  631. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  632. if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
  633. #ifdef CONFIG_IWLWIFI_DEBUG
  634. memset(&priv->accum_statistics, 0,
  635. sizeof(struct iwl_notif_statistics));
  636. memset(&priv->delta_statistics, 0,
  637. sizeof(struct iwl_notif_statistics));
  638. memset(&priv->max_delta, 0,
  639. sizeof(struct iwl_notif_statistics));
  640. #endif
  641. IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
  642. }
  643. iwl_rx_statistics(priv, rxb);
  644. }
  645. EXPORT_SYMBOL(iwl_reply_statistics);
  646. /* Calc max signal level (dBm) among 3 possible receivers */
  647. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  648. struct iwl_rx_phy_res *rx_resp)
  649. {
  650. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  651. }
  652. #ifdef CONFIG_IWLWIFI_DEBUG
  653. /**
  654. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  655. *
  656. * You may hack this function to show different aspects of received frames,
  657. * including selective frame dumps.
  658. * group100 parameter selects whether to show 1 out of 100 good data frames.
  659. * All beacon and probe response frames are printed.
  660. */
  661. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  662. struct iwl_rx_phy_res *phy_res, u16 length,
  663. struct ieee80211_hdr *header, int group100)
  664. {
  665. u32 to_us;
  666. u32 print_summary = 0;
  667. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  668. u32 hundred = 0;
  669. u32 dataframe = 0;
  670. __le16 fc;
  671. u16 seq_ctl;
  672. u16 channel;
  673. u16 phy_flags;
  674. u32 rate_n_flags;
  675. u32 tsf_low;
  676. int rssi;
  677. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  678. return;
  679. /* MAC header */
  680. fc = header->frame_control;
  681. seq_ctl = le16_to_cpu(header->seq_ctrl);
  682. /* metadata */
  683. channel = le16_to_cpu(phy_res->channel);
  684. phy_flags = le16_to_cpu(phy_res->phy_flags);
  685. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  686. /* signal statistics */
  687. rssi = iwl_calc_rssi(priv, phy_res);
  688. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  689. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  690. /* if data frame is to us and all is good,
  691. * (optionally) print summary for only 1 out of every 100 */
  692. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  693. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  694. dataframe = 1;
  695. if (!group100)
  696. print_summary = 1; /* print each frame */
  697. else if (priv->framecnt_to_us < 100) {
  698. priv->framecnt_to_us++;
  699. print_summary = 0;
  700. } else {
  701. priv->framecnt_to_us = 0;
  702. print_summary = 1;
  703. hundred = 1;
  704. }
  705. } else {
  706. /* print summary for all other frames */
  707. print_summary = 1;
  708. }
  709. if (print_summary) {
  710. char *title;
  711. int rate_idx;
  712. u32 bitrate;
  713. if (hundred)
  714. title = "100Frames";
  715. else if (ieee80211_has_retry(fc))
  716. title = "Retry";
  717. else if (ieee80211_is_assoc_resp(fc))
  718. title = "AscRsp";
  719. else if (ieee80211_is_reassoc_resp(fc))
  720. title = "RasRsp";
  721. else if (ieee80211_is_probe_resp(fc)) {
  722. title = "PrbRsp";
  723. print_dump = 1; /* dump frame contents */
  724. } else if (ieee80211_is_beacon(fc)) {
  725. title = "Beacon";
  726. print_dump = 1; /* dump frame contents */
  727. } else if (ieee80211_is_atim(fc))
  728. title = "ATIM";
  729. else if (ieee80211_is_auth(fc))
  730. title = "Auth";
  731. else if (ieee80211_is_deauth(fc))
  732. title = "DeAuth";
  733. else if (ieee80211_is_disassoc(fc))
  734. title = "DisAssoc";
  735. else
  736. title = "Frame";
  737. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  738. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  739. bitrate = 0;
  740. WARN_ON_ONCE(1);
  741. } else {
  742. bitrate = iwl_rates[rate_idx].ieee / 2;
  743. }
  744. /* print frame summary.
  745. * MAC addresses show just the last byte (for brevity),
  746. * but you can hack it to show more, if you'd like to. */
  747. if (dataframe)
  748. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  749. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  750. title, le16_to_cpu(fc), header->addr1[5],
  751. length, rssi, channel, bitrate);
  752. else {
  753. /* src/dst addresses assume managed mode */
  754. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  755. "len=%u, rssi=%d, tim=%lu usec, "
  756. "phy=0x%02x, chnl=%d\n",
  757. title, le16_to_cpu(fc), header->addr1[5],
  758. header->addr3[5], length, rssi,
  759. tsf_low - priv->scan_start_tsf,
  760. phy_flags, channel);
  761. }
  762. }
  763. if (print_dump)
  764. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  765. }
  766. #endif
  767. /*
  768. * returns non-zero if packet should be dropped
  769. */
  770. int iwl_set_decrypted_flag(struct iwl_priv *priv,
  771. struct ieee80211_hdr *hdr,
  772. u32 decrypt_res,
  773. struct ieee80211_rx_status *stats)
  774. {
  775. u16 fc = le16_to_cpu(hdr->frame_control);
  776. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  777. return 0;
  778. if (!(fc & IEEE80211_FCTL_PROTECTED))
  779. return 0;
  780. IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res);
  781. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  782. case RX_RES_STATUS_SEC_TYPE_TKIP:
  783. /* The uCode has got a bad phase 1 Key, pushes the packet.
  784. * Decryption will be done in SW. */
  785. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  786. RX_RES_STATUS_BAD_KEY_TTAK)
  787. break;
  788. case RX_RES_STATUS_SEC_TYPE_WEP:
  789. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  790. RX_RES_STATUS_BAD_ICV_MIC) {
  791. /* bad ICV, the packet is destroyed since the
  792. * decryption is inplace, drop it */
  793. IWL_DEBUG_RX(priv, "Packet destroyed\n");
  794. return -1;
  795. }
  796. case RX_RES_STATUS_SEC_TYPE_CCMP:
  797. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  798. RX_RES_STATUS_DECRYPT_OK) {
  799. IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n");
  800. stats->flag |= RX_FLAG_DECRYPTED;
  801. }
  802. break;
  803. default:
  804. break;
  805. }
  806. return 0;
  807. }
  808. EXPORT_SYMBOL(iwl_set_decrypted_flag);
  809. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  810. {
  811. u32 decrypt_out = 0;
  812. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  813. RX_RES_STATUS_STATION_FOUND)
  814. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  815. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  816. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  817. /* packet was not encrypted */
  818. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  819. RX_RES_STATUS_SEC_TYPE_NONE)
  820. return decrypt_out;
  821. /* packet was encrypted with unknown alg */
  822. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  823. RX_RES_STATUS_SEC_TYPE_ERR)
  824. return decrypt_out;
  825. /* decryption was not done in HW */
  826. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  827. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  828. return decrypt_out;
  829. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  830. case RX_RES_STATUS_SEC_TYPE_CCMP:
  831. /* alg is CCM: check MIC only */
  832. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  833. /* Bad MIC */
  834. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  835. else
  836. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  837. break;
  838. case RX_RES_STATUS_SEC_TYPE_TKIP:
  839. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  840. /* Bad TTAK */
  841. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  842. break;
  843. }
  844. /* fall through if TTAK OK */
  845. default:
  846. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  847. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  848. else
  849. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  850. break;
  851. };
  852. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  853. decrypt_in, decrypt_out);
  854. return decrypt_out;
  855. }
  856. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  857. struct ieee80211_hdr *hdr,
  858. u16 len,
  859. u32 ampdu_status,
  860. struct iwl_rx_mem_buffer *rxb,
  861. struct ieee80211_rx_status *stats)
  862. {
  863. struct sk_buff *skb;
  864. int ret = 0;
  865. __le16 fc = hdr->frame_control;
  866. /* We only process data packets if the interface is open */
  867. if (unlikely(!priv->is_open)) {
  868. IWL_DEBUG_DROP_LIMIT(priv,
  869. "Dropping packet while interface is not open.\n");
  870. return;
  871. }
  872. /* In case of HW accelerated crypto and bad decryption, drop */
  873. if (!priv->cfg->mod_params->sw_crypto &&
  874. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  875. return;
  876. skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
  877. if (!skb) {
  878. IWL_ERR(priv, "alloc_skb failed\n");
  879. return;
  880. }
  881. skb_reserve(skb, IWL_LINK_HDR_MAX);
  882. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  883. /* mac80211 currently doesn't support paged SKB. Convert it to
  884. * linear SKB for management frame and data frame requires
  885. * software decryption or software defragementation. */
  886. if (ieee80211_is_mgmt(fc) ||
  887. ieee80211_has_protected(fc) ||
  888. ieee80211_has_morefrags(fc) ||
  889. le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
  890. ret = skb_linearize(skb);
  891. else
  892. ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
  893. 0 : -ENOMEM;
  894. if (ret) {
  895. kfree_skb(skb);
  896. goto out;
  897. }
  898. /*
  899. * XXX: We cannot touch the page and its virtual memory (hdr) after
  900. * here. It might have already been freed by the above skb change.
  901. */
  902. iwl_update_stats(priv, false, fc, len);
  903. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  904. ieee80211_rx(priv->hw, skb);
  905. out:
  906. priv->alloc_rxb_page--;
  907. rxb->page = NULL;
  908. }
  909. /* This is necessary only for a number of statistics, see the caller. */
  910. static int iwl_is_network_packet(struct iwl_priv *priv,
  911. struct ieee80211_hdr *header)
  912. {
  913. /* Filter incoming packets to determine if they are targeted toward
  914. * this network, discarding packets coming from ourselves */
  915. switch (priv->iw_mode) {
  916. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  917. /* packets to our IBSS update information */
  918. return !compare_ether_addr(header->addr3, priv->bssid);
  919. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  920. /* packets to our IBSS update information */
  921. return !compare_ether_addr(header->addr2, priv->bssid);
  922. default:
  923. return 1;
  924. }
  925. }
  926. /* Called for REPLY_RX (legacy ABG frames), or
  927. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  928. void iwl_rx_reply_rx(struct iwl_priv *priv,
  929. struct iwl_rx_mem_buffer *rxb)
  930. {
  931. struct ieee80211_hdr *header;
  932. struct ieee80211_rx_status rx_status;
  933. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  934. struct iwl_rx_phy_res *phy_res;
  935. __le32 rx_pkt_status;
  936. struct iwl4965_rx_mpdu_res_start *amsdu;
  937. u32 len;
  938. u32 ampdu_status;
  939. u32 rate_n_flags;
  940. /**
  941. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  942. * REPLY_RX: physical layer info is in this buffer
  943. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  944. * command and cached in priv->last_phy_res
  945. *
  946. * Here we set up local variables depending on which command is
  947. * received.
  948. */
  949. if (pkt->hdr.cmd == REPLY_RX) {
  950. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  951. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  952. + phy_res->cfg_phy_cnt);
  953. len = le16_to_cpu(phy_res->byte_count);
  954. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  955. phy_res->cfg_phy_cnt + len);
  956. ampdu_status = le32_to_cpu(rx_pkt_status);
  957. } else {
  958. if (!priv->last_phy_res[0]) {
  959. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  960. return;
  961. }
  962. phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  963. amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  964. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  965. len = le16_to_cpu(amsdu->byte_count);
  966. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  967. ampdu_status = iwl_translate_rx_status(priv,
  968. le32_to_cpu(rx_pkt_status));
  969. }
  970. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  971. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  972. phy_res->cfg_phy_cnt);
  973. return;
  974. }
  975. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  976. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  977. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  978. le32_to_cpu(rx_pkt_status));
  979. return;
  980. }
  981. /* This will be used in several places later */
  982. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  983. /* rx_status carries information about the packet to mac80211 */
  984. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  985. rx_status.freq =
  986. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  987. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  988. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  989. rx_status.rate_idx =
  990. iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  991. rx_status.flag = 0;
  992. /* TSF isn't reliable. In order to allow smooth user experience,
  993. * this W/A doesn't propagate it to the mac80211 */
  994. /*rx_status.flag |= RX_FLAG_TSFT;*/
  995. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  996. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  997. rx_status.signal = iwl_calc_rssi(priv, phy_res);
  998. /* Meaningful noise values are available only from beacon statistics,
  999. * which are gathered only when associated, and indicate noise
  1000. * only for the associated network channel ...
  1001. * Ignore these noise values while scanning (other channels) */
  1002. if (iwl_is_associated(priv) &&
  1003. !test_bit(STATUS_SCANNING, &priv->status)) {
  1004. rx_status.noise = priv->last_rx_noise;
  1005. } else {
  1006. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1007. }
  1008. /* Reset beacon noise level if not associated. */
  1009. if (!iwl_is_associated(priv))
  1010. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1011. #ifdef CONFIG_IWLWIFI_DEBUG
  1012. /* Set "1" to report good data frames in groups of 100 */
  1013. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  1014. iwl_dbg_report_frame(priv, phy_res, len, header, 1);
  1015. #endif
  1016. iwl_dbg_log_rx_data_frame(priv, len, header);
  1017. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, TSF %llu\n",
  1018. rx_status.signal, rx_status.noise,
  1019. (unsigned long long)rx_status.mactime);
  1020. /*
  1021. * "antenna number"
  1022. *
  1023. * It seems that the antenna field in the phy flags value
  1024. * is actually a bit field. This is undefined by radiotap,
  1025. * it wants an actual antenna number but I always get "7"
  1026. * for most legacy frames I receive indicating that the
  1027. * same frame was received on all three RX chains.
  1028. *
  1029. * I think this field should be removed in favor of a
  1030. * new 802.11n radiotap field "RX chains" that is defined
  1031. * as a bitmask.
  1032. */
  1033. rx_status.antenna =
  1034. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  1035. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  1036. /* set the preamble flag if appropriate */
  1037. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1038. rx_status.flag |= RX_FLAG_SHORTPRE;
  1039. /* Set up the HT phy flags */
  1040. if (rate_n_flags & RATE_MCS_HT_MSK)
  1041. rx_status.flag |= RX_FLAG_HT;
  1042. if (rate_n_flags & RATE_MCS_HT40_MSK)
  1043. rx_status.flag |= RX_FLAG_40MHZ;
  1044. if (rate_n_flags & RATE_MCS_SGI_MSK)
  1045. rx_status.flag |= RX_FLAG_SHORT_GI;
  1046. if (iwl_is_network_packet(priv, header)) {
  1047. priv->last_rx_rssi = rx_status.signal;
  1048. priv->last_beacon_time = priv->ucode_beacon_time;
  1049. priv->last_tsf = le64_to_cpu(phy_res->timestamp);
  1050. }
  1051. iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  1052. rxb, &rx_status);
  1053. }
  1054. EXPORT_SYMBOL(iwl_rx_reply_rx);
  1055. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1056. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1057. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  1058. struct iwl_rx_mem_buffer *rxb)
  1059. {
  1060. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1061. priv->last_phy_res[0] = 1;
  1062. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  1063. sizeof(struct iwl_rx_phy_res));
  1064. }
  1065. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);