cnic.c 141 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  55. static LIST_HEAD(cnic_dev_list);
  56. static LIST_HEAD(cnic_udev_list);
  57. static DEFINE_RWLOCK(cnic_dev_lock);
  58. static DEFINE_MUTEX(cnic_lock);
  59. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  60. static int cnic_service_bnx2(void *, void *);
  61. static int cnic_service_bnx2x(void *, void *);
  62. static int cnic_ctl(void *, struct cnic_ctl_info *);
  63. static struct cnic_ops cnic_bnx2_ops = {
  64. .cnic_owner = THIS_MODULE,
  65. .cnic_handler = cnic_service_bnx2,
  66. .cnic_ctl = cnic_ctl,
  67. };
  68. static struct cnic_ops cnic_bnx2x_ops = {
  69. .cnic_owner = THIS_MODULE,
  70. .cnic_handler = cnic_service_bnx2x,
  71. .cnic_ctl = cnic_ctl,
  72. };
  73. static struct workqueue_struct *cnic_wq;
  74. static void cnic_shutdown_rings(struct cnic_dev *);
  75. static void cnic_init_rings(struct cnic_dev *);
  76. static int cnic_cm_set_pg(struct cnic_sock *);
  77. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  78. {
  79. struct cnic_uio_dev *udev = uinfo->priv;
  80. struct cnic_dev *dev;
  81. if (!capable(CAP_NET_ADMIN))
  82. return -EPERM;
  83. if (udev->uio_dev != -1)
  84. return -EBUSY;
  85. rtnl_lock();
  86. dev = udev->dev;
  87. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  88. rtnl_unlock();
  89. return -ENODEV;
  90. }
  91. udev->uio_dev = iminor(inode);
  92. cnic_shutdown_rings(dev);
  93. cnic_init_rings(dev);
  94. rtnl_unlock();
  95. return 0;
  96. }
  97. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  98. {
  99. struct cnic_uio_dev *udev = uinfo->priv;
  100. udev->uio_dev = -1;
  101. return 0;
  102. }
  103. static inline void cnic_hold(struct cnic_dev *dev)
  104. {
  105. atomic_inc(&dev->ref_count);
  106. }
  107. static inline void cnic_put(struct cnic_dev *dev)
  108. {
  109. atomic_dec(&dev->ref_count);
  110. }
  111. static inline void csk_hold(struct cnic_sock *csk)
  112. {
  113. atomic_inc(&csk->ref_count);
  114. }
  115. static inline void csk_put(struct cnic_sock *csk)
  116. {
  117. atomic_dec(&csk->ref_count);
  118. }
  119. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  120. {
  121. struct cnic_dev *cdev;
  122. read_lock(&cnic_dev_lock);
  123. list_for_each_entry(cdev, &cnic_dev_list, list) {
  124. if (netdev == cdev->netdev) {
  125. cnic_hold(cdev);
  126. read_unlock(&cnic_dev_lock);
  127. return cdev;
  128. }
  129. }
  130. read_unlock(&cnic_dev_lock);
  131. return NULL;
  132. }
  133. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  134. {
  135. atomic_inc(&ulp_ops->ref_count);
  136. }
  137. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  138. {
  139. atomic_dec(&ulp_ops->ref_count);
  140. }
  141. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  142. {
  143. struct cnic_local *cp = dev->cnic_priv;
  144. struct cnic_eth_dev *ethdev = cp->ethdev;
  145. struct drv_ctl_info info;
  146. struct drv_ctl_io *io = &info.data.io;
  147. info.cmd = DRV_CTL_CTX_WR_CMD;
  148. io->cid_addr = cid_addr;
  149. io->offset = off;
  150. io->data = val;
  151. ethdev->drv_ctl(dev->netdev, &info);
  152. }
  153. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  154. {
  155. struct cnic_local *cp = dev->cnic_priv;
  156. struct cnic_eth_dev *ethdev = cp->ethdev;
  157. struct drv_ctl_info info;
  158. struct drv_ctl_io *io = &info.data.io;
  159. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  160. io->offset = off;
  161. io->dma_addr = addr;
  162. ethdev->drv_ctl(dev->netdev, &info);
  163. }
  164. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  165. {
  166. struct cnic_local *cp = dev->cnic_priv;
  167. struct cnic_eth_dev *ethdev = cp->ethdev;
  168. struct drv_ctl_info info;
  169. struct drv_ctl_l2_ring *ring = &info.data.ring;
  170. if (start)
  171. info.cmd = DRV_CTL_START_L2_CMD;
  172. else
  173. info.cmd = DRV_CTL_STOP_L2_CMD;
  174. ring->cid = cid;
  175. ring->client_id = cl_id;
  176. ethdev->drv_ctl(dev->netdev, &info);
  177. }
  178. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  179. {
  180. struct cnic_local *cp = dev->cnic_priv;
  181. struct cnic_eth_dev *ethdev = cp->ethdev;
  182. struct drv_ctl_info info;
  183. struct drv_ctl_io *io = &info.data.io;
  184. info.cmd = DRV_CTL_IO_WR_CMD;
  185. io->offset = off;
  186. io->data = val;
  187. ethdev->drv_ctl(dev->netdev, &info);
  188. }
  189. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  190. {
  191. struct cnic_local *cp = dev->cnic_priv;
  192. struct cnic_eth_dev *ethdev = cp->ethdev;
  193. struct drv_ctl_info info;
  194. struct drv_ctl_io *io = &info.data.io;
  195. info.cmd = DRV_CTL_IO_RD_CMD;
  196. io->offset = off;
  197. ethdev->drv_ctl(dev->netdev, &info);
  198. return io->data;
  199. }
  200. static int cnic_in_use(struct cnic_sock *csk)
  201. {
  202. return test_bit(SK_F_INUSE, &csk->flags);
  203. }
  204. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  205. {
  206. struct cnic_local *cp = dev->cnic_priv;
  207. struct cnic_eth_dev *ethdev = cp->ethdev;
  208. struct drv_ctl_info info;
  209. info.cmd = cmd;
  210. info.data.credit.credit_count = count;
  211. ethdev->drv_ctl(dev->netdev, &info);
  212. }
  213. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  214. {
  215. u32 i;
  216. for (i = 0; i < cp->max_cid_space; i++) {
  217. if (cp->ctx_tbl[i].cid == cid) {
  218. *l5_cid = i;
  219. return 0;
  220. }
  221. }
  222. return -EINVAL;
  223. }
  224. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  225. struct cnic_sock *csk)
  226. {
  227. struct iscsi_path path_req;
  228. char *buf = NULL;
  229. u16 len = 0;
  230. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  231. struct cnic_ulp_ops *ulp_ops;
  232. struct cnic_uio_dev *udev = cp->udev;
  233. int rc = 0, retry = 0;
  234. if (!udev || udev->uio_dev == -1)
  235. return -ENODEV;
  236. if (csk) {
  237. len = sizeof(path_req);
  238. buf = (char *) &path_req;
  239. memset(&path_req, 0, len);
  240. msg_type = ISCSI_KEVENT_PATH_REQ;
  241. path_req.handle = (u64) csk->l5_cid;
  242. if (test_bit(SK_F_IPV6, &csk->flags)) {
  243. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  244. sizeof(struct in6_addr));
  245. path_req.ip_addr_len = 16;
  246. } else {
  247. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  248. sizeof(struct in_addr));
  249. path_req.ip_addr_len = 4;
  250. }
  251. path_req.vlan_id = csk->vlan_id;
  252. path_req.pmtu = csk->mtu;
  253. }
  254. while (retry < 3) {
  255. rc = 0;
  256. rcu_read_lock();
  257. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  258. if (ulp_ops)
  259. rc = ulp_ops->iscsi_nl_send_msg(
  260. cp->ulp_handle[CNIC_ULP_ISCSI],
  261. msg_type, buf, len);
  262. rcu_read_unlock();
  263. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  264. break;
  265. msleep(100);
  266. retry++;
  267. }
  268. return 0;
  269. }
  270. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  271. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  272. char *buf, u16 len)
  273. {
  274. int rc = -EINVAL;
  275. switch (msg_type) {
  276. case ISCSI_UEVENT_PATH_UPDATE: {
  277. struct cnic_local *cp;
  278. u32 l5_cid;
  279. struct cnic_sock *csk;
  280. struct iscsi_path *path_resp;
  281. if (len < sizeof(*path_resp))
  282. break;
  283. path_resp = (struct iscsi_path *) buf;
  284. cp = dev->cnic_priv;
  285. l5_cid = (u32) path_resp->handle;
  286. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  287. break;
  288. rcu_read_lock();
  289. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  290. rc = -ENODEV;
  291. rcu_read_unlock();
  292. break;
  293. }
  294. csk = &cp->csk_tbl[l5_cid];
  295. csk_hold(csk);
  296. if (cnic_in_use(csk) &&
  297. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  298. memcpy(csk->ha, path_resp->mac_addr, 6);
  299. if (test_bit(SK_F_IPV6, &csk->flags))
  300. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  301. sizeof(struct in6_addr));
  302. else
  303. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  304. sizeof(struct in_addr));
  305. if (is_valid_ether_addr(csk->ha)) {
  306. cnic_cm_set_pg(csk);
  307. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  308. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  309. cnic_cm_upcall(cp, csk,
  310. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  311. clear_bit(SK_F_CONNECT_START, &csk->flags);
  312. }
  313. }
  314. csk_put(csk);
  315. rcu_read_unlock();
  316. rc = 0;
  317. }
  318. }
  319. return rc;
  320. }
  321. static int cnic_offld_prep(struct cnic_sock *csk)
  322. {
  323. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  324. return 0;
  325. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  327. return 0;
  328. }
  329. return 1;
  330. }
  331. static int cnic_close_prep(struct cnic_sock *csk)
  332. {
  333. clear_bit(SK_F_CONNECT_START, &csk->flags);
  334. smp_mb__after_clear_bit();
  335. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  336. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  337. msleep(1);
  338. return 1;
  339. }
  340. return 0;
  341. }
  342. static int cnic_abort_prep(struct cnic_sock *csk)
  343. {
  344. clear_bit(SK_F_CONNECT_START, &csk->flags);
  345. smp_mb__after_clear_bit();
  346. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  347. msleep(1);
  348. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  349. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  350. return 1;
  351. }
  352. return 0;
  353. }
  354. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  355. {
  356. struct cnic_dev *dev;
  357. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  358. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  359. return -EINVAL;
  360. }
  361. mutex_lock(&cnic_lock);
  362. if (cnic_ulp_tbl[ulp_type]) {
  363. pr_err("%s: Type %d has already been registered\n",
  364. __func__, ulp_type);
  365. mutex_unlock(&cnic_lock);
  366. return -EBUSY;
  367. }
  368. read_lock(&cnic_dev_lock);
  369. list_for_each_entry(dev, &cnic_dev_list, list) {
  370. struct cnic_local *cp = dev->cnic_priv;
  371. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  372. }
  373. read_unlock(&cnic_dev_lock);
  374. atomic_set(&ulp_ops->ref_count, 0);
  375. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  376. mutex_unlock(&cnic_lock);
  377. /* Prevent race conditions with netdev_event */
  378. rtnl_lock();
  379. list_for_each_entry(dev, &cnic_dev_list, list) {
  380. struct cnic_local *cp = dev->cnic_priv;
  381. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  382. ulp_ops->cnic_init(dev);
  383. }
  384. rtnl_unlock();
  385. return 0;
  386. }
  387. int cnic_unregister_driver(int ulp_type)
  388. {
  389. struct cnic_dev *dev;
  390. struct cnic_ulp_ops *ulp_ops;
  391. int i = 0;
  392. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  393. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  394. return -EINVAL;
  395. }
  396. mutex_lock(&cnic_lock);
  397. ulp_ops = cnic_ulp_tbl[ulp_type];
  398. if (!ulp_ops) {
  399. pr_err("%s: Type %d has not been registered\n",
  400. __func__, ulp_type);
  401. goto out_unlock;
  402. }
  403. read_lock(&cnic_dev_lock);
  404. list_for_each_entry(dev, &cnic_dev_list, list) {
  405. struct cnic_local *cp = dev->cnic_priv;
  406. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  407. pr_err("%s: Type %d still has devices registered\n",
  408. __func__, ulp_type);
  409. read_unlock(&cnic_dev_lock);
  410. goto out_unlock;
  411. }
  412. }
  413. read_unlock(&cnic_dev_lock);
  414. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  415. mutex_unlock(&cnic_lock);
  416. synchronize_rcu();
  417. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  418. msleep(100);
  419. i++;
  420. }
  421. if (atomic_read(&ulp_ops->ref_count) != 0)
  422. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  423. return 0;
  424. out_unlock:
  425. mutex_unlock(&cnic_lock);
  426. return -EINVAL;
  427. }
  428. static int cnic_start_hw(struct cnic_dev *);
  429. static void cnic_stop_hw(struct cnic_dev *);
  430. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  431. void *ulp_ctx)
  432. {
  433. struct cnic_local *cp = dev->cnic_priv;
  434. struct cnic_ulp_ops *ulp_ops;
  435. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  436. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  437. return -EINVAL;
  438. }
  439. mutex_lock(&cnic_lock);
  440. if (cnic_ulp_tbl[ulp_type] == NULL) {
  441. pr_err("%s: Driver with type %d has not been registered\n",
  442. __func__, ulp_type);
  443. mutex_unlock(&cnic_lock);
  444. return -EAGAIN;
  445. }
  446. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  447. pr_err("%s: Type %d has already been registered to this device\n",
  448. __func__, ulp_type);
  449. mutex_unlock(&cnic_lock);
  450. return -EBUSY;
  451. }
  452. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  453. cp->ulp_handle[ulp_type] = ulp_ctx;
  454. ulp_ops = cnic_ulp_tbl[ulp_type];
  455. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  456. cnic_hold(dev);
  457. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  458. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  459. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  460. mutex_unlock(&cnic_lock);
  461. return 0;
  462. }
  463. EXPORT_SYMBOL(cnic_register_driver);
  464. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  465. {
  466. struct cnic_local *cp = dev->cnic_priv;
  467. int i = 0;
  468. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  469. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  470. return -EINVAL;
  471. }
  472. mutex_lock(&cnic_lock);
  473. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  474. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  475. cnic_put(dev);
  476. } else {
  477. pr_err("%s: device not registered to this ulp type %d\n",
  478. __func__, ulp_type);
  479. mutex_unlock(&cnic_lock);
  480. return -EINVAL;
  481. }
  482. mutex_unlock(&cnic_lock);
  483. if (ulp_type == CNIC_ULP_ISCSI)
  484. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  485. synchronize_rcu();
  486. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  487. i < 20) {
  488. msleep(100);
  489. i++;
  490. }
  491. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  492. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  493. return 0;
  494. }
  495. EXPORT_SYMBOL(cnic_unregister_driver);
  496. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  497. {
  498. id_tbl->start = start_id;
  499. id_tbl->max = size;
  500. id_tbl->next = 0;
  501. spin_lock_init(&id_tbl->lock);
  502. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  503. if (!id_tbl->table)
  504. return -ENOMEM;
  505. return 0;
  506. }
  507. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  508. {
  509. kfree(id_tbl->table);
  510. id_tbl->table = NULL;
  511. }
  512. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  513. {
  514. int ret = -1;
  515. id -= id_tbl->start;
  516. if (id >= id_tbl->max)
  517. return ret;
  518. spin_lock(&id_tbl->lock);
  519. if (!test_bit(id, id_tbl->table)) {
  520. set_bit(id, id_tbl->table);
  521. ret = 0;
  522. }
  523. spin_unlock(&id_tbl->lock);
  524. return ret;
  525. }
  526. /* Returns -1 if not successful */
  527. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  528. {
  529. u32 id;
  530. spin_lock(&id_tbl->lock);
  531. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  532. if (id >= id_tbl->max) {
  533. id = -1;
  534. if (id_tbl->next != 0) {
  535. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  536. if (id >= id_tbl->next)
  537. id = -1;
  538. }
  539. }
  540. if (id < id_tbl->max) {
  541. set_bit(id, id_tbl->table);
  542. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  543. id += id_tbl->start;
  544. }
  545. spin_unlock(&id_tbl->lock);
  546. return id;
  547. }
  548. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  549. {
  550. if (id == -1)
  551. return;
  552. id -= id_tbl->start;
  553. if (id >= id_tbl->max)
  554. return;
  555. clear_bit(id, id_tbl->table);
  556. }
  557. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  558. {
  559. int i;
  560. if (!dma->pg_arr)
  561. return;
  562. for (i = 0; i < dma->num_pages; i++) {
  563. if (dma->pg_arr[i]) {
  564. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  565. dma->pg_arr[i], dma->pg_map_arr[i]);
  566. dma->pg_arr[i] = NULL;
  567. }
  568. }
  569. if (dma->pgtbl) {
  570. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  571. dma->pgtbl, dma->pgtbl_map);
  572. dma->pgtbl = NULL;
  573. }
  574. kfree(dma->pg_arr);
  575. dma->pg_arr = NULL;
  576. dma->num_pages = 0;
  577. }
  578. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  579. {
  580. int i;
  581. __le32 *page_table = (__le32 *) dma->pgtbl;
  582. for (i = 0; i < dma->num_pages; i++) {
  583. /* Each entry needs to be in big endian format. */
  584. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  585. page_table++;
  586. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  587. page_table++;
  588. }
  589. }
  590. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  591. {
  592. int i;
  593. __le32 *page_table = (__le32 *) dma->pgtbl;
  594. for (i = 0; i < dma->num_pages; i++) {
  595. /* Each entry needs to be in little endian format. */
  596. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  597. page_table++;
  598. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  599. page_table++;
  600. }
  601. }
  602. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  603. int pages, int use_pg_tbl)
  604. {
  605. int i, size;
  606. struct cnic_local *cp = dev->cnic_priv;
  607. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  608. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  609. if (dma->pg_arr == NULL)
  610. return -ENOMEM;
  611. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  612. dma->num_pages = pages;
  613. for (i = 0; i < pages; i++) {
  614. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  615. BCM_PAGE_SIZE,
  616. &dma->pg_map_arr[i],
  617. GFP_ATOMIC);
  618. if (dma->pg_arr[i] == NULL)
  619. goto error;
  620. }
  621. if (!use_pg_tbl)
  622. return 0;
  623. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  624. ~(BCM_PAGE_SIZE - 1);
  625. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  626. &dma->pgtbl_map, GFP_ATOMIC);
  627. if (dma->pgtbl == NULL)
  628. goto error;
  629. cp->setup_pgtbl(dev, dma);
  630. return 0;
  631. error:
  632. cnic_free_dma(dev, dma);
  633. return -ENOMEM;
  634. }
  635. static void cnic_free_context(struct cnic_dev *dev)
  636. {
  637. struct cnic_local *cp = dev->cnic_priv;
  638. int i;
  639. for (i = 0; i < cp->ctx_blks; i++) {
  640. if (cp->ctx_arr[i].ctx) {
  641. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  642. cp->ctx_arr[i].ctx,
  643. cp->ctx_arr[i].mapping);
  644. cp->ctx_arr[i].ctx = NULL;
  645. }
  646. }
  647. }
  648. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  649. {
  650. uio_unregister_device(&udev->cnic_uinfo);
  651. if (udev->l2_buf) {
  652. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  653. udev->l2_buf, udev->l2_buf_map);
  654. udev->l2_buf = NULL;
  655. }
  656. if (udev->l2_ring) {
  657. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  658. udev->l2_ring, udev->l2_ring_map);
  659. udev->l2_ring = NULL;
  660. }
  661. pci_dev_put(udev->pdev);
  662. kfree(udev);
  663. }
  664. static void cnic_free_uio(struct cnic_uio_dev *udev)
  665. {
  666. if (!udev)
  667. return;
  668. write_lock(&cnic_dev_lock);
  669. list_del_init(&udev->list);
  670. write_unlock(&cnic_dev_lock);
  671. __cnic_free_uio(udev);
  672. }
  673. static void cnic_free_resc(struct cnic_dev *dev)
  674. {
  675. struct cnic_local *cp = dev->cnic_priv;
  676. struct cnic_uio_dev *udev = cp->udev;
  677. if (udev) {
  678. udev->dev = NULL;
  679. cp->udev = NULL;
  680. }
  681. cnic_free_context(dev);
  682. kfree(cp->ctx_arr);
  683. cp->ctx_arr = NULL;
  684. cp->ctx_blks = 0;
  685. cnic_free_dma(dev, &cp->gbl_buf_info);
  686. cnic_free_dma(dev, &cp->conn_buf_info);
  687. cnic_free_dma(dev, &cp->kwq_info);
  688. cnic_free_dma(dev, &cp->kwq_16_data_info);
  689. cnic_free_dma(dev, &cp->kcq2.dma);
  690. cnic_free_dma(dev, &cp->kcq1.dma);
  691. kfree(cp->iscsi_tbl);
  692. cp->iscsi_tbl = NULL;
  693. kfree(cp->ctx_tbl);
  694. cp->ctx_tbl = NULL;
  695. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  696. cnic_free_id_tbl(&cp->cid_tbl);
  697. }
  698. static int cnic_alloc_context(struct cnic_dev *dev)
  699. {
  700. struct cnic_local *cp = dev->cnic_priv;
  701. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  702. int i, k, arr_size;
  703. cp->ctx_blk_size = BCM_PAGE_SIZE;
  704. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  705. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  706. sizeof(struct cnic_ctx);
  707. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  708. if (cp->ctx_arr == NULL)
  709. return -ENOMEM;
  710. k = 0;
  711. for (i = 0; i < 2; i++) {
  712. u32 j, reg, off, lo, hi;
  713. if (i == 0)
  714. off = BNX2_PG_CTX_MAP;
  715. else
  716. off = BNX2_ISCSI_CTX_MAP;
  717. reg = cnic_reg_rd_ind(dev, off);
  718. lo = reg >> 16;
  719. hi = reg & 0xffff;
  720. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  721. cp->ctx_arr[k].cid = j;
  722. }
  723. cp->ctx_blks = k;
  724. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  725. cp->ctx_blks = 0;
  726. return -ENOMEM;
  727. }
  728. for (i = 0; i < cp->ctx_blks; i++) {
  729. cp->ctx_arr[i].ctx =
  730. dma_alloc_coherent(&dev->pcidev->dev,
  731. BCM_PAGE_SIZE,
  732. &cp->ctx_arr[i].mapping,
  733. GFP_KERNEL);
  734. if (cp->ctx_arr[i].ctx == NULL)
  735. return -ENOMEM;
  736. }
  737. }
  738. return 0;
  739. }
  740. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  741. {
  742. int err, i, is_bnx2 = 0;
  743. struct kcqe **kcq;
  744. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  745. is_bnx2 = 1;
  746. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  747. if (err)
  748. return err;
  749. kcq = (struct kcqe **) info->dma.pg_arr;
  750. info->kcq = kcq;
  751. if (is_bnx2)
  752. return 0;
  753. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  754. struct bnx2x_bd_chain_next *next =
  755. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  756. int j = i + 1;
  757. if (j >= KCQ_PAGE_CNT)
  758. j = 0;
  759. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  760. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  761. }
  762. return 0;
  763. }
  764. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  765. {
  766. struct cnic_local *cp = dev->cnic_priv;
  767. struct cnic_uio_dev *udev;
  768. read_lock(&cnic_dev_lock);
  769. list_for_each_entry(udev, &cnic_udev_list, list) {
  770. if (udev->pdev == dev->pcidev) {
  771. udev->dev = dev;
  772. cp->udev = udev;
  773. read_unlock(&cnic_dev_lock);
  774. return 0;
  775. }
  776. }
  777. read_unlock(&cnic_dev_lock);
  778. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  779. if (!udev)
  780. return -ENOMEM;
  781. udev->uio_dev = -1;
  782. udev->dev = dev;
  783. udev->pdev = dev->pcidev;
  784. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  785. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  786. &udev->l2_ring_map,
  787. GFP_KERNEL | __GFP_COMP);
  788. if (!udev->l2_ring)
  789. goto err_udev;
  790. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  791. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  792. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  793. &udev->l2_buf_map,
  794. GFP_KERNEL | __GFP_COMP);
  795. if (!udev->l2_buf)
  796. goto err_dma;
  797. write_lock(&cnic_dev_lock);
  798. list_add(&udev->list, &cnic_udev_list);
  799. write_unlock(&cnic_dev_lock);
  800. pci_dev_get(udev->pdev);
  801. cp->udev = udev;
  802. return 0;
  803. err_dma:
  804. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  805. udev->l2_ring, udev->l2_ring_map);
  806. err_udev:
  807. kfree(udev);
  808. return -ENOMEM;
  809. }
  810. static int cnic_init_uio(struct cnic_dev *dev)
  811. {
  812. struct cnic_local *cp = dev->cnic_priv;
  813. struct cnic_uio_dev *udev = cp->udev;
  814. struct uio_info *uinfo;
  815. int ret = 0;
  816. if (!udev)
  817. return -ENOMEM;
  818. uinfo = &udev->cnic_uinfo;
  819. uinfo->mem[0].addr = dev->netdev->base_addr;
  820. uinfo->mem[0].internal_addr = dev->regview;
  821. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  822. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  823. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  824. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  825. PAGE_MASK;
  826. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  827. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  828. else
  829. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  830. uinfo->name = "bnx2_cnic";
  831. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  832. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  833. PAGE_MASK;
  834. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  835. uinfo->name = "bnx2x_cnic";
  836. }
  837. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  838. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  839. uinfo->mem[2].size = udev->l2_ring_size;
  840. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  841. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  842. uinfo->mem[3].size = udev->l2_buf_size;
  843. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  844. uinfo->version = CNIC_MODULE_VERSION;
  845. uinfo->irq = UIO_IRQ_CUSTOM;
  846. uinfo->open = cnic_uio_open;
  847. uinfo->release = cnic_uio_close;
  848. if (udev->uio_dev == -1) {
  849. if (!uinfo->priv) {
  850. uinfo->priv = udev;
  851. ret = uio_register_device(&udev->pdev->dev, uinfo);
  852. }
  853. } else {
  854. cnic_init_rings(dev);
  855. }
  856. return ret;
  857. }
  858. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  859. {
  860. struct cnic_local *cp = dev->cnic_priv;
  861. int ret;
  862. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  863. if (ret)
  864. goto error;
  865. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  866. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  867. if (ret)
  868. goto error;
  869. ret = cnic_alloc_context(dev);
  870. if (ret)
  871. goto error;
  872. ret = cnic_alloc_uio_rings(dev, 2);
  873. if (ret)
  874. goto error;
  875. ret = cnic_init_uio(dev);
  876. if (ret)
  877. goto error;
  878. return 0;
  879. error:
  880. cnic_free_resc(dev);
  881. return ret;
  882. }
  883. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  884. {
  885. struct cnic_local *cp = dev->cnic_priv;
  886. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  887. int total_mem, blks, i;
  888. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  889. blks = total_mem / ctx_blk_size;
  890. if (total_mem % ctx_blk_size)
  891. blks++;
  892. if (blks > cp->ethdev->ctx_tbl_len)
  893. return -ENOMEM;
  894. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  895. if (cp->ctx_arr == NULL)
  896. return -ENOMEM;
  897. cp->ctx_blks = blks;
  898. cp->ctx_blk_size = ctx_blk_size;
  899. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  900. cp->ctx_align = 0;
  901. else
  902. cp->ctx_align = ctx_blk_size;
  903. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  904. for (i = 0; i < blks; i++) {
  905. cp->ctx_arr[i].ctx =
  906. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  907. &cp->ctx_arr[i].mapping,
  908. GFP_KERNEL);
  909. if (cp->ctx_arr[i].ctx == NULL)
  910. return -ENOMEM;
  911. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  912. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  913. cnic_free_context(dev);
  914. cp->ctx_blk_size += cp->ctx_align;
  915. i = -1;
  916. continue;
  917. }
  918. }
  919. }
  920. return 0;
  921. }
  922. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  923. {
  924. struct cnic_local *cp = dev->cnic_priv;
  925. struct cnic_eth_dev *ethdev = cp->ethdev;
  926. u32 start_cid = ethdev->starting_cid;
  927. int i, j, n, ret, pages;
  928. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  929. cp->iro_arr = ethdev->iro_arr;
  930. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  931. cp->iscsi_start_cid = start_cid;
  932. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  933. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  934. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  935. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  936. if (!cp->fcoe_init_cid)
  937. cp->fcoe_init_cid = 0x10;
  938. }
  939. if (start_cid < BNX2X_ISCSI_START_CID) {
  940. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  941. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  942. cp->fcoe_start_cid += delta;
  943. cp->max_cid_space += delta;
  944. }
  945. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  946. GFP_KERNEL);
  947. if (!cp->iscsi_tbl)
  948. goto error;
  949. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  950. cp->max_cid_space, GFP_KERNEL);
  951. if (!cp->ctx_tbl)
  952. goto error;
  953. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  954. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  955. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  956. }
  957. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  958. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  959. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  960. PAGE_SIZE;
  961. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  962. if (ret)
  963. return -ENOMEM;
  964. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  965. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  966. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  967. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  968. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  969. off;
  970. if ((i % n) == (n - 1))
  971. j++;
  972. }
  973. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  974. if (ret)
  975. goto error;
  976. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  977. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  978. if (ret)
  979. goto error;
  980. }
  981. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  982. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  983. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  984. if (ret)
  985. goto error;
  986. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  987. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  988. if (ret)
  989. goto error;
  990. ret = cnic_alloc_bnx2x_context(dev);
  991. if (ret)
  992. goto error;
  993. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  994. cp->l2_rx_ring_size = 15;
  995. ret = cnic_alloc_uio_rings(dev, 4);
  996. if (ret)
  997. goto error;
  998. ret = cnic_init_uio(dev);
  999. if (ret)
  1000. goto error;
  1001. return 0;
  1002. error:
  1003. cnic_free_resc(dev);
  1004. return -ENOMEM;
  1005. }
  1006. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1007. {
  1008. return cp->max_kwq_idx -
  1009. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1010. }
  1011. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1012. u32 num_wqes)
  1013. {
  1014. struct cnic_local *cp = dev->cnic_priv;
  1015. struct kwqe *prod_qe;
  1016. u16 prod, sw_prod, i;
  1017. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1018. return -EAGAIN; /* bnx2 is down */
  1019. spin_lock_bh(&cp->cnic_ulp_lock);
  1020. if (num_wqes > cnic_kwq_avail(cp) &&
  1021. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1022. spin_unlock_bh(&cp->cnic_ulp_lock);
  1023. return -EAGAIN;
  1024. }
  1025. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1026. prod = cp->kwq_prod_idx;
  1027. sw_prod = prod & MAX_KWQ_IDX;
  1028. for (i = 0; i < num_wqes; i++) {
  1029. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1030. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1031. prod++;
  1032. sw_prod = prod & MAX_KWQ_IDX;
  1033. }
  1034. cp->kwq_prod_idx = prod;
  1035. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1036. spin_unlock_bh(&cp->cnic_ulp_lock);
  1037. return 0;
  1038. }
  1039. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1040. union l5cm_specific_data *l5_data)
  1041. {
  1042. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1043. dma_addr_t map;
  1044. map = ctx->kwqe_data_mapping;
  1045. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1046. l5_data->phy_address.hi = (u64) map >> 32;
  1047. return ctx->kwqe_data;
  1048. }
  1049. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1050. u32 type, union l5cm_specific_data *l5_data)
  1051. {
  1052. struct cnic_local *cp = dev->cnic_priv;
  1053. struct l5cm_spe kwqe;
  1054. struct kwqe_16 *kwq[1];
  1055. u16 type_16;
  1056. int ret;
  1057. kwqe.hdr.conn_and_cmd_data =
  1058. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1059. BNX2X_HW_CID(cp, cid)));
  1060. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1061. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1062. SPE_HDR_FUNCTION_ID;
  1063. kwqe.hdr.type = cpu_to_le16(type_16);
  1064. kwqe.hdr.reserved1 = 0;
  1065. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1066. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1067. kwq[0] = (struct kwqe_16 *) &kwqe;
  1068. spin_lock_bh(&cp->cnic_ulp_lock);
  1069. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1070. spin_unlock_bh(&cp->cnic_ulp_lock);
  1071. if (ret == 1)
  1072. return 0;
  1073. return -EBUSY;
  1074. }
  1075. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1076. struct kcqe *cqes[], u32 num_cqes)
  1077. {
  1078. struct cnic_local *cp = dev->cnic_priv;
  1079. struct cnic_ulp_ops *ulp_ops;
  1080. rcu_read_lock();
  1081. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1082. if (likely(ulp_ops)) {
  1083. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1084. cqes, num_cqes);
  1085. }
  1086. rcu_read_unlock();
  1087. }
  1088. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1089. {
  1090. struct cnic_local *cp = dev->cnic_priv;
  1091. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1092. int hq_bds, pages;
  1093. u32 pfid = cp->pfid;
  1094. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1095. cp->num_ccells = req1->num_ccells_per_conn;
  1096. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1097. cp->num_iscsi_tasks;
  1098. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1099. BNX2X_ISCSI_R2TQE_SIZE;
  1100. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1101. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1102. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1103. cp->num_cqs = req1->num_cqs;
  1104. if (!dev->max_iscsi_conn)
  1105. return 0;
  1106. /* init Tstorm RAM */
  1107. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1108. req1->rq_num_wqes);
  1109. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1110. PAGE_SIZE);
  1111. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1112. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1113. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1114. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1115. req1->num_tasks_per_conn);
  1116. /* init Ustorm RAM */
  1117. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1118. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1119. req1->rq_buffer_size);
  1120. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1121. PAGE_SIZE);
  1122. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1123. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1124. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1125. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1126. req1->num_tasks_per_conn);
  1127. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1128. req1->rq_num_wqes);
  1129. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1130. req1->cq_num_wqes);
  1131. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1132. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1133. /* init Xstorm RAM */
  1134. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1135. PAGE_SIZE);
  1136. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1137. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1138. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1139. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1140. req1->num_tasks_per_conn);
  1141. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1142. hq_bds);
  1143. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1144. req1->num_tasks_per_conn);
  1145. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1146. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1147. /* init Cstorm RAM */
  1148. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1149. PAGE_SIZE);
  1150. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1151. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1152. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1153. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1154. req1->num_tasks_per_conn);
  1155. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1156. req1->cq_num_wqes);
  1157. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1158. hq_bds);
  1159. return 0;
  1160. }
  1161. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1162. {
  1163. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1164. struct cnic_local *cp = dev->cnic_priv;
  1165. u32 pfid = cp->pfid;
  1166. struct iscsi_kcqe kcqe;
  1167. struct kcqe *cqes[1];
  1168. memset(&kcqe, 0, sizeof(kcqe));
  1169. if (!dev->max_iscsi_conn) {
  1170. kcqe.completion_status =
  1171. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1172. goto done;
  1173. }
  1174. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1175. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1176. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1177. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1178. req2->error_bit_map[1]);
  1179. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1180. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1181. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1182. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1183. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1184. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1185. req2->error_bit_map[1]);
  1186. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1187. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1188. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1189. done:
  1190. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1191. cqes[0] = (struct kcqe *) &kcqe;
  1192. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1193. return 0;
  1194. }
  1195. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1196. {
  1197. struct cnic_local *cp = dev->cnic_priv;
  1198. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1199. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1200. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1201. cnic_free_dma(dev, &iscsi->hq_info);
  1202. cnic_free_dma(dev, &iscsi->r2tq_info);
  1203. cnic_free_dma(dev, &iscsi->task_array_info);
  1204. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1205. } else {
  1206. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1207. }
  1208. ctx->cid = 0;
  1209. }
  1210. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1211. {
  1212. u32 cid;
  1213. int ret, pages;
  1214. struct cnic_local *cp = dev->cnic_priv;
  1215. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1216. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1217. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1218. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1219. if (cid == -1) {
  1220. ret = -ENOMEM;
  1221. goto error;
  1222. }
  1223. ctx->cid = cid;
  1224. return 0;
  1225. }
  1226. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1227. if (cid == -1) {
  1228. ret = -ENOMEM;
  1229. goto error;
  1230. }
  1231. ctx->cid = cid;
  1232. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1233. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1234. if (ret)
  1235. goto error;
  1236. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1237. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1238. if (ret)
  1239. goto error;
  1240. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1241. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1242. if (ret)
  1243. goto error;
  1244. return 0;
  1245. error:
  1246. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1247. return ret;
  1248. }
  1249. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1250. struct regpair *ctx_addr)
  1251. {
  1252. struct cnic_local *cp = dev->cnic_priv;
  1253. struct cnic_eth_dev *ethdev = cp->ethdev;
  1254. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1255. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1256. unsigned long align_off = 0;
  1257. dma_addr_t ctx_map;
  1258. void *ctx;
  1259. if (cp->ctx_align) {
  1260. unsigned long mask = cp->ctx_align - 1;
  1261. if (cp->ctx_arr[blk].mapping & mask)
  1262. align_off = cp->ctx_align -
  1263. (cp->ctx_arr[blk].mapping & mask);
  1264. }
  1265. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1266. (off * BNX2X_CONTEXT_MEM_SIZE);
  1267. ctx = cp->ctx_arr[blk].ctx + align_off +
  1268. (off * BNX2X_CONTEXT_MEM_SIZE);
  1269. if (init)
  1270. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1271. ctx_addr->lo = ctx_map & 0xffffffff;
  1272. ctx_addr->hi = (u64) ctx_map >> 32;
  1273. return ctx;
  1274. }
  1275. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1276. u32 num)
  1277. {
  1278. struct cnic_local *cp = dev->cnic_priv;
  1279. struct iscsi_kwqe_conn_offload1 *req1 =
  1280. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1281. struct iscsi_kwqe_conn_offload2 *req2 =
  1282. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1283. struct iscsi_kwqe_conn_offload3 *req3;
  1284. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1285. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1286. u32 cid = ctx->cid;
  1287. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1288. struct iscsi_context *ictx;
  1289. struct regpair context_addr;
  1290. int i, j, n = 2, n_max;
  1291. ctx->ctx_flags = 0;
  1292. if (!req2->num_additional_wqes)
  1293. return -EINVAL;
  1294. n_max = req2->num_additional_wqes + 2;
  1295. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1296. if (ictx == NULL)
  1297. return -ENOMEM;
  1298. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1299. ictx->xstorm_ag_context.hq_prod = 1;
  1300. ictx->xstorm_st_context.iscsi.first_burst_length =
  1301. ISCSI_DEF_FIRST_BURST_LEN;
  1302. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1303. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1304. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1305. req1->sq_page_table_addr_lo;
  1306. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1307. req1->sq_page_table_addr_hi;
  1308. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1309. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1310. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1311. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1312. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1313. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1314. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1315. iscsi->hq_info.pgtbl[0];
  1316. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1317. iscsi->hq_info.pgtbl[1];
  1318. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1319. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1320. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1321. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1322. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1323. iscsi->r2tq_info.pgtbl[0];
  1324. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1325. iscsi->r2tq_info.pgtbl[1];
  1326. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1327. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1328. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1329. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1330. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1331. BNX2X_ISCSI_PBL_NOT_CACHED;
  1332. ictx->xstorm_st_context.iscsi.flags.flags |=
  1333. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1334. ictx->xstorm_st_context.iscsi.flags.flags |=
  1335. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1336. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1337. /* TSTORM requires the base address of RQ DB & not PTE */
  1338. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1339. req2->rq_page_table_addr_lo & PAGE_MASK;
  1340. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1341. req2->rq_page_table_addr_hi;
  1342. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1343. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1344. ictx->tstorm_st_context.tcp.flags2 |=
  1345. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1346. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1347. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1348. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1349. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1350. req2->rq_page_table_addr_lo;
  1351. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1352. req2->rq_page_table_addr_hi;
  1353. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1354. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1355. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1356. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1357. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1358. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1359. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1360. iscsi->r2tq_info.pgtbl[0];
  1361. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1362. iscsi->r2tq_info.pgtbl[1];
  1363. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1364. req1->cq_page_table_addr_lo;
  1365. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1366. req1->cq_page_table_addr_hi;
  1367. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1368. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1369. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1370. ictx->ustorm_st_context.task_pbe_cache_index =
  1371. BNX2X_ISCSI_PBL_NOT_CACHED;
  1372. ictx->ustorm_st_context.task_pdu_cache_index =
  1373. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1374. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1375. if (j == 3) {
  1376. if (n >= n_max)
  1377. break;
  1378. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1379. j = 0;
  1380. }
  1381. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1382. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1383. req3->qp_first_pte[j].hi;
  1384. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1385. req3->qp_first_pte[j].lo;
  1386. }
  1387. ictx->ustorm_st_context.task_pbl_base.lo =
  1388. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1389. ictx->ustorm_st_context.task_pbl_base.hi =
  1390. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1391. ictx->ustorm_st_context.tce_phy_addr.lo =
  1392. iscsi->task_array_info.pgtbl[0];
  1393. ictx->ustorm_st_context.tce_phy_addr.hi =
  1394. iscsi->task_array_info.pgtbl[1];
  1395. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1396. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1397. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1398. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1399. ISCSI_DEF_MAX_BURST_LEN;
  1400. ictx->ustorm_st_context.negotiated_rx |=
  1401. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1402. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1403. ictx->cstorm_st_context.hq_pbl_base.lo =
  1404. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1405. ictx->cstorm_st_context.hq_pbl_base.hi =
  1406. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1407. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1408. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1409. ictx->cstorm_st_context.task_pbl_base.lo =
  1410. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1411. ictx->cstorm_st_context.task_pbl_base.hi =
  1412. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1413. /* CSTORM and USTORM initialization is different, CSTORM requires
  1414. * CQ DB base & not PTE addr */
  1415. ictx->cstorm_st_context.cq_db_base.lo =
  1416. req1->cq_page_table_addr_lo & PAGE_MASK;
  1417. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1418. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1419. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1420. for (i = 0; i < cp->num_cqs; i++) {
  1421. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1422. ISCSI_INITIAL_SN;
  1423. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1424. ISCSI_INITIAL_SN;
  1425. }
  1426. ictx->xstorm_ag_context.cdu_reserved =
  1427. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1428. ISCSI_CONNECTION_TYPE);
  1429. ictx->ustorm_ag_context.cdu_usage =
  1430. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1431. ISCSI_CONNECTION_TYPE);
  1432. return 0;
  1433. }
  1434. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1435. u32 num, int *work)
  1436. {
  1437. struct iscsi_kwqe_conn_offload1 *req1;
  1438. struct iscsi_kwqe_conn_offload2 *req2;
  1439. struct cnic_local *cp = dev->cnic_priv;
  1440. struct cnic_context *ctx;
  1441. struct iscsi_kcqe kcqe;
  1442. struct kcqe *cqes[1];
  1443. u32 l5_cid;
  1444. int ret = 0;
  1445. if (num < 2) {
  1446. *work = num;
  1447. return -EINVAL;
  1448. }
  1449. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1450. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1451. if ((num - 2) < req2->num_additional_wqes) {
  1452. *work = num;
  1453. return -EINVAL;
  1454. }
  1455. *work = 2 + req2->num_additional_wqes;
  1456. l5_cid = req1->iscsi_conn_id;
  1457. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1458. return -EINVAL;
  1459. memset(&kcqe, 0, sizeof(kcqe));
  1460. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1461. kcqe.iscsi_conn_id = l5_cid;
  1462. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1463. ctx = &cp->ctx_tbl[l5_cid];
  1464. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1465. kcqe.completion_status =
  1466. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1467. goto done;
  1468. }
  1469. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1470. atomic_dec(&cp->iscsi_conn);
  1471. goto done;
  1472. }
  1473. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1474. if (ret) {
  1475. atomic_dec(&cp->iscsi_conn);
  1476. ret = 0;
  1477. goto done;
  1478. }
  1479. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1480. if (ret < 0) {
  1481. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1482. atomic_dec(&cp->iscsi_conn);
  1483. goto done;
  1484. }
  1485. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1486. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1487. done:
  1488. cqes[0] = (struct kcqe *) &kcqe;
  1489. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1490. return ret;
  1491. }
  1492. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1493. {
  1494. struct cnic_local *cp = dev->cnic_priv;
  1495. struct iscsi_kwqe_conn_update *req =
  1496. (struct iscsi_kwqe_conn_update *) kwqe;
  1497. void *data;
  1498. union l5cm_specific_data l5_data;
  1499. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1500. int ret;
  1501. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1502. return -EINVAL;
  1503. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1504. if (!data)
  1505. return -ENOMEM;
  1506. memcpy(data, kwqe, sizeof(struct kwqe));
  1507. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1508. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1509. return ret;
  1510. }
  1511. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1512. {
  1513. struct cnic_local *cp = dev->cnic_priv;
  1514. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1515. union l5cm_specific_data l5_data;
  1516. int ret;
  1517. u32 hw_cid;
  1518. init_waitqueue_head(&ctx->waitq);
  1519. ctx->wait_cond = 0;
  1520. memset(&l5_data, 0, sizeof(l5_data));
  1521. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1522. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1523. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1524. if (ret == 0)
  1525. wait_event(ctx->waitq, ctx->wait_cond);
  1526. return ret;
  1527. }
  1528. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1529. {
  1530. struct cnic_local *cp = dev->cnic_priv;
  1531. struct iscsi_kwqe_conn_destroy *req =
  1532. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1533. u32 l5_cid = req->reserved0;
  1534. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1535. int ret = 0;
  1536. struct iscsi_kcqe kcqe;
  1537. struct kcqe *cqes[1];
  1538. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1539. goto skip_cfc_delete;
  1540. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1541. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1542. if (delta > (2 * HZ))
  1543. delta = 0;
  1544. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1545. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1546. goto destroy_reply;
  1547. }
  1548. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1549. skip_cfc_delete:
  1550. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1551. atomic_dec(&cp->iscsi_conn);
  1552. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1553. destroy_reply:
  1554. memset(&kcqe, 0, sizeof(kcqe));
  1555. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1556. kcqe.iscsi_conn_id = l5_cid;
  1557. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1558. kcqe.iscsi_conn_context_id = req->context_id;
  1559. cqes[0] = (struct kcqe *) &kcqe;
  1560. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1561. return ret;
  1562. }
  1563. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1564. struct l4_kwq_connect_req1 *kwqe1,
  1565. struct l4_kwq_connect_req3 *kwqe3,
  1566. struct l5cm_active_conn_buffer *conn_buf)
  1567. {
  1568. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1569. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1570. &conn_buf->xstorm_conn_buffer;
  1571. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1572. &conn_buf->tstorm_conn_buffer;
  1573. struct regpair context_addr;
  1574. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1575. struct in6_addr src_ip, dst_ip;
  1576. int i;
  1577. u32 *addrp;
  1578. addrp = (u32 *) &conn_addr->local_ip_addr;
  1579. for (i = 0; i < 4; i++, addrp++)
  1580. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1581. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1582. for (i = 0; i < 4; i++, addrp++)
  1583. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1584. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1585. xstorm_buf->context_addr.hi = context_addr.hi;
  1586. xstorm_buf->context_addr.lo = context_addr.lo;
  1587. xstorm_buf->mss = 0xffff;
  1588. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1589. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1590. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1591. xstorm_buf->pseudo_header_checksum =
  1592. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1593. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1594. tstorm_buf->params |=
  1595. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1596. if (kwqe3->ka_timeout) {
  1597. tstorm_buf->ka_enable = 1;
  1598. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1599. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1600. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1601. }
  1602. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1603. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1604. tstorm_buf->max_rt_time = 0xffffffff;
  1605. }
  1606. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1607. {
  1608. struct cnic_local *cp = dev->cnic_priv;
  1609. u32 pfid = cp->pfid;
  1610. u8 *mac = dev->mac_addr;
  1611. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1612. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1613. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1614. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1615. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1616. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1617. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1618. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1619. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1620. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1621. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1622. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1623. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1624. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1625. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1626. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1627. mac[4]);
  1628. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1629. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1630. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1631. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1632. mac[2]);
  1633. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1634. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1635. mac[1]);
  1636. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1637. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1638. mac[0]);
  1639. }
  1640. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1641. {
  1642. struct cnic_local *cp = dev->cnic_priv;
  1643. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1644. u16 tstorm_flags = 0;
  1645. if (tcp_ts) {
  1646. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1647. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1648. }
  1649. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1650. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1651. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1652. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1653. }
  1654. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1655. u32 num, int *work)
  1656. {
  1657. struct cnic_local *cp = dev->cnic_priv;
  1658. struct l4_kwq_connect_req1 *kwqe1 =
  1659. (struct l4_kwq_connect_req1 *) wqes[0];
  1660. struct l4_kwq_connect_req3 *kwqe3;
  1661. struct l5cm_active_conn_buffer *conn_buf;
  1662. struct l5cm_conn_addr_params *conn_addr;
  1663. union l5cm_specific_data l5_data;
  1664. u32 l5_cid = kwqe1->pg_cid;
  1665. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1666. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1667. int ret;
  1668. if (num < 2) {
  1669. *work = num;
  1670. return -EINVAL;
  1671. }
  1672. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1673. *work = 3;
  1674. else
  1675. *work = 2;
  1676. if (num < *work) {
  1677. *work = num;
  1678. return -EINVAL;
  1679. }
  1680. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1681. netdev_err(dev->netdev, "conn_buf size too big\n");
  1682. return -ENOMEM;
  1683. }
  1684. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1685. if (!conn_buf)
  1686. return -ENOMEM;
  1687. memset(conn_buf, 0, sizeof(*conn_buf));
  1688. conn_addr = &conn_buf->conn_addr_buf;
  1689. conn_addr->remote_addr_0 = csk->ha[0];
  1690. conn_addr->remote_addr_1 = csk->ha[1];
  1691. conn_addr->remote_addr_2 = csk->ha[2];
  1692. conn_addr->remote_addr_3 = csk->ha[3];
  1693. conn_addr->remote_addr_4 = csk->ha[4];
  1694. conn_addr->remote_addr_5 = csk->ha[5];
  1695. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1696. struct l4_kwq_connect_req2 *kwqe2 =
  1697. (struct l4_kwq_connect_req2 *) wqes[1];
  1698. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1699. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1700. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1701. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1702. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1703. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1704. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1705. }
  1706. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1707. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1708. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1709. conn_addr->local_tcp_port = kwqe1->src_port;
  1710. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1711. conn_addr->pmtu = kwqe3->pmtu;
  1712. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1713. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1714. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1715. cnic_bnx2x_set_tcp_timestamp(dev,
  1716. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1717. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1718. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1719. if (!ret)
  1720. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1721. return ret;
  1722. }
  1723. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1724. {
  1725. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1726. union l5cm_specific_data l5_data;
  1727. int ret;
  1728. memset(&l5_data, 0, sizeof(l5_data));
  1729. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1730. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1731. return ret;
  1732. }
  1733. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1734. {
  1735. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1736. union l5cm_specific_data l5_data;
  1737. int ret;
  1738. memset(&l5_data, 0, sizeof(l5_data));
  1739. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1740. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1741. return ret;
  1742. }
  1743. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1744. {
  1745. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1746. struct l4_kcq kcqe;
  1747. struct kcqe *cqes[1];
  1748. memset(&kcqe, 0, sizeof(kcqe));
  1749. kcqe.pg_host_opaque = req->host_opaque;
  1750. kcqe.pg_cid = req->host_opaque;
  1751. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1752. cqes[0] = (struct kcqe *) &kcqe;
  1753. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1754. return 0;
  1755. }
  1756. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1757. {
  1758. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1759. struct l4_kcq kcqe;
  1760. struct kcqe *cqes[1];
  1761. memset(&kcqe, 0, sizeof(kcqe));
  1762. kcqe.pg_host_opaque = req->pg_host_opaque;
  1763. kcqe.pg_cid = req->pg_cid;
  1764. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1765. cqes[0] = (struct kcqe *) &kcqe;
  1766. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1767. return 0;
  1768. }
  1769. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1770. {
  1771. struct fcoe_kwqe_stat *req;
  1772. struct fcoe_stat_ramrod_params *fcoe_stat;
  1773. union l5cm_specific_data l5_data;
  1774. struct cnic_local *cp = dev->cnic_priv;
  1775. int ret;
  1776. u32 cid;
  1777. req = (struct fcoe_kwqe_stat *) kwqe;
  1778. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1779. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1780. if (!fcoe_stat)
  1781. return -ENOMEM;
  1782. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1783. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1784. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1785. FCOE_CONNECTION_TYPE, &l5_data);
  1786. return ret;
  1787. }
  1788. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1789. u32 num, int *work)
  1790. {
  1791. int ret;
  1792. struct cnic_local *cp = dev->cnic_priv;
  1793. u32 cid;
  1794. struct fcoe_init_ramrod_params *fcoe_init;
  1795. struct fcoe_kwqe_init1 *req1;
  1796. struct fcoe_kwqe_init2 *req2;
  1797. struct fcoe_kwqe_init3 *req3;
  1798. union l5cm_specific_data l5_data;
  1799. if (num < 3) {
  1800. *work = num;
  1801. return -EINVAL;
  1802. }
  1803. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1804. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1805. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1806. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1807. *work = 1;
  1808. return -EINVAL;
  1809. }
  1810. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1811. *work = 2;
  1812. return -EINVAL;
  1813. }
  1814. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1815. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1816. return -ENOMEM;
  1817. }
  1818. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1819. if (!fcoe_init)
  1820. return -ENOMEM;
  1821. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1822. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1823. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1824. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1825. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1826. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1827. fcoe_init->eq_next_page_addr.lo =
  1828. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1829. fcoe_init->eq_next_page_addr.hi =
  1830. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1831. fcoe_init->sb_num = cp->status_blk_num;
  1832. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1833. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1834. cp->kcq2.sw_prod_idx = 0;
  1835. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1836. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1837. FCOE_CONNECTION_TYPE, &l5_data);
  1838. *work = 3;
  1839. return ret;
  1840. }
  1841. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1842. u32 num, int *work)
  1843. {
  1844. int ret = 0;
  1845. u32 cid = -1, l5_cid;
  1846. struct cnic_local *cp = dev->cnic_priv;
  1847. struct fcoe_kwqe_conn_offload1 *req1;
  1848. struct fcoe_kwqe_conn_offload2 *req2;
  1849. struct fcoe_kwqe_conn_offload3 *req3;
  1850. struct fcoe_kwqe_conn_offload4 *req4;
  1851. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1852. struct cnic_context *ctx;
  1853. struct fcoe_context *fctx;
  1854. struct regpair ctx_addr;
  1855. union l5cm_specific_data l5_data;
  1856. struct fcoe_kcqe kcqe;
  1857. struct kcqe *cqes[1];
  1858. if (num < 4) {
  1859. *work = num;
  1860. return -EINVAL;
  1861. }
  1862. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1863. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1864. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1865. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1866. *work = 4;
  1867. l5_cid = req1->fcoe_conn_id;
  1868. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1869. goto err_reply;
  1870. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1871. ctx = &cp->ctx_tbl[l5_cid];
  1872. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1873. goto err_reply;
  1874. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1875. if (ret) {
  1876. ret = 0;
  1877. goto err_reply;
  1878. }
  1879. cid = ctx->cid;
  1880. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1881. if (fctx) {
  1882. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1883. u32 val;
  1884. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1885. FCOE_CONNECTION_TYPE);
  1886. fctx->xstorm_ag_context.cdu_reserved = val;
  1887. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1888. FCOE_CONNECTION_TYPE);
  1889. fctx->ustorm_ag_context.cdu_usage = val;
  1890. }
  1891. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1892. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1893. goto err_reply;
  1894. }
  1895. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1896. if (!fcoe_offload)
  1897. goto err_reply;
  1898. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1899. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1900. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1901. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1902. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1903. cid = BNX2X_HW_CID(cp, cid);
  1904. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1905. FCOE_CONNECTION_TYPE, &l5_data);
  1906. if (!ret)
  1907. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1908. return ret;
  1909. err_reply:
  1910. if (cid != -1)
  1911. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1912. memset(&kcqe, 0, sizeof(kcqe));
  1913. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1914. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1915. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1916. cqes[0] = (struct kcqe *) &kcqe;
  1917. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1918. return ret;
  1919. }
  1920. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1921. {
  1922. struct fcoe_kwqe_conn_enable_disable *req;
  1923. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1924. union l5cm_specific_data l5_data;
  1925. int ret;
  1926. u32 cid, l5_cid;
  1927. struct cnic_local *cp = dev->cnic_priv;
  1928. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1929. cid = req->context_id;
  1930. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1931. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1932. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1933. return -ENOMEM;
  1934. }
  1935. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1936. if (!fcoe_enable)
  1937. return -ENOMEM;
  1938. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1939. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1940. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1941. FCOE_CONNECTION_TYPE, &l5_data);
  1942. return ret;
  1943. }
  1944. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1945. {
  1946. struct fcoe_kwqe_conn_enable_disable *req;
  1947. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1948. union l5cm_specific_data l5_data;
  1949. int ret;
  1950. u32 cid, l5_cid;
  1951. struct cnic_local *cp = dev->cnic_priv;
  1952. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1953. cid = req->context_id;
  1954. l5_cid = req->conn_id;
  1955. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1956. return -EINVAL;
  1957. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1958. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1959. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1960. return -ENOMEM;
  1961. }
  1962. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1963. if (!fcoe_disable)
  1964. return -ENOMEM;
  1965. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1966. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  1967. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  1968. FCOE_CONNECTION_TYPE, &l5_data);
  1969. return ret;
  1970. }
  1971. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1972. {
  1973. struct fcoe_kwqe_conn_destroy *req;
  1974. union l5cm_specific_data l5_data;
  1975. int ret;
  1976. u32 cid, l5_cid;
  1977. struct cnic_local *cp = dev->cnic_priv;
  1978. struct cnic_context *ctx;
  1979. struct fcoe_kcqe kcqe;
  1980. struct kcqe *cqes[1];
  1981. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  1982. cid = req->context_id;
  1983. l5_cid = req->conn_id;
  1984. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1985. return -EINVAL;
  1986. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1987. ctx = &cp->ctx_tbl[l5_cid];
  1988. init_waitqueue_head(&ctx->waitq);
  1989. ctx->wait_cond = 0;
  1990. memset(&l5_data, 0, sizeof(l5_data));
  1991. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  1992. FCOE_CONNECTION_TYPE, &l5_data);
  1993. if (ret == 0) {
  1994. wait_event(ctx->waitq, ctx->wait_cond);
  1995. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1996. queue_delayed_work(cnic_wq, &cp->delete_task,
  1997. msecs_to_jiffies(2000));
  1998. }
  1999. memset(&kcqe, 0, sizeof(kcqe));
  2000. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2001. kcqe.fcoe_conn_id = req->conn_id;
  2002. kcqe.fcoe_conn_context_id = cid;
  2003. cqes[0] = (struct kcqe *) &kcqe;
  2004. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2005. return ret;
  2006. }
  2007. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2008. {
  2009. struct fcoe_kwqe_destroy *req;
  2010. union l5cm_specific_data l5_data;
  2011. struct cnic_local *cp = dev->cnic_priv;
  2012. int ret;
  2013. u32 cid;
  2014. req = (struct fcoe_kwqe_destroy *) kwqe;
  2015. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2016. memset(&l5_data, 0, sizeof(l5_data));
  2017. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2018. FCOE_CONNECTION_TYPE, &l5_data);
  2019. return ret;
  2020. }
  2021. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2022. struct kwqe *wqes[], u32 num_wqes)
  2023. {
  2024. int i, work, ret;
  2025. u32 opcode;
  2026. struct kwqe *kwqe;
  2027. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2028. return -EAGAIN; /* bnx2 is down */
  2029. for (i = 0; i < num_wqes; ) {
  2030. kwqe = wqes[i];
  2031. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2032. work = 1;
  2033. switch (opcode) {
  2034. case ISCSI_KWQE_OPCODE_INIT1:
  2035. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2036. break;
  2037. case ISCSI_KWQE_OPCODE_INIT2:
  2038. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2039. break;
  2040. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2041. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2042. num_wqes - i, &work);
  2043. break;
  2044. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2045. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2046. break;
  2047. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2048. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2049. break;
  2050. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2051. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2052. &work);
  2053. break;
  2054. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2055. ret = cnic_bnx2x_close(dev, kwqe);
  2056. break;
  2057. case L4_KWQE_OPCODE_VALUE_RESET:
  2058. ret = cnic_bnx2x_reset(dev, kwqe);
  2059. break;
  2060. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2061. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2062. break;
  2063. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2064. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2065. break;
  2066. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2067. ret = 0;
  2068. break;
  2069. default:
  2070. ret = 0;
  2071. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2072. opcode);
  2073. break;
  2074. }
  2075. if (ret < 0)
  2076. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2077. opcode);
  2078. i += work;
  2079. }
  2080. return 0;
  2081. }
  2082. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2083. struct kwqe *wqes[], u32 num_wqes)
  2084. {
  2085. struct cnic_local *cp = dev->cnic_priv;
  2086. int i, work, ret;
  2087. u32 opcode;
  2088. struct kwqe *kwqe;
  2089. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2090. return -EAGAIN; /* bnx2 is down */
  2091. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2092. return -EINVAL;
  2093. for (i = 0; i < num_wqes; ) {
  2094. kwqe = wqes[i];
  2095. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2096. work = 1;
  2097. switch (opcode) {
  2098. case FCOE_KWQE_OPCODE_INIT1:
  2099. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2100. num_wqes - i, &work);
  2101. break;
  2102. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2103. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2104. num_wqes - i, &work);
  2105. break;
  2106. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2107. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2108. break;
  2109. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2110. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2111. break;
  2112. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2113. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2114. break;
  2115. case FCOE_KWQE_OPCODE_DESTROY:
  2116. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2117. break;
  2118. case FCOE_KWQE_OPCODE_STAT:
  2119. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2120. break;
  2121. default:
  2122. ret = 0;
  2123. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2124. opcode);
  2125. break;
  2126. }
  2127. if (ret < 0)
  2128. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2129. opcode);
  2130. i += work;
  2131. }
  2132. return 0;
  2133. }
  2134. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2135. u32 num_wqes)
  2136. {
  2137. int ret = -EINVAL;
  2138. u32 layer_code;
  2139. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2140. return -EAGAIN; /* bnx2x is down */
  2141. if (!num_wqes)
  2142. return 0;
  2143. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2144. switch (layer_code) {
  2145. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2146. case KWQE_FLAGS_LAYER_MASK_L4:
  2147. case KWQE_FLAGS_LAYER_MASK_L2:
  2148. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2149. break;
  2150. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2151. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2152. break;
  2153. }
  2154. return ret;
  2155. }
  2156. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2157. {
  2158. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2159. return KCQE_FLAGS_LAYER_MASK_L4;
  2160. return opflag & KCQE_FLAGS_LAYER_MASK;
  2161. }
  2162. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2163. {
  2164. struct cnic_local *cp = dev->cnic_priv;
  2165. int i, j, comp = 0;
  2166. i = 0;
  2167. j = 1;
  2168. while (num_cqes) {
  2169. struct cnic_ulp_ops *ulp_ops;
  2170. int ulp_type;
  2171. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2172. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2173. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2174. comp++;
  2175. while (j < num_cqes) {
  2176. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2177. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2178. break;
  2179. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2180. comp++;
  2181. j++;
  2182. }
  2183. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2184. ulp_type = CNIC_ULP_RDMA;
  2185. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2186. ulp_type = CNIC_ULP_ISCSI;
  2187. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2188. ulp_type = CNIC_ULP_FCOE;
  2189. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2190. ulp_type = CNIC_ULP_L4;
  2191. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2192. goto end;
  2193. else {
  2194. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2195. kcqe_op_flag);
  2196. goto end;
  2197. }
  2198. rcu_read_lock();
  2199. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2200. if (likely(ulp_ops)) {
  2201. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2202. cp->completed_kcq + i, j);
  2203. }
  2204. rcu_read_unlock();
  2205. end:
  2206. num_cqes -= j;
  2207. i += j;
  2208. j = 1;
  2209. }
  2210. if (unlikely(comp))
  2211. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2212. }
  2213. static u16 cnic_bnx2_next_idx(u16 idx)
  2214. {
  2215. return idx + 1;
  2216. }
  2217. static u16 cnic_bnx2_hw_idx(u16 idx)
  2218. {
  2219. return idx;
  2220. }
  2221. static u16 cnic_bnx2x_next_idx(u16 idx)
  2222. {
  2223. idx++;
  2224. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2225. idx++;
  2226. return idx;
  2227. }
  2228. static u16 cnic_bnx2x_hw_idx(u16 idx)
  2229. {
  2230. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2231. idx++;
  2232. return idx;
  2233. }
  2234. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2235. {
  2236. struct cnic_local *cp = dev->cnic_priv;
  2237. u16 i, ri, hw_prod, last;
  2238. struct kcqe *kcqe;
  2239. int kcqe_cnt = 0, last_cnt = 0;
  2240. i = ri = last = info->sw_prod_idx;
  2241. ri &= MAX_KCQ_IDX;
  2242. hw_prod = *info->hw_prod_idx_ptr;
  2243. hw_prod = cp->hw_idx(hw_prod);
  2244. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2245. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2246. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2247. i = cp->next_idx(i);
  2248. ri = i & MAX_KCQ_IDX;
  2249. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2250. last_cnt = kcqe_cnt;
  2251. last = i;
  2252. }
  2253. }
  2254. info->sw_prod_idx = last;
  2255. return last_cnt;
  2256. }
  2257. static int cnic_l2_completion(struct cnic_local *cp)
  2258. {
  2259. u16 hw_cons, sw_cons;
  2260. struct cnic_uio_dev *udev = cp->udev;
  2261. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2262. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2263. u32 cmd;
  2264. int comp = 0;
  2265. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2266. return 0;
  2267. hw_cons = *cp->rx_cons_ptr;
  2268. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2269. hw_cons++;
  2270. sw_cons = cp->rx_cons;
  2271. while (sw_cons != hw_cons) {
  2272. u8 cqe_fp_flags;
  2273. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2274. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2275. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2276. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2277. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2278. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2279. cmd == RAMROD_CMD_ID_ETH_HALT)
  2280. comp++;
  2281. }
  2282. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2283. }
  2284. return comp;
  2285. }
  2286. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2287. {
  2288. u16 rx_cons, tx_cons;
  2289. int comp = 0;
  2290. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2291. return;
  2292. rx_cons = *cp->rx_cons_ptr;
  2293. tx_cons = *cp->tx_cons_ptr;
  2294. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2295. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2296. comp = cnic_l2_completion(cp);
  2297. cp->tx_cons = tx_cons;
  2298. cp->rx_cons = rx_cons;
  2299. if (cp->udev)
  2300. uio_event_notify(&cp->udev->cnic_uinfo);
  2301. }
  2302. if (comp)
  2303. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2304. }
  2305. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2306. {
  2307. struct cnic_local *cp = dev->cnic_priv;
  2308. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2309. int kcqe_cnt;
  2310. /* status block index must be read before reading other fields */
  2311. rmb();
  2312. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2313. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2314. service_kcqes(dev, kcqe_cnt);
  2315. /* Tell compiler that status_blk fields can change. */
  2316. barrier();
  2317. if (status_idx != *cp->kcq1.status_idx_ptr) {
  2318. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2319. /* status block index must be read first */
  2320. rmb();
  2321. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2322. } else
  2323. break;
  2324. }
  2325. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2326. cnic_chk_pkt_rings(cp);
  2327. return status_idx;
  2328. }
  2329. static int cnic_service_bnx2(void *data, void *status_blk)
  2330. {
  2331. struct cnic_dev *dev = data;
  2332. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2333. struct status_block *sblk = status_blk;
  2334. return sblk->status_idx;
  2335. }
  2336. return cnic_service_bnx2_queues(dev);
  2337. }
  2338. static void cnic_service_bnx2_msix(unsigned long data)
  2339. {
  2340. struct cnic_dev *dev = (struct cnic_dev *) data;
  2341. struct cnic_local *cp = dev->cnic_priv;
  2342. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2343. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2344. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2345. }
  2346. static void cnic_doirq(struct cnic_dev *dev)
  2347. {
  2348. struct cnic_local *cp = dev->cnic_priv;
  2349. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2350. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2351. prefetch(cp->status_blk.gen);
  2352. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2353. tasklet_schedule(&cp->cnic_irq_task);
  2354. }
  2355. }
  2356. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2357. {
  2358. struct cnic_dev *dev = dev_instance;
  2359. struct cnic_local *cp = dev->cnic_priv;
  2360. if (cp->ack_int)
  2361. cp->ack_int(dev);
  2362. cnic_doirq(dev);
  2363. return IRQ_HANDLED;
  2364. }
  2365. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2366. u16 index, u8 op, u8 update)
  2367. {
  2368. struct cnic_local *cp = dev->cnic_priv;
  2369. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2370. COMMAND_REG_INT_ACK);
  2371. struct igu_ack_register igu_ack;
  2372. igu_ack.status_block_index = index;
  2373. igu_ack.sb_id_and_flags =
  2374. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2375. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2376. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2377. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2378. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2379. }
  2380. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2381. u16 index, u8 op, u8 update)
  2382. {
  2383. struct igu_regular cmd_data;
  2384. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2385. cmd_data.sb_id_and_flags =
  2386. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2387. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2388. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2389. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2390. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2391. }
  2392. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2393. {
  2394. struct cnic_local *cp = dev->cnic_priv;
  2395. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2396. IGU_INT_DISABLE, 0);
  2397. }
  2398. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2399. {
  2400. struct cnic_local *cp = dev->cnic_priv;
  2401. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2402. IGU_INT_DISABLE, 0);
  2403. }
  2404. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2405. {
  2406. u32 last_status = *info->status_idx_ptr;
  2407. int kcqe_cnt;
  2408. /* status block index must be read before reading the KCQ */
  2409. rmb();
  2410. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2411. service_kcqes(dev, kcqe_cnt);
  2412. /* Tell compiler that sblk fields can change. */
  2413. barrier();
  2414. if (last_status == *info->status_idx_ptr)
  2415. break;
  2416. last_status = *info->status_idx_ptr;
  2417. /* status block index must be read before reading the KCQ */
  2418. rmb();
  2419. }
  2420. return last_status;
  2421. }
  2422. static void cnic_service_bnx2x_bh(unsigned long data)
  2423. {
  2424. struct cnic_dev *dev = (struct cnic_dev *) data;
  2425. struct cnic_local *cp = dev->cnic_priv;
  2426. u32 status_idx;
  2427. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2428. return;
  2429. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2430. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2431. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2432. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2433. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2434. MAX_KCQ_IDX);
  2435. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2436. status_idx, IGU_INT_ENABLE, 1);
  2437. } else {
  2438. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2439. status_idx, IGU_INT_ENABLE, 1);
  2440. }
  2441. }
  2442. static int cnic_service_bnx2x(void *data, void *status_blk)
  2443. {
  2444. struct cnic_dev *dev = data;
  2445. struct cnic_local *cp = dev->cnic_priv;
  2446. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2447. cnic_doirq(dev);
  2448. cnic_chk_pkt_rings(cp);
  2449. return 0;
  2450. }
  2451. static void cnic_ulp_stop(struct cnic_dev *dev)
  2452. {
  2453. struct cnic_local *cp = dev->cnic_priv;
  2454. int if_type;
  2455. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2456. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2457. struct cnic_ulp_ops *ulp_ops;
  2458. mutex_lock(&cnic_lock);
  2459. ulp_ops = cp->ulp_ops[if_type];
  2460. if (!ulp_ops) {
  2461. mutex_unlock(&cnic_lock);
  2462. continue;
  2463. }
  2464. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2465. mutex_unlock(&cnic_lock);
  2466. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2467. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2468. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2469. }
  2470. }
  2471. static void cnic_ulp_start(struct cnic_dev *dev)
  2472. {
  2473. struct cnic_local *cp = dev->cnic_priv;
  2474. int if_type;
  2475. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2476. struct cnic_ulp_ops *ulp_ops;
  2477. mutex_lock(&cnic_lock);
  2478. ulp_ops = cp->ulp_ops[if_type];
  2479. if (!ulp_ops || !ulp_ops->cnic_start) {
  2480. mutex_unlock(&cnic_lock);
  2481. continue;
  2482. }
  2483. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2484. mutex_unlock(&cnic_lock);
  2485. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2486. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2487. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2488. }
  2489. }
  2490. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2491. {
  2492. struct cnic_dev *dev = data;
  2493. switch (info->cmd) {
  2494. case CNIC_CTL_STOP_CMD:
  2495. cnic_hold(dev);
  2496. cnic_ulp_stop(dev);
  2497. cnic_stop_hw(dev);
  2498. cnic_put(dev);
  2499. break;
  2500. case CNIC_CTL_START_CMD:
  2501. cnic_hold(dev);
  2502. if (!cnic_start_hw(dev))
  2503. cnic_ulp_start(dev);
  2504. cnic_put(dev);
  2505. break;
  2506. case CNIC_CTL_COMPLETION_CMD: {
  2507. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2508. u32 l5_cid;
  2509. struct cnic_local *cp = dev->cnic_priv;
  2510. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2511. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2512. ctx->wait_cond = 1;
  2513. wake_up(&ctx->waitq);
  2514. }
  2515. break;
  2516. }
  2517. default:
  2518. return -EINVAL;
  2519. }
  2520. return 0;
  2521. }
  2522. static void cnic_ulp_init(struct cnic_dev *dev)
  2523. {
  2524. int i;
  2525. struct cnic_local *cp = dev->cnic_priv;
  2526. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2527. struct cnic_ulp_ops *ulp_ops;
  2528. mutex_lock(&cnic_lock);
  2529. ulp_ops = cnic_ulp_tbl[i];
  2530. if (!ulp_ops || !ulp_ops->cnic_init) {
  2531. mutex_unlock(&cnic_lock);
  2532. continue;
  2533. }
  2534. ulp_get(ulp_ops);
  2535. mutex_unlock(&cnic_lock);
  2536. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2537. ulp_ops->cnic_init(dev);
  2538. ulp_put(ulp_ops);
  2539. }
  2540. }
  2541. static void cnic_ulp_exit(struct cnic_dev *dev)
  2542. {
  2543. int i;
  2544. struct cnic_local *cp = dev->cnic_priv;
  2545. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2546. struct cnic_ulp_ops *ulp_ops;
  2547. mutex_lock(&cnic_lock);
  2548. ulp_ops = cnic_ulp_tbl[i];
  2549. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2550. mutex_unlock(&cnic_lock);
  2551. continue;
  2552. }
  2553. ulp_get(ulp_ops);
  2554. mutex_unlock(&cnic_lock);
  2555. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2556. ulp_ops->cnic_exit(dev);
  2557. ulp_put(ulp_ops);
  2558. }
  2559. }
  2560. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2561. {
  2562. struct cnic_dev *dev = csk->dev;
  2563. struct l4_kwq_offload_pg *l4kwqe;
  2564. struct kwqe *wqes[1];
  2565. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2566. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2567. wqes[0] = (struct kwqe *) l4kwqe;
  2568. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2569. l4kwqe->flags =
  2570. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2571. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2572. l4kwqe->da0 = csk->ha[0];
  2573. l4kwqe->da1 = csk->ha[1];
  2574. l4kwqe->da2 = csk->ha[2];
  2575. l4kwqe->da3 = csk->ha[3];
  2576. l4kwqe->da4 = csk->ha[4];
  2577. l4kwqe->da5 = csk->ha[5];
  2578. l4kwqe->sa0 = dev->mac_addr[0];
  2579. l4kwqe->sa1 = dev->mac_addr[1];
  2580. l4kwqe->sa2 = dev->mac_addr[2];
  2581. l4kwqe->sa3 = dev->mac_addr[3];
  2582. l4kwqe->sa4 = dev->mac_addr[4];
  2583. l4kwqe->sa5 = dev->mac_addr[5];
  2584. l4kwqe->etype = ETH_P_IP;
  2585. l4kwqe->ipid_start = DEF_IPID_START;
  2586. l4kwqe->host_opaque = csk->l5_cid;
  2587. if (csk->vlan_id) {
  2588. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2589. l4kwqe->vlan_tag = csk->vlan_id;
  2590. l4kwqe->l2hdr_nbytes += 4;
  2591. }
  2592. return dev->submit_kwqes(dev, wqes, 1);
  2593. }
  2594. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2595. {
  2596. struct cnic_dev *dev = csk->dev;
  2597. struct l4_kwq_update_pg *l4kwqe;
  2598. struct kwqe *wqes[1];
  2599. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2600. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2601. wqes[0] = (struct kwqe *) l4kwqe;
  2602. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2603. l4kwqe->flags =
  2604. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2605. l4kwqe->pg_cid = csk->pg_cid;
  2606. l4kwqe->da0 = csk->ha[0];
  2607. l4kwqe->da1 = csk->ha[1];
  2608. l4kwqe->da2 = csk->ha[2];
  2609. l4kwqe->da3 = csk->ha[3];
  2610. l4kwqe->da4 = csk->ha[4];
  2611. l4kwqe->da5 = csk->ha[5];
  2612. l4kwqe->pg_host_opaque = csk->l5_cid;
  2613. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2614. return dev->submit_kwqes(dev, wqes, 1);
  2615. }
  2616. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2617. {
  2618. struct cnic_dev *dev = csk->dev;
  2619. struct l4_kwq_upload *l4kwqe;
  2620. struct kwqe *wqes[1];
  2621. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2622. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2623. wqes[0] = (struct kwqe *) l4kwqe;
  2624. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2625. l4kwqe->flags =
  2626. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2627. l4kwqe->cid = csk->pg_cid;
  2628. return dev->submit_kwqes(dev, wqes, 1);
  2629. }
  2630. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2631. {
  2632. struct cnic_dev *dev = csk->dev;
  2633. struct l4_kwq_connect_req1 *l4kwqe1;
  2634. struct l4_kwq_connect_req2 *l4kwqe2;
  2635. struct l4_kwq_connect_req3 *l4kwqe3;
  2636. struct kwqe *wqes[3];
  2637. u8 tcp_flags = 0;
  2638. int num_wqes = 2;
  2639. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2640. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2641. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2642. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2643. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2644. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2645. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2646. l4kwqe3->flags =
  2647. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2648. l4kwqe3->ka_timeout = csk->ka_timeout;
  2649. l4kwqe3->ka_interval = csk->ka_interval;
  2650. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2651. l4kwqe3->tos = csk->tos;
  2652. l4kwqe3->ttl = csk->ttl;
  2653. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2654. l4kwqe3->pmtu = csk->mtu;
  2655. l4kwqe3->rcv_buf = csk->rcv_buf;
  2656. l4kwqe3->snd_buf = csk->snd_buf;
  2657. l4kwqe3->seed = csk->seed;
  2658. wqes[0] = (struct kwqe *) l4kwqe1;
  2659. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2660. wqes[1] = (struct kwqe *) l4kwqe2;
  2661. wqes[2] = (struct kwqe *) l4kwqe3;
  2662. num_wqes = 3;
  2663. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2664. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2665. l4kwqe2->flags =
  2666. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2667. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2668. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2669. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2670. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2671. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2672. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2673. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2674. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2675. sizeof(struct tcphdr);
  2676. } else {
  2677. wqes[1] = (struct kwqe *) l4kwqe3;
  2678. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2679. sizeof(struct tcphdr);
  2680. }
  2681. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2682. l4kwqe1->flags =
  2683. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2684. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2685. l4kwqe1->cid = csk->cid;
  2686. l4kwqe1->pg_cid = csk->pg_cid;
  2687. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2688. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2689. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2690. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2691. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2692. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2693. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2694. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2695. if (csk->tcp_flags & SK_TCP_NAGLE)
  2696. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2697. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2698. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2699. if (csk->tcp_flags & SK_TCP_SACK)
  2700. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2701. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2702. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2703. l4kwqe1->tcp_flags = tcp_flags;
  2704. return dev->submit_kwqes(dev, wqes, num_wqes);
  2705. }
  2706. static int cnic_cm_close_req(struct cnic_sock *csk)
  2707. {
  2708. struct cnic_dev *dev = csk->dev;
  2709. struct l4_kwq_close_req *l4kwqe;
  2710. struct kwqe *wqes[1];
  2711. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2712. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2713. wqes[0] = (struct kwqe *) l4kwqe;
  2714. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2715. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2716. l4kwqe->cid = csk->cid;
  2717. return dev->submit_kwqes(dev, wqes, 1);
  2718. }
  2719. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2720. {
  2721. struct cnic_dev *dev = csk->dev;
  2722. struct l4_kwq_reset_req *l4kwqe;
  2723. struct kwqe *wqes[1];
  2724. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2725. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2726. wqes[0] = (struct kwqe *) l4kwqe;
  2727. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2728. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2729. l4kwqe->cid = csk->cid;
  2730. return dev->submit_kwqes(dev, wqes, 1);
  2731. }
  2732. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2733. u32 l5_cid, struct cnic_sock **csk, void *context)
  2734. {
  2735. struct cnic_local *cp = dev->cnic_priv;
  2736. struct cnic_sock *csk1;
  2737. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2738. return -EINVAL;
  2739. if (cp->ctx_tbl) {
  2740. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2741. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2742. return -EAGAIN;
  2743. }
  2744. csk1 = &cp->csk_tbl[l5_cid];
  2745. if (atomic_read(&csk1->ref_count))
  2746. return -EAGAIN;
  2747. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2748. return -EBUSY;
  2749. csk1->dev = dev;
  2750. csk1->cid = cid;
  2751. csk1->l5_cid = l5_cid;
  2752. csk1->ulp_type = ulp_type;
  2753. csk1->context = context;
  2754. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2755. csk1->ka_interval = DEF_KA_INTERVAL;
  2756. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2757. csk1->tos = DEF_TOS;
  2758. csk1->ttl = DEF_TTL;
  2759. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2760. csk1->rcv_buf = DEF_RCV_BUF;
  2761. csk1->snd_buf = DEF_SND_BUF;
  2762. csk1->seed = DEF_SEED;
  2763. *csk = csk1;
  2764. return 0;
  2765. }
  2766. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2767. {
  2768. if (csk->src_port) {
  2769. struct cnic_dev *dev = csk->dev;
  2770. struct cnic_local *cp = dev->cnic_priv;
  2771. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2772. csk->src_port = 0;
  2773. }
  2774. }
  2775. static void cnic_close_conn(struct cnic_sock *csk)
  2776. {
  2777. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2778. cnic_cm_upload_pg(csk);
  2779. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2780. }
  2781. cnic_cm_cleanup(csk);
  2782. }
  2783. static int cnic_cm_destroy(struct cnic_sock *csk)
  2784. {
  2785. if (!cnic_in_use(csk))
  2786. return -EINVAL;
  2787. csk_hold(csk);
  2788. clear_bit(SK_F_INUSE, &csk->flags);
  2789. smp_mb__after_clear_bit();
  2790. while (atomic_read(&csk->ref_count) != 1)
  2791. msleep(1);
  2792. cnic_cm_cleanup(csk);
  2793. csk->flags = 0;
  2794. csk_put(csk);
  2795. return 0;
  2796. }
  2797. static inline u16 cnic_get_vlan(struct net_device *dev,
  2798. struct net_device **vlan_dev)
  2799. {
  2800. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2801. *vlan_dev = vlan_dev_real_dev(dev);
  2802. return vlan_dev_vlan_id(dev);
  2803. }
  2804. *vlan_dev = dev;
  2805. return 0;
  2806. }
  2807. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2808. struct dst_entry **dst)
  2809. {
  2810. #if defined(CONFIG_INET)
  2811. struct flowi fl;
  2812. int err;
  2813. struct rtable *rt;
  2814. memset(&fl, 0, sizeof(fl));
  2815. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2816. err = ip_route_output_key(&init_net, &rt, &fl);
  2817. if (!err)
  2818. *dst = &rt->dst;
  2819. return err;
  2820. #else
  2821. return -ENETUNREACH;
  2822. #endif
  2823. }
  2824. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2825. struct dst_entry **dst)
  2826. {
  2827. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2828. struct flowi fl;
  2829. memset(&fl, 0, sizeof(fl));
  2830. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2831. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2832. fl.oif = dst_addr->sin6_scope_id;
  2833. *dst = ip6_route_output(&init_net, NULL, &fl);
  2834. if (*dst)
  2835. return 0;
  2836. #endif
  2837. return -ENETUNREACH;
  2838. }
  2839. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2840. int ulp_type)
  2841. {
  2842. struct cnic_dev *dev = NULL;
  2843. struct dst_entry *dst;
  2844. struct net_device *netdev = NULL;
  2845. int err = -ENETUNREACH;
  2846. if (dst_addr->sin_family == AF_INET)
  2847. err = cnic_get_v4_route(dst_addr, &dst);
  2848. else if (dst_addr->sin_family == AF_INET6) {
  2849. struct sockaddr_in6 *dst_addr6 =
  2850. (struct sockaddr_in6 *) dst_addr;
  2851. err = cnic_get_v6_route(dst_addr6, &dst);
  2852. } else
  2853. return NULL;
  2854. if (err)
  2855. return NULL;
  2856. if (!dst->dev)
  2857. goto done;
  2858. cnic_get_vlan(dst->dev, &netdev);
  2859. dev = cnic_from_netdev(netdev);
  2860. done:
  2861. dst_release(dst);
  2862. if (dev)
  2863. cnic_put(dev);
  2864. return dev;
  2865. }
  2866. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2867. {
  2868. struct cnic_dev *dev = csk->dev;
  2869. struct cnic_local *cp = dev->cnic_priv;
  2870. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2871. }
  2872. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2873. {
  2874. struct cnic_dev *dev = csk->dev;
  2875. struct cnic_local *cp = dev->cnic_priv;
  2876. int is_v6, rc = 0;
  2877. struct dst_entry *dst = NULL;
  2878. struct net_device *realdev;
  2879. __be16 local_port;
  2880. u32 port_id;
  2881. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2882. saddr->remote.v6.sin6_family == AF_INET6)
  2883. is_v6 = 1;
  2884. else if (saddr->local.v4.sin_family == AF_INET &&
  2885. saddr->remote.v4.sin_family == AF_INET)
  2886. is_v6 = 0;
  2887. else
  2888. return -EINVAL;
  2889. clear_bit(SK_F_IPV6, &csk->flags);
  2890. if (is_v6) {
  2891. set_bit(SK_F_IPV6, &csk->flags);
  2892. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2893. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2894. sizeof(struct in6_addr));
  2895. csk->dst_port = saddr->remote.v6.sin6_port;
  2896. local_port = saddr->local.v6.sin6_port;
  2897. } else {
  2898. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2899. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2900. csk->dst_port = saddr->remote.v4.sin_port;
  2901. local_port = saddr->local.v4.sin_port;
  2902. }
  2903. csk->vlan_id = 0;
  2904. csk->mtu = dev->netdev->mtu;
  2905. if (dst && dst->dev) {
  2906. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2907. if (realdev == dev->netdev) {
  2908. csk->vlan_id = vlan;
  2909. csk->mtu = dst_mtu(dst);
  2910. }
  2911. }
  2912. port_id = be16_to_cpu(local_port);
  2913. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2914. port_id < CNIC_LOCAL_PORT_MAX) {
  2915. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2916. port_id = 0;
  2917. } else
  2918. port_id = 0;
  2919. if (!port_id) {
  2920. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2921. if (port_id == -1) {
  2922. rc = -ENOMEM;
  2923. goto err_out;
  2924. }
  2925. local_port = cpu_to_be16(port_id);
  2926. }
  2927. csk->src_port = local_port;
  2928. err_out:
  2929. dst_release(dst);
  2930. return rc;
  2931. }
  2932. static void cnic_init_csk_state(struct cnic_sock *csk)
  2933. {
  2934. csk->state = 0;
  2935. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2936. clear_bit(SK_F_CLOSING, &csk->flags);
  2937. }
  2938. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2939. {
  2940. int err = 0;
  2941. if (!cnic_in_use(csk))
  2942. return -EINVAL;
  2943. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2944. return -EINVAL;
  2945. cnic_init_csk_state(csk);
  2946. err = cnic_get_route(csk, saddr);
  2947. if (err)
  2948. goto err_out;
  2949. err = cnic_resolve_addr(csk, saddr);
  2950. if (!err)
  2951. return 0;
  2952. err_out:
  2953. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2954. return err;
  2955. }
  2956. static int cnic_cm_abort(struct cnic_sock *csk)
  2957. {
  2958. struct cnic_local *cp = csk->dev->cnic_priv;
  2959. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2960. if (!cnic_in_use(csk))
  2961. return -EINVAL;
  2962. if (cnic_abort_prep(csk))
  2963. return cnic_cm_abort_req(csk);
  2964. /* Getting here means that we haven't started connect, or
  2965. * connect was not successful.
  2966. */
  2967. cp->close_conn(csk, opcode);
  2968. if (csk->state != opcode)
  2969. return -EALREADY;
  2970. return 0;
  2971. }
  2972. static int cnic_cm_close(struct cnic_sock *csk)
  2973. {
  2974. if (!cnic_in_use(csk))
  2975. return -EINVAL;
  2976. if (cnic_close_prep(csk)) {
  2977. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2978. return cnic_cm_close_req(csk);
  2979. } else {
  2980. return -EALREADY;
  2981. }
  2982. return 0;
  2983. }
  2984. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2985. u8 opcode)
  2986. {
  2987. struct cnic_ulp_ops *ulp_ops;
  2988. int ulp_type = csk->ulp_type;
  2989. rcu_read_lock();
  2990. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2991. if (ulp_ops) {
  2992. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2993. ulp_ops->cm_connect_complete(csk);
  2994. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2995. ulp_ops->cm_close_complete(csk);
  2996. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2997. ulp_ops->cm_remote_abort(csk);
  2998. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2999. ulp_ops->cm_abort_complete(csk);
  3000. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3001. ulp_ops->cm_remote_close(csk);
  3002. }
  3003. rcu_read_unlock();
  3004. }
  3005. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3006. {
  3007. if (cnic_offld_prep(csk)) {
  3008. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3009. cnic_cm_update_pg(csk);
  3010. else
  3011. cnic_cm_offload_pg(csk);
  3012. }
  3013. return 0;
  3014. }
  3015. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3016. {
  3017. struct cnic_local *cp = dev->cnic_priv;
  3018. u32 l5_cid = kcqe->pg_host_opaque;
  3019. u8 opcode = kcqe->op_code;
  3020. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3021. csk_hold(csk);
  3022. if (!cnic_in_use(csk))
  3023. goto done;
  3024. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3025. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3026. goto done;
  3027. }
  3028. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3029. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3030. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3031. cnic_cm_upcall(cp, csk,
  3032. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3033. goto done;
  3034. }
  3035. csk->pg_cid = kcqe->pg_cid;
  3036. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3037. cnic_cm_conn_req(csk);
  3038. done:
  3039. csk_put(csk);
  3040. }
  3041. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3042. {
  3043. struct cnic_local *cp = dev->cnic_priv;
  3044. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3045. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3046. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3047. ctx->timestamp = jiffies;
  3048. ctx->wait_cond = 1;
  3049. wake_up(&ctx->waitq);
  3050. }
  3051. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3052. {
  3053. struct cnic_local *cp = dev->cnic_priv;
  3054. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3055. u8 opcode = l4kcqe->op_code;
  3056. u32 l5_cid;
  3057. struct cnic_sock *csk;
  3058. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3059. cnic_process_fcoe_term_conn(dev, kcqe);
  3060. return;
  3061. }
  3062. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3063. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3064. cnic_cm_process_offld_pg(dev, l4kcqe);
  3065. return;
  3066. }
  3067. l5_cid = l4kcqe->conn_id;
  3068. if (opcode & 0x80)
  3069. l5_cid = l4kcqe->cid;
  3070. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3071. return;
  3072. csk = &cp->csk_tbl[l5_cid];
  3073. csk_hold(csk);
  3074. if (!cnic_in_use(csk)) {
  3075. csk_put(csk);
  3076. return;
  3077. }
  3078. switch (opcode) {
  3079. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3080. if (l4kcqe->status != 0) {
  3081. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3082. cnic_cm_upcall(cp, csk,
  3083. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3084. }
  3085. break;
  3086. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3087. if (l4kcqe->status == 0)
  3088. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3089. smp_mb__before_clear_bit();
  3090. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3091. cnic_cm_upcall(cp, csk, opcode);
  3092. break;
  3093. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3094. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3095. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3096. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3097. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3098. cp->close_conn(csk, opcode);
  3099. break;
  3100. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3101. cnic_cm_upcall(cp, csk, opcode);
  3102. break;
  3103. }
  3104. csk_put(csk);
  3105. }
  3106. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3107. {
  3108. struct cnic_dev *dev = data;
  3109. int i;
  3110. for (i = 0; i < num; i++)
  3111. cnic_cm_process_kcqe(dev, kcqe[i]);
  3112. }
  3113. static struct cnic_ulp_ops cm_ulp_ops = {
  3114. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3115. };
  3116. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3117. {
  3118. struct cnic_local *cp = dev->cnic_priv;
  3119. kfree(cp->csk_tbl);
  3120. cp->csk_tbl = NULL;
  3121. cnic_free_id_tbl(&cp->csk_port_tbl);
  3122. }
  3123. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3124. {
  3125. struct cnic_local *cp = dev->cnic_priv;
  3126. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3127. GFP_KERNEL);
  3128. if (!cp->csk_tbl)
  3129. return -ENOMEM;
  3130. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3131. CNIC_LOCAL_PORT_MIN)) {
  3132. cnic_cm_free_mem(dev);
  3133. return -ENOMEM;
  3134. }
  3135. return 0;
  3136. }
  3137. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3138. {
  3139. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3140. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3141. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3142. csk->state = opcode;
  3143. }
  3144. /* 1. If event opcode matches the expected event in csk->state
  3145. * 2. If the expected event is CLOSE_COMP, we accept any event
  3146. * 3. If the expected event is 0, meaning the connection was never
  3147. * never established, we accept the opcode from cm_abort.
  3148. */
  3149. if (opcode == csk->state || csk->state == 0 ||
  3150. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  3151. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3152. if (csk->state == 0)
  3153. csk->state = opcode;
  3154. return 1;
  3155. }
  3156. }
  3157. return 0;
  3158. }
  3159. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3160. {
  3161. struct cnic_dev *dev = csk->dev;
  3162. struct cnic_local *cp = dev->cnic_priv;
  3163. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3164. cnic_cm_upcall(cp, csk, opcode);
  3165. return;
  3166. }
  3167. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3168. cnic_close_conn(csk);
  3169. csk->state = opcode;
  3170. cnic_cm_upcall(cp, csk, opcode);
  3171. }
  3172. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3173. {
  3174. }
  3175. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3176. {
  3177. u32 seed;
  3178. get_random_bytes(&seed, 4);
  3179. cnic_ctx_wr(dev, 45, 0, seed);
  3180. return 0;
  3181. }
  3182. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3183. {
  3184. struct cnic_dev *dev = csk->dev;
  3185. struct cnic_local *cp = dev->cnic_priv;
  3186. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3187. union l5cm_specific_data l5_data;
  3188. u32 cmd = 0;
  3189. int close_complete = 0;
  3190. switch (opcode) {
  3191. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3192. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3193. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3194. if (cnic_ready_to_close(csk, opcode)) {
  3195. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3196. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3197. else
  3198. close_complete = 1;
  3199. }
  3200. break;
  3201. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3202. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3203. break;
  3204. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3205. close_complete = 1;
  3206. break;
  3207. }
  3208. if (cmd) {
  3209. memset(&l5_data, 0, sizeof(l5_data));
  3210. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3211. &l5_data);
  3212. } else if (close_complete) {
  3213. ctx->timestamp = jiffies;
  3214. cnic_close_conn(csk);
  3215. cnic_cm_upcall(cp, csk, csk->state);
  3216. }
  3217. }
  3218. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3219. {
  3220. struct cnic_local *cp = dev->cnic_priv;
  3221. int i;
  3222. if (!cp->ctx_tbl)
  3223. return;
  3224. if (!netif_running(dev->netdev))
  3225. return;
  3226. for (i = 0; i < cp->max_cid_space; i++) {
  3227. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3228. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3229. msleep(10);
  3230. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3231. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3232. ctx->cid);
  3233. }
  3234. cancel_delayed_work(&cp->delete_task);
  3235. flush_workqueue(cnic_wq);
  3236. if (atomic_read(&cp->iscsi_conn) != 0)
  3237. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3238. atomic_read(&cp->iscsi_conn));
  3239. }
  3240. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3241. {
  3242. struct cnic_local *cp = dev->cnic_priv;
  3243. u32 pfid = cp->pfid;
  3244. u32 port = CNIC_PORT(cp);
  3245. cnic_init_bnx2x_mac(dev);
  3246. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3247. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3248. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3249. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3250. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3251. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3252. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3253. DEF_MAX_DA_COUNT);
  3254. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3255. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3256. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3257. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3258. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3259. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3260. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3261. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3262. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3263. DEF_MAX_CWND);
  3264. return 0;
  3265. }
  3266. static void cnic_delete_task(struct work_struct *work)
  3267. {
  3268. struct cnic_local *cp;
  3269. struct cnic_dev *dev;
  3270. u32 i;
  3271. int need_resched = 0;
  3272. cp = container_of(work, struct cnic_local, delete_task.work);
  3273. dev = cp->dev;
  3274. for (i = 0; i < cp->max_cid_space; i++) {
  3275. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3276. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3277. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3278. continue;
  3279. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3280. need_resched = 1;
  3281. continue;
  3282. }
  3283. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3284. continue;
  3285. cnic_bnx2x_destroy_ramrod(dev, i);
  3286. cnic_free_bnx2x_conn_resc(dev, i);
  3287. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3288. atomic_dec(&cp->iscsi_conn);
  3289. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3290. }
  3291. if (need_resched)
  3292. queue_delayed_work(cnic_wq, &cp->delete_task,
  3293. msecs_to_jiffies(10));
  3294. }
  3295. static int cnic_cm_open(struct cnic_dev *dev)
  3296. {
  3297. struct cnic_local *cp = dev->cnic_priv;
  3298. int err;
  3299. err = cnic_cm_alloc_mem(dev);
  3300. if (err)
  3301. return err;
  3302. err = cp->start_cm(dev);
  3303. if (err)
  3304. goto err_out;
  3305. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3306. dev->cm_create = cnic_cm_create;
  3307. dev->cm_destroy = cnic_cm_destroy;
  3308. dev->cm_connect = cnic_cm_connect;
  3309. dev->cm_abort = cnic_cm_abort;
  3310. dev->cm_close = cnic_cm_close;
  3311. dev->cm_select_dev = cnic_cm_select_dev;
  3312. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3313. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3314. return 0;
  3315. err_out:
  3316. cnic_cm_free_mem(dev);
  3317. return err;
  3318. }
  3319. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3320. {
  3321. struct cnic_local *cp = dev->cnic_priv;
  3322. int i;
  3323. cp->stop_cm(dev);
  3324. if (!cp->csk_tbl)
  3325. return 0;
  3326. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3327. struct cnic_sock *csk = &cp->csk_tbl[i];
  3328. clear_bit(SK_F_INUSE, &csk->flags);
  3329. cnic_cm_cleanup(csk);
  3330. }
  3331. cnic_cm_free_mem(dev);
  3332. return 0;
  3333. }
  3334. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3335. {
  3336. u32 cid_addr;
  3337. int i;
  3338. cid_addr = GET_CID_ADDR(cid);
  3339. for (i = 0; i < CTX_SIZE; i += 4)
  3340. cnic_ctx_wr(dev, cid_addr, i, 0);
  3341. }
  3342. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3343. {
  3344. struct cnic_local *cp = dev->cnic_priv;
  3345. int ret = 0, i;
  3346. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3347. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3348. return 0;
  3349. for (i = 0; i < cp->ctx_blks; i++) {
  3350. int j;
  3351. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3352. u32 val;
  3353. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3354. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3355. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3356. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3357. (u64) cp->ctx_arr[i].mapping >> 32);
  3358. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3359. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3360. for (j = 0; j < 10; j++) {
  3361. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3362. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3363. break;
  3364. udelay(5);
  3365. }
  3366. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3367. ret = -EBUSY;
  3368. break;
  3369. }
  3370. }
  3371. return ret;
  3372. }
  3373. static void cnic_free_irq(struct cnic_dev *dev)
  3374. {
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. struct cnic_eth_dev *ethdev = cp->ethdev;
  3377. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3378. cp->disable_int_sync(dev);
  3379. tasklet_kill(&cp->cnic_irq_task);
  3380. free_irq(ethdev->irq_arr[0].vector, dev);
  3381. }
  3382. }
  3383. static int cnic_request_irq(struct cnic_dev *dev)
  3384. {
  3385. struct cnic_local *cp = dev->cnic_priv;
  3386. struct cnic_eth_dev *ethdev = cp->ethdev;
  3387. int err;
  3388. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3389. if (err)
  3390. tasklet_disable(&cp->cnic_irq_task);
  3391. return err;
  3392. }
  3393. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3394. {
  3395. struct cnic_local *cp = dev->cnic_priv;
  3396. struct cnic_eth_dev *ethdev = cp->ethdev;
  3397. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3398. int err, i = 0;
  3399. int sblk_num = cp->status_blk_num;
  3400. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3401. BNX2_HC_SB_CONFIG_1;
  3402. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3403. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3404. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3405. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3406. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3407. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3408. (unsigned long) dev);
  3409. err = cnic_request_irq(dev);
  3410. if (err)
  3411. return err;
  3412. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3413. i < 10) {
  3414. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3415. 1 << (11 + sblk_num));
  3416. udelay(10);
  3417. i++;
  3418. barrier();
  3419. }
  3420. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3421. cnic_free_irq(dev);
  3422. goto failed;
  3423. }
  3424. } else {
  3425. struct status_block *sblk = cp->status_blk.gen;
  3426. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3427. int i = 0;
  3428. while (sblk->status_completion_producer_index && i < 10) {
  3429. CNIC_WR(dev, BNX2_HC_COMMAND,
  3430. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3431. udelay(10);
  3432. i++;
  3433. barrier();
  3434. }
  3435. if (sblk->status_completion_producer_index)
  3436. goto failed;
  3437. }
  3438. return 0;
  3439. failed:
  3440. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3441. return -EBUSY;
  3442. }
  3443. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3444. {
  3445. struct cnic_local *cp = dev->cnic_priv;
  3446. struct cnic_eth_dev *ethdev = cp->ethdev;
  3447. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3448. return;
  3449. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3450. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3451. }
  3452. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3453. {
  3454. struct cnic_local *cp = dev->cnic_priv;
  3455. struct cnic_eth_dev *ethdev = cp->ethdev;
  3456. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3457. return;
  3458. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3459. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3460. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3461. synchronize_irq(ethdev->irq_arr[0].vector);
  3462. }
  3463. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3464. {
  3465. struct cnic_local *cp = dev->cnic_priv;
  3466. struct cnic_eth_dev *ethdev = cp->ethdev;
  3467. struct cnic_uio_dev *udev = cp->udev;
  3468. u32 cid_addr, tx_cid, sb_id;
  3469. u32 val, offset0, offset1, offset2, offset3;
  3470. int i;
  3471. struct tx_bd *txbd;
  3472. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3473. struct status_block *s_blk = cp->status_blk.gen;
  3474. sb_id = cp->status_blk_num;
  3475. tx_cid = 20;
  3476. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3477. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3478. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3479. tx_cid = TX_TSS_CID + sb_id - 1;
  3480. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3481. (TX_TSS_CID << 7));
  3482. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3483. }
  3484. cp->tx_cons = *cp->tx_cons_ptr;
  3485. cid_addr = GET_CID_ADDR(tx_cid);
  3486. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3487. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3488. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3489. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3490. offset0 = BNX2_L2CTX_TYPE_XI;
  3491. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3492. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3493. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3494. } else {
  3495. cnic_init_context(dev, tx_cid);
  3496. cnic_init_context(dev, tx_cid + 1);
  3497. offset0 = BNX2_L2CTX_TYPE;
  3498. offset1 = BNX2_L2CTX_CMD_TYPE;
  3499. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3500. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3501. }
  3502. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3503. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3504. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3505. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3506. txbd = (struct tx_bd *) udev->l2_ring;
  3507. buf_map = udev->l2_buf_map;
  3508. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3509. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3510. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3511. }
  3512. val = (u64) ring_map >> 32;
  3513. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3514. txbd->tx_bd_haddr_hi = val;
  3515. val = (u64) ring_map & 0xffffffff;
  3516. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3517. txbd->tx_bd_haddr_lo = val;
  3518. }
  3519. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3520. {
  3521. struct cnic_local *cp = dev->cnic_priv;
  3522. struct cnic_eth_dev *ethdev = cp->ethdev;
  3523. struct cnic_uio_dev *udev = cp->udev;
  3524. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3525. int i;
  3526. struct rx_bd *rxbd;
  3527. struct status_block *s_blk = cp->status_blk.gen;
  3528. dma_addr_t ring_map = udev->l2_ring_map;
  3529. sb_id = cp->status_blk_num;
  3530. cnic_init_context(dev, 2);
  3531. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3532. coal_reg = BNX2_HC_COMMAND;
  3533. coal_val = CNIC_RD(dev, coal_reg);
  3534. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3535. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3536. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3537. coal_reg = BNX2_HC_COALESCE_NOW;
  3538. coal_val = 1 << (11 + sb_id);
  3539. }
  3540. i = 0;
  3541. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3542. CNIC_WR(dev, coal_reg, coal_val);
  3543. udelay(10);
  3544. i++;
  3545. barrier();
  3546. }
  3547. cp->rx_cons = *cp->rx_cons_ptr;
  3548. cid_addr = GET_CID_ADDR(2);
  3549. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3550. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3551. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3552. if (sb_id == 0)
  3553. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3554. else
  3555. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3556. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3557. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3558. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3559. dma_addr_t buf_map;
  3560. int n = (i % cp->l2_rx_ring_size) + 1;
  3561. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3562. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3563. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3564. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3565. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3566. }
  3567. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3568. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3569. rxbd->rx_bd_haddr_hi = val;
  3570. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3571. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3572. rxbd->rx_bd_haddr_lo = val;
  3573. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3574. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3575. }
  3576. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3577. {
  3578. struct kwqe *wqes[1], l2kwqe;
  3579. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3580. wqes[0] = &l2kwqe;
  3581. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3582. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3583. KWQE_OPCODE_SHIFT) | 2;
  3584. dev->submit_kwqes(dev, wqes, 1);
  3585. }
  3586. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. u32 val;
  3590. val = cp->func << 2;
  3591. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3592. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3593. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3594. dev->mac_addr[0] = (u8) (val >> 8);
  3595. dev->mac_addr[1] = (u8) val;
  3596. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3597. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3598. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3599. dev->mac_addr[2] = (u8) (val >> 24);
  3600. dev->mac_addr[3] = (u8) (val >> 16);
  3601. dev->mac_addr[4] = (u8) (val >> 8);
  3602. dev->mac_addr[5] = (u8) val;
  3603. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3604. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3605. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3606. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3607. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3608. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3609. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3610. }
  3611. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3612. {
  3613. struct cnic_local *cp = dev->cnic_priv;
  3614. struct cnic_eth_dev *ethdev = cp->ethdev;
  3615. struct status_block *sblk = cp->status_blk.gen;
  3616. u32 val, kcq_cid_addr, kwq_cid_addr;
  3617. int err;
  3618. cnic_set_bnx2_mac(dev);
  3619. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3620. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3621. if (BCM_PAGE_BITS > 12)
  3622. val |= (12 - 8) << 4;
  3623. else
  3624. val |= (BCM_PAGE_BITS - 8) << 4;
  3625. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3626. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3627. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3628. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3629. err = cnic_setup_5709_context(dev, 1);
  3630. if (err)
  3631. return err;
  3632. cnic_init_context(dev, KWQ_CID);
  3633. cnic_init_context(dev, KCQ_CID);
  3634. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3635. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3636. cp->max_kwq_idx = MAX_KWQ_IDX;
  3637. cp->kwq_prod_idx = 0;
  3638. cp->kwq_con_idx = 0;
  3639. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3640. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3641. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3642. else
  3643. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3644. /* Initialize the kernel work queue context. */
  3645. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3646. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3647. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3648. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3649. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3650. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3651. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3652. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3653. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3654. val = (u32) cp->kwq_info.pgtbl_map;
  3655. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3656. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3657. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3658. cp->kcq1.sw_prod_idx = 0;
  3659. cp->kcq1.hw_prod_idx_ptr =
  3660. (u16 *) &sblk->status_completion_producer_index;
  3661. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3662. /* Initialize the kernel complete queue context. */
  3663. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3664. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3665. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3666. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3667. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3668. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3669. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3670. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3671. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3672. val = (u32) cp->kcq1.dma.pgtbl_map;
  3673. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3674. cp->int_num = 0;
  3675. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3676. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3677. u32 sb_id = cp->status_blk_num;
  3678. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3679. cp->kcq1.hw_prod_idx_ptr =
  3680. (u16 *) &msblk->status_completion_producer_index;
  3681. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3682. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3683. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3684. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3685. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3686. }
  3687. /* Enable Commnad Scheduler notification when we write to the
  3688. * host producer index of the kernel contexts. */
  3689. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3690. /* Enable Command Scheduler notification when we write to either
  3691. * the Send Queue or Receive Queue producer indexes of the kernel
  3692. * bypass contexts. */
  3693. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3694. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3695. /* Notify COM when the driver post an application buffer. */
  3696. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3697. /* Set the CP and COM doorbells. These two processors polls the
  3698. * doorbell for a non zero value before running. This must be done
  3699. * after setting up the kernel queue contexts. */
  3700. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3701. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3702. cnic_init_bnx2_tx_ring(dev);
  3703. cnic_init_bnx2_rx_ring(dev);
  3704. err = cnic_init_bnx2_irq(dev);
  3705. if (err) {
  3706. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3707. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3708. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3709. return err;
  3710. }
  3711. return 0;
  3712. }
  3713. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3714. {
  3715. struct cnic_local *cp = dev->cnic_priv;
  3716. struct cnic_eth_dev *ethdev = cp->ethdev;
  3717. u32 start_offset = ethdev->ctx_tbl_offset;
  3718. int i;
  3719. for (i = 0; i < cp->ctx_blks; i++) {
  3720. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3721. dma_addr_t map = ctx->mapping;
  3722. if (cp->ctx_align) {
  3723. unsigned long mask = cp->ctx_align - 1;
  3724. map = (map + mask) & ~mask;
  3725. }
  3726. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3727. }
  3728. }
  3729. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3730. {
  3731. struct cnic_local *cp = dev->cnic_priv;
  3732. struct cnic_eth_dev *ethdev = cp->ethdev;
  3733. int err = 0;
  3734. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3735. (unsigned long) dev);
  3736. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3737. err = cnic_request_irq(dev);
  3738. return err;
  3739. }
  3740. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3741. u16 sb_id, u8 sb_index,
  3742. u8 disable)
  3743. {
  3744. u32 addr = BAR_CSTRORM_INTMEM +
  3745. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3746. offsetof(struct hc_status_block_data_e1x, index_data) +
  3747. sizeof(struct hc_index_data)*sb_index +
  3748. offsetof(struct hc_index_data, flags);
  3749. u16 flags = CNIC_RD16(dev, addr);
  3750. /* clear and set */
  3751. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3752. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3753. HC_INDEX_DATA_HC_ENABLED);
  3754. CNIC_WR16(dev, addr, flags);
  3755. }
  3756. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3757. {
  3758. struct cnic_local *cp = dev->cnic_priv;
  3759. u8 sb_id = cp->status_blk_num;
  3760. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3761. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3762. offsetof(struct hc_status_block_data_e1x, index_data) +
  3763. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3764. offsetof(struct hc_index_data, timeout), 64 / 12);
  3765. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3766. }
  3767. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3768. {
  3769. }
  3770. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3771. struct client_init_ramrod_data *data)
  3772. {
  3773. struct cnic_local *cp = dev->cnic_priv;
  3774. struct cnic_uio_dev *udev = cp->udev;
  3775. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3776. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3777. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3778. int port = CNIC_PORT(cp);
  3779. int i;
  3780. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3781. u32 val;
  3782. memset(txbd, 0, BCM_PAGE_SIZE);
  3783. buf_map = udev->l2_buf_map;
  3784. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3785. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3786. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3787. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3788. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3789. reg_bd->addr_hi = start_bd->addr_hi;
  3790. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3791. start_bd->nbytes = cpu_to_le16(0x10);
  3792. start_bd->nbd = cpu_to_le16(3);
  3793. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3794. start_bd->general_data = (UNICAST_ADDRESS <<
  3795. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3796. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3797. }
  3798. val = (u64) ring_map >> 32;
  3799. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3800. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3801. val = (u64) ring_map & 0xffffffff;
  3802. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3803. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3804. /* Other ramrod params */
  3805. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3806. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3807. /* reset xstorm per client statistics */
  3808. if (cli < MAX_STAT_COUNTER_ID) {
  3809. val = BAR_XSTRORM_INTMEM +
  3810. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3811. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3812. CNIC_WR(dev, val + i * 4, 0);
  3813. }
  3814. cp->tx_cons_ptr =
  3815. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3816. }
  3817. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3818. struct client_init_ramrod_data *data)
  3819. {
  3820. struct cnic_local *cp = dev->cnic_priv;
  3821. struct cnic_uio_dev *udev = cp->udev;
  3822. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3823. BCM_PAGE_SIZE);
  3824. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3825. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3826. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3827. int i;
  3828. int port = CNIC_PORT(cp);
  3829. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3830. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3831. u32 val;
  3832. dma_addr_t ring_map = udev->l2_ring_map;
  3833. /* General data */
  3834. data->general.client_id = cli;
  3835. data->general.statistics_en_flg = 1;
  3836. data->general.statistics_counter_id = cli;
  3837. data->general.activate_flg = 1;
  3838. data->general.sp_client_id = cli;
  3839. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3840. dma_addr_t buf_map;
  3841. int n = (i % cp->l2_rx_ring_size) + 1;
  3842. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3843. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3844. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3845. }
  3846. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3847. rxbd->addr_hi = cpu_to_le32(val);
  3848. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3849. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3850. rxbd->addr_lo = cpu_to_le32(val);
  3851. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3852. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3853. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3854. rxcqe->addr_hi = cpu_to_le32(val);
  3855. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3856. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3857. rxcqe->addr_lo = cpu_to_le32(val);
  3858. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3859. /* Other ramrod params */
  3860. data->rx.client_qzone_id = cl_qzone_id;
  3861. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3862. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3863. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3864. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3865. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3866. data->rx.outer_vlan_removal_enable_flg = 1;
  3867. /* reset tstorm and ustorm per client statistics */
  3868. if (cli < MAX_STAT_COUNTER_ID) {
  3869. val = BAR_TSTRORM_INTMEM +
  3870. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3871. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3872. CNIC_WR(dev, val + i * 4, 0);
  3873. val = BAR_USTRORM_INTMEM +
  3874. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3875. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3876. CNIC_WR(dev, val + i * 4, 0);
  3877. }
  3878. cp->rx_cons_ptr =
  3879. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3880. cp->rx_cons = *cp->rx_cons_ptr;
  3881. }
  3882. static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
  3883. u32 lower_addr)
  3884. {
  3885. u32 val;
  3886. u8 mac[6];
  3887. val = CNIC_RD(dev, upper_addr);
  3888. mac[0] = (u8) (val >> 8);
  3889. mac[1] = (u8) val;
  3890. val = CNIC_RD(dev, lower_addr);
  3891. mac[2] = (u8) (val >> 24);
  3892. mac[3] = (u8) (val >> 16);
  3893. mac[4] = (u8) (val >> 8);
  3894. mac[5] = (u8) val;
  3895. if (is_valid_ether_addr(mac)) {
  3896. memcpy(dev->mac_addr, mac, 6);
  3897. return 0;
  3898. } else {
  3899. return -EINVAL;
  3900. }
  3901. }
  3902. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3903. {
  3904. struct cnic_local *cp = dev->cnic_priv;
  3905. u32 base, base2, addr, addr1, val;
  3906. int port = CNIC_PORT(cp);
  3907. dev->max_iscsi_conn = 0;
  3908. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3909. if (base == 0)
  3910. return;
  3911. base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
  3912. MISC_REG_GENERIC_CR_0));
  3913. addr = BNX2X_SHMEM_ADDR(base,
  3914. dev_info.port_hw_config[port].iscsi_mac_upper);
  3915. addr1 = BNX2X_SHMEM_ADDR(base,
  3916. dev_info.port_hw_config[port].iscsi_mac_lower);
  3917. cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
  3918. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3919. val = CNIC_RD(dev, addr);
  3920. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3921. u16 val16;
  3922. addr = BNX2X_SHMEM_ADDR(base,
  3923. drv_lic_key[port].max_iscsi_init_conn);
  3924. val16 = CNIC_RD16(dev, addr);
  3925. if (val16)
  3926. val16 ^= 0x1e1e;
  3927. dev->max_iscsi_conn = val16;
  3928. }
  3929. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  3930. dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  3931. if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3932. int func = CNIC_FUNC(cp);
  3933. u32 mf_cfg_addr;
  3934. if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
  3935. mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
  3936. mf_cfg_addr));
  3937. else
  3938. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3939. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3940. /* Must determine if the MF is SD vs SI mode */
  3941. addr = BNX2X_SHMEM_ADDR(base,
  3942. dev_info.shared_feature_config.config);
  3943. val = CNIC_RD(dev, addr);
  3944. if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
  3945. SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
  3946. int rc;
  3947. /* MULTI_FUNCTION_SI mode */
  3948. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3949. func_ext_config[func].func_cfg);
  3950. val = CNIC_RD(dev, addr);
  3951. if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
  3952. dev->max_iscsi_conn = 0;
  3953. if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
  3954. dev->max_fcoe_conn = 0;
  3955. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3956. func_ext_config[func].
  3957. iscsi_mac_addr_upper);
  3958. addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3959. func_ext_config[func].
  3960. iscsi_mac_addr_lower);
  3961. rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
  3962. addr1);
  3963. if (rc && func > 1)
  3964. dev->max_iscsi_conn = 0;
  3965. return;
  3966. }
  3967. }
  3968. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3969. func_mf_config[func].e1hov_tag);
  3970. val = CNIC_RD(dev, addr);
  3971. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3972. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3973. dev->max_fcoe_conn = 0;
  3974. dev->max_iscsi_conn = 0;
  3975. }
  3976. }
  3977. if (!is_valid_ether_addr(dev->mac_addr))
  3978. dev->max_iscsi_conn = 0;
  3979. }
  3980. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3981. {
  3982. struct cnic_local *cp = dev->cnic_priv;
  3983. u32 pfid = cp->pfid;
  3984. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3985. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3986. cp->kcq1.sw_prod_idx = 0;
  3987. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3988. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3989. cp->kcq1.hw_prod_idx_ptr =
  3990. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3991. cp->kcq1.status_idx_ptr =
  3992. &sb->sb.running_index[SM_RX_ID];
  3993. } else {
  3994. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3995. cp->kcq1.hw_prod_idx_ptr =
  3996. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3997. cp->kcq1.status_idx_ptr =
  3998. &sb->sb.running_index[SM_RX_ID];
  3999. }
  4000. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  4001. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4002. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4003. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4004. cp->kcq2.sw_prod_idx = 0;
  4005. cp->kcq2.hw_prod_idx_ptr =
  4006. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4007. cp->kcq2.status_idx_ptr =
  4008. &sb->sb.running_index[SM_RX_ID];
  4009. }
  4010. }
  4011. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4012. {
  4013. struct cnic_local *cp = dev->cnic_priv;
  4014. struct cnic_eth_dev *ethdev = cp->ethdev;
  4015. int func = CNIC_FUNC(cp), ret, i;
  4016. u32 pfid;
  4017. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  4018. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4019. if (!(val & 1))
  4020. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4021. else
  4022. val = (val >> 1) & 1;
  4023. if (val)
  4024. cp->pfid = func >> 1;
  4025. else
  4026. cp->pfid = func & 0x6;
  4027. } else {
  4028. cp->pfid = func;
  4029. }
  4030. pfid = cp->pfid;
  4031. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4032. cp->iscsi_start_cid);
  4033. if (ret)
  4034. return -ENOMEM;
  4035. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  4036. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  4037. BNX2X_FCOE_NUM_CONNECTIONS,
  4038. cp->fcoe_start_cid);
  4039. if (ret)
  4040. return -ENOMEM;
  4041. }
  4042. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4043. cnic_init_bnx2x_kcq(dev);
  4044. cnic_get_bnx2x_iscsi_info(dev);
  4045. /* Only 1 EQ */
  4046. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4047. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4048. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4049. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4050. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4051. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4052. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4053. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4054. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4055. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4056. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4057. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4058. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4059. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4060. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4061. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4062. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4063. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4064. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4065. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4066. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4067. HC_INDEX_ISCSI_EQ_CONS);
  4068. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  4069. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4070. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  4071. cp->conn_buf_info.pgtbl[2 * i]);
  4072. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4073. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  4074. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  4075. }
  4076. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4077. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4078. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4079. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4080. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4081. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4082. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4083. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4084. cnic_setup_bnx2x_context(dev);
  4085. ret = cnic_init_bnx2x_irq(dev);
  4086. if (ret)
  4087. return ret;
  4088. return 0;
  4089. }
  4090. static void cnic_init_rings(struct cnic_dev *dev)
  4091. {
  4092. struct cnic_local *cp = dev->cnic_priv;
  4093. struct cnic_uio_dev *udev = cp->udev;
  4094. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4095. return;
  4096. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4097. cnic_init_bnx2_tx_ring(dev);
  4098. cnic_init_bnx2_rx_ring(dev);
  4099. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4100. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4101. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4102. u32 cid = cp->ethdev->iscsi_l2_cid;
  4103. u32 cl_qzone_id;
  4104. struct client_init_ramrod_data *data;
  4105. union l5cm_specific_data l5_data;
  4106. struct ustorm_eth_rx_producers rx_prods = {0};
  4107. u32 off, i;
  4108. rx_prods.bd_prod = 0;
  4109. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4110. barrier();
  4111. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4112. off = BAR_USTRORM_INTMEM +
  4113. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4114. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4115. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4116. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4117. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4118. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4119. data = udev->l2_buf;
  4120. memset(data, 0, sizeof(*data));
  4121. cnic_init_bnx2x_tx_ring(dev, data);
  4122. cnic_init_bnx2x_rx_ring(dev, data);
  4123. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4124. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4125. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4126. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4127. cid, ETH_CONNECTION_TYPE, &l5_data);
  4128. i = 0;
  4129. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4130. ++i < 10)
  4131. msleep(1);
  4132. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4133. netdev_err(dev->netdev,
  4134. "iSCSI CLIENT_SETUP did not complete\n");
  4135. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4136. cnic_ring_ctl(dev, cid, cli, 1);
  4137. }
  4138. }
  4139. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4140. {
  4141. struct cnic_local *cp = dev->cnic_priv;
  4142. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4143. return;
  4144. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4145. cnic_shutdown_bnx2_rx_ring(dev);
  4146. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4147. struct cnic_local *cp = dev->cnic_priv;
  4148. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4149. u32 cid = cp->ethdev->iscsi_l2_cid;
  4150. union l5cm_specific_data l5_data;
  4151. int i;
  4152. cnic_ring_ctl(dev, cid, cli, 0);
  4153. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4154. l5_data.phy_address.lo = cli;
  4155. l5_data.phy_address.hi = 0;
  4156. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4157. cid, ETH_CONNECTION_TYPE, &l5_data);
  4158. i = 0;
  4159. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4160. ++i < 10)
  4161. msleep(1);
  4162. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4163. netdev_err(dev->netdev,
  4164. "iSCSI CLIENT_HALT did not complete\n");
  4165. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4166. memset(&l5_data, 0, sizeof(l5_data));
  4167. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4168. cid, NONE_CONNECTION_TYPE, &l5_data);
  4169. msleep(10);
  4170. }
  4171. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4172. }
  4173. static int cnic_register_netdev(struct cnic_dev *dev)
  4174. {
  4175. struct cnic_local *cp = dev->cnic_priv;
  4176. struct cnic_eth_dev *ethdev = cp->ethdev;
  4177. int err;
  4178. if (!ethdev)
  4179. return -ENODEV;
  4180. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4181. return 0;
  4182. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4183. if (err)
  4184. netdev_err(dev->netdev, "register_cnic failed\n");
  4185. return err;
  4186. }
  4187. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4188. {
  4189. struct cnic_local *cp = dev->cnic_priv;
  4190. struct cnic_eth_dev *ethdev = cp->ethdev;
  4191. if (!ethdev)
  4192. return;
  4193. ethdev->drv_unregister_cnic(dev->netdev);
  4194. }
  4195. static int cnic_start_hw(struct cnic_dev *dev)
  4196. {
  4197. struct cnic_local *cp = dev->cnic_priv;
  4198. struct cnic_eth_dev *ethdev = cp->ethdev;
  4199. int err;
  4200. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4201. return -EALREADY;
  4202. dev->regview = ethdev->io_base;
  4203. pci_dev_get(dev->pcidev);
  4204. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4205. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4206. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4207. err = cp->alloc_resc(dev);
  4208. if (err) {
  4209. netdev_err(dev->netdev, "allocate resource failure\n");
  4210. goto err1;
  4211. }
  4212. err = cp->start_hw(dev);
  4213. if (err)
  4214. goto err1;
  4215. err = cnic_cm_open(dev);
  4216. if (err)
  4217. goto err1;
  4218. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4219. cp->enable_int(dev);
  4220. return 0;
  4221. err1:
  4222. cp->free_resc(dev);
  4223. pci_dev_put(dev->pcidev);
  4224. return err;
  4225. }
  4226. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4227. {
  4228. cnic_disable_bnx2_int_sync(dev);
  4229. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4230. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4231. cnic_init_context(dev, KWQ_CID);
  4232. cnic_init_context(dev, KCQ_CID);
  4233. cnic_setup_5709_context(dev, 0);
  4234. cnic_free_irq(dev);
  4235. cnic_free_resc(dev);
  4236. }
  4237. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4238. {
  4239. struct cnic_local *cp = dev->cnic_priv;
  4240. cnic_free_irq(dev);
  4241. *cp->kcq1.hw_prod_idx_ptr = 0;
  4242. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4243. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4244. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4245. cnic_free_resc(dev);
  4246. }
  4247. static void cnic_stop_hw(struct cnic_dev *dev)
  4248. {
  4249. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4250. struct cnic_local *cp = dev->cnic_priv;
  4251. int i = 0;
  4252. /* Need to wait for the ring shutdown event to complete
  4253. * before clearing the CNIC_UP flag.
  4254. */
  4255. while (cp->udev->uio_dev != -1 && i < 15) {
  4256. msleep(100);
  4257. i++;
  4258. }
  4259. cnic_shutdown_rings(dev);
  4260. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4261. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4262. synchronize_rcu();
  4263. cnic_cm_shutdown(dev);
  4264. cp->stop_hw(dev);
  4265. pci_dev_put(dev->pcidev);
  4266. }
  4267. }
  4268. static void cnic_free_dev(struct cnic_dev *dev)
  4269. {
  4270. int i = 0;
  4271. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4272. msleep(100);
  4273. i++;
  4274. }
  4275. if (atomic_read(&dev->ref_count) != 0)
  4276. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4277. netdev_info(dev->netdev, "Removed CNIC device\n");
  4278. dev_put(dev->netdev);
  4279. kfree(dev);
  4280. }
  4281. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4282. struct pci_dev *pdev)
  4283. {
  4284. struct cnic_dev *cdev;
  4285. struct cnic_local *cp;
  4286. int alloc_size;
  4287. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4288. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4289. if (cdev == NULL) {
  4290. netdev_err(dev, "allocate dev struct failure\n");
  4291. return NULL;
  4292. }
  4293. cdev->netdev = dev;
  4294. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4295. cdev->register_device = cnic_register_device;
  4296. cdev->unregister_device = cnic_unregister_device;
  4297. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4298. cp = cdev->cnic_priv;
  4299. cp->dev = cdev;
  4300. cp->l2_single_buf_size = 0x400;
  4301. cp->l2_rx_ring_size = 3;
  4302. spin_lock_init(&cp->cnic_ulp_lock);
  4303. netdev_info(dev, "Added CNIC device\n");
  4304. return cdev;
  4305. }
  4306. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4307. {
  4308. struct pci_dev *pdev;
  4309. struct cnic_dev *cdev;
  4310. struct cnic_local *cp;
  4311. struct cnic_eth_dev *ethdev = NULL;
  4312. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4313. probe = symbol_get(bnx2_cnic_probe);
  4314. if (probe) {
  4315. ethdev = (*probe)(dev);
  4316. symbol_put(bnx2_cnic_probe);
  4317. }
  4318. if (!ethdev)
  4319. return NULL;
  4320. pdev = ethdev->pdev;
  4321. if (!pdev)
  4322. return NULL;
  4323. dev_hold(dev);
  4324. pci_dev_get(pdev);
  4325. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4326. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  4327. u8 rev;
  4328. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  4329. if (rev < 0x10) {
  4330. pci_dev_put(pdev);
  4331. goto cnic_err;
  4332. }
  4333. }
  4334. pci_dev_put(pdev);
  4335. cdev = cnic_alloc_dev(dev, pdev);
  4336. if (cdev == NULL)
  4337. goto cnic_err;
  4338. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4339. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4340. cp = cdev->cnic_priv;
  4341. cp->ethdev = ethdev;
  4342. cdev->pcidev = pdev;
  4343. cp->chip_id = ethdev->chip_id;
  4344. cp->cnic_ops = &cnic_bnx2_ops;
  4345. cp->start_hw = cnic_start_bnx2_hw;
  4346. cp->stop_hw = cnic_stop_bnx2_hw;
  4347. cp->setup_pgtbl = cnic_setup_page_tbl;
  4348. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4349. cp->free_resc = cnic_free_resc;
  4350. cp->start_cm = cnic_cm_init_bnx2_hw;
  4351. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4352. cp->enable_int = cnic_enable_bnx2_int;
  4353. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4354. cp->close_conn = cnic_close_bnx2_conn;
  4355. cp->next_idx = cnic_bnx2_next_idx;
  4356. cp->hw_idx = cnic_bnx2_hw_idx;
  4357. return cdev;
  4358. cnic_err:
  4359. dev_put(dev);
  4360. return NULL;
  4361. }
  4362. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4363. {
  4364. struct pci_dev *pdev;
  4365. struct cnic_dev *cdev;
  4366. struct cnic_local *cp;
  4367. struct cnic_eth_dev *ethdev = NULL;
  4368. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4369. probe = symbol_get(bnx2x_cnic_probe);
  4370. if (probe) {
  4371. ethdev = (*probe)(dev);
  4372. symbol_put(bnx2x_cnic_probe);
  4373. }
  4374. if (!ethdev)
  4375. return NULL;
  4376. pdev = ethdev->pdev;
  4377. if (!pdev)
  4378. return NULL;
  4379. dev_hold(dev);
  4380. cdev = cnic_alloc_dev(dev, pdev);
  4381. if (cdev == NULL) {
  4382. dev_put(dev);
  4383. return NULL;
  4384. }
  4385. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4386. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4387. cp = cdev->cnic_priv;
  4388. cp->ethdev = ethdev;
  4389. cdev->pcidev = pdev;
  4390. cp->chip_id = ethdev->chip_id;
  4391. cp->cnic_ops = &cnic_bnx2x_ops;
  4392. cp->start_hw = cnic_start_bnx2x_hw;
  4393. cp->stop_hw = cnic_stop_bnx2x_hw;
  4394. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4395. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4396. cp->free_resc = cnic_free_resc;
  4397. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4398. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4399. cp->enable_int = cnic_enable_bnx2x_int;
  4400. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4401. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  4402. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4403. else
  4404. cp->ack_int = cnic_ack_bnx2x_msix;
  4405. cp->close_conn = cnic_close_bnx2x_conn;
  4406. cp->next_idx = cnic_bnx2x_next_idx;
  4407. cp->hw_idx = cnic_bnx2x_hw_idx;
  4408. return cdev;
  4409. }
  4410. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4411. {
  4412. struct ethtool_drvinfo drvinfo;
  4413. struct cnic_dev *cdev = NULL;
  4414. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4415. memset(&drvinfo, 0, sizeof(drvinfo));
  4416. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4417. if (!strcmp(drvinfo.driver, "bnx2"))
  4418. cdev = init_bnx2_cnic(dev);
  4419. if (!strcmp(drvinfo.driver, "bnx2x"))
  4420. cdev = init_bnx2x_cnic(dev);
  4421. if (cdev) {
  4422. write_lock(&cnic_dev_lock);
  4423. list_add(&cdev->list, &cnic_dev_list);
  4424. write_unlock(&cnic_dev_lock);
  4425. }
  4426. }
  4427. return cdev;
  4428. }
  4429. /**
  4430. * netdev event handler
  4431. */
  4432. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4433. void *ptr)
  4434. {
  4435. struct net_device *netdev = ptr;
  4436. struct cnic_dev *dev;
  4437. int if_type;
  4438. int new_dev = 0;
  4439. dev = cnic_from_netdev(netdev);
  4440. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  4441. /* Check for the hot-plug device */
  4442. dev = is_cnic_dev(netdev);
  4443. if (dev) {
  4444. new_dev = 1;
  4445. cnic_hold(dev);
  4446. }
  4447. }
  4448. if (dev) {
  4449. struct cnic_local *cp = dev->cnic_priv;
  4450. if (new_dev)
  4451. cnic_ulp_init(dev);
  4452. else if (event == NETDEV_UNREGISTER)
  4453. cnic_ulp_exit(dev);
  4454. if (event == NETDEV_UP) {
  4455. if (cnic_register_netdev(dev) != 0) {
  4456. cnic_put(dev);
  4457. goto done;
  4458. }
  4459. if (!cnic_start_hw(dev))
  4460. cnic_ulp_start(dev);
  4461. }
  4462. rcu_read_lock();
  4463. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4464. struct cnic_ulp_ops *ulp_ops;
  4465. void *ctx;
  4466. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4467. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4468. continue;
  4469. ctx = cp->ulp_handle[if_type];
  4470. ulp_ops->indicate_netevent(ctx, event);
  4471. }
  4472. rcu_read_unlock();
  4473. if (event == NETDEV_GOING_DOWN) {
  4474. cnic_ulp_stop(dev);
  4475. cnic_stop_hw(dev);
  4476. cnic_unregister_netdev(dev);
  4477. } else if (event == NETDEV_UNREGISTER) {
  4478. write_lock(&cnic_dev_lock);
  4479. list_del_init(&dev->list);
  4480. write_unlock(&cnic_dev_lock);
  4481. cnic_put(dev);
  4482. cnic_free_dev(dev);
  4483. goto done;
  4484. }
  4485. cnic_put(dev);
  4486. }
  4487. done:
  4488. return NOTIFY_DONE;
  4489. }
  4490. static struct notifier_block cnic_netdev_notifier = {
  4491. .notifier_call = cnic_netdev_event
  4492. };
  4493. static void cnic_release(void)
  4494. {
  4495. struct cnic_dev *dev;
  4496. struct cnic_uio_dev *udev;
  4497. while (!list_empty(&cnic_dev_list)) {
  4498. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4499. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4500. cnic_ulp_stop(dev);
  4501. cnic_stop_hw(dev);
  4502. }
  4503. cnic_ulp_exit(dev);
  4504. cnic_unregister_netdev(dev);
  4505. list_del_init(&dev->list);
  4506. cnic_free_dev(dev);
  4507. }
  4508. while (!list_empty(&cnic_udev_list)) {
  4509. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4510. list);
  4511. cnic_free_uio(udev);
  4512. }
  4513. }
  4514. static int __init cnic_init(void)
  4515. {
  4516. int rc = 0;
  4517. pr_info("%s", version);
  4518. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4519. if (rc) {
  4520. cnic_release();
  4521. return rc;
  4522. }
  4523. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4524. if (!cnic_wq) {
  4525. cnic_release();
  4526. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4527. return -ENOMEM;
  4528. }
  4529. return 0;
  4530. }
  4531. static void __exit cnic_exit(void)
  4532. {
  4533. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4534. cnic_release();
  4535. destroy_workqueue(cnic_wq);
  4536. }
  4537. module_init(cnic_init);
  4538. module_exit(cnic_exit);