main.c 102 KB

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  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  58. static int modparam_pio;
  59. module_param_named(pio, modparam_pio, int, 0444);
  60. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  61. #elif defined(CONFIG_B43LEGACY_DMA)
  62. # define modparam_pio 0
  63. #elif defined(CONFIG_B43LEGACY_PIO)
  64. # define modparam_pio 1
  65. #endif
  66. static int modparam_bad_frames_preempt;
  67. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  68. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  69. " Preemption");
  70. static int modparam_short_retry = B43legacy_DEFAULT_SHORT_RETRY_LIMIT;
  71. module_param_named(short_retry, modparam_short_retry, int, 0444);
  72. MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  73. static int modparam_long_retry = B43legacy_DEFAULT_LONG_RETRY_LIMIT;
  74. module_param_named(long_retry, modparam_long_retry, int, 0444);
  75. MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  76. static int modparam_noleds;
  77. module_param_named(noleds, modparam_noleds, int, 0444);
  78. MODULE_PARM_DESC(noleds, "Turn off all LED activity");
  79. static char modparam_fwpostfix[16];
  80. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  81. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  82. static int modparam_mon_keep_bad;
  83. module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
  84. MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
  85. static int modparam_mon_keep_badplcp;
  86. module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
  87. MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
  88. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  89. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  90. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  91. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  92. SSB_DEVTABLE_END
  93. };
  94. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  95. /* Channel and ratetables are shared for all devices.
  96. * They can't be const, because ieee80211 puts some precalculated
  97. * data in there. This data is the same for all devices, so we don't
  98. * get concurrency issues */
  99. #define RATETAB_ENT(_rateid, _flags) \
  100. { \
  101. .rate = B43legacy_RATE_TO_100KBPS(_rateid), \
  102. .val = (_rateid), \
  103. .val2 = (_rateid), \
  104. .flags = (_flags), \
  105. }
  106. static struct ieee80211_rate __b43legacy_ratetable[] = {
  107. RATETAB_ENT(B43legacy_CCK_RATE_1MB, IEEE80211_RATE_CCK),
  108. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
  109. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
  110. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
  111. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
  112. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
  113. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
  114. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
  115. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
  116. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
  117. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
  118. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
  119. };
  120. #define b43legacy_a_ratetable (__b43legacy_ratetable + 4)
  121. #define b43legacy_a_ratetable_size 8
  122. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  123. #define b43legacy_b_ratetable_size 4
  124. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  125. #define b43legacy_g_ratetable_size 12
  126. #define CHANTAB_ENT(_chanid, _freq) \
  127. { \
  128. .chan = (_chanid), \
  129. .freq = (_freq), \
  130. .val = (_chanid), \
  131. .flag = IEEE80211_CHAN_W_SCAN | \
  132. IEEE80211_CHAN_W_ACTIVE_SCAN | \
  133. IEEE80211_CHAN_W_IBSS, \
  134. .power_level = 0x0A, \
  135. .antenna_max = 0xFF, \
  136. }
  137. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  138. CHANTAB_ENT(1, 2412),
  139. CHANTAB_ENT(2, 2417),
  140. CHANTAB_ENT(3, 2422),
  141. CHANTAB_ENT(4, 2427),
  142. CHANTAB_ENT(5, 2432),
  143. CHANTAB_ENT(6, 2437),
  144. CHANTAB_ENT(7, 2442),
  145. CHANTAB_ENT(8, 2447),
  146. CHANTAB_ENT(9, 2452),
  147. CHANTAB_ENT(10, 2457),
  148. CHANTAB_ENT(11, 2462),
  149. CHANTAB_ENT(12, 2467),
  150. CHANTAB_ENT(13, 2472),
  151. CHANTAB_ENT(14, 2484),
  152. };
  153. #define b43legacy_bg_chantable_size ARRAY_SIZE(b43legacy_bg_chantable)
  154. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  155. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  156. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  157. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  158. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  159. {
  160. if (!wl || !wl->current_dev)
  161. return 1;
  162. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  163. return 1;
  164. /* We are up and running.
  165. * Ratelimit the messages to avoid DoS over the net. */
  166. return net_ratelimit();
  167. }
  168. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  169. {
  170. va_list args;
  171. if (!b43legacy_ratelimit(wl))
  172. return;
  173. va_start(args, fmt);
  174. printk(KERN_INFO "b43legacy-%s: ",
  175. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  176. vprintk(fmt, args);
  177. va_end(args);
  178. }
  179. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  180. {
  181. va_list args;
  182. if (!b43legacy_ratelimit(wl))
  183. return;
  184. va_start(args, fmt);
  185. printk(KERN_ERR "b43legacy-%s ERROR: ",
  186. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  187. vprintk(fmt, args);
  188. va_end(args);
  189. }
  190. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  191. {
  192. va_list args;
  193. if (!b43legacy_ratelimit(wl))
  194. return;
  195. va_start(args, fmt);
  196. printk(KERN_WARNING "b43legacy-%s warning: ",
  197. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  198. vprintk(fmt, args);
  199. va_end(args);
  200. }
  201. #if B43legacy_DEBUG
  202. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  203. {
  204. va_list args;
  205. va_start(args, fmt);
  206. printk(KERN_DEBUG "b43legacy-%s debug: ",
  207. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  208. vprintk(fmt, args);
  209. va_end(args);
  210. }
  211. #endif /* DEBUG */
  212. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  213. u32 val)
  214. {
  215. u32 status;
  216. B43legacy_WARN_ON(offset % 4 != 0);
  217. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  218. if (status & B43legacy_SBF_XFER_REG_BYTESWAP)
  219. val = swab32(val);
  220. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  221. mmiowb();
  222. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  223. }
  224. static inline
  225. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  226. u16 routing, u16 offset)
  227. {
  228. u32 control;
  229. /* "offset" is the WORD offset. */
  230. control = routing;
  231. control <<= 16;
  232. control |= offset;
  233. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  234. }
  235. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  236. u16 routing, u16 offset)
  237. {
  238. u32 ret;
  239. if (routing == B43legacy_SHM_SHARED) {
  240. B43legacy_WARN_ON((offset & 0x0001) != 0);
  241. if (offset & 0x0003) {
  242. /* Unaligned access */
  243. b43legacy_shm_control_word(dev, routing, offset >> 2);
  244. ret = b43legacy_read16(dev,
  245. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  246. ret <<= 16;
  247. b43legacy_shm_control_word(dev, routing,
  248. (offset >> 2) + 1);
  249. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  250. return ret;
  251. }
  252. offset >>= 2;
  253. }
  254. b43legacy_shm_control_word(dev, routing, offset);
  255. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  256. return ret;
  257. }
  258. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  259. u16 routing, u16 offset)
  260. {
  261. u16 ret;
  262. if (routing == B43legacy_SHM_SHARED) {
  263. B43legacy_WARN_ON((offset & 0x0001) != 0);
  264. if (offset & 0x0003) {
  265. /* Unaligned access */
  266. b43legacy_shm_control_word(dev, routing, offset >> 2);
  267. ret = b43legacy_read16(dev,
  268. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  269. return ret;
  270. }
  271. offset >>= 2;
  272. }
  273. b43legacy_shm_control_word(dev, routing, offset);
  274. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  275. return ret;
  276. }
  277. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  278. u16 routing, u16 offset,
  279. u32 value)
  280. {
  281. if (routing == B43legacy_SHM_SHARED) {
  282. B43legacy_WARN_ON((offset & 0x0001) != 0);
  283. if (offset & 0x0003) {
  284. /* Unaligned access */
  285. b43legacy_shm_control_word(dev, routing, offset >> 2);
  286. mmiowb();
  287. b43legacy_write16(dev,
  288. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  289. (value >> 16) & 0xffff);
  290. mmiowb();
  291. b43legacy_shm_control_word(dev, routing,
  292. (offset >> 2) + 1);
  293. mmiowb();
  294. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  295. value & 0xffff);
  296. return;
  297. }
  298. offset >>= 2;
  299. }
  300. b43legacy_shm_control_word(dev, routing, offset);
  301. mmiowb();
  302. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  303. }
  304. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  305. u16 value)
  306. {
  307. if (routing == B43legacy_SHM_SHARED) {
  308. B43legacy_WARN_ON((offset & 0x0001) != 0);
  309. if (offset & 0x0003) {
  310. /* Unaligned access */
  311. b43legacy_shm_control_word(dev, routing, offset >> 2);
  312. mmiowb();
  313. b43legacy_write16(dev,
  314. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  315. value);
  316. return;
  317. }
  318. offset >>= 2;
  319. }
  320. b43legacy_shm_control_word(dev, routing, offset);
  321. mmiowb();
  322. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  323. }
  324. /* Read HostFlags */
  325. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  326. {
  327. u32 ret;
  328. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  329. B43legacy_SHM_SH_HOSTFHI);
  330. ret <<= 16;
  331. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  332. B43legacy_SHM_SH_HOSTFLO);
  333. return ret;
  334. }
  335. /* Write HostFlags */
  336. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  337. {
  338. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  339. B43legacy_SHM_SH_HOSTFLO,
  340. (value & 0x0000FFFF));
  341. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  342. B43legacy_SHM_SH_HOSTFHI,
  343. ((value & 0xFFFF0000) >> 16));
  344. }
  345. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  346. {
  347. /* We need to be careful. As we read the TSF from multiple
  348. * registers, we should take care of register overflows.
  349. * In theory, the whole tsf read process should be atomic.
  350. * We try to be atomic here, by restaring the read process,
  351. * if any of the high registers changed (overflew).
  352. */
  353. if (dev->dev->id.revision >= 3) {
  354. u32 low;
  355. u32 high;
  356. u32 high2;
  357. do {
  358. high = b43legacy_read32(dev,
  359. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  360. low = b43legacy_read32(dev,
  361. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  362. high2 = b43legacy_read32(dev,
  363. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  364. } while (unlikely(high != high2));
  365. *tsf = high;
  366. *tsf <<= 32;
  367. *tsf |= low;
  368. } else {
  369. u64 tmp;
  370. u16 v0;
  371. u16 v1;
  372. u16 v2;
  373. u16 v3;
  374. u16 test1;
  375. u16 test2;
  376. u16 test3;
  377. do {
  378. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  379. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  380. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  381. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  382. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  383. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  384. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  385. } while (v3 != test3 || v2 != test2 || v1 != test1);
  386. *tsf = v3;
  387. *tsf <<= 48;
  388. tmp = v2;
  389. tmp <<= 32;
  390. *tsf |= tmp;
  391. tmp = v1;
  392. tmp <<= 16;
  393. *tsf |= tmp;
  394. *tsf |= v0;
  395. }
  396. }
  397. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  398. {
  399. u32 status;
  400. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  401. status |= B43legacy_SBF_TIME_UPDATE;
  402. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  403. mmiowb();
  404. }
  405. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  406. {
  407. u32 status;
  408. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  409. status &= ~B43legacy_SBF_TIME_UPDATE;
  410. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  411. }
  412. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  413. {
  414. /* Be careful with the in-progress timer.
  415. * First zero out the low register, so we have a full
  416. * register-overflow duration to complete the operation.
  417. */
  418. if (dev->dev->id.revision >= 3) {
  419. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  420. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  421. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  422. mmiowb();
  423. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  424. hi);
  425. mmiowb();
  426. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  427. lo);
  428. } else {
  429. u16 v0 = (tsf & 0x000000000000FFFFULL);
  430. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  431. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  432. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  433. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  434. mmiowb();
  435. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  436. mmiowb();
  437. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  438. mmiowb();
  439. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  440. mmiowb();
  441. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  442. }
  443. }
  444. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  445. {
  446. b43legacy_time_lock(dev);
  447. b43legacy_tsf_write_locked(dev, tsf);
  448. b43legacy_time_unlock(dev);
  449. }
  450. static
  451. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  452. u16 offset, const u8 *mac)
  453. {
  454. static const u8 zero_addr[ETH_ALEN] = { 0 };
  455. u16 data;
  456. if (!mac)
  457. mac = zero_addr;
  458. offset |= 0x0020;
  459. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  460. data = mac[0];
  461. data |= mac[1] << 8;
  462. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  463. data = mac[2];
  464. data |= mac[3] << 8;
  465. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  466. data = mac[4];
  467. data |= mac[5] << 8;
  468. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  469. }
  470. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  471. {
  472. static const u8 zero_addr[ETH_ALEN] = { 0 };
  473. const u8 *mac = dev->wl->mac_addr;
  474. const u8 *bssid = dev->wl->bssid;
  475. u8 mac_bssid[ETH_ALEN * 2];
  476. int i;
  477. u32 tmp;
  478. if (!bssid)
  479. bssid = zero_addr;
  480. if (!mac)
  481. mac = zero_addr;
  482. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  483. memcpy(mac_bssid, mac, ETH_ALEN);
  484. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  485. /* Write our MAC address and BSSID to template ram */
  486. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  487. tmp = (u32)(mac_bssid[i + 0]);
  488. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  489. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  490. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  491. b43legacy_ram_write(dev, 0x20 + i, tmp);
  492. b43legacy_ram_write(dev, 0x78 + i, tmp);
  493. b43legacy_ram_write(dev, 0x478 + i, tmp);
  494. }
  495. }
  496. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev,
  497. const u8 *mac_addr)
  498. {
  499. dev->wl->mac_addr = mac_addr;
  500. b43legacy_write_mac_bssid_templates(dev);
  501. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF, mac_addr);
  502. }
  503. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  504. u16 slot_time)
  505. {
  506. /* slot_time is in usec. */
  507. if (dev->phy.type != B43legacy_PHYTYPE_G)
  508. return;
  509. b43legacy_write16(dev, 0x684, 510 + slot_time);
  510. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  511. slot_time);
  512. }
  513. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  514. {
  515. b43legacy_set_slot_time(dev, 9);
  516. dev->short_slot = 1;
  517. }
  518. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  519. {
  520. b43legacy_set_slot_time(dev, 20);
  521. dev->short_slot = 0;
  522. }
  523. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  524. * Returns the _previously_ enabled IRQ mask.
  525. */
  526. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  527. u32 mask)
  528. {
  529. u32 old_mask;
  530. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  531. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  532. mask);
  533. return old_mask;
  534. }
  535. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  536. * Returns the _previously_ enabled IRQ mask.
  537. */
  538. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  539. u32 mask)
  540. {
  541. u32 old_mask;
  542. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  543. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  544. return old_mask;
  545. }
  546. /* Synchronize IRQ top- and bottom-half.
  547. * IRQs must be masked before calling this.
  548. * This must not be called with the irq_lock held.
  549. */
  550. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  551. {
  552. synchronize_irq(dev->dev->irq);
  553. tasklet_kill(&dev->isr_tasklet);
  554. }
  555. /* DummyTransmission function, as documented on
  556. * http://bcm-specs.sipsolutions.net/DummyTransmission
  557. */
  558. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  559. {
  560. struct b43legacy_phy *phy = &dev->phy;
  561. unsigned int i;
  562. unsigned int max_loop;
  563. u16 value;
  564. u32 buffer[5] = {
  565. 0x00000000,
  566. 0x00D40000,
  567. 0x00000000,
  568. 0x01000000,
  569. 0x00000000,
  570. };
  571. switch (phy->type) {
  572. case B43legacy_PHYTYPE_B:
  573. case B43legacy_PHYTYPE_G:
  574. max_loop = 0xFA;
  575. buffer[0] = 0x000B846E;
  576. break;
  577. default:
  578. B43legacy_BUG_ON(1);
  579. return;
  580. }
  581. for (i = 0; i < 5; i++)
  582. b43legacy_ram_write(dev, i * 4, buffer[i]);
  583. /* dummy read follows */
  584. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  585. b43legacy_write16(dev, 0x0568, 0x0000);
  586. b43legacy_write16(dev, 0x07C0, 0x0000);
  587. b43legacy_write16(dev, 0x050C, 0x0000);
  588. b43legacy_write16(dev, 0x0508, 0x0000);
  589. b43legacy_write16(dev, 0x050A, 0x0000);
  590. b43legacy_write16(dev, 0x054C, 0x0000);
  591. b43legacy_write16(dev, 0x056A, 0x0014);
  592. b43legacy_write16(dev, 0x0568, 0x0826);
  593. b43legacy_write16(dev, 0x0500, 0x0000);
  594. b43legacy_write16(dev, 0x0502, 0x0030);
  595. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  596. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  597. for (i = 0x00; i < max_loop; i++) {
  598. value = b43legacy_read16(dev, 0x050E);
  599. if (value & 0x0080)
  600. break;
  601. udelay(10);
  602. }
  603. for (i = 0x00; i < 0x0A; i++) {
  604. value = b43legacy_read16(dev, 0x050E);
  605. if (value & 0x0400)
  606. break;
  607. udelay(10);
  608. }
  609. for (i = 0x00; i < 0x0A; i++) {
  610. value = b43legacy_read16(dev, 0x0690);
  611. if (!(value & 0x0100))
  612. break;
  613. udelay(10);
  614. }
  615. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  616. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  617. }
  618. /* Turn the Analog ON/OFF */
  619. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  620. {
  621. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  622. }
  623. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  624. {
  625. u32 tmslow;
  626. u32 macctl;
  627. flags |= B43legacy_TMSLOW_PHYCLKEN;
  628. flags |= B43legacy_TMSLOW_PHYRESET;
  629. ssb_device_enable(dev->dev, flags);
  630. msleep(2); /* Wait for the PLL to turn on. */
  631. /* Now take the PHY out of Reset again */
  632. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  633. tmslow |= SSB_TMSLOW_FGC;
  634. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  635. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  636. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  637. msleep(1);
  638. tmslow &= ~SSB_TMSLOW_FGC;
  639. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  640. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  641. msleep(1);
  642. /* Turn Analog ON */
  643. b43legacy_switch_analog(dev, 1);
  644. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  645. macctl &= ~B43legacy_MACCTL_GMODE;
  646. if (flags & B43legacy_TMSLOW_GMODE) {
  647. macctl |= B43legacy_MACCTL_GMODE;
  648. dev->phy.gmode = 1;
  649. } else
  650. dev->phy.gmode = 0;
  651. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  652. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  653. }
  654. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  655. {
  656. u32 v0;
  657. u32 v1;
  658. u16 tmp;
  659. struct b43legacy_txstatus stat;
  660. while (1) {
  661. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  662. if (!(v0 & 0x00000001))
  663. break;
  664. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  665. stat.cookie = (v0 >> 16);
  666. stat.seq = (v1 & 0x0000FFFF);
  667. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  668. tmp = (v0 & 0x0000FFFF);
  669. stat.frame_count = ((tmp & 0xF000) >> 12);
  670. stat.rts_count = ((tmp & 0x0F00) >> 8);
  671. stat.supp_reason = ((tmp & 0x001C) >> 2);
  672. stat.pm_indicated = !!(tmp & 0x0080);
  673. stat.intermediate = !!(tmp & 0x0040);
  674. stat.for_ampdu = !!(tmp & 0x0020);
  675. stat.acked = !!(tmp & 0x0002);
  676. b43legacy_handle_txstatus(dev, &stat);
  677. }
  678. }
  679. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  680. {
  681. u32 dummy;
  682. if (dev->dev->id.revision < 5)
  683. return;
  684. /* Read all entries from the microcode TXstatus FIFO
  685. * and throw them away.
  686. */
  687. while (1) {
  688. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  689. if (!(dummy & 0x00000001))
  690. break;
  691. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  692. }
  693. }
  694. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  695. {
  696. u32 val = 0;
  697. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  698. val <<= 16;
  699. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  700. return val;
  701. }
  702. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  703. {
  704. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  705. (jssi & 0x0000FFFF));
  706. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  707. (jssi & 0xFFFF0000) >> 16);
  708. }
  709. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  710. {
  711. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  712. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  713. b43legacy_read32(dev,
  714. B43legacy_MMIO_STATUS2_BITFIELD)
  715. | (1 << 4));
  716. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  717. dev->phy.channel);
  718. }
  719. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  720. {
  721. /* Top half of Link Quality calculation. */
  722. if (dev->noisecalc.calculation_running)
  723. return;
  724. dev->noisecalc.channel_at_start = dev->phy.channel;
  725. dev->noisecalc.calculation_running = 1;
  726. dev->noisecalc.nr_samples = 0;
  727. b43legacy_generate_noise_sample(dev);
  728. }
  729. static void handle_irq_noise(struct b43legacy_wldev *dev)
  730. {
  731. struct b43legacy_phy *phy = &dev->phy;
  732. u16 tmp;
  733. u8 noise[4];
  734. u8 i;
  735. u8 j;
  736. s32 average;
  737. /* Bottom half of Link Quality calculation. */
  738. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  739. if (dev->noisecalc.channel_at_start != phy->channel)
  740. goto drop_calculation;
  741. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  742. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  743. noise[2] == 0x7F || noise[3] == 0x7F)
  744. goto generate_new;
  745. /* Get the noise samples. */
  746. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  747. i = dev->noisecalc.nr_samples;
  748. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  749. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  750. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  751. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  752. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  753. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  754. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  755. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  756. dev->noisecalc.nr_samples++;
  757. if (dev->noisecalc.nr_samples == 8) {
  758. /* Calculate the Link Quality by the noise samples. */
  759. average = 0;
  760. for (i = 0; i < 8; i++) {
  761. for (j = 0; j < 4; j++)
  762. average += dev->noisecalc.samples[i][j];
  763. }
  764. average /= (8 * 4);
  765. average *= 125;
  766. average += 64;
  767. average /= 128;
  768. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  769. 0x40C);
  770. tmp = (tmp / 128) & 0x1F;
  771. if (tmp >= 8)
  772. average += 2;
  773. else
  774. average -= 25;
  775. if (tmp == 8)
  776. average -= 72;
  777. else
  778. average -= 48;
  779. dev->stats.link_noise = average;
  780. drop_calculation:
  781. dev->noisecalc.calculation_running = 0;
  782. return;
  783. }
  784. generate_new:
  785. b43legacy_generate_noise_sample(dev);
  786. }
  787. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  788. {
  789. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  790. /* TODO: PS TBTT */
  791. } else {
  792. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  793. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  794. }
  795. dev->reg124_set_0x4 = 0;
  796. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  797. dev->reg124_set_0x4 = 1;
  798. }
  799. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  800. {
  801. if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
  802. return;
  803. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  804. b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD)
  805. | 0x4);
  806. }
  807. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  808. {
  809. u32 tmp;
  810. /* TODO: AP mode. */
  811. while (1) {
  812. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  813. if (!(tmp & 0x00000008))
  814. break;
  815. }
  816. /* 16bit write is odd, but correct. */
  817. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  818. }
  819. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  820. const u8 *data, u16 size,
  821. u16 ram_offset,
  822. u16 shm_size_offset, u8 rate)
  823. {
  824. u32 i;
  825. u32 tmp;
  826. struct b43legacy_plcp_hdr4 plcp;
  827. plcp.data = 0;
  828. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  829. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  830. ram_offset += sizeof(u32);
  831. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  832. * So leave the first two bytes of the next write blank.
  833. */
  834. tmp = (u32)(data[0]) << 16;
  835. tmp |= (u32)(data[1]) << 24;
  836. b43legacy_ram_write(dev, ram_offset, tmp);
  837. ram_offset += sizeof(u32);
  838. for (i = 2; i < size; i += sizeof(u32)) {
  839. tmp = (u32)(data[i + 0]);
  840. if (i + 1 < size)
  841. tmp |= (u32)(data[i + 1]) << 8;
  842. if (i + 2 < size)
  843. tmp |= (u32)(data[i + 2]) << 16;
  844. if (i + 3 < size)
  845. tmp |= (u32)(data[i + 3]) << 24;
  846. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  847. }
  848. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  849. size + sizeof(struct b43legacy_plcp_hdr6));
  850. }
  851. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  852. u16 ram_offset,
  853. u16 shm_size_offset, u8 rate)
  854. {
  855. int len;
  856. const u8 *data;
  857. B43legacy_WARN_ON(!dev->cached_beacon);
  858. len = min((size_t)dev->cached_beacon->len,
  859. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  860. data = (const u8 *)(dev->cached_beacon->data);
  861. b43legacy_write_template_common(dev, data,
  862. len, ram_offset,
  863. shm_size_offset, rate);
  864. }
  865. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  866. u16 shm_offset, u16 size,
  867. u8 rate)
  868. {
  869. struct b43legacy_plcp_hdr4 plcp;
  870. u32 tmp;
  871. __le16 dur;
  872. plcp.data = 0;
  873. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  874. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  875. dev->wl->if_id,
  876. size,
  877. B43legacy_RATE_TO_100KBPS(rate));
  878. /* Write PLCP in two parts and timing for packet transfer */
  879. tmp = le32_to_cpu(plcp.data);
  880. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  881. tmp & 0xFFFF);
  882. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  883. tmp >> 16);
  884. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  885. le16_to_cpu(dur));
  886. }
  887. /* Instead of using custom probe response template, this function
  888. * just patches custom beacon template by:
  889. * 1) Changing packet type
  890. * 2) Patching duration field
  891. * 3) Stripping TIM
  892. */
  893. static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  894. u16 *dest_size, u8 rate)
  895. {
  896. const u8 *src_data;
  897. u8 *dest_data;
  898. u16 src_size;
  899. u16 elem_size;
  900. u16 src_pos;
  901. u16 dest_pos;
  902. __le16 dur;
  903. struct ieee80211_hdr *hdr;
  904. B43legacy_WARN_ON(!dev->cached_beacon);
  905. src_size = dev->cached_beacon->len;
  906. src_data = (const u8 *)dev->cached_beacon->data;
  907. if (unlikely(src_size < 0x24)) {
  908. b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
  909. "invalid beacon\n");
  910. return NULL;
  911. }
  912. dest_data = kmalloc(src_size, GFP_ATOMIC);
  913. if (unlikely(!dest_data))
  914. return NULL;
  915. /* 0x24 is offset of first variable-len Information-Element
  916. * in beacon frame.
  917. */
  918. memcpy(dest_data, src_data, 0x24);
  919. src_pos = 0x24;
  920. dest_pos = 0x24;
  921. for (; src_pos < src_size - 2; src_pos += elem_size) {
  922. elem_size = src_data[src_pos + 1] + 2;
  923. if (src_data[src_pos] != 0x05) { /* TIM */
  924. memcpy(dest_data + dest_pos, src_data + src_pos,
  925. elem_size);
  926. dest_pos += elem_size;
  927. }
  928. }
  929. *dest_size = dest_pos;
  930. hdr = (struct ieee80211_hdr *)dest_data;
  931. /* Set the frame control. */
  932. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  933. IEEE80211_STYPE_PROBE_RESP);
  934. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  935. dev->wl->if_id,
  936. *dest_size,
  937. B43legacy_RATE_TO_100KBPS(rate));
  938. hdr->duration_id = dur;
  939. return dest_data;
  940. }
  941. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  942. u16 ram_offset,
  943. u16 shm_size_offset, u8 rate)
  944. {
  945. u8 *probe_resp_data;
  946. u16 size;
  947. B43legacy_WARN_ON(!dev->cached_beacon);
  948. size = dev->cached_beacon->len;
  949. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  950. if (unlikely(!probe_resp_data))
  951. return;
  952. /* Looks like PLCP headers plus packet timings are stored for
  953. * all possible basic rates
  954. */
  955. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  956. B43legacy_CCK_RATE_1MB);
  957. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  958. B43legacy_CCK_RATE_2MB);
  959. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  960. B43legacy_CCK_RATE_5MB);
  961. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  962. B43legacy_CCK_RATE_11MB);
  963. size = min((size_t)size,
  964. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  965. b43legacy_write_template_common(dev, probe_resp_data,
  966. size, ram_offset,
  967. shm_size_offset, rate);
  968. kfree(probe_resp_data);
  969. }
  970. static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
  971. struct sk_buff *beacon)
  972. {
  973. if (dev->cached_beacon)
  974. kfree_skb(dev->cached_beacon);
  975. dev->cached_beacon = beacon;
  976. return 0;
  977. }
  978. static void b43legacy_update_templates(struct b43legacy_wldev *dev)
  979. {
  980. u32 status;
  981. B43legacy_WARN_ON(!dev->cached_beacon);
  982. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  983. B43legacy_CCK_RATE_1MB);
  984. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  985. B43legacy_CCK_RATE_1MB);
  986. b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
  987. B43legacy_CCK_RATE_11MB);
  988. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  989. status |= 0x03;
  990. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD, status);
  991. }
  992. static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
  993. struct sk_buff *beacon)
  994. {
  995. int err;
  996. err = b43legacy_refresh_cached_beacon(dev, beacon);
  997. if (unlikely(err))
  998. return;
  999. b43legacy_update_templates(dev);
  1000. }
  1001. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  1002. const u8 *ssid, u8 ssid_len)
  1003. {
  1004. u32 tmp;
  1005. u16 i;
  1006. u16 len;
  1007. len = min((u16)ssid_len, (u16)0x100);
  1008. for (i = 0; i < len; i += sizeof(u32)) {
  1009. tmp = (u32)(ssid[i + 0]);
  1010. if (i + 1 < len)
  1011. tmp |= (u32)(ssid[i + 1]) << 8;
  1012. if (i + 2 < len)
  1013. tmp |= (u32)(ssid[i + 2]) << 16;
  1014. if (i + 3 < len)
  1015. tmp |= (u32)(ssid[i + 3]) << 24;
  1016. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1017. 0x380 + i, tmp);
  1018. }
  1019. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1020. 0x48, len);
  1021. }
  1022. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1023. u16 beacon_int)
  1024. {
  1025. b43legacy_time_lock(dev);
  1026. if (dev->dev->id.revision >= 3)
  1027. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1028. else {
  1029. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1030. b43legacy_write16(dev, 0x610, beacon_int);
  1031. }
  1032. b43legacy_time_unlock(dev);
  1033. }
  1034. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1035. {
  1036. u32 status;
  1037. if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  1038. return;
  1039. dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
  1040. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  1041. if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
  1042. /* ACK beacon IRQ. */
  1043. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1044. B43legacy_IRQ_BEACON);
  1045. dev->irq_savedstate |= B43legacy_IRQ_BEACON;
  1046. if (dev->cached_beacon)
  1047. kfree_skb(dev->cached_beacon);
  1048. dev->cached_beacon = NULL;
  1049. return;
  1050. }
  1051. if (!(status & 0x1)) {
  1052. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  1053. B43legacy_CCK_RATE_1MB);
  1054. status |= 0x1;
  1055. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1056. status);
  1057. }
  1058. if (!(status & 0x2)) {
  1059. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  1060. B43legacy_CCK_RATE_1MB);
  1061. status |= 0x2;
  1062. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1063. status);
  1064. }
  1065. }
  1066. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1067. {
  1068. }
  1069. /* Interrupt handler bottom-half */
  1070. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1071. {
  1072. u32 reason;
  1073. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1074. u32 merged_dma_reason = 0;
  1075. int i;
  1076. int activity = 0;
  1077. unsigned long flags;
  1078. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1079. B43legacy_WARN_ON(b43legacy_status(dev) <
  1080. B43legacy_STAT_INITIALIZED);
  1081. reason = dev->irq_reason;
  1082. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1083. dma_reason[i] = dev->dma_reason[i];
  1084. merged_dma_reason |= dma_reason[i];
  1085. }
  1086. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1087. b43legacyerr(dev->wl, "MAC transmission error\n");
  1088. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR))
  1089. b43legacyerr(dev->wl, "PHY transmission error\n");
  1090. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1091. B43legacy_DMAIRQ_NONFATALMASK))) {
  1092. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1093. b43legacyerr(dev->wl, "Fatal DMA error: "
  1094. "0x%08X, 0x%08X, 0x%08X, "
  1095. "0x%08X, 0x%08X, 0x%08X\n",
  1096. dma_reason[0], dma_reason[1],
  1097. dma_reason[2], dma_reason[3],
  1098. dma_reason[4], dma_reason[5]);
  1099. b43legacy_controller_restart(dev, "DMA error");
  1100. mmiowb();
  1101. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1102. return;
  1103. }
  1104. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1105. b43legacyerr(dev->wl, "DMA error: "
  1106. "0x%08X, 0x%08X, 0x%08X, "
  1107. "0x%08X, 0x%08X, 0x%08X\n",
  1108. dma_reason[0], dma_reason[1],
  1109. dma_reason[2], dma_reason[3],
  1110. dma_reason[4], dma_reason[5]);
  1111. }
  1112. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1113. handle_irq_ucode_debug(dev);
  1114. if (reason & B43legacy_IRQ_TBTT_INDI)
  1115. handle_irq_tbtt_indication(dev);
  1116. if (reason & B43legacy_IRQ_ATIM_END)
  1117. handle_irq_atim_end(dev);
  1118. if (reason & B43legacy_IRQ_BEACON)
  1119. handle_irq_beacon(dev);
  1120. if (reason & B43legacy_IRQ_PMQ)
  1121. handle_irq_pmq(dev);
  1122. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1123. ;/*TODO*/
  1124. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1125. handle_irq_noise(dev);
  1126. /* Check the DMA reason registers for received data. */
  1127. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1128. if (b43legacy_using_pio(dev))
  1129. b43legacy_pio_rx(dev->pio.queue0);
  1130. else
  1131. b43legacy_dma_rx(dev->dma.rx_ring0);
  1132. /* We intentionally don't set "activity" to 1, here. */
  1133. }
  1134. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1135. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1136. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1137. if (b43legacy_using_pio(dev))
  1138. b43legacy_pio_rx(dev->pio.queue3);
  1139. else
  1140. b43legacy_dma_rx(dev->dma.rx_ring3);
  1141. activity = 1;
  1142. }
  1143. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1144. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1145. if (reason & B43legacy_IRQ_TX_OK) {
  1146. handle_irq_transmit_status(dev);
  1147. activity = 1;
  1148. /* TODO: In AP mode, this also causes sending of powersave
  1149. responses. */
  1150. }
  1151. if (!modparam_noleds)
  1152. b43legacy_leds_update(dev, activity);
  1153. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1154. mmiowb();
  1155. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1156. }
  1157. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1158. u16 base, int queueidx)
  1159. {
  1160. u16 rxctl;
  1161. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1162. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1163. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1164. else
  1165. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1166. }
  1167. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1168. {
  1169. if (b43legacy_using_pio(dev) &&
  1170. (dev->dev->id.revision < 3) &&
  1171. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1172. /* Apply a PIO specific workaround to the dma_reasons */
  1173. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1174. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1175. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1176. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1177. }
  1178. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1179. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1180. dev->dma_reason[0]);
  1181. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1182. dev->dma_reason[1]);
  1183. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1184. dev->dma_reason[2]);
  1185. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1186. dev->dma_reason[3]);
  1187. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1188. dev->dma_reason[4]);
  1189. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1190. dev->dma_reason[5]);
  1191. }
  1192. /* Interrupt handler top-half */
  1193. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1194. {
  1195. irqreturn_t ret = IRQ_NONE;
  1196. struct b43legacy_wldev *dev = dev_id;
  1197. u32 reason;
  1198. if (!dev)
  1199. return IRQ_NONE;
  1200. spin_lock(&dev->wl->irq_lock);
  1201. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1202. goto out;
  1203. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1204. if (reason == 0xffffffff) /* shared IRQ */
  1205. goto out;
  1206. ret = IRQ_HANDLED;
  1207. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1208. if (!reason)
  1209. goto out;
  1210. dev->dma_reason[0] = b43legacy_read32(dev,
  1211. B43legacy_MMIO_DMA0_REASON)
  1212. & 0x0001DC00;
  1213. dev->dma_reason[1] = b43legacy_read32(dev,
  1214. B43legacy_MMIO_DMA1_REASON)
  1215. & 0x0000DC00;
  1216. dev->dma_reason[2] = b43legacy_read32(dev,
  1217. B43legacy_MMIO_DMA2_REASON)
  1218. & 0x0000DC00;
  1219. dev->dma_reason[3] = b43legacy_read32(dev,
  1220. B43legacy_MMIO_DMA3_REASON)
  1221. & 0x0001DC00;
  1222. dev->dma_reason[4] = b43legacy_read32(dev,
  1223. B43legacy_MMIO_DMA4_REASON)
  1224. & 0x0000DC00;
  1225. dev->dma_reason[5] = b43legacy_read32(dev,
  1226. B43legacy_MMIO_DMA5_REASON)
  1227. & 0x0000DC00;
  1228. b43legacy_interrupt_ack(dev, reason);
  1229. /* disable all IRQs. They are enabled again in the bottom half. */
  1230. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1231. B43legacy_IRQ_ALL);
  1232. /* save the reason code and call our bottom half. */
  1233. dev->irq_reason = reason;
  1234. tasklet_schedule(&dev->isr_tasklet);
  1235. out:
  1236. mmiowb();
  1237. spin_unlock(&dev->wl->irq_lock);
  1238. return ret;
  1239. }
  1240. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1241. {
  1242. release_firmware(dev->fw.ucode);
  1243. dev->fw.ucode = NULL;
  1244. release_firmware(dev->fw.pcm);
  1245. dev->fw.pcm = NULL;
  1246. release_firmware(dev->fw.initvals);
  1247. dev->fw.initvals = NULL;
  1248. release_firmware(dev->fw.initvals_band);
  1249. dev->fw.initvals_band = NULL;
  1250. }
  1251. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1252. {
  1253. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1254. "Drivers/bcm43xx#devicefirmware "
  1255. "and download the correct firmware (version 3).\n");
  1256. }
  1257. static int do_request_fw(struct b43legacy_wldev *dev,
  1258. const char *name,
  1259. const struct firmware **fw)
  1260. {
  1261. char path[sizeof(modparam_fwpostfix) + 32];
  1262. struct b43legacy_fw_header *hdr;
  1263. u32 size;
  1264. int err;
  1265. if (!name)
  1266. return 0;
  1267. snprintf(path, ARRAY_SIZE(path),
  1268. "b43legacy%s/%s.fw",
  1269. modparam_fwpostfix, name);
  1270. err = request_firmware(fw, path, dev->dev->dev);
  1271. if (err) {
  1272. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1273. "or load failed.\n", path);
  1274. return err;
  1275. }
  1276. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1277. goto err_format;
  1278. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1279. switch (hdr->type) {
  1280. case B43legacy_FW_TYPE_UCODE:
  1281. case B43legacy_FW_TYPE_PCM:
  1282. size = be32_to_cpu(hdr->size);
  1283. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1284. goto err_format;
  1285. /* fallthrough */
  1286. case B43legacy_FW_TYPE_IV:
  1287. if (hdr->ver != 1)
  1288. goto err_format;
  1289. break;
  1290. default:
  1291. goto err_format;
  1292. }
  1293. return err;
  1294. err_format:
  1295. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1296. return -EPROTO;
  1297. }
  1298. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1299. {
  1300. struct b43legacy_firmware *fw = &dev->fw;
  1301. const u8 rev = dev->dev->id.revision;
  1302. const char *filename;
  1303. u32 tmshigh;
  1304. int err;
  1305. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1306. if (!fw->ucode) {
  1307. if (rev == 2)
  1308. filename = "ucode2";
  1309. else if (rev == 4)
  1310. filename = "ucode4";
  1311. else
  1312. filename = "ucode5";
  1313. err = do_request_fw(dev, filename, &fw->ucode);
  1314. if (err)
  1315. goto err_load;
  1316. }
  1317. if (!fw->pcm) {
  1318. if (rev < 5)
  1319. filename = "pcm4";
  1320. else
  1321. filename = "pcm5";
  1322. err = do_request_fw(dev, filename, &fw->pcm);
  1323. if (err)
  1324. goto err_load;
  1325. }
  1326. if (!fw->initvals) {
  1327. switch (dev->phy.type) {
  1328. case B43legacy_PHYTYPE_G:
  1329. if ((rev >= 5) && (rev <= 10))
  1330. filename = "b0g0initvals5";
  1331. else if (rev == 2 || rev == 4)
  1332. filename = "b0g0initvals2";
  1333. else
  1334. goto err_no_initvals;
  1335. break;
  1336. default:
  1337. goto err_no_initvals;
  1338. }
  1339. err = do_request_fw(dev, filename, &fw->initvals);
  1340. if (err)
  1341. goto err_load;
  1342. }
  1343. if (!fw->initvals_band) {
  1344. switch (dev->phy.type) {
  1345. case B43legacy_PHYTYPE_G:
  1346. if ((rev >= 5) && (rev <= 10))
  1347. filename = "b0g0bsinitvals5";
  1348. else if (rev >= 11)
  1349. filename = NULL;
  1350. else if (rev == 2 || rev == 4)
  1351. filename = NULL;
  1352. else
  1353. goto err_no_initvals;
  1354. break;
  1355. default:
  1356. goto err_no_initvals;
  1357. }
  1358. err = do_request_fw(dev, filename, &fw->initvals_band);
  1359. if (err)
  1360. goto err_load;
  1361. }
  1362. return 0;
  1363. err_load:
  1364. b43legacy_print_fw_helptext(dev->wl);
  1365. goto error;
  1366. err_no_initvals:
  1367. err = -ENODEV;
  1368. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1369. "core rev %u\n", dev->phy.type, rev);
  1370. goto error;
  1371. error:
  1372. b43legacy_release_firmware(dev);
  1373. return err;
  1374. }
  1375. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1376. {
  1377. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1378. const __be32 *data;
  1379. unsigned int i;
  1380. unsigned int len;
  1381. u16 fwrev;
  1382. u16 fwpatch;
  1383. u16 fwdate;
  1384. u16 fwtime;
  1385. u32 tmp;
  1386. int err = 0;
  1387. /* Upload Microcode. */
  1388. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1389. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1390. b43legacy_shm_control_word(dev,
  1391. B43legacy_SHM_UCODE |
  1392. B43legacy_SHM_AUTOINC_W,
  1393. 0x0000);
  1394. for (i = 0; i < len; i++) {
  1395. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1396. be32_to_cpu(data[i]));
  1397. udelay(10);
  1398. }
  1399. if (dev->fw.pcm) {
  1400. /* Upload PCM data. */
  1401. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1402. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1403. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1404. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1405. /* No need for autoinc bit in SHM_HW */
  1406. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1407. for (i = 0; i < len; i++) {
  1408. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1409. be32_to_cpu(data[i]));
  1410. udelay(10);
  1411. }
  1412. }
  1413. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1414. B43legacy_IRQ_ALL);
  1415. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0x00020402);
  1416. /* Wait for the microcode to load and respond */
  1417. i = 0;
  1418. while (1) {
  1419. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1420. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1421. break;
  1422. i++;
  1423. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1424. b43legacyerr(dev->wl, "Microcode not responding\n");
  1425. b43legacy_print_fw_helptext(dev->wl);
  1426. err = -ENODEV;
  1427. goto out;
  1428. }
  1429. udelay(10);
  1430. }
  1431. /* dummy read follows */
  1432. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1433. /* Get and check the revisions. */
  1434. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1435. B43legacy_SHM_SH_UCODEREV);
  1436. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1437. B43legacy_SHM_SH_UCODEPATCH);
  1438. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1439. B43legacy_SHM_SH_UCODEDATE);
  1440. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1441. B43legacy_SHM_SH_UCODETIME);
  1442. if (fwrev > 0x128) {
  1443. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1444. " Only firmware from binary drivers version 3.x"
  1445. " is supported. You must change your firmware"
  1446. " files.\n");
  1447. b43legacy_print_fw_helptext(dev->wl);
  1448. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0);
  1449. err = -EOPNOTSUPP;
  1450. goto out;
  1451. }
  1452. b43legacydbg(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1453. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1454. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1455. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  1456. dev->fw.rev = fwrev;
  1457. dev->fw.patch = fwpatch;
  1458. out:
  1459. return err;
  1460. }
  1461. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1462. const struct b43legacy_iv *ivals,
  1463. size_t count,
  1464. size_t array_size)
  1465. {
  1466. const struct b43legacy_iv *iv;
  1467. u16 offset;
  1468. size_t i;
  1469. bool bit32;
  1470. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1471. iv = ivals;
  1472. for (i = 0; i < count; i++) {
  1473. if (array_size < sizeof(iv->offset_size))
  1474. goto err_format;
  1475. array_size -= sizeof(iv->offset_size);
  1476. offset = be16_to_cpu(iv->offset_size);
  1477. bit32 = !!(offset & B43legacy_IV_32BIT);
  1478. offset &= B43legacy_IV_OFFSET_MASK;
  1479. if (offset >= 0x1000)
  1480. goto err_format;
  1481. if (bit32) {
  1482. u32 value;
  1483. if (array_size < sizeof(iv->data.d32))
  1484. goto err_format;
  1485. array_size -= sizeof(iv->data.d32);
  1486. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1487. b43legacy_write32(dev, offset, value);
  1488. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1489. sizeof(__be16) +
  1490. sizeof(__be32));
  1491. } else {
  1492. u16 value;
  1493. if (array_size < sizeof(iv->data.d16))
  1494. goto err_format;
  1495. array_size -= sizeof(iv->data.d16);
  1496. value = be16_to_cpu(iv->data.d16);
  1497. b43legacy_write16(dev, offset, value);
  1498. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1499. sizeof(__be16) +
  1500. sizeof(__be16));
  1501. }
  1502. }
  1503. if (array_size)
  1504. goto err_format;
  1505. return 0;
  1506. err_format:
  1507. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1508. b43legacy_print_fw_helptext(dev->wl);
  1509. return -EPROTO;
  1510. }
  1511. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1512. {
  1513. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1514. const struct b43legacy_fw_header *hdr;
  1515. struct b43legacy_firmware *fw = &dev->fw;
  1516. const struct b43legacy_iv *ivals;
  1517. size_t count;
  1518. int err;
  1519. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1520. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1521. count = be32_to_cpu(hdr->size);
  1522. err = b43legacy_write_initvals(dev, ivals, count,
  1523. fw->initvals->size - hdr_len);
  1524. if (err)
  1525. goto out;
  1526. if (fw->initvals_band) {
  1527. hdr = (const struct b43legacy_fw_header *)
  1528. (fw->initvals_band->data);
  1529. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1530. + hdr_len);
  1531. count = be32_to_cpu(hdr->size);
  1532. err = b43legacy_write_initvals(dev, ivals, count,
  1533. fw->initvals_band->size - hdr_len);
  1534. if (err)
  1535. goto out;
  1536. }
  1537. out:
  1538. return err;
  1539. }
  1540. /* Initialize the GPIOs
  1541. * http://bcm-specs.sipsolutions.net/GPIO
  1542. */
  1543. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1544. {
  1545. struct ssb_bus *bus = dev->dev->bus;
  1546. struct ssb_device *gpiodev, *pcidev = NULL;
  1547. u32 mask;
  1548. u32 set;
  1549. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1550. b43legacy_read32(dev,
  1551. B43legacy_MMIO_STATUS_BITFIELD)
  1552. & 0xFFFF3FFF);
  1553. b43legacy_leds_switch_all(dev, 0);
  1554. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1555. b43legacy_read16(dev,
  1556. B43legacy_MMIO_GPIO_MASK)
  1557. | 0x000F);
  1558. mask = 0x0000001F;
  1559. set = 0x0000000F;
  1560. if (dev->dev->bus->chip_id == 0x4301) {
  1561. mask |= 0x0060;
  1562. set |= 0x0060;
  1563. }
  1564. if (dev->dev->bus->sprom.r1.boardflags_lo & B43legacy_BFL_PACTRL) {
  1565. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1566. b43legacy_read16(dev,
  1567. B43legacy_MMIO_GPIO_MASK)
  1568. | 0x0200);
  1569. mask |= 0x0200;
  1570. set |= 0x0200;
  1571. }
  1572. if (dev->dev->id.revision >= 2)
  1573. mask |= 0x0010; /* FIXME: This is redundant. */
  1574. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1575. pcidev = bus->pcicore.dev;
  1576. #endif
  1577. gpiodev = bus->chipco.dev ? : pcidev;
  1578. if (!gpiodev)
  1579. return 0;
  1580. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1581. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1582. & mask) | set);
  1583. return 0;
  1584. }
  1585. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1586. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1587. {
  1588. struct ssb_bus *bus = dev->dev->bus;
  1589. struct ssb_device *gpiodev, *pcidev = NULL;
  1590. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1591. pcidev = bus->pcicore.dev;
  1592. #endif
  1593. gpiodev = bus->chipco.dev ? : pcidev;
  1594. if (!gpiodev)
  1595. return;
  1596. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1597. }
  1598. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1599. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1600. {
  1601. dev->mac_suspended--;
  1602. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1603. if (dev->mac_suspended == 0) {
  1604. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1605. b43legacy_read32(dev,
  1606. B43legacy_MMIO_STATUS_BITFIELD)
  1607. | B43legacy_SBF_MAC_ENABLED);
  1608. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1609. B43legacy_IRQ_MAC_SUSPENDED);
  1610. /* the next two are dummy reads */
  1611. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1612. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1613. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1614. }
  1615. }
  1616. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1617. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1618. {
  1619. int i;
  1620. u32 tmp;
  1621. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1622. if (dev->mac_suspended == 0) {
  1623. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1624. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1625. b43legacy_read32(dev,
  1626. B43legacy_MMIO_STATUS_BITFIELD)
  1627. & ~B43legacy_SBF_MAC_ENABLED);
  1628. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1629. for (i = 10000; i; i--) {
  1630. tmp = b43legacy_read32(dev,
  1631. B43legacy_MMIO_GEN_IRQ_REASON);
  1632. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1633. goto out;
  1634. udelay(1);
  1635. }
  1636. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1637. }
  1638. out:
  1639. dev->mac_suspended++;
  1640. }
  1641. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1642. {
  1643. struct b43legacy_wl *wl = dev->wl;
  1644. u32 ctl;
  1645. u16 cfp_pretbtt;
  1646. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1647. /* Reset status to STA infrastructure mode. */
  1648. ctl &= ~B43legacy_MACCTL_AP;
  1649. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1650. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1651. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1652. ctl &= ~B43legacy_MACCTL_PROMISC;
  1653. ctl |= B43legacy_MACCTL_INFRA;
  1654. if (wl->operating) {
  1655. switch (wl->if_type) {
  1656. case IEEE80211_IF_TYPE_AP:
  1657. ctl |= B43legacy_MACCTL_AP;
  1658. break;
  1659. case IEEE80211_IF_TYPE_IBSS:
  1660. ctl &= ~B43legacy_MACCTL_INFRA;
  1661. break;
  1662. case IEEE80211_IF_TYPE_STA:
  1663. case IEEE80211_IF_TYPE_MNTR:
  1664. case IEEE80211_IF_TYPE_WDS:
  1665. break;
  1666. default:
  1667. b43legacyerr(wl, "Improper value of %d for"
  1668. " wl->if_type\n", wl->if_type);
  1669. }
  1670. }
  1671. if (wl->monitor) {
  1672. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1673. if (modparam_mon_keep_bad)
  1674. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1675. if (modparam_mon_keep_badplcp)
  1676. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1677. }
  1678. if (wl->promisc)
  1679. ctl |= B43legacy_MACCTL_PROMISC;
  1680. /* Workaround: On old hardware the HW-MAC-address-filter
  1681. * doesn't work properly, so always run promisc in filter
  1682. * it in software. */
  1683. if (dev->dev->id.revision <= 4)
  1684. ctl |= B43legacy_MACCTL_PROMISC;
  1685. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1686. cfp_pretbtt = 2;
  1687. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1688. !(ctl & B43legacy_MACCTL_AP)) {
  1689. if (dev->dev->bus->chip_id == 0x4306 &&
  1690. dev->dev->bus->chip_rev == 3)
  1691. cfp_pretbtt = 100;
  1692. else
  1693. cfp_pretbtt = 50;
  1694. }
  1695. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1696. }
  1697. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1698. u16 rate,
  1699. int is_ofdm)
  1700. {
  1701. u16 offset;
  1702. if (is_ofdm) {
  1703. offset = 0x480;
  1704. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1705. } else {
  1706. offset = 0x4C0;
  1707. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1708. }
  1709. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1710. b43legacy_shm_read16(dev,
  1711. B43legacy_SHM_SHARED, offset));
  1712. }
  1713. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1714. {
  1715. switch (dev->phy.type) {
  1716. case B43legacy_PHYTYPE_G:
  1717. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1718. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1719. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1720. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1721. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1722. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1723. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1724. /* fallthrough */
  1725. case B43legacy_PHYTYPE_B:
  1726. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1727. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1728. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1729. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1730. break;
  1731. default:
  1732. B43legacy_BUG_ON(1);
  1733. }
  1734. }
  1735. /* Set the TX-Antenna for management frames sent by firmware. */
  1736. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1737. int antenna)
  1738. {
  1739. u16 ant = 0;
  1740. u16 tmp;
  1741. switch (antenna) {
  1742. case B43legacy_ANTENNA0:
  1743. ant |= B43legacy_TX4_PHY_ANT0;
  1744. break;
  1745. case B43legacy_ANTENNA1:
  1746. ant |= B43legacy_TX4_PHY_ANT1;
  1747. break;
  1748. case B43legacy_ANTENNA_AUTO:
  1749. ant |= B43legacy_TX4_PHY_ANTLAST;
  1750. break;
  1751. default:
  1752. B43legacy_BUG_ON(1);
  1753. }
  1754. /* FIXME We also need to set the other flags of the PHY control
  1755. * field somewhere. */
  1756. /* For Beacons */
  1757. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1758. B43legacy_SHM_SH_BEACPHYCTL);
  1759. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1760. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1761. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1762. /* For ACK/CTS */
  1763. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1764. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1765. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1766. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1767. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1768. /* For Probe Resposes */
  1769. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1770. B43legacy_SHM_SH_PRPHYCTL);
  1771. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1772. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1773. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1774. }
  1775. /* Returns TRUE, if the radio is enabled in hardware. */
  1776. static bool b43legacy_is_hw_radio_enabled(struct b43legacy_wldev *dev)
  1777. {
  1778. if (dev->phy.rev >= 3) {
  1779. if (!(b43legacy_read32(dev, B43legacy_MMIO_RADIO_HWENABLED_HI)
  1780. & B43legacy_MMIO_RADIO_HWENABLED_HI_MASK))
  1781. return 1;
  1782. } else {
  1783. if (b43legacy_read16(dev, B43legacy_MMIO_RADIO_HWENABLED_LO)
  1784. & B43legacy_MMIO_RADIO_HWENABLED_LO_MASK)
  1785. return 1;
  1786. }
  1787. return 0;
  1788. }
  1789. /* This is the opposite of b43legacy_chip_init() */
  1790. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1791. {
  1792. b43legacy_radio_turn_off(dev);
  1793. if (!modparam_noleds)
  1794. b43legacy_leds_exit(dev);
  1795. b43legacy_gpio_cleanup(dev);
  1796. /* firmware is released later */
  1797. }
  1798. /* Initialize the chip
  1799. * http://bcm-specs.sipsolutions.net/ChipInit
  1800. */
  1801. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1802. {
  1803. struct b43legacy_phy *phy = &dev->phy;
  1804. int err;
  1805. int tmp;
  1806. u32 value32;
  1807. u16 value16;
  1808. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1809. B43legacy_SBF_CORE_READY
  1810. | B43legacy_SBF_400);
  1811. err = b43legacy_request_firmware(dev);
  1812. if (err)
  1813. goto out;
  1814. err = b43legacy_upload_microcode(dev);
  1815. if (err)
  1816. goto out; /* firmware is released later */
  1817. err = b43legacy_gpio_init(dev);
  1818. if (err)
  1819. goto out; /* firmware is released later */
  1820. err = b43legacy_upload_initvals(dev);
  1821. if (err)
  1822. goto err_gpio_cleanup;
  1823. b43legacy_radio_turn_on(dev);
  1824. b43legacy_write16(dev, 0x03E6, 0x0000);
  1825. err = b43legacy_phy_init(dev);
  1826. if (err)
  1827. goto err_radio_off;
  1828. /* Select initial Interference Mitigation. */
  1829. tmp = phy->interfmode;
  1830. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1831. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1832. b43legacy_phy_set_antenna_diversity(dev);
  1833. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1834. if (phy->type == B43legacy_PHYTYPE_B) {
  1835. value16 = b43legacy_read16(dev, 0x005E);
  1836. value16 |= 0x0004;
  1837. b43legacy_write16(dev, 0x005E, value16);
  1838. }
  1839. b43legacy_write32(dev, 0x0100, 0x01000000);
  1840. if (dev->dev->id.revision < 5)
  1841. b43legacy_write32(dev, 0x010C, 0x01000000);
  1842. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1843. value32 &= ~B43legacy_SBF_MODE_NOTADHOC;
  1844. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1845. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1846. value32 |= B43legacy_SBF_MODE_NOTADHOC;
  1847. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1848. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1849. value32 |= 0x100000;
  1850. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1851. if (b43legacy_using_pio(dev)) {
  1852. b43legacy_write32(dev, 0x0210, 0x00000100);
  1853. b43legacy_write32(dev, 0x0230, 0x00000100);
  1854. b43legacy_write32(dev, 0x0250, 0x00000100);
  1855. b43legacy_write32(dev, 0x0270, 0x00000100);
  1856. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1857. 0x0000);
  1858. }
  1859. /* Probe Response Timeout value */
  1860. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1861. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1862. /* Initially set the wireless operation mode. */
  1863. b43legacy_adjust_opmode(dev);
  1864. if (dev->dev->id.revision < 3) {
  1865. b43legacy_write16(dev, 0x060E, 0x0000);
  1866. b43legacy_write16(dev, 0x0610, 0x8000);
  1867. b43legacy_write16(dev, 0x0604, 0x0000);
  1868. b43legacy_write16(dev, 0x0606, 0x0200);
  1869. } else {
  1870. b43legacy_write32(dev, 0x0188, 0x80000000);
  1871. b43legacy_write32(dev, 0x018C, 0x02000000);
  1872. }
  1873. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1874. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1875. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1876. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1877. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1878. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1879. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1880. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1881. value32 |= 0x00100000;
  1882. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1883. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1884. dev->dev->bus->chipco.fast_pwrup_delay);
  1885. B43legacy_WARN_ON(err != 0);
  1886. b43legacydbg(dev->wl, "Chip initialized\n");
  1887. out:
  1888. return err;
  1889. err_radio_off:
  1890. b43legacy_radio_turn_off(dev);
  1891. err_gpio_cleanup:
  1892. b43legacy_gpio_cleanup(dev);
  1893. goto out;
  1894. }
  1895. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1896. {
  1897. struct b43legacy_phy *phy = &dev->phy;
  1898. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1899. return;
  1900. b43legacy_mac_suspend(dev);
  1901. b43legacy_phy_lo_g_measure(dev);
  1902. b43legacy_mac_enable(dev);
  1903. }
  1904. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1905. {
  1906. b43legacy_phy_lo_mark_all_unused(dev);
  1907. if (dev->dev->bus->sprom.r1.boardflags_lo & B43legacy_BFL_RSSI) {
  1908. b43legacy_mac_suspend(dev);
  1909. b43legacy_calc_nrssi_slope(dev);
  1910. b43legacy_mac_enable(dev);
  1911. }
  1912. }
  1913. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1914. {
  1915. /* Update device statistics. */
  1916. b43legacy_calculate_link_quality(dev);
  1917. }
  1918. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1919. {
  1920. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1921. }
  1922. static void b43legacy_periodic_every1sec(struct b43legacy_wldev *dev)
  1923. {
  1924. bool radio_hw_enable;
  1925. /* check if radio hardware enabled status changed */
  1926. radio_hw_enable = b43legacy_is_hw_radio_enabled(dev);
  1927. if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
  1928. dev->radio_hw_enable = radio_hw_enable;
  1929. b43legacyinfo(dev->wl, "Radio hardware status changed to %s\n",
  1930. (radio_hw_enable) ? "enabled" : "disabled");
  1931. b43legacy_leds_update(dev, 0);
  1932. }
  1933. }
  1934. static void do_periodic_work(struct b43legacy_wldev *dev)
  1935. {
  1936. unsigned int state;
  1937. state = dev->periodic_state;
  1938. if (state % 120 == 0)
  1939. b43legacy_periodic_every120sec(dev);
  1940. if (state % 60 == 0)
  1941. b43legacy_periodic_every60sec(dev);
  1942. if (state % 30 == 0)
  1943. b43legacy_periodic_every30sec(dev);
  1944. if (state % 15 == 0)
  1945. b43legacy_periodic_every15sec(dev);
  1946. b43legacy_periodic_every1sec(dev);
  1947. }
  1948. /* Estimate a "Badness" value based on the periodic work
  1949. * state-machine state. "Badness" is worse (bigger), if the
  1950. * periodic work will take longer.
  1951. */
  1952. static int estimate_periodic_work_badness(unsigned int state)
  1953. {
  1954. int badness = 0;
  1955. if (state % 120 == 0) /* every 120 sec */
  1956. badness += 10;
  1957. if (state % 60 == 0) /* every 60 sec */
  1958. badness += 5;
  1959. if (state % 30 == 0) /* every 30 sec */
  1960. badness += 1;
  1961. if (state % 15 == 0) /* every 15 sec */
  1962. badness += 1;
  1963. #define BADNESS_LIMIT 4
  1964. return badness;
  1965. }
  1966. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1967. {
  1968. struct b43legacy_wldev *dev =
  1969. container_of(work, struct b43legacy_wldev,
  1970. periodic_work.work);
  1971. unsigned long flags;
  1972. unsigned long delay;
  1973. u32 savedirqs = 0;
  1974. int badness;
  1975. mutex_lock(&dev->wl->mutex);
  1976. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1977. goto out;
  1978. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1979. goto out_requeue;
  1980. badness = estimate_periodic_work_badness(dev->periodic_state);
  1981. if (badness > BADNESS_LIMIT) {
  1982. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1983. /* Suspend TX as we don't want to transmit packets while
  1984. * we recalibrate the hardware. */
  1985. b43legacy_tx_suspend(dev);
  1986. savedirqs = b43legacy_interrupt_disable(dev,
  1987. B43legacy_IRQ_ALL);
  1988. /* Periodic work will take a long time, so we want it to
  1989. * be preemtible and release the spinlock. */
  1990. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1991. b43legacy_synchronize_irq(dev);
  1992. do_periodic_work(dev);
  1993. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1994. b43legacy_interrupt_enable(dev, savedirqs);
  1995. b43legacy_tx_resume(dev);
  1996. mmiowb();
  1997. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1998. } else {
  1999. /* Take the global driver lock. This will lock any operation. */
  2000. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  2001. do_periodic_work(dev);
  2002. mmiowb();
  2003. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  2004. }
  2005. dev->periodic_state++;
  2006. out_requeue:
  2007. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  2008. delay = msecs_to_jiffies(50);
  2009. else
  2010. delay = round_jiffies(HZ);
  2011. queue_delayed_work(dev->wl->hw->workqueue,
  2012. &dev->periodic_work, delay);
  2013. out:
  2014. mutex_unlock(&dev->wl->mutex);
  2015. }
  2016. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  2017. {
  2018. struct delayed_work *work = &dev->periodic_work;
  2019. dev->periodic_state = 0;
  2020. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  2021. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  2022. }
  2023. /* Validate access to the chip (SHM) */
  2024. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  2025. {
  2026. u32 value;
  2027. u32 shm_backup;
  2028. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  2029. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  2030. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2031. 0xAA5555AA)
  2032. goto error;
  2033. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  2034. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2035. 0x55AAAA55)
  2036. goto error;
  2037. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  2038. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2039. if ((value | B43legacy_MACCTL_GMODE) !=
  2040. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  2041. goto error;
  2042. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  2043. if (value)
  2044. goto error;
  2045. return 0;
  2046. error:
  2047. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  2048. return -ENODEV;
  2049. }
  2050. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  2051. {
  2052. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  2053. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  2054. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  2055. 0x0056);
  2056. /* KTP is a word address, but we address SHM bytewise.
  2057. * So multiply by two.
  2058. */
  2059. dev->ktp *= 2;
  2060. if (dev->dev->id.revision >= 5)
  2061. /* Number of RCMTA address slots */
  2062. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  2063. dev->max_nr_keys - 8);
  2064. }
  2065. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  2066. {
  2067. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  2068. unsigned long flags;
  2069. /* Don't take wl->mutex here, as it could deadlock with
  2070. * hwrng internal locking. It's not needed to take
  2071. * wl->mutex here, anyway. */
  2072. spin_lock_irqsave(&wl->irq_lock, flags);
  2073. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  2074. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2075. return (sizeof(u16));
  2076. }
  2077. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  2078. {
  2079. if (wl->rng_initialized)
  2080. hwrng_unregister(&wl->rng);
  2081. }
  2082. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  2083. {
  2084. int err;
  2085. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2086. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2087. wl->rng.name = wl->rng_name;
  2088. wl->rng.data_read = b43legacy_rng_read;
  2089. wl->rng.priv = (unsigned long)wl;
  2090. wl->rng_initialized = 1;
  2091. err = hwrng_register(&wl->rng);
  2092. if (err) {
  2093. wl->rng_initialized = 0;
  2094. b43legacyerr(wl, "Failed to register the random "
  2095. "number generator (%d)\n", err);
  2096. }
  2097. return err;
  2098. }
  2099. static int b43legacy_tx(struct ieee80211_hw *hw,
  2100. struct sk_buff *skb,
  2101. struct ieee80211_tx_control *ctl)
  2102. {
  2103. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2104. struct b43legacy_wldev *dev = wl->current_dev;
  2105. int err = -ENODEV;
  2106. unsigned long flags;
  2107. if (unlikely(!dev))
  2108. goto out;
  2109. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2110. goto out;
  2111. /* DMA-TX is done without a global lock. */
  2112. if (b43legacy_using_pio(dev)) {
  2113. spin_lock_irqsave(&wl->irq_lock, flags);
  2114. err = b43legacy_pio_tx(dev, skb, ctl);
  2115. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2116. } else
  2117. err = b43legacy_dma_tx(dev, skb, ctl);
  2118. out:
  2119. if (unlikely(err))
  2120. return NETDEV_TX_BUSY;
  2121. return NETDEV_TX_OK;
  2122. }
  2123. static int b43legacy_conf_tx(struct ieee80211_hw *hw,
  2124. int queue,
  2125. const struct ieee80211_tx_queue_params *params)
  2126. {
  2127. return 0;
  2128. }
  2129. static int b43legacy_get_tx_stats(struct ieee80211_hw *hw,
  2130. struct ieee80211_tx_queue_stats *stats)
  2131. {
  2132. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2133. struct b43legacy_wldev *dev = wl->current_dev;
  2134. unsigned long flags;
  2135. int err = -ENODEV;
  2136. if (!dev)
  2137. goto out;
  2138. spin_lock_irqsave(&wl->irq_lock, flags);
  2139. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2140. if (b43legacy_using_pio(dev))
  2141. b43legacy_pio_get_tx_stats(dev, stats);
  2142. else
  2143. b43legacy_dma_get_tx_stats(dev, stats);
  2144. err = 0;
  2145. }
  2146. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2147. out:
  2148. return err;
  2149. }
  2150. static int b43legacy_get_stats(struct ieee80211_hw *hw,
  2151. struct ieee80211_low_level_stats *stats)
  2152. {
  2153. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2154. unsigned long flags;
  2155. spin_lock_irqsave(&wl->irq_lock, flags);
  2156. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2157. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2158. return 0;
  2159. }
  2160. static const char *phymode_to_string(unsigned int phymode)
  2161. {
  2162. switch (phymode) {
  2163. case B43legacy_PHYMODE_B:
  2164. return "B";
  2165. case B43legacy_PHYMODE_G:
  2166. return "G";
  2167. default:
  2168. B43legacy_BUG_ON(1);
  2169. }
  2170. return "";
  2171. }
  2172. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2173. unsigned int phymode,
  2174. struct b43legacy_wldev **dev,
  2175. bool *gmode)
  2176. {
  2177. struct b43legacy_wldev *d;
  2178. list_for_each_entry(d, &wl->devlist, list) {
  2179. if (d->phy.possible_phymodes & phymode) {
  2180. /* Ok, this device supports the PHY-mode.
  2181. * Set the gmode bit. */
  2182. *gmode = 1;
  2183. *dev = d;
  2184. return 0;
  2185. }
  2186. }
  2187. return -ESRCH;
  2188. }
  2189. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2190. {
  2191. struct ssb_device *sdev = dev->dev;
  2192. u32 tmslow;
  2193. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2194. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2195. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2196. tmslow |= SSB_TMSLOW_FGC;
  2197. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2198. msleep(1);
  2199. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2200. tmslow &= ~SSB_TMSLOW_FGC;
  2201. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2202. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2203. msleep(1);
  2204. }
  2205. /* Expects wl->mutex locked */
  2206. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2207. unsigned int new_mode)
  2208. {
  2209. struct b43legacy_wldev *up_dev;
  2210. struct b43legacy_wldev *down_dev;
  2211. int err;
  2212. bool gmode = 0;
  2213. int prev_status;
  2214. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2215. if (err) {
  2216. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2217. phymode_to_string(new_mode));
  2218. return err;
  2219. }
  2220. if ((up_dev == wl->current_dev) &&
  2221. (!!wl->current_dev->phy.gmode == !!gmode))
  2222. /* This device is already running. */
  2223. return 0;
  2224. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2225. phymode_to_string(new_mode));
  2226. down_dev = wl->current_dev;
  2227. prev_status = b43legacy_status(down_dev);
  2228. /* Shutdown the currently running core. */
  2229. if (prev_status >= B43legacy_STAT_STARTED)
  2230. b43legacy_wireless_core_stop(down_dev);
  2231. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2232. b43legacy_wireless_core_exit(down_dev);
  2233. if (down_dev != up_dev)
  2234. /* We switch to a different core, so we put PHY into
  2235. * RESET on the old core. */
  2236. b43legacy_put_phy_into_reset(down_dev);
  2237. /* Now start the new core. */
  2238. up_dev->phy.gmode = gmode;
  2239. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2240. err = b43legacy_wireless_core_init(up_dev);
  2241. if (err) {
  2242. b43legacyerr(wl, "Fatal: Could not initialize device"
  2243. " for newly selected %s-PHY mode\n",
  2244. phymode_to_string(new_mode));
  2245. goto init_failure;
  2246. }
  2247. }
  2248. if (prev_status >= B43legacy_STAT_STARTED) {
  2249. err = b43legacy_wireless_core_start(up_dev);
  2250. if (err) {
  2251. b43legacyerr(wl, "Fatal: Coult not start device for "
  2252. "newly selected %s-PHY mode\n",
  2253. phymode_to_string(new_mode));
  2254. b43legacy_wireless_core_exit(up_dev);
  2255. goto init_failure;
  2256. }
  2257. }
  2258. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2259. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2260. wl->current_dev = up_dev;
  2261. return 0;
  2262. init_failure:
  2263. /* Whoops, failed to init the new core. No core is operating now. */
  2264. wl->current_dev = NULL;
  2265. return err;
  2266. }
  2267. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2268. {
  2269. switch (antenna) {
  2270. case 0: /* default/diversity */
  2271. return B43legacy_ANTENNA_DEFAULT;
  2272. case 1: /* Antenna 0 */
  2273. return B43legacy_ANTENNA0;
  2274. case 2: /* Antenna 1 */
  2275. return B43legacy_ANTENNA1;
  2276. default:
  2277. return B43legacy_ANTENNA_DEFAULT;
  2278. }
  2279. }
  2280. static int b43legacy_dev_config(struct ieee80211_hw *hw,
  2281. struct ieee80211_conf *conf)
  2282. {
  2283. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2284. struct b43legacy_wldev *dev;
  2285. struct b43legacy_phy *phy;
  2286. unsigned long flags;
  2287. unsigned int new_phymode = 0xFFFF;
  2288. int antenna_tx;
  2289. int antenna_rx;
  2290. int err = 0;
  2291. u32 savedirqs;
  2292. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2293. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2294. mutex_lock(&wl->mutex);
  2295. /* Switch the PHY mode (if necessary). */
  2296. switch (conf->phymode) {
  2297. case MODE_IEEE80211B:
  2298. new_phymode = B43legacy_PHYMODE_B;
  2299. break;
  2300. case MODE_IEEE80211G:
  2301. new_phymode = B43legacy_PHYMODE_G;
  2302. break;
  2303. default:
  2304. B43legacy_WARN_ON(1);
  2305. }
  2306. err = b43legacy_switch_phymode(wl, new_phymode);
  2307. if (err)
  2308. goto out_unlock_mutex;
  2309. dev = wl->current_dev;
  2310. phy = &dev->phy;
  2311. /* Disable IRQs while reconfiguring the device.
  2312. * This makes it possible to drop the spinlock throughout
  2313. * the reconfiguration process. */
  2314. spin_lock_irqsave(&wl->irq_lock, flags);
  2315. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2316. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2317. goto out_unlock_mutex;
  2318. }
  2319. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2320. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2321. b43legacy_synchronize_irq(dev);
  2322. /* Switch to the requested channel.
  2323. * The firmware takes care of races with the TX handler. */
  2324. if (conf->channel_val != phy->channel)
  2325. b43legacy_radio_selectchannel(dev, conf->channel_val, 0);
  2326. /* Enable/Disable ShortSlot timing. */
  2327. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2328. != dev->short_slot) {
  2329. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2330. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2331. b43legacy_short_slot_timing_enable(dev);
  2332. else
  2333. b43legacy_short_slot_timing_disable(dev);
  2334. }
  2335. /* Adjust the desired TX power level. */
  2336. if (conf->power_level != 0) {
  2337. if (conf->power_level != phy->power_level) {
  2338. phy->power_level = conf->power_level;
  2339. b43legacy_phy_xmitpower(dev);
  2340. }
  2341. }
  2342. /* Antennas for RX and management frame TX. */
  2343. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2344. /* Update templates for AP mode. */
  2345. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2346. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2347. if (!!conf->radio_enabled != phy->radio_on) {
  2348. if (conf->radio_enabled) {
  2349. b43legacy_radio_turn_on(dev);
  2350. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2351. if (!dev->radio_hw_enable)
  2352. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2353. " button still turns the radio"
  2354. " physically off. Press the"
  2355. " button to turn it on.\n");
  2356. } else {
  2357. b43legacy_radio_turn_off(dev);
  2358. b43legacyinfo(dev->wl, "Radio turned off by"
  2359. " software\n");
  2360. }
  2361. }
  2362. spin_lock_irqsave(&wl->irq_lock, flags);
  2363. b43legacy_interrupt_enable(dev, savedirqs);
  2364. mmiowb();
  2365. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2366. out_unlock_mutex:
  2367. mutex_unlock(&wl->mutex);
  2368. return err;
  2369. }
  2370. static int b43legacy_dev_set_key(struct ieee80211_hw *hw,
  2371. set_key_cmd cmd,
  2372. const u8 *local_addr, const u8 *addr,
  2373. struct ieee80211_key_conf *key)
  2374. {
  2375. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2376. struct b43legacy_wldev *dev = wl->current_dev;
  2377. unsigned long flags;
  2378. int err = -EOPNOTSUPP;
  2379. DECLARE_MAC_BUF(mac);
  2380. if (!dev)
  2381. return -ENODEV;
  2382. mutex_lock(&wl->mutex);
  2383. spin_lock_irqsave(&wl->irq_lock, flags);
  2384. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2385. err = -ENODEV;
  2386. }
  2387. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2388. mutex_unlock(&wl->mutex);
  2389. b43legacydbg(wl, "Using software based encryption for "
  2390. "mac: %s\n", print_mac(mac, addr));
  2391. return err;
  2392. }
  2393. static void b43legacy_set_multicast_list(struct ieee80211_hw *hw,
  2394. unsigned short netflags,
  2395. int mc_count)
  2396. {
  2397. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2398. struct b43legacy_wldev *dev = wl->current_dev;
  2399. unsigned long flags;
  2400. if (!dev)
  2401. return;
  2402. spin_lock_irqsave(&wl->irq_lock, flags);
  2403. if (wl->promisc != !!(netflags & IFF_PROMISC)) {
  2404. wl->promisc = !!(netflags & IFF_PROMISC);
  2405. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2406. b43legacy_adjust_opmode(dev);
  2407. }
  2408. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2409. }
  2410. static int b43legacy_config_interface(struct ieee80211_hw *hw,
  2411. int if_id,
  2412. struct ieee80211_if_conf *conf)
  2413. {
  2414. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2415. struct b43legacy_wldev *dev = wl->current_dev;
  2416. unsigned long flags;
  2417. if (!dev)
  2418. return -ENODEV;
  2419. mutex_lock(&wl->mutex);
  2420. spin_lock_irqsave(&wl->irq_lock, flags);
  2421. if (conf->type != IEEE80211_IF_TYPE_MNTR) {
  2422. B43legacy_WARN_ON(wl->if_id != if_id);
  2423. wl->bssid = conf->bssid;
  2424. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2425. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2426. B43legacy_WARN_ON(conf->type !=
  2427. IEEE80211_IF_TYPE_AP);
  2428. b43legacy_set_ssid(dev, conf->ssid,
  2429. conf->ssid_len);
  2430. if (conf->beacon)
  2431. b43legacy_refresh_templates(dev,
  2432. conf->beacon);
  2433. }
  2434. b43legacy_write_mac_bssid_templates(dev);
  2435. }
  2436. }
  2437. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2438. mutex_unlock(&wl->mutex);
  2439. return 0;
  2440. }
  2441. /* Locking: wl->mutex */
  2442. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2443. {
  2444. struct b43legacy_wl *wl = dev->wl;
  2445. unsigned long flags;
  2446. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2447. return;
  2448. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2449. mutex_unlock(&wl->mutex);
  2450. /* Must unlock as it would otherwise deadlock. No races here.
  2451. * Cancel the possibly running self-rearming periodic work. */
  2452. cancel_delayed_work_sync(&dev->periodic_work);
  2453. mutex_lock(&wl->mutex);
  2454. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2455. /* Disable and sync interrupts. */
  2456. spin_lock_irqsave(&wl->irq_lock, flags);
  2457. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2458. B43legacy_IRQ_ALL);
  2459. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2460. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2461. b43legacy_synchronize_irq(dev);
  2462. b43legacy_mac_suspend(dev);
  2463. free_irq(dev->dev->irq, dev);
  2464. b43legacydbg(wl, "Wireless interface stopped\n");
  2465. }
  2466. /* Locking: wl->mutex */
  2467. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2468. {
  2469. int err;
  2470. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2471. drain_txstatus_queue(dev);
  2472. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2473. IRQF_SHARED, KBUILD_MODNAME, dev);
  2474. if (err) {
  2475. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2476. dev->dev->irq);
  2477. goto out;
  2478. }
  2479. /* We are ready to run. */
  2480. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2481. /* Start data flow (TX/RX) */
  2482. b43legacy_mac_enable(dev);
  2483. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2484. ieee80211_start_queues(dev->wl->hw);
  2485. /* Start maintenance work */
  2486. b43legacy_periodic_tasks_setup(dev);
  2487. b43legacydbg(dev->wl, "Wireless interface started\n");
  2488. out:
  2489. return err;
  2490. }
  2491. /* Get PHY and RADIO versioning numbers */
  2492. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2493. {
  2494. struct b43legacy_phy *phy = &dev->phy;
  2495. u32 tmp;
  2496. u8 analog_type;
  2497. u8 phy_type;
  2498. u8 phy_rev;
  2499. u16 radio_manuf;
  2500. u16 radio_ver;
  2501. u16 radio_rev;
  2502. int unsupported = 0;
  2503. /* Get PHY versioning */
  2504. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2505. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2506. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2507. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2508. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2509. switch (phy_type) {
  2510. case B43legacy_PHYTYPE_B:
  2511. if (phy_rev != 2 && phy_rev != 4
  2512. && phy_rev != 6 && phy_rev != 7)
  2513. unsupported = 1;
  2514. break;
  2515. case B43legacy_PHYTYPE_G:
  2516. if (phy_rev > 8)
  2517. unsupported = 1;
  2518. break;
  2519. default:
  2520. unsupported = 1;
  2521. };
  2522. if (unsupported) {
  2523. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2524. "(Analog %u, Type %u, Revision %u)\n",
  2525. analog_type, phy_type, phy_rev);
  2526. return -EOPNOTSUPP;
  2527. }
  2528. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2529. analog_type, phy_type, phy_rev);
  2530. /* Get RADIO versioning */
  2531. if (dev->dev->bus->chip_id == 0x4317) {
  2532. if (dev->dev->bus->chip_rev == 0)
  2533. tmp = 0x3205017F;
  2534. else if (dev->dev->bus->chip_rev == 1)
  2535. tmp = 0x4205017F;
  2536. else
  2537. tmp = 0x5205017F;
  2538. } else {
  2539. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2540. B43legacy_RADIOCTL_ID);
  2541. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2542. tmp <<= 16;
  2543. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2544. B43legacy_RADIOCTL_ID);
  2545. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2546. }
  2547. radio_manuf = (tmp & 0x00000FFF);
  2548. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2549. radio_rev = (tmp & 0xF0000000) >> 28;
  2550. switch (phy_type) {
  2551. case B43legacy_PHYTYPE_B:
  2552. if ((radio_ver & 0xFFF0) != 0x2050)
  2553. unsupported = 1;
  2554. break;
  2555. case B43legacy_PHYTYPE_G:
  2556. if (radio_ver != 0x2050)
  2557. unsupported = 1;
  2558. break;
  2559. default:
  2560. B43legacy_BUG_ON(1);
  2561. }
  2562. if (unsupported) {
  2563. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2564. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2565. radio_manuf, radio_ver, radio_rev);
  2566. return -EOPNOTSUPP;
  2567. }
  2568. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2569. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2570. phy->radio_manuf = radio_manuf;
  2571. phy->radio_ver = radio_ver;
  2572. phy->radio_rev = radio_rev;
  2573. phy->analog = analog_type;
  2574. phy->type = phy_type;
  2575. phy->rev = phy_rev;
  2576. return 0;
  2577. }
  2578. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2579. struct b43legacy_phy *phy)
  2580. {
  2581. struct b43legacy_lopair *lo;
  2582. int i;
  2583. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2584. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2585. /* Flags */
  2586. phy->locked = 0;
  2587. /* Assume the radio is enabled. If it's not enabled, the state will
  2588. * immediately get fixed on the first periodic work run. */
  2589. dev->radio_hw_enable = 1;
  2590. phy->savedpctlreg = 0xFFFF;
  2591. phy->aci_enable = 0;
  2592. phy->aci_wlan_automatic = 0;
  2593. phy->aci_hw_rssi = 0;
  2594. lo = phy->_lo_pairs;
  2595. if (lo)
  2596. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2597. B43legacy_LO_COUNT);
  2598. phy->max_lb_gain = 0;
  2599. phy->trsw_rx_gain = 0;
  2600. /* Set default attenuation values. */
  2601. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2602. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2603. phy->txctl1 = b43legacy_default_txctl1(dev);
  2604. phy->txpwr_offset = 0;
  2605. /* NRSSI */
  2606. phy->nrssislope = 0;
  2607. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2608. phy->nrssi[i] = -1000;
  2609. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2610. phy->nrssi_lt[i] = i;
  2611. phy->lofcal = 0xFFFF;
  2612. phy->initval = 0xFFFF;
  2613. spin_lock_init(&phy->lock);
  2614. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2615. phy->channel = 0xFF;
  2616. }
  2617. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2618. {
  2619. /* Flags */
  2620. dev->reg124_set_0x4 = 0;
  2621. /* Stats */
  2622. memset(&dev->stats, 0, sizeof(dev->stats));
  2623. setup_struct_phy_for_init(dev, &dev->phy);
  2624. /* IRQ related flags */
  2625. dev->irq_reason = 0;
  2626. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2627. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2628. dev->mac_suspended = 1;
  2629. /* Noise calculation context */
  2630. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2631. }
  2632. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2633. {
  2634. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2635. struct ssb_bus *bus = dev->dev->bus;
  2636. u32 tmp;
  2637. if (bus->pcicore.dev &&
  2638. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2639. bus->pcicore.dev->id.revision <= 5) {
  2640. /* IMCFGLO timeouts workaround. */
  2641. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2642. tmp &= ~SSB_IMCFGLO_REQTO;
  2643. tmp &= ~SSB_IMCFGLO_SERTO;
  2644. switch (bus->bustype) {
  2645. case SSB_BUSTYPE_PCI:
  2646. case SSB_BUSTYPE_PCMCIA:
  2647. tmp |= 0x32;
  2648. break;
  2649. case SSB_BUSTYPE_SSB:
  2650. tmp |= 0x53;
  2651. break;
  2652. }
  2653. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2654. }
  2655. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2656. }
  2657. /* Shutdown a wireless core */
  2658. /* Locking: wl->mutex */
  2659. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2660. {
  2661. struct b43legacy_wl *wl = dev->wl;
  2662. struct b43legacy_phy *phy = &dev->phy;
  2663. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2664. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2665. return;
  2666. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2667. mutex_unlock(&wl->mutex);
  2668. /* Must unlock as it would otherwise deadlock. No races here.
  2669. * Cancel possibly pending workqueues. */
  2670. cancel_work_sync(&dev->restart_work);
  2671. mutex_lock(&wl->mutex);
  2672. b43legacy_rng_exit(dev->wl);
  2673. b43legacy_pio_free(dev);
  2674. b43legacy_dma_free(dev);
  2675. b43legacy_chip_exit(dev);
  2676. b43legacy_radio_turn_off(dev);
  2677. b43legacy_switch_analog(dev, 0);
  2678. if (phy->dyn_tssi_tbl)
  2679. kfree(phy->tssi2dbm);
  2680. kfree(phy->lo_control);
  2681. phy->lo_control = NULL;
  2682. ssb_device_disable(dev->dev, 0);
  2683. ssb_bus_may_powerdown(dev->dev->bus);
  2684. }
  2685. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2686. {
  2687. struct b43legacy_phy *phy = &dev->phy;
  2688. int i;
  2689. /* Set default attenuation values. */
  2690. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2691. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2692. phy->txctl1 = b43legacy_default_txctl1(dev);
  2693. phy->txctl2 = 0xFFFF;
  2694. phy->txpwr_offset = 0;
  2695. /* NRSSI */
  2696. phy->nrssislope = 0;
  2697. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2698. phy->nrssi[i] = -1000;
  2699. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2700. phy->nrssi_lt[i] = i;
  2701. phy->lofcal = 0xFFFF;
  2702. phy->initval = 0xFFFF;
  2703. phy->aci_enable = 0;
  2704. phy->aci_wlan_automatic = 0;
  2705. phy->aci_hw_rssi = 0;
  2706. phy->antenna_diversity = 0xFFFF;
  2707. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2708. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2709. /* Flags */
  2710. phy->calibrated = 0;
  2711. phy->locked = 0;
  2712. if (phy->_lo_pairs)
  2713. memset(phy->_lo_pairs, 0,
  2714. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2715. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2716. }
  2717. /* Initialize a wireless core */
  2718. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2719. {
  2720. struct b43legacy_wl *wl = dev->wl;
  2721. struct ssb_bus *bus = dev->dev->bus;
  2722. struct b43legacy_phy *phy = &dev->phy;
  2723. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2724. int err;
  2725. u32 hf;
  2726. u32 tmp;
  2727. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2728. err = ssb_bus_powerup(bus, 0);
  2729. if (err)
  2730. goto out;
  2731. if (!ssb_device_is_enabled(dev->dev)) {
  2732. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2733. b43legacy_wireless_core_reset(dev, tmp);
  2734. }
  2735. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2736. (phy->type == B43legacy_PHYTYPE_G)) {
  2737. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2738. * B43legacy_LO_COUNT,
  2739. GFP_KERNEL);
  2740. if (!phy->_lo_pairs)
  2741. return -ENOMEM;
  2742. }
  2743. setup_struct_wldev_for_init(dev);
  2744. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2745. if (err)
  2746. goto err_kfree_lo_control;
  2747. /* Enable IRQ routing to this device. */
  2748. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2749. b43legacy_imcfglo_timeouts_workaround(dev);
  2750. prepare_phy_data_for_init(dev);
  2751. b43legacy_phy_calibrate(dev);
  2752. err = b43legacy_chip_init(dev);
  2753. if (err)
  2754. goto err_kfree_tssitbl;
  2755. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2756. B43legacy_SHM_SH_WLCOREREV,
  2757. dev->dev->id.revision);
  2758. hf = b43legacy_hf_read(dev);
  2759. if (phy->type == B43legacy_PHYTYPE_G) {
  2760. hf |= B43legacy_HF_SYMW;
  2761. if (phy->rev == 1)
  2762. hf |= B43legacy_HF_GDCW;
  2763. if (sprom->r1.boardflags_lo & B43legacy_BFL_PACTRL)
  2764. hf |= B43legacy_HF_OFDMPABOOST;
  2765. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2766. hf |= B43legacy_HF_SYMW;
  2767. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2768. hf &= ~B43legacy_HF_GDCW;
  2769. }
  2770. b43legacy_hf_write(dev, hf);
  2771. /* Short/Long Retry Limit.
  2772. * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
  2773. * the chip-internal counter.
  2774. */
  2775. tmp = limit_value(modparam_short_retry, 0, 0xF);
  2776. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2777. 0x0006, tmp);
  2778. tmp = limit_value(modparam_long_retry, 0, 0xF);
  2779. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2780. 0x0007, tmp);
  2781. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2782. 0x0044, 3);
  2783. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2784. 0x0046, 2);
  2785. /* Disable sending probe responses from firmware.
  2786. * Setting the MaxTime to one usec will always trigger
  2787. * a timeout, so we never send any probe resp.
  2788. * A timeout of zero is infinite. */
  2789. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2790. B43legacy_SHM_SH_PRMAXTIME, 1);
  2791. b43legacy_rate_memory_init(dev);
  2792. /* Minimum Contention Window */
  2793. if (phy->type == B43legacy_PHYTYPE_B)
  2794. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2795. 0x0003, 31);
  2796. else
  2797. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2798. 0x0003, 15);
  2799. /* Maximum Contention Window */
  2800. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2801. 0x0004, 1023);
  2802. do {
  2803. if (b43legacy_using_pio(dev))
  2804. err = b43legacy_pio_init(dev);
  2805. else {
  2806. err = b43legacy_dma_init(dev);
  2807. if (!err)
  2808. b43legacy_qos_init(dev);
  2809. }
  2810. } while (err == -EAGAIN);
  2811. if (err)
  2812. goto err_chip_exit;
  2813. b43legacy_write16(dev, 0x0612, 0x0050);
  2814. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
  2815. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
  2816. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2817. wl->bssid = NULL;
  2818. b43legacy_upload_card_macaddress(dev, NULL);
  2819. b43legacy_security_init(dev);
  2820. b43legacy_rng_init(wl);
  2821. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2822. out:
  2823. return err;
  2824. err_chip_exit:
  2825. b43legacy_chip_exit(dev);
  2826. err_kfree_tssitbl:
  2827. if (phy->dyn_tssi_tbl)
  2828. kfree(phy->tssi2dbm);
  2829. err_kfree_lo_control:
  2830. kfree(phy->lo_control);
  2831. phy->lo_control = NULL;
  2832. ssb_bus_may_powerdown(bus);
  2833. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2834. return err;
  2835. }
  2836. static int b43legacy_add_interface(struct ieee80211_hw *hw,
  2837. struct ieee80211_if_init_conf *conf)
  2838. {
  2839. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2840. struct b43legacy_wldev *dev;
  2841. unsigned long flags;
  2842. int err = -EOPNOTSUPP;
  2843. int did_init = 0;
  2844. mutex_lock(&wl->mutex);
  2845. if ((conf->type != IEEE80211_IF_TYPE_MNTR) &&
  2846. wl->operating)
  2847. goto out_mutex_unlock;
  2848. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2849. dev = wl->current_dev;
  2850. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2851. err = b43legacy_wireless_core_init(dev);
  2852. if (err)
  2853. goto out_mutex_unlock;
  2854. did_init = 1;
  2855. }
  2856. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2857. err = b43legacy_wireless_core_start(dev);
  2858. if (err) {
  2859. if (did_init)
  2860. b43legacy_wireless_core_exit(dev);
  2861. goto out_mutex_unlock;
  2862. }
  2863. }
  2864. spin_lock_irqsave(&wl->irq_lock, flags);
  2865. switch (conf->type) {
  2866. case IEEE80211_IF_TYPE_MNTR:
  2867. wl->monitor++;
  2868. break;
  2869. default:
  2870. wl->operating = 1;
  2871. wl->if_id = conf->if_id;
  2872. wl->if_type = conf->type;
  2873. b43legacy_upload_card_macaddress(dev, conf->mac_addr);
  2874. }
  2875. b43legacy_adjust_opmode(dev);
  2876. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2877. err = 0;
  2878. out_mutex_unlock:
  2879. mutex_unlock(&wl->mutex);
  2880. return err;
  2881. }
  2882. static void b43legacy_remove_interface(struct ieee80211_hw *hw,
  2883. struct ieee80211_if_init_conf *conf)
  2884. {
  2885. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2886. struct b43legacy_wldev *dev;
  2887. unsigned long flags;
  2888. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2889. mutex_lock(&wl->mutex);
  2890. if (conf->type == IEEE80211_IF_TYPE_MNTR) {
  2891. wl->monitor--;
  2892. B43legacy_WARN_ON(wl->monitor < 0);
  2893. } else {
  2894. B43legacy_WARN_ON(!wl->operating);
  2895. wl->operating = 0;
  2896. }
  2897. dev = wl->current_dev;
  2898. if (!wl->operating && wl->monitor == 0) {
  2899. /* No interface left. */
  2900. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2901. b43legacy_wireless_core_stop(dev);
  2902. b43legacy_wireless_core_exit(dev);
  2903. } else {
  2904. /* Just monitor interfaces left. */
  2905. spin_lock_irqsave(&wl->irq_lock, flags);
  2906. b43legacy_adjust_opmode(dev);
  2907. if (!wl->operating)
  2908. b43legacy_upload_card_macaddress(dev, NULL);
  2909. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2910. }
  2911. mutex_unlock(&wl->mutex);
  2912. }
  2913. static const struct ieee80211_ops b43legacy_hw_ops = {
  2914. .tx = b43legacy_tx,
  2915. .conf_tx = b43legacy_conf_tx,
  2916. .add_interface = b43legacy_add_interface,
  2917. .remove_interface = b43legacy_remove_interface,
  2918. .config = b43legacy_dev_config,
  2919. .config_interface = b43legacy_config_interface,
  2920. .set_key = b43legacy_dev_set_key,
  2921. .set_multicast_list = b43legacy_set_multicast_list,
  2922. .get_stats = b43legacy_get_stats,
  2923. .get_tx_stats = b43legacy_get_tx_stats,
  2924. };
  2925. /* Hard-reset the chip. Do not call this directly.
  2926. * Use b43legacy_controller_restart()
  2927. */
  2928. static void b43legacy_chip_reset(struct work_struct *work)
  2929. {
  2930. struct b43legacy_wldev *dev =
  2931. container_of(work, struct b43legacy_wldev, restart_work);
  2932. struct b43legacy_wl *wl = dev->wl;
  2933. int err = 0;
  2934. int prev_status;
  2935. mutex_lock(&wl->mutex);
  2936. prev_status = b43legacy_status(dev);
  2937. /* Bring the device down... */
  2938. if (prev_status >= B43legacy_STAT_STARTED)
  2939. b43legacy_wireless_core_stop(dev);
  2940. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2941. b43legacy_wireless_core_exit(dev);
  2942. /* ...and up again. */
  2943. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2944. err = b43legacy_wireless_core_init(dev);
  2945. if (err)
  2946. goto out;
  2947. }
  2948. if (prev_status >= B43legacy_STAT_STARTED) {
  2949. err = b43legacy_wireless_core_start(dev);
  2950. if (err) {
  2951. b43legacy_wireless_core_exit(dev);
  2952. goto out;
  2953. }
  2954. }
  2955. out:
  2956. mutex_unlock(&wl->mutex);
  2957. if (err)
  2958. b43legacyerr(wl, "Controller restart FAILED\n");
  2959. else
  2960. b43legacyinfo(wl, "Controller restarted\n");
  2961. }
  2962. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  2963. int have_bphy,
  2964. int have_gphy)
  2965. {
  2966. struct ieee80211_hw *hw = dev->wl->hw;
  2967. struct ieee80211_hw_mode *mode;
  2968. struct b43legacy_phy *phy = &dev->phy;
  2969. int cnt = 0;
  2970. int err;
  2971. phy->possible_phymodes = 0;
  2972. for (; 1; cnt++) {
  2973. if (have_bphy) {
  2974. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2975. mode = &phy->hwmodes[cnt];
  2976. mode->mode = MODE_IEEE80211B;
  2977. mode->num_channels = b43legacy_bg_chantable_size;
  2978. mode->channels = b43legacy_bg_chantable;
  2979. mode->num_rates = b43legacy_b_ratetable_size;
  2980. mode->rates = b43legacy_b_ratetable;
  2981. err = ieee80211_register_hwmode(hw, mode);
  2982. if (err)
  2983. return err;
  2984. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  2985. have_bphy = 0;
  2986. continue;
  2987. }
  2988. if (have_gphy) {
  2989. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2990. mode = &phy->hwmodes[cnt];
  2991. mode->mode = MODE_IEEE80211G;
  2992. mode->num_channels = b43legacy_bg_chantable_size;
  2993. mode->channels = b43legacy_bg_chantable;
  2994. mode->num_rates = b43legacy_g_ratetable_size;
  2995. mode->rates = b43legacy_g_ratetable;
  2996. err = ieee80211_register_hwmode(hw, mode);
  2997. if (err)
  2998. return err;
  2999. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  3000. have_gphy = 0;
  3001. continue;
  3002. }
  3003. break;
  3004. }
  3005. return 0;
  3006. }
  3007. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  3008. {
  3009. /* We release firmware that late to not be required to re-request
  3010. * is all the time when we reinit the core. */
  3011. b43legacy_release_firmware(dev);
  3012. }
  3013. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  3014. {
  3015. struct b43legacy_wl *wl = dev->wl;
  3016. struct ssb_bus *bus = dev->dev->bus;
  3017. struct pci_dev *pdev = bus->host_pci;
  3018. int err;
  3019. int have_bphy = 0;
  3020. int have_gphy = 0;
  3021. u32 tmp;
  3022. /* Do NOT do any device initialization here.
  3023. * Do it in wireless_core_init() instead.
  3024. * This function is for gathering basic information about the HW, only.
  3025. * Also some structs may be set up here. But most likely you want to
  3026. * have that in core_init(), too.
  3027. */
  3028. err = ssb_bus_powerup(bus, 0);
  3029. if (err) {
  3030. b43legacyerr(wl, "Bus powerup failed\n");
  3031. goto out;
  3032. }
  3033. /* Get the PHY type. */
  3034. if (dev->dev->id.revision >= 5) {
  3035. u32 tmshigh;
  3036. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3037. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  3038. if (!have_gphy)
  3039. have_bphy = 1;
  3040. } else if (dev->dev->id.revision == 4)
  3041. have_gphy = 1;
  3042. else
  3043. have_bphy = 1;
  3044. /* Initialize LEDs structs. */
  3045. err = b43legacy_leds_init(dev);
  3046. if (err)
  3047. goto err_powerdown;
  3048. dev->phy.gmode = (have_gphy || have_bphy);
  3049. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3050. b43legacy_wireless_core_reset(dev, tmp);
  3051. err = b43legacy_phy_versioning(dev);
  3052. if (err)
  3053. goto err_leds_exit;
  3054. /* Check if this device supports multiband. */
  3055. if (!pdev ||
  3056. (pdev->device != 0x4312 &&
  3057. pdev->device != 0x4319 &&
  3058. pdev->device != 0x4324)) {
  3059. /* No multiband support. */
  3060. have_bphy = 0;
  3061. have_gphy = 0;
  3062. switch (dev->phy.type) {
  3063. case B43legacy_PHYTYPE_B:
  3064. have_bphy = 1;
  3065. break;
  3066. case B43legacy_PHYTYPE_G:
  3067. have_gphy = 1;
  3068. break;
  3069. default:
  3070. B43legacy_BUG_ON(1);
  3071. }
  3072. }
  3073. dev->phy.gmode = (have_gphy || have_bphy);
  3074. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3075. b43legacy_wireless_core_reset(dev, tmp);
  3076. err = b43legacy_validate_chipaccess(dev);
  3077. if (err)
  3078. goto err_leds_exit;
  3079. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3080. if (err)
  3081. goto err_leds_exit;
  3082. /* Now set some default "current_dev" */
  3083. if (!wl->current_dev)
  3084. wl->current_dev = dev;
  3085. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3086. b43legacy_radio_turn_off(dev);
  3087. b43legacy_switch_analog(dev, 0);
  3088. ssb_device_disable(dev->dev, 0);
  3089. ssb_bus_may_powerdown(bus);
  3090. out:
  3091. return err;
  3092. err_leds_exit:
  3093. b43legacy_leds_exit(dev);
  3094. err_powerdown:
  3095. ssb_bus_may_powerdown(bus);
  3096. return err;
  3097. }
  3098. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3099. {
  3100. struct b43legacy_wldev *wldev;
  3101. struct b43legacy_wl *wl;
  3102. wldev = ssb_get_drvdata(dev);
  3103. wl = wldev->wl;
  3104. cancel_work_sync(&wldev->restart_work);
  3105. b43legacy_debugfs_remove_device(wldev);
  3106. b43legacy_wireless_core_detach(wldev);
  3107. list_del(&wldev->list);
  3108. wl->nr_devs--;
  3109. ssb_set_drvdata(dev, NULL);
  3110. kfree(wldev);
  3111. }
  3112. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3113. struct b43legacy_wl *wl)
  3114. {
  3115. struct b43legacy_wldev *wldev;
  3116. struct pci_dev *pdev;
  3117. int err = -ENOMEM;
  3118. if (!list_empty(&wl->devlist)) {
  3119. /* We are not the first core on this chip. */
  3120. pdev = dev->bus->host_pci;
  3121. /* Only special chips support more than one wireless
  3122. * core, although some of the other chips have more than
  3123. * one wireless core as well. Check for this and
  3124. * bail out early.
  3125. */
  3126. if (!pdev ||
  3127. ((pdev->device != 0x4321) &&
  3128. (pdev->device != 0x4313) &&
  3129. (pdev->device != 0x431A))) {
  3130. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3131. return -ENODEV;
  3132. }
  3133. }
  3134. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3135. if (!wldev)
  3136. goto out;
  3137. wldev->dev = dev;
  3138. wldev->wl = wl;
  3139. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3140. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3141. tasklet_init(&wldev->isr_tasklet,
  3142. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3143. (unsigned long)wldev);
  3144. if (modparam_pio)
  3145. wldev->__using_pio = 1;
  3146. INIT_LIST_HEAD(&wldev->list);
  3147. err = b43legacy_wireless_core_attach(wldev);
  3148. if (err)
  3149. goto err_kfree_wldev;
  3150. list_add(&wldev->list, &wl->devlist);
  3151. wl->nr_devs++;
  3152. ssb_set_drvdata(dev, wldev);
  3153. b43legacy_debugfs_add_device(wldev);
  3154. out:
  3155. return err;
  3156. err_kfree_wldev:
  3157. kfree(wldev);
  3158. return err;
  3159. }
  3160. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3161. {
  3162. /* boardflags workarounds */
  3163. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3164. bus->boardinfo.type == 0x4E &&
  3165. bus->boardinfo.rev > 0x40)
  3166. bus->sprom.r1.boardflags_lo |= B43legacy_BFL_PACTRL;
  3167. /* Convert Antennagain values to Q5.2 */
  3168. if (bus->sprom.r1.antenna_gain_bg == 0xFF)
  3169. bus->sprom.r1.antenna_gain_bg = 2; /* if unset, use 2 dBm */
  3170. bus->sprom.r1.antenna_gain_bg <<= 2;
  3171. }
  3172. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3173. struct b43legacy_wl *wl)
  3174. {
  3175. struct ieee80211_hw *hw = wl->hw;
  3176. ssb_set_devtypedata(dev, NULL);
  3177. ieee80211_free_hw(hw);
  3178. }
  3179. static int b43legacy_wireless_init(struct ssb_device *dev)
  3180. {
  3181. struct ssb_sprom *sprom = &dev->bus->sprom;
  3182. struct ieee80211_hw *hw;
  3183. struct b43legacy_wl *wl;
  3184. int err = -ENOMEM;
  3185. b43legacy_sprom_fixup(dev->bus);
  3186. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3187. if (!hw) {
  3188. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3189. goto out;
  3190. }
  3191. /* fill hw info */
  3192. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3193. IEEE80211_HW_RX_INCLUDES_FCS;
  3194. hw->max_signal = 100;
  3195. hw->max_rssi = -110;
  3196. hw->max_noise = -110;
  3197. hw->queues = 1; /* FIXME: hardware has more queues */
  3198. SET_IEEE80211_DEV(hw, dev->dev);
  3199. if (is_valid_ether_addr(sprom->r1.et1mac))
  3200. SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
  3201. else
  3202. SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
  3203. /* Get and initialize struct b43legacy_wl */
  3204. wl = hw_to_b43legacy_wl(hw);
  3205. memset(wl, 0, sizeof(*wl));
  3206. wl->hw = hw;
  3207. spin_lock_init(&wl->irq_lock);
  3208. spin_lock_init(&wl->leds_lock);
  3209. mutex_init(&wl->mutex);
  3210. INIT_LIST_HEAD(&wl->devlist);
  3211. ssb_set_devtypedata(dev, wl);
  3212. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3213. err = 0;
  3214. out:
  3215. return err;
  3216. }
  3217. static int b43legacy_probe(struct ssb_device *dev,
  3218. const struct ssb_device_id *id)
  3219. {
  3220. struct b43legacy_wl *wl;
  3221. int err;
  3222. int first = 0;
  3223. wl = ssb_get_devtypedata(dev);
  3224. if (!wl) {
  3225. /* Probing the first core - setup common struct b43legacy_wl */
  3226. first = 1;
  3227. err = b43legacy_wireless_init(dev);
  3228. if (err)
  3229. goto out;
  3230. wl = ssb_get_devtypedata(dev);
  3231. B43legacy_WARN_ON(!wl);
  3232. }
  3233. err = b43legacy_one_core_attach(dev, wl);
  3234. if (err)
  3235. goto err_wireless_exit;
  3236. if (first) {
  3237. err = ieee80211_register_hw(wl->hw);
  3238. if (err)
  3239. goto err_one_core_detach;
  3240. }
  3241. out:
  3242. return err;
  3243. err_one_core_detach:
  3244. b43legacy_one_core_detach(dev);
  3245. err_wireless_exit:
  3246. if (first)
  3247. b43legacy_wireless_exit(dev, wl);
  3248. return err;
  3249. }
  3250. static void b43legacy_remove(struct ssb_device *dev)
  3251. {
  3252. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3253. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3254. B43legacy_WARN_ON(!wl);
  3255. if (wl->current_dev == wldev)
  3256. ieee80211_unregister_hw(wl->hw);
  3257. b43legacy_one_core_detach(dev);
  3258. if (list_empty(&wl->devlist))
  3259. /* Last core on the chip unregistered.
  3260. * We can destroy common struct b43legacy_wl.
  3261. */
  3262. b43legacy_wireless_exit(dev, wl);
  3263. }
  3264. /* Perform a hardware reset. This can be called from any context. */
  3265. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3266. const char *reason)
  3267. {
  3268. /* Must avoid requeueing, if we are in shutdown. */
  3269. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3270. return;
  3271. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3272. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3273. }
  3274. #ifdef CONFIG_PM
  3275. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3276. {
  3277. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3278. struct b43legacy_wl *wl = wldev->wl;
  3279. b43legacydbg(wl, "Suspending...\n");
  3280. mutex_lock(&wl->mutex);
  3281. wldev->suspend_init_status = b43legacy_status(wldev);
  3282. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3283. b43legacy_wireless_core_stop(wldev);
  3284. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3285. b43legacy_wireless_core_exit(wldev);
  3286. mutex_unlock(&wl->mutex);
  3287. b43legacydbg(wl, "Device suspended.\n");
  3288. return 0;
  3289. }
  3290. static int b43legacy_resume(struct ssb_device *dev)
  3291. {
  3292. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3293. struct b43legacy_wl *wl = wldev->wl;
  3294. int err = 0;
  3295. b43legacydbg(wl, "Resuming...\n");
  3296. mutex_lock(&wl->mutex);
  3297. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3298. err = b43legacy_wireless_core_init(wldev);
  3299. if (err) {
  3300. b43legacyerr(wl, "Resume failed at core init\n");
  3301. goto out;
  3302. }
  3303. }
  3304. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3305. err = b43legacy_wireless_core_start(wldev);
  3306. if (err) {
  3307. b43legacy_wireless_core_exit(wldev);
  3308. b43legacyerr(wl, "Resume failed at core start\n");
  3309. goto out;
  3310. }
  3311. }
  3312. mutex_unlock(&wl->mutex);
  3313. b43legacydbg(wl, "Device resumed.\n");
  3314. out:
  3315. return err;
  3316. }
  3317. #else /* CONFIG_PM */
  3318. # define b43legacy_suspend NULL
  3319. # define b43legacy_resume NULL
  3320. #endif /* CONFIG_PM */
  3321. static struct ssb_driver b43legacy_ssb_driver = {
  3322. .name = KBUILD_MODNAME,
  3323. .id_table = b43legacy_ssb_tbl,
  3324. .probe = b43legacy_probe,
  3325. .remove = b43legacy_remove,
  3326. .suspend = b43legacy_suspend,
  3327. .resume = b43legacy_resume,
  3328. };
  3329. static int __init b43legacy_init(void)
  3330. {
  3331. int err;
  3332. b43legacy_debugfs_init();
  3333. err = ssb_driver_register(&b43legacy_ssb_driver);
  3334. if (err)
  3335. goto err_dfs_exit;
  3336. return err;
  3337. err_dfs_exit:
  3338. b43legacy_debugfs_exit();
  3339. return err;
  3340. }
  3341. static void __exit b43legacy_exit(void)
  3342. {
  3343. ssb_driver_unregister(&b43legacy_ssb_driver);
  3344. b43legacy_debugfs_exit();
  3345. }
  3346. module_init(b43legacy_init)
  3347. module_exit(b43legacy_exit)