intel_display.c 162 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include "drm_dp_helper.h"
  37. #include "drm_crtc_helper.h"
  38. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  39. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  40. static void intel_update_watermarks(struct drm_device *dev);
  41. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  42. typedef struct {
  43. /* given values */
  44. int n;
  45. int m1, m2;
  46. int p1, p2;
  47. /* derived values */
  48. int dot;
  49. int vco;
  50. int m;
  51. int p;
  52. } intel_clock_t;
  53. typedef struct {
  54. int min, max;
  55. } intel_range_t;
  56. typedef struct {
  57. int dot_limit;
  58. int p2_slow, p2_fast;
  59. } intel_p2_t;
  60. #define INTEL_P2_NUM 2
  61. typedef struct intel_limit intel_limit_t;
  62. struct intel_limit {
  63. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  64. intel_p2_t p2;
  65. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  66. int, int, intel_clock_t *);
  67. };
  68. #define I8XX_DOT_MIN 25000
  69. #define I8XX_DOT_MAX 350000
  70. #define I8XX_VCO_MIN 930000
  71. #define I8XX_VCO_MAX 1400000
  72. #define I8XX_N_MIN 3
  73. #define I8XX_N_MAX 16
  74. #define I8XX_M_MIN 96
  75. #define I8XX_M_MAX 140
  76. #define I8XX_M1_MIN 18
  77. #define I8XX_M1_MAX 26
  78. #define I8XX_M2_MIN 6
  79. #define I8XX_M2_MAX 16
  80. #define I8XX_P_MIN 4
  81. #define I8XX_P_MAX 128
  82. #define I8XX_P1_MIN 2
  83. #define I8XX_P1_MAX 33
  84. #define I8XX_P1_LVDS_MIN 1
  85. #define I8XX_P1_LVDS_MAX 6
  86. #define I8XX_P2_SLOW 4
  87. #define I8XX_P2_FAST 2
  88. #define I8XX_P2_LVDS_SLOW 14
  89. #define I8XX_P2_LVDS_FAST 7
  90. #define I8XX_P2_SLOW_LIMIT 165000
  91. #define I9XX_DOT_MIN 20000
  92. #define I9XX_DOT_MAX 400000
  93. #define I9XX_VCO_MIN 1400000
  94. #define I9XX_VCO_MAX 2800000
  95. #define PINEVIEW_VCO_MIN 1700000
  96. #define PINEVIEW_VCO_MAX 3500000
  97. #define I9XX_N_MIN 1
  98. #define I9XX_N_MAX 6
  99. /* Pineview's Ncounter is a ring counter */
  100. #define PINEVIEW_N_MIN 3
  101. #define PINEVIEW_N_MAX 6
  102. #define I9XX_M_MIN 70
  103. #define I9XX_M_MAX 120
  104. #define PINEVIEW_M_MIN 2
  105. #define PINEVIEW_M_MAX 256
  106. #define I9XX_M1_MIN 10
  107. #define I9XX_M1_MAX 22
  108. #define I9XX_M2_MIN 5
  109. #define I9XX_M2_MAX 9
  110. /* Pineview M1 is reserved, and must be 0 */
  111. #define PINEVIEW_M1_MIN 0
  112. #define PINEVIEW_M1_MAX 0
  113. #define PINEVIEW_M2_MIN 0
  114. #define PINEVIEW_M2_MAX 254
  115. #define I9XX_P_SDVO_DAC_MIN 5
  116. #define I9XX_P_SDVO_DAC_MAX 80
  117. #define I9XX_P_LVDS_MIN 7
  118. #define I9XX_P_LVDS_MAX 98
  119. #define PINEVIEW_P_LVDS_MIN 7
  120. #define PINEVIEW_P_LVDS_MAX 112
  121. #define I9XX_P1_MIN 1
  122. #define I9XX_P1_MAX 8
  123. #define I9XX_P2_SDVO_DAC_SLOW 10
  124. #define I9XX_P2_SDVO_DAC_FAST 5
  125. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  126. #define I9XX_P2_LVDS_SLOW 14
  127. #define I9XX_P2_LVDS_FAST 7
  128. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  129. /*The parameter is for SDVO on G4x platform*/
  130. #define G4X_DOT_SDVO_MIN 25000
  131. #define G4X_DOT_SDVO_MAX 270000
  132. #define G4X_VCO_MIN 1750000
  133. #define G4X_VCO_MAX 3500000
  134. #define G4X_N_SDVO_MIN 1
  135. #define G4X_N_SDVO_MAX 4
  136. #define G4X_M_SDVO_MIN 104
  137. #define G4X_M_SDVO_MAX 138
  138. #define G4X_M1_SDVO_MIN 17
  139. #define G4X_M1_SDVO_MAX 23
  140. #define G4X_M2_SDVO_MIN 5
  141. #define G4X_M2_SDVO_MAX 11
  142. #define G4X_P_SDVO_MIN 10
  143. #define G4X_P_SDVO_MAX 30
  144. #define G4X_P1_SDVO_MIN 1
  145. #define G4X_P1_SDVO_MAX 3
  146. #define G4X_P2_SDVO_SLOW 10
  147. #define G4X_P2_SDVO_FAST 10
  148. #define G4X_P2_SDVO_LIMIT 270000
  149. /*The parameter is for HDMI_DAC on G4x platform*/
  150. #define G4X_DOT_HDMI_DAC_MIN 22000
  151. #define G4X_DOT_HDMI_DAC_MAX 400000
  152. #define G4X_N_HDMI_DAC_MIN 1
  153. #define G4X_N_HDMI_DAC_MAX 4
  154. #define G4X_M_HDMI_DAC_MIN 104
  155. #define G4X_M_HDMI_DAC_MAX 138
  156. #define G4X_M1_HDMI_DAC_MIN 16
  157. #define G4X_M1_HDMI_DAC_MAX 23
  158. #define G4X_M2_HDMI_DAC_MIN 5
  159. #define G4X_M2_HDMI_DAC_MAX 11
  160. #define G4X_P_HDMI_DAC_MIN 5
  161. #define G4X_P_HDMI_DAC_MAX 80
  162. #define G4X_P1_HDMI_DAC_MIN 1
  163. #define G4X_P1_HDMI_DAC_MAX 8
  164. #define G4X_P2_HDMI_DAC_SLOW 10
  165. #define G4X_P2_HDMI_DAC_FAST 5
  166. #define G4X_P2_HDMI_DAC_LIMIT 165000
  167. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  168. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  169. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  170. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  171. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  172. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  173. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  174. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  175. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  176. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  177. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  178. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  179. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  180. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  181. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  182. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  183. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  185. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  186. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  187. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  188. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  189. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  190. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  191. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  192. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  193. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  194. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  195. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  196. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  197. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  198. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  199. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  200. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  201. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  203. /*The parameter is for DISPLAY PORT on G4x platform*/
  204. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  205. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  206. #define G4X_N_DISPLAY_PORT_MIN 1
  207. #define G4X_N_DISPLAY_PORT_MAX 2
  208. #define G4X_M_DISPLAY_PORT_MIN 97
  209. #define G4X_M_DISPLAY_PORT_MAX 108
  210. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  211. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  212. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  213. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  214. #define G4X_P_DISPLAY_PORT_MIN 10
  215. #define G4X_P_DISPLAY_PORT_MAX 20
  216. #define G4X_P1_DISPLAY_PORT_MIN 1
  217. #define G4X_P1_DISPLAY_PORT_MAX 2
  218. #define G4X_P2_DISPLAY_PORT_SLOW 10
  219. #define G4X_P2_DISPLAY_PORT_FAST 10
  220. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  221. /* Ironlake / Sandybridge */
  222. /* as we calculate clock using (register_value + 2) for
  223. N/M1/M2, so here the range value for them is (actual_value-2).
  224. */
  225. #define IRONLAKE_DOT_MIN 25000
  226. #define IRONLAKE_DOT_MAX 350000
  227. #define IRONLAKE_VCO_MIN 1760000
  228. #define IRONLAKE_VCO_MAX 3510000
  229. #define IRONLAKE_M1_MIN 12
  230. #define IRONLAKE_M1_MAX 22
  231. #define IRONLAKE_M2_MIN 5
  232. #define IRONLAKE_M2_MAX 9
  233. #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
  234. /* We have parameter ranges for different type of outputs. */
  235. /* DAC & HDMI Refclk 120Mhz */
  236. #define IRONLAKE_DAC_N_MIN 1
  237. #define IRONLAKE_DAC_N_MAX 5
  238. #define IRONLAKE_DAC_M_MIN 79
  239. #define IRONLAKE_DAC_M_MAX 127
  240. #define IRONLAKE_DAC_P_MIN 5
  241. #define IRONLAKE_DAC_P_MAX 80
  242. #define IRONLAKE_DAC_P1_MIN 1
  243. #define IRONLAKE_DAC_P1_MAX 8
  244. #define IRONLAKE_DAC_P2_SLOW 10
  245. #define IRONLAKE_DAC_P2_FAST 5
  246. /* LVDS single-channel 120Mhz refclk */
  247. #define IRONLAKE_LVDS_S_N_MIN 1
  248. #define IRONLAKE_LVDS_S_N_MAX 3
  249. #define IRONLAKE_LVDS_S_M_MIN 79
  250. #define IRONLAKE_LVDS_S_M_MAX 118
  251. #define IRONLAKE_LVDS_S_P_MIN 28
  252. #define IRONLAKE_LVDS_S_P_MAX 112
  253. #define IRONLAKE_LVDS_S_P1_MIN 2
  254. #define IRONLAKE_LVDS_S_P1_MAX 8
  255. #define IRONLAKE_LVDS_S_P2_SLOW 14
  256. #define IRONLAKE_LVDS_S_P2_FAST 14
  257. /* LVDS dual-channel 120Mhz refclk */
  258. #define IRONLAKE_LVDS_D_N_MIN 1
  259. #define IRONLAKE_LVDS_D_N_MAX 3
  260. #define IRONLAKE_LVDS_D_M_MIN 79
  261. #define IRONLAKE_LVDS_D_M_MAX 127
  262. #define IRONLAKE_LVDS_D_P_MIN 14
  263. #define IRONLAKE_LVDS_D_P_MAX 56
  264. #define IRONLAKE_LVDS_D_P1_MIN 2
  265. #define IRONLAKE_LVDS_D_P1_MAX 8
  266. #define IRONLAKE_LVDS_D_P2_SLOW 7
  267. #define IRONLAKE_LVDS_D_P2_FAST 7
  268. /* LVDS single-channel 100Mhz refclk */
  269. #define IRONLAKE_LVDS_S_SSC_N_MIN 1
  270. #define IRONLAKE_LVDS_S_SSC_N_MAX 2
  271. #define IRONLAKE_LVDS_S_SSC_M_MIN 79
  272. #define IRONLAKE_LVDS_S_SSC_M_MAX 126
  273. #define IRONLAKE_LVDS_S_SSC_P_MIN 28
  274. #define IRONLAKE_LVDS_S_SSC_P_MAX 112
  275. #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
  276. #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
  277. #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
  278. #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
  279. /* LVDS dual-channel 100Mhz refclk */
  280. #define IRONLAKE_LVDS_D_SSC_N_MIN 1
  281. #define IRONLAKE_LVDS_D_SSC_N_MAX 3
  282. #define IRONLAKE_LVDS_D_SSC_M_MIN 79
  283. #define IRONLAKE_LVDS_D_SSC_M_MAX 126
  284. #define IRONLAKE_LVDS_D_SSC_P_MIN 14
  285. #define IRONLAKE_LVDS_D_SSC_P_MAX 42
  286. #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
  287. #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
  288. #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
  289. #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
  290. /* DisplayPort */
  291. #define IRONLAKE_DP_N_MIN 1
  292. #define IRONLAKE_DP_N_MAX 2
  293. #define IRONLAKE_DP_M_MIN 81
  294. #define IRONLAKE_DP_M_MAX 90
  295. #define IRONLAKE_DP_P_MIN 10
  296. #define IRONLAKE_DP_P_MAX 20
  297. #define IRONLAKE_DP_P2_FAST 10
  298. #define IRONLAKE_DP_P2_SLOW 10
  299. #define IRONLAKE_DP_P2_LIMIT 0
  300. #define IRONLAKE_DP_P1_MIN 1
  301. #define IRONLAKE_DP_P1_MAX 2
  302. static bool
  303. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  304. int target, int refclk, intel_clock_t *best_clock);
  305. static bool
  306. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  307. int target, int refclk, intel_clock_t *best_clock);
  308. static bool
  309. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  310. int target, int refclk, intel_clock_t *best_clock);
  311. static bool
  312. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  313. int target, int refclk, intel_clock_t *best_clock);
  314. static const intel_limit_t intel_limits_i8xx_dvo = {
  315. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  316. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  317. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  318. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  319. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  320. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  321. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  322. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  323. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  324. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  325. .find_pll = intel_find_best_PLL,
  326. };
  327. static const intel_limit_t intel_limits_i8xx_lvds = {
  328. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  329. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  330. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  331. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  332. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  333. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  334. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  335. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  336. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  337. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  338. .find_pll = intel_find_best_PLL,
  339. };
  340. static const intel_limit_t intel_limits_i9xx_sdvo = {
  341. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  342. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  343. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  344. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  345. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  346. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  347. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  348. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  349. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  350. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  351. .find_pll = intel_find_best_PLL,
  352. };
  353. static const intel_limit_t intel_limits_i9xx_lvds = {
  354. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  355. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  356. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  357. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  358. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  359. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  360. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  361. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  362. /* The single-channel range is 25-112Mhz, and dual-channel
  363. * is 80-224Mhz. Prefer single channel as much as possible.
  364. */
  365. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  366. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  367. .find_pll = intel_find_best_PLL,
  368. };
  369. /* below parameter and function is for G4X Chipset Family*/
  370. static const intel_limit_t intel_limits_g4x_sdvo = {
  371. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  372. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  373. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  374. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  375. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  376. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  377. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  378. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  379. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  380. .p2_slow = G4X_P2_SDVO_SLOW,
  381. .p2_fast = G4X_P2_SDVO_FAST
  382. },
  383. .find_pll = intel_g4x_find_best_PLL,
  384. };
  385. static const intel_limit_t intel_limits_g4x_hdmi = {
  386. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  387. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  388. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  389. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  390. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  391. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  392. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  393. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  394. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  395. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  396. .p2_fast = G4X_P2_HDMI_DAC_FAST
  397. },
  398. .find_pll = intel_g4x_find_best_PLL,
  399. };
  400. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  401. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  402. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  403. .vco = { .min = G4X_VCO_MIN,
  404. .max = G4X_VCO_MAX },
  405. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  406. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  407. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  408. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  409. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  410. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  411. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  412. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  413. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  414. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  415. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  416. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  417. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  418. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  419. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  420. },
  421. .find_pll = intel_g4x_find_best_PLL,
  422. };
  423. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  424. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  425. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  426. .vco = { .min = G4X_VCO_MIN,
  427. .max = G4X_VCO_MAX },
  428. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  429. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  430. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  431. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  432. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  433. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  434. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  435. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  436. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  437. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  438. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  439. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  440. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  441. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  442. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  443. },
  444. .find_pll = intel_g4x_find_best_PLL,
  445. };
  446. static const intel_limit_t intel_limits_g4x_display_port = {
  447. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  448. .max = G4X_DOT_DISPLAY_PORT_MAX },
  449. .vco = { .min = G4X_VCO_MIN,
  450. .max = G4X_VCO_MAX},
  451. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  452. .max = G4X_N_DISPLAY_PORT_MAX },
  453. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  454. .max = G4X_M_DISPLAY_PORT_MAX },
  455. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  456. .max = G4X_M1_DISPLAY_PORT_MAX },
  457. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  458. .max = G4X_M2_DISPLAY_PORT_MAX },
  459. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  460. .max = G4X_P_DISPLAY_PORT_MAX },
  461. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  462. .max = G4X_P1_DISPLAY_PORT_MAX},
  463. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  464. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  465. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  466. .find_pll = intel_find_pll_g4x_dp,
  467. };
  468. static const intel_limit_t intel_limits_pineview_sdvo = {
  469. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  470. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  471. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  472. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  473. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  474. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  475. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  476. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  477. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  478. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  479. .find_pll = intel_find_best_PLL,
  480. };
  481. static const intel_limit_t intel_limits_pineview_lvds = {
  482. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  483. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  484. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  485. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  486. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  487. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  488. .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
  489. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  490. /* Pineview only supports single-channel mode. */
  491. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  492. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  493. .find_pll = intel_find_best_PLL,
  494. };
  495. static const intel_limit_t intel_limits_ironlake_dac = {
  496. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  497. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  498. .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
  499. .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
  500. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  501. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  502. .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
  503. .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
  504. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  505. .p2_slow = IRONLAKE_DAC_P2_SLOW,
  506. .p2_fast = IRONLAKE_DAC_P2_FAST },
  507. .find_pll = intel_g4x_find_best_PLL,
  508. };
  509. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  510. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  511. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  512. .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
  513. .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
  514. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  515. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  516. .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
  517. .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
  518. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  519. .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
  520. .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
  521. .find_pll = intel_g4x_find_best_PLL,
  522. };
  523. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  524. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  525. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  526. .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
  527. .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
  528. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  529. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  530. .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
  531. .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
  532. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  533. .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
  534. .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
  535. .find_pll = intel_g4x_find_best_PLL,
  536. };
  537. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  538. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  539. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  540. .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
  541. .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
  542. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  543. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  544. .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
  545. .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
  546. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  547. .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
  548. .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
  549. .find_pll = intel_g4x_find_best_PLL,
  550. };
  551. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  552. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  553. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  554. .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
  555. .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
  556. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  557. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  558. .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
  559. .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
  560. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  561. .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
  562. .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
  563. .find_pll = intel_g4x_find_best_PLL,
  564. };
  565. static const intel_limit_t intel_limits_ironlake_display_port = {
  566. .dot = { .min = IRONLAKE_DOT_MIN,
  567. .max = IRONLAKE_DOT_MAX },
  568. .vco = { .min = IRONLAKE_VCO_MIN,
  569. .max = IRONLAKE_VCO_MAX},
  570. .n = { .min = IRONLAKE_DP_N_MIN,
  571. .max = IRONLAKE_DP_N_MAX },
  572. .m = { .min = IRONLAKE_DP_M_MIN,
  573. .max = IRONLAKE_DP_M_MAX },
  574. .m1 = { .min = IRONLAKE_M1_MIN,
  575. .max = IRONLAKE_M1_MAX },
  576. .m2 = { .min = IRONLAKE_M2_MIN,
  577. .max = IRONLAKE_M2_MAX },
  578. .p = { .min = IRONLAKE_DP_P_MIN,
  579. .max = IRONLAKE_DP_P_MAX },
  580. .p1 = { .min = IRONLAKE_DP_P1_MIN,
  581. .max = IRONLAKE_DP_P1_MAX},
  582. .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
  583. .p2_slow = IRONLAKE_DP_P2_SLOW,
  584. .p2_fast = IRONLAKE_DP_P2_FAST },
  585. .find_pll = intel_find_pll_ironlake_dp,
  586. };
  587. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
  588. {
  589. struct drm_device *dev = crtc->dev;
  590. struct drm_i915_private *dev_priv = dev->dev_private;
  591. const intel_limit_t *limit;
  592. int refclk = 120;
  593. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  594. if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
  595. refclk = 100;
  596. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  597. LVDS_CLKB_POWER_UP) {
  598. /* LVDS dual channel */
  599. if (refclk == 100)
  600. limit = &intel_limits_ironlake_dual_lvds_100m;
  601. else
  602. limit = &intel_limits_ironlake_dual_lvds;
  603. } else {
  604. if (refclk == 100)
  605. limit = &intel_limits_ironlake_single_lvds_100m;
  606. else
  607. limit = &intel_limits_ironlake_single_lvds;
  608. }
  609. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  610. HAS_eDP)
  611. limit = &intel_limits_ironlake_display_port;
  612. else
  613. limit = &intel_limits_ironlake_dac;
  614. return limit;
  615. }
  616. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  617. {
  618. struct drm_device *dev = crtc->dev;
  619. struct drm_i915_private *dev_priv = dev->dev_private;
  620. const intel_limit_t *limit;
  621. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  622. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  623. LVDS_CLKB_POWER_UP)
  624. /* LVDS with dual channel */
  625. limit = &intel_limits_g4x_dual_channel_lvds;
  626. else
  627. /* LVDS with dual channel */
  628. limit = &intel_limits_g4x_single_channel_lvds;
  629. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  630. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  631. limit = &intel_limits_g4x_hdmi;
  632. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  633. limit = &intel_limits_g4x_sdvo;
  634. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  635. limit = &intel_limits_g4x_display_port;
  636. } else /* The option is for other outputs */
  637. limit = &intel_limits_i9xx_sdvo;
  638. return limit;
  639. }
  640. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  641. {
  642. struct drm_device *dev = crtc->dev;
  643. const intel_limit_t *limit;
  644. if (HAS_PCH_SPLIT(dev))
  645. limit = intel_ironlake_limit(crtc);
  646. else if (IS_G4X(dev)) {
  647. limit = intel_g4x_limit(crtc);
  648. } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
  649. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  650. limit = &intel_limits_i9xx_lvds;
  651. else
  652. limit = &intel_limits_i9xx_sdvo;
  653. } else if (IS_PINEVIEW(dev)) {
  654. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  655. limit = &intel_limits_pineview_lvds;
  656. else
  657. limit = &intel_limits_pineview_sdvo;
  658. } else {
  659. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  660. limit = &intel_limits_i8xx_lvds;
  661. else
  662. limit = &intel_limits_i8xx_dvo;
  663. }
  664. return limit;
  665. }
  666. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  667. static void pineview_clock(int refclk, intel_clock_t *clock)
  668. {
  669. clock->m = clock->m2 + 2;
  670. clock->p = clock->p1 * clock->p2;
  671. clock->vco = refclk * clock->m / clock->n;
  672. clock->dot = clock->vco / clock->p;
  673. }
  674. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  675. {
  676. if (IS_PINEVIEW(dev)) {
  677. pineview_clock(refclk, clock);
  678. return;
  679. }
  680. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  681. clock->p = clock->p1 * clock->p2;
  682. clock->vco = refclk * clock->m / (clock->n + 2);
  683. clock->dot = clock->vco / clock->p;
  684. }
  685. /**
  686. * Returns whether any output on the specified pipe is of the specified type
  687. */
  688. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  689. {
  690. struct drm_device *dev = crtc->dev;
  691. struct drm_mode_config *mode_config = &dev->mode_config;
  692. struct drm_encoder *l_entry;
  693. list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
  694. if (l_entry && l_entry->crtc == crtc) {
  695. struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
  696. if (intel_encoder->type == type)
  697. return true;
  698. }
  699. }
  700. return false;
  701. }
  702. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  703. /**
  704. * Returns whether the given set of divisors are valid for a given refclk with
  705. * the given connectors.
  706. */
  707. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  708. {
  709. const intel_limit_t *limit = intel_limit (crtc);
  710. struct drm_device *dev = crtc->dev;
  711. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  712. INTELPllInvalid ("p1 out of range\n");
  713. if (clock->p < limit->p.min || limit->p.max < clock->p)
  714. INTELPllInvalid ("p out of range\n");
  715. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  716. INTELPllInvalid ("m2 out of range\n");
  717. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  718. INTELPllInvalid ("m1 out of range\n");
  719. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  720. INTELPllInvalid ("m1 <= m2\n");
  721. if (clock->m < limit->m.min || limit->m.max < clock->m)
  722. INTELPllInvalid ("m out of range\n");
  723. if (clock->n < limit->n.min || limit->n.max < clock->n)
  724. INTELPllInvalid ("n out of range\n");
  725. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  726. INTELPllInvalid ("vco out of range\n");
  727. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  728. * connector, etc., rather than just a single range.
  729. */
  730. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  731. INTELPllInvalid ("dot out of range\n");
  732. return true;
  733. }
  734. static bool
  735. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  736. int target, int refclk, intel_clock_t *best_clock)
  737. {
  738. struct drm_device *dev = crtc->dev;
  739. struct drm_i915_private *dev_priv = dev->dev_private;
  740. intel_clock_t clock;
  741. int err = target;
  742. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  743. (I915_READ(LVDS)) != 0) {
  744. /*
  745. * For LVDS, if the panel is on, just rely on its current
  746. * settings for dual-channel. We haven't figured out how to
  747. * reliably set up different single/dual channel state, if we
  748. * even can.
  749. */
  750. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  751. LVDS_CLKB_POWER_UP)
  752. clock.p2 = limit->p2.p2_fast;
  753. else
  754. clock.p2 = limit->p2.p2_slow;
  755. } else {
  756. if (target < limit->p2.dot_limit)
  757. clock.p2 = limit->p2.p2_slow;
  758. else
  759. clock.p2 = limit->p2.p2_fast;
  760. }
  761. memset (best_clock, 0, sizeof (*best_clock));
  762. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  763. clock.m1++) {
  764. for (clock.m2 = limit->m2.min;
  765. clock.m2 <= limit->m2.max; clock.m2++) {
  766. /* m1 is always 0 in Pineview */
  767. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  768. break;
  769. for (clock.n = limit->n.min;
  770. clock.n <= limit->n.max; clock.n++) {
  771. for (clock.p1 = limit->p1.min;
  772. clock.p1 <= limit->p1.max; clock.p1++) {
  773. int this_err;
  774. intel_clock(dev, refclk, &clock);
  775. if (!intel_PLL_is_valid(crtc, &clock))
  776. continue;
  777. this_err = abs(clock.dot - target);
  778. if (this_err < err) {
  779. *best_clock = clock;
  780. err = this_err;
  781. }
  782. }
  783. }
  784. }
  785. }
  786. return (err != target);
  787. }
  788. static bool
  789. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  790. int target, int refclk, intel_clock_t *best_clock)
  791. {
  792. struct drm_device *dev = crtc->dev;
  793. struct drm_i915_private *dev_priv = dev->dev_private;
  794. intel_clock_t clock;
  795. int max_n;
  796. bool found;
  797. /* approximately equals target * 0.00488 */
  798. int err_most = (target >> 8) + (target >> 10);
  799. found = false;
  800. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  801. int lvds_reg;
  802. if (HAS_PCH_SPLIT(dev))
  803. lvds_reg = PCH_LVDS;
  804. else
  805. lvds_reg = LVDS;
  806. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  807. LVDS_CLKB_POWER_UP)
  808. clock.p2 = limit->p2.p2_fast;
  809. else
  810. clock.p2 = limit->p2.p2_slow;
  811. } else {
  812. if (target < limit->p2.dot_limit)
  813. clock.p2 = limit->p2.p2_slow;
  814. else
  815. clock.p2 = limit->p2.p2_fast;
  816. }
  817. memset(best_clock, 0, sizeof(*best_clock));
  818. max_n = limit->n.max;
  819. /* based on hardware requirement, prefer smaller n to precision */
  820. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  821. /* based on hardware requirement, prefere larger m1,m2 */
  822. for (clock.m1 = limit->m1.max;
  823. clock.m1 >= limit->m1.min; clock.m1--) {
  824. for (clock.m2 = limit->m2.max;
  825. clock.m2 >= limit->m2.min; clock.m2--) {
  826. for (clock.p1 = limit->p1.max;
  827. clock.p1 >= limit->p1.min; clock.p1--) {
  828. int this_err;
  829. intel_clock(dev, refclk, &clock);
  830. if (!intel_PLL_is_valid(crtc, &clock))
  831. continue;
  832. this_err = abs(clock.dot - target) ;
  833. if (this_err < err_most) {
  834. *best_clock = clock;
  835. err_most = this_err;
  836. max_n = clock.n;
  837. found = true;
  838. }
  839. }
  840. }
  841. }
  842. }
  843. return found;
  844. }
  845. static bool
  846. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  847. int target, int refclk, intel_clock_t *best_clock)
  848. {
  849. struct drm_device *dev = crtc->dev;
  850. intel_clock_t clock;
  851. /* return directly when it is eDP */
  852. if (HAS_eDP)
  853. return true;
  854. if (target < 200000) {
  855. clock.n = 1;
  856. clock.p1 = 2;
  857. clock.p2 = 10;
  858. clock.m1 = 12;
  859. clock.m2 = 9;
  860. } else {
  861. clock.n = 2;
  862. clock.p1 = 1;
  863. clock.p2 = 10;
  864. clock.m1 = 14;
  865. clock.m2 = 8;
  866. }
  867. intel_clock(dev, refclk, &clock);
  868. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  869. return true;
  870. }
  871. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  872. static bool
  873. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  874. int target, int refclk, intel_clock_t *best_clock)
  875. {
  876. intel_clock_t clock;
  877. if (target < 200000) {
  878. clock.p1 = 2;
  879. clock.p2 = 10;
  880. clock.n = 2;
  881. clock.m1 = 23;
  882. clock.m2 = 8;
  883. } else {
  884. clock.p1 = 1;
  885. clock.p2 = 10;
  886. clock.n = 1;
  887. clock.m1 = 14;
  888. clock.m2 = 2;
  889. }
  890. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  891. clock.p = (clock.p1 * clock.p2);
  892. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  893. clock.vco = 0;
  894. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  895. return true;
  896. }
  897. void
  898. intel_wait_for_vblank(struct drm_device *dev)
  899. {
  900. /* Wait for 20ms, i.e. one cycle at 50hz. */
  901. msleep(20);
  902. }
  903. /* Parameters have changed, update FBC info */
  904. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  905. {
  906. struct drm_device *dev = crtc->dev;
  907. struct drm_i915_private *dev_priv = dev->dev_private;
  908. struct drm_framebuffer *fb = crtc->fb;
  909. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  910. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  911. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  912. int plane, i;
  913. u32 fbc_ctl, fbc_ctl2;
  914. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  915. if (fb->pitch < dev_priv->cfb_pitch)
  916. dev_priv->cfb_pitch = fb->pitch;
  917. /* FBC_CTL wants 64B units */
  918. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  919. dev_priv->cfb_fence = obj_priv->fence_reg;
  920. dev_priv->cfb_plane = intel_crtc->plane;
  921. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  922. /* Clear old tags */
  923. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  924. I915_WRITE(FBC_TAG + (i * 4), 0);
  925. /* Set it up... */
  926. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  927. if (obj_priv->tiling_mode != I915_TILING_NONE)
  928. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  929. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  930. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  931. /* enable it... */
  932. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  933. if (IS_I945GM(dev))
  934. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  935. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  936. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  937. if (obj_priv->tiling_mode != I915_TILING_NONE)
  938. fbc_ctl |= dev_priv->cfb_fence;
  939. I915_WRITE(FBC_CONTROL, fbc_ctl);
  940. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  941. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  942. }
  943. void i8xx_disable_fbc(struct drm_device *dev)
  944. {
  945. struct drm_i915_private *dev_priv = dev->dev_private;
  946. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  947. u32 fbc_ctl;
  948. if (!I915_HAS_FBC(dev))
  949. return;
  950. if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
  951. return; /* Already off, just return */
  952. /* Disable compression */
  953. fbc_ctl = I915_READ(FBC_CONTROL);
  954. fbc_ctl &= ~FBC_CTL_EN;
  955. I915_WRITE(FBC_CONTROL, fbc_ctl);
  956. /* Wait for compressing bit to clear */
  957. while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
  958. if (time_after(jiffies, timeout)) {
  959. DRM_DEBUG_DRIVER("FBC idle timed out\n");
  960. break;
  961. }
  962. ; /* do nothing */
  963. }
  964. intel_wait_for_vblank(dev);
  965. DRM_DEBUG_KMS("disabled FBC\n");
  966. }
  967. static bool i8xx_fbc_enabled(struct drm_device *dev)
  968. {
  969. struct drm_i915_private *dev_priv = dev->dev_private;
  970. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  971. }
  972. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  973. {
  974. struct drm_device *dev = crtc->dev;
  975. struct drm_i915_private *dev_priv = dev->dev_private;
  976. struct drm_framebuffer *fb = crtc->fb;
  977. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  978. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  979. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  980. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  981. DPFC_CTL_PLANEB);
  982. unsigned long stall_watermark = 200;
  983. u32 dpfc_ctl;
  984. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  985. dev_priv->cfb_fence = obj_priv->fence_reg;
  986. dev_priv->cfb_plane = intel_crtc->plane;
  987. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  988. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  989. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  990. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  991. } else {
  992. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  993. }
  994. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  995. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  996. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  997. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  998. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  999. /* enable it... */
  1000. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1001. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1002. }
  1003. void g4x_disable_fbc(struct drm_device *dev)
  1004. {
  1005. struct drm_i915_private *dev_priv = dev->dev_private;
  1006. u32 dpfc_ctl;
  1007. /* Disable compression */
  1008. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1009. dpfc_ctl &= ~DPFC_CTL_EN;
  1010. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1011. intel_wait_for_vblank(dev);
  1012. DRM_DEBUG_KMS("disabled FBC\n");
  1013. }
  1014. static bool g4x_fbc_enabled(struct drm_device *dev)
  1015. {
  1016. struct drm_i915_private *dev_priv = dev->dev_private;
  1017. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1018. }
  1019. bool intel_fbc_enabled(struct drm_device *dev)
  1020. {
  1021. struct drm_i915_private *dev_priv = dev->dev_private;
  1022. if (!dev_priv->display.fbc_enabled)
  1023. return false;
  1024. return dev_priv->display.fbc_enabled(dev);
  1025. }
  1026. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1027. {
  1028. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1029. if (!dev_priv->display.enable_fbc)
  1030. return;
  1031. dev_priv->display.enable_fbc(crtc, interval);
  1032. }
  1033. void intel_disable_fbc(struct drm_device *dev)
  1034. {
  1035. struct drm_i915_private *dev_priv = dev->dev_private;
  1036. if (!dev_priv->display.disable_fbc)
  1037. return;
  1038. dev_priv->display.disable_fbc(dev);
  1039. }
  1040. /**
  1041. * intel_update_fbc - enable/disable FBC as needed
  1042. * @crtc: CRTC to point the compressor at
  1043. * @mode: mode in use
  1044. *
  1045. * Set up the framebuffer compression hardware at mode set time. We
  1046. * enable it if possible:
  1047. * - plane A only (on pre-965)
  1048. * - no pixel mulitply/line duplication
  1049. * - no alpha buffer discard
  1050. * - no dual wide
  1051. * - framebuffer <= 2048 in width, 1536 in height
  1052. *
  1053. * We can't assume that any compression will take place (worst case),
  1054. * so the compressed buffer has to be the same size as the uncompressed
  1055. * one. It also must reside (along with the line length buffer) in
  1056. * stolen memory.
  1057. *
  1058. * We need to enable/disable FBC on a global basis.
  1059. */
  1060. static void intel_update_fbc(struct drm_crtc *crtc,
  1061. struct drm_display_mode *mode)
  1062. {
  1063. struct drm_device *dev = crtc->dev;
  1064. struct drm_i915_private *dev_priv = dev->dev_private;
  1065. struct drm_framebuffer *fb = crtc->fb;
  1066. struct intel_framebuffer *intel_fb;
  1067. struct drm_i915_gem_object *obj_priv;
  1068. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1069. int plane = intel_crtc->plane;
  1070. if (!i915_powersave)
  1071. return;
  1072. if (!I915_HAS_FBC(dev))
  1073. return;
  1074. if (!crtc->fb)
  1075. return;
  1076. intel_fb = to_intel_framebuffer(fb);
  1077. obj_priv = to_intel_bo(intel_fb->obj);
  1078. /*
  1079. * If FBC is already on, we just have to verify that we can
  1080. * keep it that way...
  1081. * Need to disable if:
  1082. * - changing FBC params (stride, fence, mode)
  1083. * - new fb is too large to fit in compressed buffer
  1084. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1085. */
  1086. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1087. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1088. "compression\n");
  1089. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1090. goto out_disable;
  1091. }
  1092. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1093. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1094. DRM_DEBUG_KMS("mode incompatible with compression, "
  1095. "disabling\n");
  1096. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1097. goto out_disable;
  1098. }
  1099. if ((mode->hdisplay > 2048) ||
  1100. (mode->vdisplay > 1536)) {
  1101. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1102. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1103. goto out_disable;
  1104. }
  1105. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1106. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1107. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1108. goto out_disable;
  1109. }
  1110. if (obj_priv->tiling_mode != I915_TILING_X) {
  1111. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1112. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1113. goto out_disable;
  1114. }
  1115. if (intel_fbc_enabled(dev)) {
  1116. /* We can re-enable it in this case, but need to update pitch */
  1117. if ((fb->pitch > dev_priv->cfb_pitch) ||
  1118. (obj_priv->fence_reg != dev_priv->cfb_fence) ||
  1119. (plane != dev_priv->cfb_plane))
  1120. intel_disable_fbc(dev);
  1121. }
  1122. /* Now try to turn it back on if possible */
  1123. if (!intel_fbc_enabled(dev))
  1124. intel_enable_fbc(crtc, 500);
  1125. return;
  1126. out_disable:
  1127. /* Multiple disables should be harmless */
  1128. if (intel_fbc_enabled(dev)) {
  1129. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1130. intel_disable_fbc(dev);
  1131. }
  1132. }
  1133. static int
  1134. intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
  1135. {
  1136. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1137. u32 alignment;
  1138. int ret;
  1139. switch (obj_priv->tiling_mode) {
  1140. case I915_TILING_NONE:
  1141. alignment = 64 * 1024;
  1142. break;
  1143. case I915_TILING_X:
  1144. /* pin() will align the object as required by fence */
  1145. alignment = 0;
  1146. break;
  1147. case I915_TILING_Y:
  1148. /* FIXME: Is this true? */
  1149. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1150. return -EINVAL;
  1151. default:
  1152. BUG();
  1153. }
  1154. ret = i915_gem_object_pin(obj, alignment);
  1155. if (ret != 0)
  1156. return ret;
  1157. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1158. * fence, whereas 965+ only requires a fence if using
  1159. * framebuffer compression. For simplicity, we always install
  1160. * a fence as the cost is not that onerous.
  1161. */
  1162. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1163. obj_priv->tiling_mode != I915_TILING_NONE) {
  1164. ret = i915_gem_object_get_fence_reg(obj);
  1165. if (ret != 0) {
  1166. i915_gem_object_unpin(obj);
  1167. return ret;
  1168. }
  1169. }
  1170. return 0;
  1171. }
  1172. static int
  1173. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1174. struct drm_framebuffer *old_fb)
  1175. {
  1176. struct drm_device *dev = crtc->dev;
  1177. struct drm_i915_private *dev_priv = dev->dev_private;
  1178. struct drm_i915_master_private *master_priv;
  1179. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1180. struct intel_framebuffer *intel_fb;
  1181. struct drm_i915_gem_object *obj_priv;
  1182. struct drm_gem_object *obj;
  1183. int pipe = intel_crtc->pipe;
  1184. int plane = intel_crtc->plane;
  1185. unsigned long Start, Offset;
  1186. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1187. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1188. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1189. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1190. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1191. u32 dspcntr;
  1192. int ret;
  1193. /* no fb bound */
  1194. if (!crtc->fb) {
  1195. DRM_DEBUG_KMS("No FB bound\n");
  1196. return 0;
  1197. }
  1198. switch (plane) {
  1199. case 0:
  1200. case 1:
  1201. break;
  1202. default:
  1203. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1204. return -EINVAL;
  1205. }
  1206. intel_fb = to_intel_framebuffer(crtc->fb);
  1207. obj = intel_fb->obj;
  1208. obj_priv = to_intel_bo(obj);
  1209. mutex_lock(&dev->struct_mutex);
  1210. ret = intel_pin_and_fence_fb_obj(dev, obj);
  1211. if (ret != 0) {
  1212. mutex_unlock(&dev->struct_mutex);
  1213. return ret;
  1214. }
  1215. ret = i915_gem_object_set_to_display_plane(obj);
  1216. if (ret != 0) {
  1217. i915_gem_object_unpin(obj);
  1218. mutex_unlock(&dev->struct_mutex);
  1219. return ret;
  1220. }
  1221. dspcntr = I915_READ(dspcntr_reg);
  1222. /* Mask out pixel format bits in case we change it */
  1223. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1224. switch (crtc->fb->bits_per_pixel) {
  1225. case 8:
  1226. dspcntr |= DISPPLANE_8BPP;
  1227. break;
  1228. case 16:
  1229. if (crtc->fb->depth == 15)
  1230. dspcntr |= DISPPLANE_15_16BPP;
  1231. else
  1232. dspcntr |= DISPPLANE_16BPP;
  1233. break;
  1234. case 24:
  1235. case 32:
  1236. if (crtc->fb->depth == 30)
  1237. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1238. else
  1239. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1240. break;
  1241. default:
  1242. DRM_ERROR("Unknown color depth\n");
  1243. i915_gem_object_unpin(obj);
  1244. mutex_unlock(&dev->struct_mutex);
  1245. return -EINVAL;
  1246. }
  1247. if (IS_I965G(dev)) {
  1248. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1249. dspcntr |= DISPPLANE_TILED;
  1250. else
  1251. dspcntr &= ~DISPPLANE_TILED;
  1252. }
  1253. if (HAS_PCH_SPLIT(dev))
  1254. /* must disable */
  1255. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1256. I915_WRITE(dspcntr_reg, dspcntr);
  1257. Start = obj_priv->gtt_offset;
  1258. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  1259. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1260. Start, Offset, x, y, crtc->fb->pitch);
  1261. I915_WRITE(dspstride, crtc->fb->pitch);
  1262. if (IS_I965G(dev)) {
  1263. I915_WRITE(dspbase, Offset);
  1264. I915_READ(dspbase);
  1265. I915_WRITE(dspsurf, Start);
  1266. I915_READ(dspsurf);
  1267. I915_WRITE(dsptileoff, (y << 16) | x);
  1268. } else {
  1269. I915_WRITE(dspbase, Start + Offset);
  1270. I915_READ(dspbase);
  1271. }
  1272. if ((IS_I965G(dev) || plane == 0))
  1273. intel_update_fbc(crtc, &crtc->mode);
  1274. intel_wait_for_vblank(dev);
  1275. if (old_fb) {
  1276. intel_fb = to_intel_framebuffer(old_fb);
  1277. obj_priv = to_intel_bo(intel_fb->obj);
  1278. i915_gem_object_unpin(intel_fb->obj);
  1279. }
  1280. intel_increase_pllclock(crtc, true);
  1281. mutex_unlock(&dev->struct_mutex);
  1282. if (!dev->primary->master)
  1283. return 0;
  1284. master_priv = dev->primary->master->driver_priv;
  1285. if (!master_priv->sarea_priv)
  1286. return 0;
  1287. if (pipe) {
  1288. master_priv->sarea_priv->pipeB_x = x;
  1289. master_priv->sarea_priv->pipeB_y = y;
  1290. } else {
  1291. master_priv->sarea_priv->pipeA_x = x;
  1292. master_priv->sarea_priv->pipeA_y = y;
  1293. }
  1294. return 0;
  1295. }
  1296. /* Disable the VGA plane that we never use */
  1297. static void i915_disable_vga (struct drm_device *dev)
  1298. {
  1299. struct drm_i915_private *dev_priv = dev->dev_private;
  1300. u8 sr1;
  1301. u32 vga_reg;
  1302. if (HAS_PCH_SPLIT(dev))
  1303. vga_reg = CPU_VGACNTRL;
  1304. else
  1305. vga_reg = VGACNTRL;
  1306. if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
  1307. return;
  1308. I915_WRITE8(VGA_SR_INDEX, 1);
  1309. sr1 = I915_READ8(VGA_SR_DATA);
  1310. I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
  1311. udelay(100);
  1312. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  1313. }
  1314. static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
  1315. {
  1316. struct drm_device *dev = crtc->dev;
  1317. struct drm_i915_private *dev_priv = dev->dev_private;
  1318. u32 dpa_ctl;
  1319. DRM_DEBUG_KMS("\n");
  1320. dpa_ctl = I915_READ(DP_A);
  1321. dpa_ctl &= ~DP_PLL_ENABLE;
  1322. I915_WRITE(DP_A, dpa_ctl);
  1323. }
  1324. static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
  1325. {
  1326. struct drm_device *dev = crtc->dev;
  1327. struct drm_i915_private *dev_priv = dev->dev_private;
  1328. u32 dpa_ctl;
  1329. dpa_ctl = I915_READ(DP_A);
  1330. dpa_ctl |= DP_PLL_ENABLE;
  1331. I915_WRITE(DP_A, dpa_ctl);
  1332. udelay(200);
  1333. }
  1334. static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
  1335. {
  1336. struct drm_device *dev = crtc->dev;
  1337. struct drm_i915_private *dev_priv = dev->dev_private;
  1338. u32 dpa_ctl;
  1339. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1340. dpa_ctl = I915_READ(DP_A);
  1341. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1342. if (clock < 200000) {
  1343. u32 temp;
  1344. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1345. /* workaround for 160Mhz:
  1346. 1) program 0x4600c bits 15:0 = 0x8124
  1347. 2) program 0x46010 bit 0 = 1
  1348. 3) program 0x46034 bit 24 = 1
  1349. 4) program 0x64000 bit 14 = 1
  1350. */
  1351. temp = I915_READ(0x4600c);
  1352. temp &= 0xffff0000;
  1353. I915_WRITE(0x4600c, temp | 0x8124);
  1354. temp = I915_READ(0x46010);
  1355. I915_WRITE(0x46010, temp | 1);
  1356. temp = I915_READ(0x46034);
  1357. I915_WRITE(0x46034, temp | (1 << 24));
  1358. } else {
  1359. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1360. }
  1361. I915_WRITE(DP_A, dpa_ctl);
  1362. udelay(500);
  1363. }
  1364. /* The FDI link training functions for ILK/Ibexpeak. */
  1365. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1366. {
  1367. struct drm_device *dev = crtc->dev;
  1368. struct drm_i915_private *dev_priv = dev->dev_private;
  1369. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1370. int pipe = intel_crtc->pipe;
  1371. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1372. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1373. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1374. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1375. u32 temp, tries = 0;
  1376. /* enable CPU FDI TX and PCH FDI RX */
  1377. temp = I915_READ(fdi_tx_reg);
  1378. temp |= FDI_TX_ENABLE;
  1379. temp &= ~(7 << 19);
  1380. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1381. temp &= ~FDI_LINK_TRAIN_NONE;
  1382. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1383. I915_WRITE(fdi_tx_reg, temp);
  1384. I915_READ(fdi_tx_reg);
  1385. temp = I915_READ(fdi_rx_reg);
  1386. temp &= ~FDI_LINK_TRAIN_NONE;
  1387. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1388. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1389. I915_READ(fdi_rx_reg);
  1390. udelay(150);
  1391. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1392. for train result */
  1393. temp = I915_READ(fdi_rx_imr_reg);
  1394. temp &= ~FDI_RX_SYMBOL_LOCK;
  1395. temp &= ~FDI_RX_BIT_LOCK;
  1396. I915_WRITE(fdi_rx_imr_reg, temp);
  1397. I915_READ(fdi_rx_imr_reg);
  1398. udelay(150);
  1399. for (;;) {
  1400. temp = I915_READ(fdi_rx_iir_reg);
  1401. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1402. if ((temp & FDI_RX_BIT_LOCK)) {
  1403. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1404. I915_WRITE(fdi_rx_iir_reg,
  1405. temp | FDI_RX_BIT_LOCK);
  1406. break;
  1407. }
  1408. tries++;
  1409. if (tries > 5) {
  1410. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1411. break;
  1412. }
  1413. }
  1414. /* Train 2 */
  1415. temp = I915_READ(fdi_tx_reg);
  1416. temp &= ~FDI_LINK_TRAIN_NONE;
  1417. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1418. I915_WRITE(fdi_tx_reg, temp);
  1419. temp = I915_READ(fdi_rx_reg);
  1420. temp &= ~FDI_LINK_TRAIN_NONE;
  1421. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1422. I915_WRITE(fdi_rx_reg, temp);
  1423. udelay(150);
  1424. tries = 0;
  1425. for (;;) {
  1426. temp = I915_READ(fdi_rx_iir_reg);
  1427. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1428. if (temp & FDI_RX_SYMBOL_LOCK) {
  1429. I915_WRITE(fdi_rx_iir_reg,
  1430. temp | FDI_RX_SYMBOL_LOCK);
  1431. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1432. break;
  1433. }
  1434. tries++;
  1435. if (tries > 5) {
  1436. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1437. break;
  1438. }
  1439. }
  1440. DRM_DEBUG_KMS("FDI train done\n");
  1441. }
  1442. static int snb_b_fdi_train_param [] = {
  1443. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1444. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1445. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1446. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1447. };
  1448. /* The FDI link training functions for SNB/Cougarpoint. */
  1449. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1450. {
  1451. struct drm_device *dev = crtc->dev;
  1452. struct drm_i915_private *dev_priv = dev->dev_private;
  1453. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1454. int pipe = intel_crtc->pipe;
  1455. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1456. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1457. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1458. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1459. u32 temp, i;
  1460. /* enable CPU FDI TX and PCH FDI RX */
  1461. temp = I915_READ(fdi_tx_reg);
  1462. temp |= FDI_TX_ENABLE;
  1463. temp &= ~(7 << 19);
  1464. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1465. temp &= ~FDI_LINK_TRAIN_NONE;
  1466. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1467. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1468. /* SNB-B */
  1469. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1470. I915_WRITE(fdi_tx_reg, temp);
  1471. I915_READ(fdi_tx_reg);
  1472. temp = I915_READ(fdi_rx_reg);
  1473. if (HAS_PCH_CPT(dev)) {
  1474. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1475. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1476. } else {
  1477. temp &= ~FDI_LINK_TRAIN_NONE;
  1478. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1479. }
  1480. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1481. I915_READ(fdi_rx_reg);
  1482. udelay(150);
  1483. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1484. for train result */
  1485. temp = I915_READ(fdi_rx_imr_reg);
  1486. temp &= ~FDI_RX_SYMBOL_LOCK;
  1487. temp &= ~FDI_RX_BIT_LOCK;
  1488. I915_WRITE(fdi_rx_imr_reg, temp);
  1489. I915_READ(fdi_rx_imr_reg);
  1490. udelay(150);
  1491. for (i = 0; i < 4; i++ ) {
  1492. temp = I915_READ(fdi_tx_reg);
  1493. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1494. temp |= snb_b_fdi_train_param[i];
  1495. I915_WRITE(fdi_tx_reg, temp);
  1496. udelay(500);
  1497. temp = I915_READ(fdi_rx_iir_reg);
  1498. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1499. if (temp & FDI_RX_BIT_LOCK) {
  1500. I915_WRITE(fdi_rx_iir_reg,
  1501. temp | FDI_RX_BIT_LOCK);
  1502. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1503. break;
  1504. }
  1505. }
  1506. if (i == 4)
  1507. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1508. /* Train 2 */
  1509. temp = I915_READ(fdi_tx_reg);
  1510. temp &= ~FDI_LINK_TRAIN_NONE;
  1511. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1512. if (IS_GEN6(dev)) {
  1513. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1514. /* SNB-B */
  1515. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1516. }
  1517. I915_WRITE(fdi_tx_reg, temp);
  1518. temp = I915_READ(fdi_rx_reg);
  1519. if (HAS_PCH_CPT(dev)) {
  1520. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1521. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  1522. } else {
  1523. temp &= ~FDI_LINK_TRAIN_NONE;
  1524. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1525. }
  1526. I915_WRITE(fdi_rx_reg, temp);
  1527. udelay(150);
  1528. for (i = 0; i < 4; i++ ) {
  1529. temp = I915_READ(fdi_tx_reg);
  1530. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1531. temp |= snb_b_fdi_train_param[i];
  1532. I915_WRITE(fdi_tx_reg, temp);
  1533. udelay(500);
  1534. temp = I915_READ(fdi_rx_iir_reg);
  1535. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1536. if (temp & FDI_RX_SYMBOL_LOCK) {
  1537. I915_WRITE(fdi_rx_iir_reg,
  1538. temp | FDI_RX_SYMBOL_LOCK);
  1539. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1540. break;
  1541. }
  1542. }
  1543. if (i == 4)
  1544. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1545. DRM_DEBUG_KMS("FDI train done.\n");
  1546. }
  1547. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  1548. {
  1549. struct drm_device *dev = crtc->dev;
  1550. struct drm_i915_private *dev_priv = dev->dev_private;
  1551. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1552. int pipe = intel_crtc->pipe;
  1553. int plane = intel_crtc->plane;
  1554. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1555. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1556. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1557. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1558. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1559. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1560. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1561. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  1562. int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
  1563. int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
  1564. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1565. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1566. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1567. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1568. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1569. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1570. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1571. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1572. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1573. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1574. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1575. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1576. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  1577. u32 temp;
  1578. int n;
  1579. u32 pipe_bpc;
  1580. temp = I915_READ(pipeconf_reg);
  1581. pipe_bpc = temp & PIPE_BPC_MASK;
  1582. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1583. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1584. */
  1585. switch (mode) {
  1586. case DRM_MODE_DPMS_ON:
  1587. case DRM_MODE_DPMS_STANDBY:
  1588. case DRM_MODE_DPMS_SUSPEND:
  1589. DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
  1590. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1591. temp = I915_READ(PCH_LVDS);
  1592. if ((temp & LVDS_PORT_EN) == 0) {
  1593. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  1594. POSTING_READ(PCH_LVDS);
  1595. }
  1596. }
  1597. if (HAS_eDP) {
  1598. /* enable eDP PLL */
  1599. ironlake_enable_pll_edp(crtc);
  1600. } else {
  1601. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1602. temp = I915_READ(fdi_rx_reg);
  1603. /*
  1604. * make the BPC in FDI Rx be consistent with that in
  1605. * pipeconf reg.
  1606. */
  1607. temp &= ~(0x7 << 16);
  1608. temp |= (pipe_bpc << 11);
  1609. temp &= ~(7 << 19);
  1610. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1611. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  1612. I915_READ(fdi_rx_reg);
  1613. udelay(200);
  1614. /* Switch from Rawclk to PCDclk */
  1615. temp = I915_READ(fdi_rx_reg);
  1616. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  1617. I915_READ(fdi_rx_reg);
  1618. udelay(200);
  1619. /* Enable CPU FDI TX PLL, always on for Ironlake */
  1620. temp = I915_READ(fdi_tx_reg);
  1621. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1622. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1623. I915_READ(fdi_tx_reg);
  1624. udelay(100);
  1625. }
  1626. }
  1627. /* Enable panel fitting for LVDS */
  1628. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1629. temp = I915_READ(pf_ctl_reg);
  1630. I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
  1631. /* currently full aspect */
  1632. I915_WRITE(pf_win_pos, 0);
  1633. I915_WRITE(pf_win_size,
  1634. (dev_priv->panel_fixed_mode->hdisplay << 16) |
  1635. (dev_priv->panel_fixed_mode->vdisplay));
  1636. }
  1637. /* Enable CPU pipe */
  1638. temp = I915_READ(pipeconf_reg);
  1639. if ((temp & PIPEACONF_ENABLE) == 0) {
  1640. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1641. I915_READ(pipeconf_reg);
  1642. udelay(100);
  1643. }
  1644. /* configure and enable CPU plane */
  1645. temp = I915_READ(dspcntr_reg);
  1646. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1647. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1648. /* Flush the plane changes */
  1649. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1650. }
  1651. if (!HAS_eDP) {
  1652. /* For PCH output, training FDI link */
  1653. if (IS_GEN6(dev))
  1654. gen6_fdi_link_train(crtc);
  1655. else
  1656. ironlake_fdi_link_train(crtc);
  1657. /* enable PCH DPLL */
  1658. temp = I915_READ(pch_dpll_reg);
  1659. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1660. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1661. I915_READ(pch_dpll_reg);
  1662. }
  1663. udelay(200);
  1664. if (HAS_PCH_CPT(dev)) {
  1665. /* Be sure PCH DPLL SEL is set */
  1666. temp = I915_READ(PCH_DPLL_SEL);
  1667. if (trans_dpll_sel == 0 &&
  1668. (temp & TRANSA_DPLL_ENABLE) == 0)
  1669. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  1670. else if (trans_dpll_sel == 1 &&
  1671. (temp & TRANSB_DPLL_ENABLE) == 0)
  1672. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1673. I915_WRITE(PCH_DPLL_SEL, temp);
  1674. I915_READ(PCH_DPLL_SEL);
  1675. }
  1676. /* set transcoder timing */
  1677. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1678. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1679. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1680. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1681. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1682. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1683. /* enable normal train */
  1684. temp = I915_READ(fdi_tx_reg);
  1685. temp &= ~FDI_LINK_TRAIN_NONE;
  1686. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1687. FDI_TX_ENHANCE_FRAME_ENABLE);
  1688. I915_READ(fdi_tx_reg);
  1689. temp = I915_READ(fdi_rx_reg);
  1690. if (HAS_PCH_CPT(dev)) {
  1691. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1692. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1693. } else {
  1694. temp &= ~FDI_LINK_TRAIN_NONE;
  1695. temp |= FDI_LINK_TRAIN_NONE;
  1696. }
  1697. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1698. I915_READ(fdi_rx_reg);
  1699. /* wait one idle pattern time */
  1700. udelay(100);
  1701. /* For PCH DP, enable TRANS_DP_CTL */
  1702. if (HAS_PCH_CPT(dev) &&
  1703. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  1704. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1705. int reg;
  1706. reg = I915_READ(trans_dp_ctl);
  1707. reg &= ~TRANS_DP_PORT_SEL_MASK;
  1708. reg = TRANS_DP_OUTPUT_ENABLE |
  1709. TRANS_DP_ENH_FRAMING |
  1710. TRANS_DP_VSYNC_ACTIVE_HIGH |
  1711. TRANS_DP_HSYNC_ACTIVE_HIGH;
  1712. switch (intel_trans_dp_port_sel(crtc)) {
  1713. case PCH_DP_B:
  1714. reg |= TRANS_DP_PORT_SEL_B;
  1715. break;
  1716. case PCH_DP_C:
  1717. reg |= TRANS_DP_PORT_SEL_C;
  1718. break;
  1719. case PCH_DP_D:
  1720. reg |= TRANS_DP_PORT_SEL_D;
  1721. break;
  1722. default:
  1723. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  1724. reg |= TRANS_DP_PORT_SEL_B;
  1725. break;
  1726. }
  1727. I915_WRITE(trans_dp_ctl, reg);
  1728. POSTING_READ(trans_dp_ctl);
  1729. }
  1730. /* enable PCH transcoder */
  1731. temp = I915_READ(transconf_reg);
  1732. /*
  1733. * make the BPC in transcoder be consistent with
  1734. * that in pipeconf reg.
  1735. */
  1736. temp &= ~PIPE_BPC_MASK;
  1737. temp |= pipe_bpc;
  1738. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1739. I915_READ(transconf_reg);
  1740. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1741. ;
  1742. }
  1743. intel_crtc_load_lut(crtc);
  1744. break;
  1745. case DRM_MODE_DPMS_OFF:
  1746. DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
  1747. drm_vblank_off(dev, pipe);
  1748. /* Disable display plane */
  1749. temp = I915_READ(dspcntr_reg);
  1750. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1751. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1752. /* Flush the plane changes */
  1753. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1754. I915_READ(dspbase_reg);
  1755. }
  1756. i915_disable_vga(dev);
  1757. /* disable cpu pipe, disable after all planes disabled */
  1758. temp = I915_READ(pipeconf_reg);
  1759. if ((temp & PIPEACONF_ENABLE) != 0) {
  1760. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1761. I915_READ(pipeconf_reg);
  1762. n = 0;
  1763. /* wait for cpu pipe off, pipe state */
  1764. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
  1765. n++;
  1766. if (n < 60) {
  1767. udelay(500);
  1768. continue;
  1769. } else {
  1770. DRM_DEBUG_KMS("pipe %d off delay\n",
  1771. pipe);
  1772. break;
  1773. }
  1774. }
  1775. } else
  1776. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  1777. udelay(100);
  1778. /* Disable PF */
  1779. temp = I915_READ(pf_ctl_reg);
  1780. if ((temp & PF_ENABLE) != 0) {
  1781. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1782. I915_READ(pf_ctl_reg);
  1783. }
  1784. I915_WRITE(pf_win_size, 0);
  1785. POSTING_READ(pf_win_size);
  1786. /* disable CPU FDI tx and PCH FDI rx */
  1787. temp = I915_READ(fdi_tx_reg);
  1788. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1789. I915_READ(fdi_tx_reg);
  1790. temp = I915_READ(fdi_rx_reg);
  1791. /* BPC in FDI rx is consistent with that in pipeconf */
  1792. temp &= ~(0x07 << 16);
  1793. temp |= (pipe_bpc << 11);
  1794. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1795. I915_READ(fdi_rx_reg);
  1796. udelay(100);
  1797. /* still set train pattern 1 */
  1798. temp = I915_READ(fdi_tx_reg);
  1799. temp &= ~FDI_LINK_TRAIN_NONE;
  1800. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1801. I915_WRITE(fdi_tx_reg, temp);
  1802. POSTING_READ(fdi_tx_reg);
  1803. temp = I915_READ(fdi_rx_reg);
  1804. if (HAS_PCH_CPT(dev)) {
  1805. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1806. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1807. } else {
  1808. temp &= ~FDI_LINK_TRAIN_NONE;
  1809. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1810. }
  1811. I915_WRITE(fdi_rx_reg, temp);
  1812. POSTING_READ(fdi_rx_reg);
  1813. udelay(100);
  1814. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1815. temp = I915_READ(PCH_LVDS);
  1816. I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
  1817. I915_READ(PCH_LVDS);
  1818. udelay(100);
  1819. }
  1820. /* disable PCH transcoder */
  1821. temp = I915_READ(transconf_reg);
  1822. if ((temp & TRANS_ENABLE) != 0) {
  1823. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1824. I915_READ(transconf_reg);
  1825. n = 0;
  1826. /* wait for PCH transcoder off, transcoder state */
  1827. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
  1828. n++;
  1829. if (n < 60) {
  1830. udelay(500);
  1831. continue;
  1832. } else {
  1833. DRM_DEBUG_KMS("transcoder %d off "
  1834. "delay\n", pipe);
  1835. break;
  1836. }
  1837. }
  1838. }
  1839. temp = I915_READ(transconf_reg);
  1840. /* BPC in transcoder is consistent with that in pipeconf */
  1841. temp &= ~PIPE_BPC_MASK;
  1842. temp |= pipe_bpc;
  1843. I915_WRITE(transconf_reg, temp);
  1844. I915_READ(transconf_reg);
  1845. udelay(100);
  1846. if (HAS_PCH_CPT(dev)) {
  1847. /* disable TRANS_DP_CTL */
  1848. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1849. int reg;
  1850. reg = I915_READ(trans_dp_ctl);
  1851. reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  1852. I915_WRITE(trans_dp_ctl, reg);
  1853. POSTING_READ(trans_dp_ctl);
  1854. /* disable DPLL_SEL */
  1855. temp = I915_READ(PCH_DPLL_SEL);
  1856. if (trans_dpll_sel == 0)
  1857. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  1858. else
  1859. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1860. I915_WRITE(PCH_DPLL_SEL, temp);
  1861. I915_READ(PCH_DPLL_SEL);
  1862. }
  1863. /* disable PCH DPLL */
  1864. temp = I915_READ(pch_dpll_reg);
  1865. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1866. I915_READ(pch_dpll_reg);
  1867. if (HAS_eDP) {
  1868. ironlake_disable_pll_edp(crtc);
  1869. }
  1870. /* Switch from PCDclk to Rawclk */
  1871. temp = I915_READ(fdi_rx_reg);
  1872. temp &= ~FDI_SEL_PCDCLK;
  1873. I915_WRITE(fdi_rx_reg, temp);
  1874. I915_READ(fdi_rx_reg);
  1875. /* Disable CPU FDI TX PLL */
  1876. temp = I915_READ(fdi_tx_reg);
  1877. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  1878. I915_READ(fdi_tx_reg);
  1879. udelay(100);
  1880. temp = I915_READ(fdi_rx_reg);
  1881. temp &= ~FDI_RX_PLL_ENABLE;
  1882. I915_WRITE(fdi_rx_reg, temp);
  1883. I915_READ(fdi_rx_reg);
  1884. /* Wait for the clocks to turn off. */
  1885. udelay(100);
  1886. break;
  1887. }
  1888. }
  1889. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  1890. {
  1891. struct intel_overlay *overlay;
  1892. int ret;
  1893. if (!enable && intel_crtc->overlay) {
  1894. overlay = intel_crtc->overlay;
  1895. mutex_lock(&overlay->dev->struct_mutex);
  1896. for (;;) {
  1897. ret = intel_overlay_switch_off(overlay);
  1898. if (ret == 0)
  1899. break;
  1900. ret = intel_overlay_recover_from_interrupt(overlay, 0);
  1901. if (ret != 0) {
  1902. /* overlay doesn't react anymore. Usually
  1903. * results in a black screen and an unkillable
  1904. * X server. */
  1905. BUG();
  1906. overlay->hw_wedged = HW_WEDGED;
  1907. break;
  1908. }
  1909. }
  1910. mutex_unlock(&overlay->dev->struct_mutex);
  1911. }
  1912. /* Let userspace switch the overlay on again. In most cases userspace
  1913. * has to recompute where to put it anyway. */
  1914. return;
  1915. }
  1916. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1917. {
  1918. struct drm_device *dev = crtc->dev;
  1919. struct drm_i915_private *dev_priv = dev->dev_private;
  1920. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1921. int pipe = intel_crtc->pipe;
  1922. int plane = intel_crtc->plane;
  1923. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1924. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1925. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1926. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1927. u32 temp;
  1928. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1929. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1930. */
  1931. switch (mode) {
  1932. case DRM_MODE_DPMS_ON:
  1933. case DRM_MODE_DPMS_STANDBY:
  1934. case DRM_MODE_DPMS_SUSPEND:
  1935. intel_update_watermarks(dev);
  1936. /* Enable the DPLL */
  1937. temp = I915_READ(dpll_reg);
  1938. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1939. I915_WRITE(dpll_reg, temp);
  1940. I915_READ(dpll_reg);
  1941. /* Wait for the clocks to stabilize. */
  1942. udelay(150);
  1943. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1944. I915_READ(dpll_reg);
  1945. /* Wait for the clocks to stabilize. */
  1946. udelay(150);
  1947. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1948. I915_READ(dpll_reg);
  1949. /* Wait for the clocks to stabilize. */
  1950. udelay(150);
  1951. }
  1952. /* Enable the pipe */
  1953. temp = I915_READ(pipeconf_reg);
  1954. if ((temp & PIPEACONF_ENABLE) == 0)
  1955. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1956. /* Enable the plane */
  1957. temp = I915_READ(dspcntr_reg);
  1958. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1959. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1960. /* Flush the plane changes */
  1961. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1962. }
  1963. intel_crtc_load_lut(crtc);
  1964. if ((IS_I965G(dev) || plane == 0))
  1965. intel_update_fbc(crtc, &crtc->mode);
  1966. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1967. intel_crtc_dpms_overlay(intel_crtc, true);
  1968. break;
  1969. case DRM_MODE_DPMS_OFF:
  1970. intel_update_watermarks(dev);
  1971. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1972. intel_crtc_dpms_overlay(intel_crtc, false);
  1973. drm_vblank_off(dev, pipe);
  1974. if (dev_priv->cfb_plane == plane &&
  1975. dev_priv->display.disable_fbc)
  1976. dev_priv->display.disable_fbc(dev);
  1977. /* Disable the VGA plane that we never use */
  1978. i915_disable_vga(dev);
  1979. /* Disable display plane */
  1980. temp = I915_READ(dspcntr_reg);
  1981. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1982. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1983. /* Flush the plane changes */
  1984. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1985. I915_READ(dspbase_reg);
  1986. }
  1987. if (!IS_I9XX(dev)) {
  1988. /* Wait for vblank for the disable to take effect */
  1989. intel_wait_for_vblank(dev);
  1990. }
  1991. /* Next, disable display pipes */
  1992. temp = I915_READ(pipeconf_reg);
  1993. if ((temp & PIPEACONF_ENABLE) != 0) {
  1994. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1995. I915_READ(pipeconf_reg);
  1996. }
  1997. /* Wait for vblank for the disable to take effect. */
  1998. intel_wait_for_vblank(dev);
  1999. temp = I915_READ(dpll_reg);
  2000. if ((temp & DPLL_VCO_ENABLE) != 0) {
  2001. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  2002. I915_READ(dpll_reg);
  2003. }
  2004. /* Wait for the clocks to turn off. */
  2005. udelay(150);
  2006. break;
  2007. }
  2008. }
  2009. /**
  2010. * Sets the power management mode of the pipe and plane.
  2011. *
  2012. * This code should probably grow support for turning the cursor off and back
  2013. * on appropriately at the same time as we're turning the pipe off/on.
  2014. */
  2015. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2016. {
  2017. struct drm_device *dev = crtc->dev;
  2018. struct drm_i915_private *dev_priv = dev->dev_private;
  2019. struct drm_i915_master_private *master_priv;
  2020. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2021. int pipe = intel_crtc->pipe;
  2022. bool enabled;
  2023. dev_priv->display.dpms(crtc, mode);
  2024. intel_crtc->dpms_mode = mode;
  2025. if (!dev->primary->master)
  2026. return;
  2027. master_priv = dev->primary->master->driver_priv;
  2028. if (!master_priv->sarea_priv)
  2029. return;
  2030. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2031. switch (pipe) {
  2032. case 0:
  2033. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2034. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2035. break;
  2036. case 1:
  2037. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2038. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2039. break;
  2040. default:
  2041. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  2042. break;
  2043. }
  2044. }
  2045. static void intel_crtc_prepare (struct drm_crtc *crtc)
  2046. {
  2047. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2048. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2049. }
  2050. static void intel_crtc_commit (struct drm_crtc *crtc)
  2051. {
  2052. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2053. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  2054. }
  2055. void intel_encoder_prepare (struct drm_encoder *encoder)
  2056. {
  2057. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2058. /* lvds has its own version of prepare see intel_lvds_prepare */
  2059. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2060. }
  2061. void intel_encoder_commit (struct drm_encoder *encoder)
  2062. {
  2063. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2064. /* lvds has its own version of commit see intel_lvds_commit */
  2065. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2066. }
  2067. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2068. struct drm_display_mode *mode,
  2069. struct drm_display_mode *adjusted_mode)
  2070. {
  2071. struct drm_device *dev = crtc->dev;
  2072. if (HAS_PCH_SPLIT(dev)) {
  2073. /* FDI link clock is fixed at 2.7G */
  2074. if (mode->clock * 3 > 27000 * 4)
  2075. return MODE_CLOCK_HIGH;
  2076. }
  2077. drm_mode_set_crtcinfo(adjusted_mode, 0);
  2078. return true;
  2079. }
  2080. static int i945_get_display_clock_speed(struct drm_device *dev)
  2081. {
  2082. return 400000;
  2083. }
  2084. static int i915_get_display_clock_speed(struct drm_device *dev)
  2085. {
  2086. return 333000;
  2087. }
  2088. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2089. {
  2090. return 200000;
  2091. }
  2092. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2093. {
  2094. u16 gcfgc = 0;
  2095. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2096. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2097. return 133000;
  2098. else {
  2099. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2100. case GC_DISPLAY_CLOCK_333_MHZ:
  2101. return 333000;
  2102. default:
  2103. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2104. return 190000;
  2105. }
  2106. }
  2107. }
  2108. static int i865_get_display_clock_speed(struct drm_device *dev)
  2109. {
  2110. return 266000;
  2111. }
  2112. static int i855_get_display_clock_speed(struct drm_device *dev)
  2113. {
  2114. u16 hpllcc = 0;
  2115. /* Assume that the hardware is in the high speed state. This
  2116. * should be the default.
  2117. */
  2118. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2119. case GC_CLOCK_133_200:
  2120. case GC_CLOCK_100_200:
  2121. return 200000;
  2122. case GC_CLOCK_166_250:
  2123. return 250000;
  2124. case GC_CLOCK_100_133:
  2125. return 133000;
  2126. }
  2127. /* Shouldn't happen */
  2128. return 0;
  2129. }
  2130. static int i830_get_display_clock_speed(struct drm_device *dev)
  2131. {
  2132. return 133000;
  2133. }
  2134. /**
  2135. * Return the pipe currently connected to the panel fitter,
  2136. * or -1 if the panel fitter is not present or not in use
  2137. */
  2138. int intel_panel_fitter_pipe (struct drm_device *dev)
  2139. {
  2140. struct drm_i915_private *dev_priv = dev->dev_private;
  2141. u32 pfit_control;
  2142. /* i830 doesn't have a panel fitter */
  2143. if (IS_I830(dev))
  2144. return -1;
  2145. pfit_control = I915_READ(PFIT_CONTROL);
  2146. /* See if the panel fitter is in use */
  2147. if ((pfit_control & PFIT_ENABLE) == 0)
  2148. return -1;
  2149. /* 965 can place panel fitter on either pipe */
  2150. if (IS_I965G(dev))
  2151. return (pfit_control >> 29) & 0x3;
  2152. /* older chips can only use pipe 1 */
  2153. return 1;
  2154. }
  2155. struct fdi_m_n {
  2156. u32 tu;
  2157. u32 gmch_m;
  2158. u32 gmch_n;
  2159. u32 link_m;
  2160. u32 link_n;
  2161. };
  2162. static void
  2163. fdi_reduce_ratio(u32 *num, u32 *den)
  2164. {
  2165. while (*num > 0xffffff || *den > 0xffffff) {
  2166. *num >>= 1;
  2167. *den >>= 1;
  2168. }
  2169. }
  2170. #define DATA_N 0x800000
  2171. #define LINK_N 0x80000
  2172. static void
  2173. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2174. int link_clock, struct fdi_m_n *m_n)
  2175. {
  2176. u64 temp;
  2177. m_n->tu = 64; /* default size */
  2178. temp = (u64) DATA_N * pixel_clock;
  2179. temp = div_u64(temp, link_clock);
  2180. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  2181. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  2182. m_n->gmch_n = DATA_N;
  2183. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2184. temp = (u64) LINK_N * pixel_clock;
  2185. m_n->link_m = div_u64(temp, link_clock);
  2186. m_n->link_n = LINK_N;
  2187. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2188. }
  2189. struct intel_watermark_params {
  2190. unsigned long fifo_size;
  2191. unsigned long max_wm;
  2192. unsigned long default_wm;
  2193. unsigned long guard_size;
  2194. unsigned long cacheline_size;
  2195. };
  2196. /* Pineview has different values for various configs */
  2197. static struct intel_watermark_params pineview_display_wm = {
  2198. PINEVIEW_DISPLAY_FIFO,
  2199. PINEVIEW_MAX_WM,
  2200. PINEVIEW_DFT_WM,
  2201. PINEVIEW_GUARD_WM,
  2202. PINEVIEW_FIFO_LINE_SIZE
  2203. };
  2204. static struct intel_watermark_params pineview_display_hplloff_wm = {
  2205. PINEVIEW_DISPLAY_FIFO,
  2206. PINEVIEW_MAX_WM,
  2207. PINEVIEW_DFT_HPLLOFF_WM,
  2208. PINEVIEW_GUARD_WM,
  2209. PINEVIEW_FIFO_LINE_SIZE
  2210. };
  2211. static struct intel_watermark_params pineview_cursor_wm = {
  2212. PINEVIEW_CURSOR_FIFO,
  2213. PINEVIEW_CURSOR_MAX_WM,
  2214. PINEVIEW_CURSOR_DFT_WM,
  2215. PINEVIEW_CURSOR_GUARD_WM,
  2216. PINEVIEW_FIFO_LINE_SIZE,
  2217. };
  2218. static struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2219. PINEVIEW_CURSOR_FIFO,
  2220. PINEVIEW_CURSOR_MAX_WM,
  2221. PINEVIEW_CURSOR_DFT_WM,
  2222. PINEVIEW_CURSOR_GUARD_WM,
  2223. PINEVIEW_FIFO_LINE_SIZE
  2224. };
  2225. static struct intel_watermark_params g4x_wm_info = {
  2226. G4X_FIFO_SIZE,
  2227. G4X_MAX_WM,
  2228. G4X_MAX_WM,
  2229. 2,
  2230. G4X_FIFO_LINE_SIZE,
  2231. };
  2232. static struct intel_watermark_params i945_wm_info = {
  2233. I945_FIFO_SIZE,
  2234. I915_MAX_WM,
  2235. 1,
  2236. 2,
  2237. I915_FIFO_LINE_SIZE
  2238. };
  2239. static struct intel_watermark_params i915_wm_info = {
  2240. I915_FIFO_SIZE,
  2241. I915_MAX_WM,
  2242. 1,
  2243. 2,
  2244. I915_FIFO_LINE_SIZE
  2245. };
  2246. static struct intel_watermark_params i855_wm_info = {
  2247. I855GM_FIFO_SIZE,
  2248. I915_MAX_WM,
  2249. 1,
  2250. 2,
  2251. I830_FIFO_LINE_SIZE
  2252. };
  2253. static struct intel_watermark_params i830_wm_info = {
  2254. I830_FIFO_SIZE,
  2255. I915_MAX_WM,
  2256. 1,
  2257. 2,
  2258. I830_FIFO_LINE_SIZE
  2259. };
  2260. static struct intel_watermark_params ironlake_display_wm_info = {
  2261. ILK_DISPLAY_FIFO,
  2262. ILK_DISPLAY_MAXWM,
  2263. ILK_DISPLAY_DFTWM,
  2264. 2,
  2265. ILK_FIFO_LINE_SIZE
  2266. };
  2267. static struct intel_watermark_params ironlake_display_srwm_info = {
  2268. ILK_DISPLAY_SR_FIFO,
  2269. ILK_DISPLAY_MAX_SRWM,
  2270. ILK_DISPLAY_DFT_SRWM,
  2271. 2,
  2272. ILK_FIFO_LINE_SIZE
  2273. };
  2274. static struct intel_watermark_params ironlake_cursor_srwm_info = {
  2275. ILK_CURSOR_SR_FIFO,
  2276. ILK_CURSOR_MAX_SRWM,
  2277. ILK_CURSOR_DFT_SRWM,
  2278. 2,
  2279. ILK_FIFO_LINE_SIZE
  2280. };
  2281. /**
  2282. * intel_calculate_wm - calculate watermark level
  2283. * @clock_in_khz: pixel clock
  2284. * @wm: chip FIFO params
  2285. * @pixel_size: display pixel size
  2286. * @latency_ns: memory latency for the platform
  2287. *
  2288. * Calculate the watermark level (the level at which the display plane will
  2289. * start fetching from memory again). Each chip has a different display
  2290. * FIFO size and allocation, so the caller needs to figure that out and pass
  2291. * in the correct intel_watermark_params structure.
  2292. *
  2293. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2294. * on the pixel size. When it reaches the watermark level, it'll start
  2295. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2296. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2297. * will occur, and a display engine hang could result.
  2298. */
  2299. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2300. struct intel_watermark_params *wm,
  2301. int pixel_size,
  2302. unsigned long latency_ns)
  2303. {
  2304. long entries_required, wm_size;
  2305. /*
  2306. * Note: we need to make sure we don't overflow for various clock &
  2307. * latency values.
  2308. * clocks go from a few thousand to several hundred thousand.
  2309. * latency is usually a few thousand
  2310. */
  2311. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2312. 1000;
  2313. entries_required /= wm->cacheline_size;
  2314. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  2315. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  2316. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  2317. /* Don't promote wm_size to unsigned... */
  2318. if (wm_size > (long)wm->max_wm)
  2319. wm_size = wm->max_wm;
  2320. if (wm_size <= 0)
  2321. wm_size = wm->default_wm;
  2322. return wm_size;
  2323. }
  2324. struct cxsr_latency {
  2325. int is_desktop;
  2326. int is_ddr3;
  2327. unsigned long fsb_freq;
  2328. unsigned long mem_freq;
  2329. unsigned long display_sr;
  2330. unsigned long display_hpll_disable;
  2331. unsigned long cursor_sr;
  2332. unsigned long cursor_hpll_disable;
  2333. };
  2334. static struct cxsr_latency cxsr_latency_table[] = {
  2335. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2336. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2337. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2338. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  2339. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  2340. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2341. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2342. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2343. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  2344. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  2345. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2346. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2347. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2348. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  2349. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  2350. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2351. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2352. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2353. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  2354. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  2355. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2356. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2357. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2358. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  2359. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  2360. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2361. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2362. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2363. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  2364. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  2365. };
  2366. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
  2367. int fsb, int mem)
  2368. {
  2369. int i;
  2370. struct cxsr_latency *latency;
  2371. if (fsb == 0 || mem == 0)
  2372. return NULL;
  2373. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2374. latency = &cxsr_latency_table[i];
  2375. if (is_desktop == latency->is_desktop &&
  2376. is_ddr3 == latency->is_ddr3 &&
  2377. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2378. return latency;
  2379. }
  2380. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2381. return NULL;
  2382. }
  2383. static void pineview_disable_cxsr(struct drm_device *dev)
  2384. {
  2385. struct drm_i915_private *dev_priv = dev->dev_private;
  2386. u32 reg;
  2387. /* deactivate cxsr */
  2388. reg = I915_READ(DSPFW3);
  2389. reg &= ~(PINEVIEW_SELF_REFRESH_EN);
  2390. I915_WRITE(DSPFW3, reg);
  2391. DRM_INFO("Big FIFO is disabled\n");
  2392. }
  2393. /*
  2394. * Latency for FIFO fetches is dependent on several factors:
  2395. * - memory configuration (speed, channels)
  2396. * - chipset
  2397. * - current MCH state
  2398. * It can be fairly high in some situations, so here we assume a fairly
  2399. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2400. * set this value too high, the FIFO will fetch frequently to stay full)
  2401. * and power consumption (set it too low to save power and we might see
  2402. * FIFO underruns and display "flicker").
  2403. *
  2404. * A value of 5us seems to be a good balance; safe for very low end
  2405. * platforms but not overly aggressive on lower latency configs.
  2406. */
  2407. static const int latency_ns = 5000;
  2408. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2409. {
  2410. struct drm_i915_private *dev_priv = dev->dev_private;
  2411. uint32_t dsparb = I915_READ(DSPARB);
  2412. int size;
  2413. if (plane == 0)
  2414. size = dsparb & 0x7f;
  2415. else
  2416. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
  2417. (dsparb & 0x7f);
  2418. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2419. plane ? "B" : "A", size);
  2420. return size;
  2421. }
  2422. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2423. {
  2424. struct drm_i915_private *dev_priv = dev->dev_private;
  2425. uint32_t dsparb = I915_READ(DSPARB);
  2426. int size;
  2427. if (plane == 0)
  2428. size = dsparb & 0x1ff;
  2429. else
  2430. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
  2431. (dsparb & 0x1ff);
  2432. size >>= 1; /* Convert to cachelines */
  2433. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2434. plane ? "B" : "A", size);
  2435. return size;
  2436. }
  2437. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2438. {
  2439. struct drm_i915_private *dev_priv = dev->dev_private;
  2440. uint32_t dsparb = I915_READ(DSPARB);
  2441. int size;
  2442. size = dsparb & 0x7f;
  2443. size >>= 2; /* Convert to cachelines */
  2444. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2445. plane ? "B" : "A",
  2446. size);
  2447. return size;
  2448. }
  2449. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2450. {
  2451. struct drm_i915_private *dev_priv = dev->dev_private;
  2452. uint32_t dsparb = I915_READ(DSPARB);
  2453. int size;
  2454. size = dsparb & 0x7f;
  2455. size >>= 1; /* Convert to cachelines */
  2456. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2457. plane ? "B" : "A", size);
  2458. return size;
  2459. }
  2460. static void pineview_update_wm(struct drm_device *dev, int planea_clock,
  2461. int planeb_clock, int sr_hdisplay, int pixel_size)
  2462. {
  2463. struct drm_i915_private *dev_priv = dev->dev_private;
  2464. u32 reg;
  2465. unsigned long wm;
  2466. struct cxsr_latency *latency;
  2467. int sr_clock;
  2468. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  2469. dev_priv->fsb_freq, dev_priv->mem_freq);
  2470. if (!latency) {
  2471. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2472. pineview_disable_cxsr(dev);
  2473. return;
  2474. }
  2475. if (!planea_clock || !planeb_clock) {
  2476. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2477. /* Display SR */
  2478. wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
  2479. pixel_size, latency->display_sr);
  2480. reg = I915_READ(DSPFW1);
  2481. reg &= ~DSPFW_SR_MASK;
  2482. reg |= wm << DSPFW_SR_SHIFT;
  2483. I915_WRITE(DSPFW1, reg);
  2484. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2485. /* cursor SR */
  2486. wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
  2487. pixel_size, latency->cursor_sr);
  2488. reg = I915_READ(DSPFW3);
  2489. reg &= ~DSPFW_CURSOR_SR_MASK;
  2490. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  2491. I915_WRITE(DSPFW3, reg);
  2492. /* Display HPLL off SR */
  2493. wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
  2494. pixel_size, latency->display_hpll_disable);
  2495. reg = I915_READ(DSPFW3);
  2496. reg &= ~DSPFW_HPLL_SR_MASK;
  2497. reg |= wm & DSPFW_HPLL_SR_MASK;
  2498. I915_WRITE(DSPFW3, reg);
  2499. /* cursor HPLL off SR */
  2500. wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
  2501. pixel_size, latency->cursor_hpll_disable);
  2502. reg = I915_READ(DSPFW3);
  2503. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  2504. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  2505. I915_WRITE(DSPFW3, reg);
  2506. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2507. /* activate cxsr */
  2508. reg = I915_READ(DSPFW3);
  2509. reg |= PINEVIEW_SELF_REFRESH_EN;
  2510. I915_WRITE(DSPFW3, reg);
  2511. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  2512. } else {
  2513. pineview_disable_cxsr(dev);
  2514. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  2515. }
  2516. }
  2517. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2518. int planeb_clock, int sr_hdisplay, int pixel_size)
  2519. {
  2520. struct drm_i915_private *dev_priv = dev->dev_private;
  2521. int total_size, cacheline_size;
  2522. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2523. struct intel_watermark_params planea_params, planeb_params;
  2524. unsigned long line_time_us;
  2525. int sr_clock, sr_entries = 0, entries_required;
  2526. /* Create copies of the base settings for each pipe */
  2527. planea_params = planeb_params = g4x_wm_info;
  2528. /* Grab a couple of global values before we overwrite them */
  2529. total_size = planea_params.fifo_size;
  2530. cacheline_size = planea_params.cacheline_size;
  2531. /*
  2532. * Note: we need to make sure we don't overflow for various clock &
  2533. * latency values.
  2534. * clocks go from a few thousand to several hundred thousand.
  2535. * latency is usually a few thousand
  2536. */
  2537. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2538. 1000;
  2539. entries_required /= G4X_FIFO_LINE_SIZE;
  2540. planea_wm = entries_required + planea_params.guard_size;
  2541. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2542. 1000;
  2543. entries_required /= G4X_FIFO_LINE_SIZE;
  2544. planeb_wm = entries_required + planeb_params.guard_size;
  2545. cursora_wm = cursorb_wm = 16;
  2546. cursor_sr = 32;
  2547. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2548. /* Calc sr entries for one plane configs */
  2549. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2550. /* self-refresh has much higher latency */
  2551. static const int sr_latency_ns = 12000;
  2552. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2553. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2554. /* Use ns/us then divide to preserve precision */
  2555. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2556. pixel_size * sr_hdisplay) / 1000;
  2557. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2558. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2559. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2560. } else {
  2561. /* Turn off self refresh if both pipes are enabled */
  2562. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2563. & ~FW_BLC_SELF_EN);
  2564. }
  2565. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2566. planea_wm, planeb_wm, sr_entries);
  2567. planea_wm &= 0x3f;
  2568. planeb_wm &= 0x3f;
  2569. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2570. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2571. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2572. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2573. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2574. /* HPLL off in SR has some issues on G4x... disable it */
  2575. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2576. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2577. }
  2578. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2579. int planeb_clock, int sr_hdisplay, int pixel_size)
  2580. {
  2581. struct drm_i915_private *dev_priv = dev->dev_private;
  2582. unsigned long line_time_us;
  2583. int sr_clock, sr_entries, srwm = 1;
  2584. /* Calc sr entries for one plane configs */
  2585. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2586. /* self-refresh has much higher latency */
  2587. static const int sr_latency_ns = 12000;
  2588. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2589. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2590. /* Use ns/us then divide to preserve precision */
  2591. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2592. pixel_size * sr_hdisplay) / 1000;
  2593. sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
  2594. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2595. srwm = I945_FIFO_SIZE - sr_entries;
  2596. if (srwm < 0)
  2597. srwm = 1;
  2598. srwm &= 0x3f;
  2599. if (IS_I965GM(dev))
  2600. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2601. } else {
  2602. /* Turn off self refresh if both pipes are enabled */
  2603. if (IS_I965GM(dev))
  2604. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2605. & ~FW_BLC_SELF_EN);
  2606. }
  2607. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2608. srwm);
  2609. /* 965 has limitations... */
  2610. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2611. (8 << 0));
  2612. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2613. }
  2614. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2615. int planeb_clock, int sr_hdisplay, int pixel_size)
  2616. {
  2617. struct drm_i915_private *dev_priv = dev->dev_private;
  2618. uint32_t fwater_lo;
  2619. uint32_t fwater_hi;
  2620. int total_size, cacheline_size, cwm, srwm = 1;
  2621. int planea_wm, planeb_wm;
  2622. struct intel_watermark_params planea_params, planeb_params;
  2623. unsigned long line_time_us;
  2624. int sr_clock, sr_entries = 0;
  2625. /* Create copies of the base settings for each pipe */
  2626. if (IS_I965GM(dev) || IS_I945GM(dev))
  2627. planea_params = planeb_params = i945_wm_info;
  2628. else if (IS_I9XX(dev))
  2629. planea_params = planeb_params = i915_wm_info;
  2630. else
  2631. planea_params = planeb_params = i855_wm_info;
  2632. /* Grab a couple of global values before we overwrite them */
  2633. total_size = planea_params.fifo_size;
  2634. cacheline_size = planea_params.cacheline_size;
  2635. /* Update per-plane FIFO sizes */
  2636. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2637. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2638. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2639. pixel_size, latency_ns);
  2640. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2641. pixel_size, latency_ns);
  2642. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2643. /*
  2644. * Overlay gets an aggressive default since video jitter is bad.
  2645. */
  2646. cwm = 2;
  2647. /* Calc sr entries for one plane configs */
  2648. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2649. (!planea_clock || !planeb_clock)) {
  2650. /* self-refresh has much higher latency */
  2651. static const int sr_latency_ns = 6000;
  2652. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2653. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2654. /* Use ns/us then divide to preserve precision */
  2655. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2656. pixel_size * sr_hdisplay) / 1000;
  2657. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2658. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2659. srwm = total_size - sr_entries;
  2660. if (srwm < 0)
  2661. srwm = 1;
  2662. if (IS_I945G(dev) || IS_I945GM(dev))
  2663. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  2664. else if (IS_I915GM(dev)) {
  2665. /* 915M has a smaller SRWM field */
  2666. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  2667. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  2668. }
  2669. } else {
  2670. /* Turn off self refresh if both pipes are enabled */
  2671. if (IS_I945G(dev) || IS_I945GM(dev)) {
  2672. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2673. & ~FW_BLC_SELF_EN);
  2674. } else if (IS_I915GM(dev)) {
  2675. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  2676. }
  2677. }
  2678. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2679. planea_wm, planeb_wm, cwm, srwm);
  2680. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2681. fwater_hi = (cwm & 0x1f);
  2682. /* Set request length to 8 cachelines per fetch */
  2683. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2684. fwater_hi = fwater_hi | (1 << 8);
  2685. I915_WRITE(FW_BLC, fwater_lo);
  2686. I915_WRITE(FW_BLC2, fwater_hi);
  2687. }
  2688. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2689. int unused2, int pixel_size)
  2690. {
  2691. struct drm_i915_private *dev_priv = dev->dev_private;
  2692. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2693. int planea_wm;
  2694. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2695. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2696. pixel_size, latency_ns);
  2697. fwater_lo |= (3<<8) | planea_wm;
  2698. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2699. I915_WRITE(FW_BLC, fwater_lo);
  2700. }
  2701. #define ILK_LP0_PLANE_LATENCY 700
  2702. static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
  2703. int planeb_clock, int sr_hdisplay, int pixel_size)
  2704. {
  2705. struct drm_i915_private *dev_priv = dev->dev_private;
  2706. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  2707. int sr_wm, cursor_wm;
  2708. unsigned long line_time_us;
  2709. int sr_clock, entries_required;
  2710. u32 reg_value;
  2711. /* Calculate and update the watermark for plane A */
  2712. if (planea_clock) {
  2713. entries_required = ((planea_clock / 1000) * pixel_size *
  2714. ILK_LP0_PLANE_LATENCY) / 1000;
  2715. entries_required = DIV_ROUND_UP(entries_required,
  2716. ironlake_display_wm_info.cacheline_size);
  2717. planea_wm = entries_required +
  2718. ironlake_display_wm_info.guard_size;
  2719. if (planea_wm > (int)ironlake_display_wm_info.max_wm)
  2720. planea_wm = ironlake_display_wm_info.max_wm;
  2721. cursora_wm = 16;
  2722. reg_value = I915_READ(WM0_PIPEA_ILK);
  2723. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2724. reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
  2725. (cursora_wm & WM0_PIPE_CURSOR_MASK);
  2726. I915_WRITE(WM0_PIPEA_ILK, reg_value);
  2727. DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
  2728. "cursor: %d\n", planea_wm, cursora_wm);
  2729. }
  2730. /* Calculate and update the watermark for plane B */
  2731. if (planeb_clock) {
  2732. entries_required = ((planeb_clock / 1000) * pixel_size *
  2733. ILK_LP0_PLANE_LATENCY) / 1000;
  2734. entries_required = DIV_ROUND_UP(entries_required,
  2735. ironlake_display_wm_info.cacheline_size);
  2736. planeb_wm = entries_required +
  2737. ironlake_display_wm_info.guard_size;
  2738. if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
  2739. planeb_wm = ironlake_display_wm_info.max_wm;
  2740. cursorb_wm = 16;
  2741. reg_value = I915_READ(WM0_PIPEB_ILK);
  2742. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2743. reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
  2744. (cursorb_wm & WM0_PIPE_CURSOR_MASK);
  2745. I915_WRITE(WM0_PIPEB_ILK, reg_value);
  2746. DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
  2747. "cursor: %d\n", planeb_wm, cursorb_wm);
  2748. }
  2749. /*
  2750. * Calculate and update the self-refresh watermark only when one
  2751. * display plane is used.
  2752. */
  2753. if (!planea_clock || !planeb_clock) {
  2754. int line_count;
  2755. /* Read the self-refresh latency. The unit is 0.5us */
  2756. int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
  2757. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2758. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2759. /* Use ns/us then divide to preserve precision */
  2760. line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
  2761. / 1000;
  2762. /* calculate the self-refresh watermark for display plane */
  2763. entries_required = line_count * sr_hdisplay * pixel_size;
  2764. entries_required = DIV_ROUND_UP(entries_required,
  2765. ironlake_display_srwm_info.cacheline_size);
  2766. sr_wm = entries_required +
  2767. ironlake_display_srwm_info.guard_size;
  2768. /* calculate the self-refresh watermark for display cursor */
  2769. entries_required = line_count * pixel_size * 64;
  2770. entries_required = DIV_ROUND_UP(entries_required,
  2771. ironlake_cursor_srwm_info.cacheline_size);
  2772. cursor_wm = entries_required +
  2773. ironlake_cursor_srwm_info.guard_size;
  2774. /* configure watermark and enable self-refresh */
  2775. reg_value = I915_READ(WM1_LP_ILK);
  2776. reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
  2777. WM1_LP_CURSOR_MASK);
  2778. reg_value |= WM1_LP_SR_EN |
  2779. (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
  2780. (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
  2781. I915_WRITE(WM1_LP_ILK, reg_value);
  2782. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2783. "cursor %d\n", sr_wm, cursor_wm);
  2784. } else {
  2785. /* Turn off self refresh if both pipes are enabled */
  2786. I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
  2787. }
  2788. }
  2789. /**
  2790. * intel_update_watermarks - update FIFO watermark values based on current modes
  2791. *
  2792. * Calculate watermark values for the various WM regs based on current mode
  2793. * and plane configuration.
  2794. *
  2795. * There are several cases to deal with here:
  2796. * - normal (i.e. non-self-refresh)
  2797. * - self-refresh (SR) mode
  2798. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2799. * - lines are small relative to FIFO size (buffer can hold more than 2
  2800. * lines), so need to account for TLB latency
  2801. *
  2802. * The normal calculation is:
  2803. * watermark = dotclock * bytes per pixel * latency
  2804. * where latency is platform & configuration dependent (we assume pessimal
  2805. * values here).
  2806. *
  2807. * The SR calculation is:
  2808. * watermark = (trunc(latency/line time)+1) * surface width *
  2809. * bytes per pixel
  2810. * where
  2811. * line time = htotal / dotclock
  2812. * and latency is assumed to be high, as above.
  2813. *
  2814. * The final value programmed to the register should always be rounded up,
  2815. * and include an extra 2 entries to account for clock crossings.
  2816. *
  2817. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2818. * to set the non-SR watermarks to 8.
  2819. */
  2820. static void intel_update_watermarks(struct drm_device *dev)
  2821. {
  2822. struct drm_i915_private *dev_priv = dev->dev_private;
  2823. struct drm_crtc *crtc;
  2824. struct intel_crtc *intel_crtc;
  2825. int sr_hdisplay = 0;
  2826. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  2827. int enabled = 0, pixel_size = 0;
  2828. if (!dev_priv->display.update_wm)
  2829. return;
  2830. /* Get the clock config from both planes */
  2831. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2832. intel_crtc = to_intel_crtc(crtc);
  2833. if (crtc->enabled) {
  2834. enabled++;
  2835. if (intel_crtc->plane == 0) {
  2836. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  2837. intel_crtc->pipe, crtc->mode.clock);
  2838. planea_clock = crtc->mode.clock;
  2839. } else {
  2840. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  2841. intel_crtc->pipe, crtc->mode.clock);
  2842. planeb_clock = crtc->mode.clock;
  2843. }
  2844. sr_hdisplay = crtc->mode.hdisplay;
  2845. sr_clock = crtc->mode.clock;
  2846. if (crtc->fb)
  2847. pixel_size = crtc->fb->bits_per_pixel / 8;
  2848. else
  2849. pixel_size = 4; /* by default */
  2850. }
  2851. }
  2852. if (enabled <= 0)
  2853. return;
  2854. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  2855. sr_hdisplay, pixel_size);
  2856. }
  2857. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  2858. struct drm_display_mode *mode,
  2859. struct drm_display_mode *adjusted_mode,
  2860. int x, int y,
  2861. struct drm_framebuffer *old_fb)
  2862. {
  2863. struct drm_device *dev = crtc->dev;
  2864. struct drm_i915_private *dev_priv = dev->dev_private;
  2865. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2866. int pipe = intel_crtc->pipe;
  2867. int plane = intel_crtc->plane;
  2868. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  2869. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2870. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  2871. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2872. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2873. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  2874. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  2875. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  2876. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  2877. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  2878. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  2879. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  2880. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  2881. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  2882. int refclk, num_connectors = 0;
  2883. intel_clock_t clock, reduced_clock;
  2884. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  2885. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  2886. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  2887. bool is_edp = false;
  2888. struct drm_mode_config *mode_config = &dev->mode_config;
  2889. struct drm_encoder *encoder;
  2890. struct intel_encoder *intel_encoder = NULL;
  2891. const intel_limit_t *limit;
  2892. int ret;
  2893. struct fdi_m_n m_n = {0};
  2894. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  2895. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  2896. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  2897. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  2898. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  2899. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  2900. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  2901. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  2902. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  2903. int lvds_reg = LVDS;
  2904. u32 temp;
  2905. int sdvo_pixel_multiply;
  2906. int target_clock;
  2907. drm_vblank_pre_modeset(dev, pipe);
  2908. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  2909. if (!encoder || encoder->crtc != crtc)
  2910. continue;
  2911. intel_encoder = enc_to_intel_encoder(encoder);
  2912. switch (intel_encoder->type) {
  2913. case INTEL_OUTPUT_LVDS:
  2914. is_lvds = true;
  2915. break;
  2916. case INTEL_OUTPUT_SDVO:
  2917. case INTEL_OUTPUT_HDMI:
  2918. is_sdvo = true;
  2919. if (intel_encoder->needs_tv_clock)
  2920. is_tv = true;
  2921. break;
  2922. case INTEL_OUTPUT_DVO:
  2923. is_dvo = true;
  2924. break;
  2925. case INTEL_OUTPUT_TVOUT:
  2926. is_tv = true;
  2927. break;
  2928. case INTEL_OUTPUT_ANALOG:
  2929. is_crt = true;
  2930. break;
  2931. case INTEL_OUTPUT_DISPLAYPORT:
  2932. is_dp = true;
  2933. break;
  2934. case INTEL_OUTPUT_EDP:
  2935. is_edp = true;
  2936. break;
  2937. }
  2938. num_connectors++;
  2939. }
  2940. if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
  2941. refclk = dev_priv->lvds_ssc_freq * 1000;
  2942. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  2943. refclk / 1000);
  2944. } else if (IS_I9XX(dev)) {
  2945. refclk = 96000;
  2946. if (HAS_PCH_SPLIT(dev))
  2947. refclk = 120000; /* 120Mhz refclk */
  2948. } else {
  2949. refclk = 48000;
  2950. }
  2951. /*
  2952. * Returns a set of divisors for the desired target clock with the given
  2953. * refclk, or FALSE. The returned values represent the clock equation:
  2954. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  2955. */
  2956. limit = intel_limit(crtc);
  2957. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  2958. if (!ok) {
  2959. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  2960. drm_vblank_post_modeset(dev, pipe);
  2961. return -EINVAL;
  2962. }
  2963. if (is_lvds && dev_priv->lvds_downclock_avail) {
  2964. has_reduced_clock = limit->find_pll(limit, crtc,
  2965. dev_priv->lvds_downclock,
  2966. refclk,
  2967. &reduced_clock);
  2968. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  2969. /*
  2970. * If the different P is found, it means that we can't
  2971. * switch the display clock by using the FP0/FP1.
  2972. * In such case we will disable the LVDS downclock
  2973. * feature.
  2974. */
  2975. DRM_DEBUG_KMS("Different P is found for "
  2976. "LVDS clock/downclock\n");
  2977. has_reduced_clock = 0;
  2978. }
  2979. }
  2980. /* SDVO TV has fixed PLL values depend on its clock range,
  2981. this mirrors vbios setting. */
  2982. if (is_sdvo && is_tv) {
  2983. if (adjusted_mode->clock >= 100000
  2984. && adjusted_mode->clock < 140500) {
  2985. clock.p1 = 2;
  2986. clock.p2 = 10;
  2987. clock.n = 3;
  2988. clock.m1 = 16;
  2989. clock.m2 = 8;
  2990. } else if (adjusted_mode->clock >= 140500
  2991. && adjusted_mode->clock <= 200000) {
  2992. clock.p1 = 1;
  2993. clock.p2 = 10;
  2994. clock.n = 6;
  2995. clock.m1 = 12;
  2996. clock.m2 = 8;
  2997. }
  2998. }
  2999. /* FDI link */
  3000. if (HAS_PCH_SPLIT(dev)) {
  3001. int lane = 0, link_bw, bpp;
  3002. /* eDP doesn't require FDI link, so just set DP M/N
  3003. according to current link config */
  3004. if (is_edp) {
  3005. target_clock = mode->clock;
  3006. intel_edp_link_config(intel_encoder,
  3007. &lane, &link_bw);
  3008. } else {
  3009. /* DP over FDI requires target mode clock
  3010. instead of link clock */
  3011. if (is_dp)
  3012. target_clock = mode->clock;
  3013. else
  3014. target_clock = adjusted_mode->clock;
  3015. link_bw = 270000;
  3016. }
  3017. /* determine panel color depth */
  3018. temp = I915_READ(pipeconf_reg);
  3019. temp &= ~PIPE_BPC_MASK;
  3020. if (is_lvds) {
  3021. int lvds_reg = I915_READ(PCH_LVDS);
  3022. /* the BPC will be 6 if it is 18-bit LVDS panel */
  3023. if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  3024. temp |= PIPE_8BPC;
  3025. else
  3026. temp |= PIPE_6BPC;
  3027. } else if (is_edp) {
  3028. switch (dev_priv->edp_bpp/3) {
  3029. case 8:
  3030. temp |= PIPE_8BPC;
  3031. break;
  3032. case 10:
  3033. temp |= PIPE_10BPC;
  3034. break;
  3035. case 6:
  3036. temp |= PIPE_6BPC;
  3037. break;
  3038. case 12:
  3039. temp |= PIPE_12BPC;
  3040. break;
  3041. }
  3042. } else
  3043. temp |= PIPE_8BPC;
  3044. I915_WRITE(pipeconf_reg, temp);
  3045. I915_READ(pipeconf_reg);
  3046. switch (temp & PIPE_BPC_MASK) {
  3047. case PIPE_8BPC:
  3048. bpp = 24;
  3049. break;
  3050. case PIPE_10BPC:
  3051. bpp = 30;
  3052. break;
  3053. case PIPE_6BPC:
  3054. bpp = 18;
  3055. break;
  3056. case PIPE_12BPC:
  3057. bpp = 36;
  3058. break;
  3059. default:
  3060. DRM_ERROR("unknown pipe bpc value\n");
  3061. bpp = 24;
  3062. }
  3063. if (!lane) {
  3064. /*
  3065. * Account for spread spectrum to avoid
  3066. * oversubscribing the link. Max center spread
  3067. * is 2.5%; use 5% for safety's sake.
  3068. */
  3069. u32 bps = target_clock * bpp * 21 / 20;
  3070. lane = bps / (link_bw * 8) + 1;
  3071. }
  3072. intel_crtc->fdi_lanes = lane;
  3073. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  3074. }
  3075. /* Ironlake: try to setup display ref clock before DPLL
  3076. * enabling. This is only under driver's control after
  3077. * PCH B stepping, previous chipset stepping should be
  3078. * ignoring this setting.
  3079. */
  3080. if (HAS_PCH_SPLIT(dev)) {
  3081. temp = I915_READ(PCH_DREF_CONTROL);
  3082. /* Always enable nonspread source */
  3083. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3084. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3085. I915_WRITE(PCH_DREF_CONTROL, temp);
  3086. POSTING_READ(PCH_DREF_CONTROL);
  3087. temp &= ~DREF_SSC_SOURCE_MASK;
  3088. temp |= DREF_SSC_SOURCE_ENABLE;
  3089. I915_WRITE(PCH_DREF_CONTROL, temp);
  3090. POSTING_READ(PCH_DREF_CONTROL);
  3091. udelay(200);
  3092. if (is_edp) {
  3093. if (dev_priv->lvds_use_ssc) {
  3094. temp |= DREF_SSC1_ENABLE;
  3095. I915_WRITE(PCH_DREF_CONTROL, temp);
  3096. POSTING_READ(PCH_DREF_CONTROL);
  3097. udelay(200);
  3098. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3099. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3100. I915_WRITE(PCH_DREF_CONTROL, temp);
  3101. POSTING_READ(PCH_DREF_CONTROL);
  3102. } else {
  3103. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3104. I915_WRITE(PCH_DREF_CONTROL, temp);
  3105. POSTING_READ(PCH_DREF_CONTROL);
  3106. }
  3107. }
  3108. }
  3109. if (IS_PINEVIEW(dev)) {
  3110. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3111. if (has_reduced_clock)
  3112. fp2 = (1 << reduced_clock.n) << 16 |
  3113. reduced_clock.m1 << 8 | reduced_clock.m2;
  3114. } else {
  3115. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3116. if (has_reduced_clock)
  3117. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3118. reduced_clock.m2;
  3119. }
  3120. if (!HAS_PCH_SPLIT(dev))
  3121. dpll = DPLL_VGA_MODE_DIS;
  3122. if (IS_I9XX(dev)) {
  3123. if (is_lvds)
  3124. dpll |= DPLLB_MODE_LVDS;
  3125. else
  3126. dpll |= DPLLB_MODE_DAC_SERIAL;
  3127. if (is_sdvo) {
  3128. dpll |= DPLL_DVO_HIGH_SPEED;
  3129. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3130. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3131. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3132. else if (HAS_PCH_SPLIT(dev))
  3133. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  3134. }
  3135. if (is_dp)
  3136. dpll |= DPLL_DVO_HIGH_SPEED;
  3137. /* compute bitmask from p1 value */
  3138. if (IS_PINEVIEW(dev))
  3139. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3140. else {
  3141. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3142. /* also FPA1 */
  3143. if (HAS_PCH_SPLIT(dev))
  3144. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3145. if (IS_G4X(dev) && has_reduced_clock)
  3146. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3147. }
  3148. switch (clock.p2) {
  3149. case 5:
  3150. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3151. break;
  3152. case 7:
  3153. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3154. break;
  3155. case 10:
  3156. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3157. break;
  3158. case 14:
  3159. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3160. break;
  3161. }
  3162. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
  3163. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3164. } else {
  3165. if (is_lvds) {
  3166. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3167. } else {
  3168. if (clock.p1 == 2)
  3169. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3170. else
  3171. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3172. if (clock.p2 == 4)
  3173. dpll |= PLL_P2_DIVIDE_BY_4;
  3174. }
  3175. }
  3176. if (is_sdvo && is_tv)
  3177. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3178. else if (is_tv)
  3179. /* XXX: just matching BIOS for now */
  3180. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3181. dpll |= 3;
  3182. else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
  3183. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3184. else
  3185. dpll |= PLL_REF_INPUT_DREFCLK;
  3186. /* setup pipeconf */
  3187. pipeconf = I915_READ(pipeconf_reg);
  3188. /* Set up the display plane register */
  3189. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3190. /* Ironlake's plane is forced to pipe, bit 24 is to
  3191. enable color space conversion */
  3192. if (!HAS_PCH_SPLIT(dev)) {
  3193. if (pipe == 0)
  3194. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3195. else
  3196. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3197. }
  3198. if (pipe == 0 && !IS_I965G(dev)) {
  3199. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3200. * core speed.
  3201. *
  3202. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3203. * pipe == 0 check?
  3204. */
  3205. if (mode->clock >
  3206. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3207. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  3208. else
  3209. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  3210. }
  3211. dspcntr |= DISPLAY_PLANE_ENABLE;
  3212. pipeconf |= PIPEACONF_ENABLE;
  3213. dpll |= DPLL_VCO_ENABLE;
  3214. /* Disable the panel fitter if it was on our pipe */
  3215. if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
  3216. I915_WRITE(PFIT_CONTROL, 0);
  3217. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3218. drm_mode_debug_printmodeline(mode);
  3219. /* assign to Ironlake registers */
  3220. if (HAS_PCH_SPLIT(dev)) {
  3221. fp_reg = pch_fp_reg;
  3222. dpll_reg = pch_dpll_reg;
  3223. }
  3224. if (is_edp) {
  3225. ironlake_disable_pll_edp(crtc);
  3226. } else if ((dpll & DPLL_VCO_ENABLE)) {
  3227. I915_WRITE(fp_reg, fp);
  3228. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  3229. I915_READ(dpll_reg);
  3230. udelay(150);
  3231. }
  3232. /* enable transcoder DPLL */
  3233. if (HAS_PCH_CPT(dev)) {
  3234. temp = I915_READ(PCH_DPLL_SEL);
  3235. if (trans_dpll_sel == 0)
  3236. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  3237. else
  3238. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  3239. I915_WRITE(PCH_DPLL_SEL, temp);
  3240. I915_READ(PCH_DPLL_SEL);
  3241. udelay(150);
  3242. }
  3243. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3244. * This is an exception to the general rule that mode_set doesn't turn
  3245. * things on.
  3246. */
  3247. if (is_lvds) {
  3248. u32 lvds;
  3249. if (HAS_PCH_SPLIT(dev))
  3250. lvds_reg = PCH_LVDS;
  3251. lvds = I915_READ(lvds_reg);
  3252. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3253. if (pipe == 1) {
  3254. if (HAS_PCH_CPT(dev))
  3255. lvds |= PORT_TRANS_B_SEL_CPT;
  3256. else
  3257. lvds |= LVDS_PIPEB_SELECT;
  3258. } else {
  3259. if (HAS_PCH_CPT(dev))
  3260. lvds &= ~PORT_TRANS_SEL_MASK;
  3261. else
  3262. lvds &= ~LVDS_PIPEB_SELECT;
  3263. }
  3264. /* set the corresponsding LVDS_BORDER bit */
  3265. lvds |= dev_priv->lvds_border_bits;
  3266. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3267. * set the DPLLs for dual-channel mode or not.
  3268. */
  3269. if (clock.p2 == 7)
  3270. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3271. else
  3272. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3273. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3274. * appropriately here, but we need to look more thoroughly into how
  3275. * panels behave in the two modes.
  3276. */
  3277. /* set the dithering flag */
  3278. if (IS_I965G(dev)) {
  3279. if (dev_priv->lvds_dither) {
  3280. if (HAS_PCH_SPLIT(dev)) {
  3281. pipeconf |= PIPE_ENABLE_DITHER;
  3282. pipeconf |= PIPE_DITHER_TYPE_ST01;
  3283. } else
  3284. lvds |= LVDS_ENABLE_DITHER;
  3285. } else {
  3286. if (HAS_PCH_SPLIT(dev)) {
  3287. pipeconf &= ~PIPE_ENABLE_DITHER;
  3288. pipeconf &= ~PIPE_DITHER_TYPE_MASK;
  3289. } else
  3290. lvds &= ~LVDS_ENABLE_DITHER;
  3291. }
  3292. }
  3293. I915_WRITE(lvds_reg, lvds);
  3294. I915_READ(lvds_reg);
  3295. }
  3296. if (is_dp)
  3297. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3298. else if (HAS_PCH_SPLIT(dev)) {
  3299. /* For non-DP output, clear any trans DP clock recovery setting.*/
  3300. if (pipe == 0) {
  3301. I915_WRITE(TRANSA_DATA_M1, 0);
  3302. I915_WRITE(TRANSA_DATA_N1, 0);
  3303. I915_WRITE(TRANSA_DP_LINK_M1, 0);
  3304. I915_WRITE(TRANSA_DP_LINK_N1, 0);
  3305. } else {
  3306. I915_WRITE(TRANSB_DATA_M1, 0);
  3307. I915_WRITE(TRANSB_DATA_N1, 0);
  3308. I915_WRITE(TRANSB_DP_LINK_M1, 0);
  3309. I915_WRITE(TRANSB_DP_LINK_N1, 0);
  3310. }
  3311. }
  3312. if (!is_edp) {
  3313. I915_WRITE(fp_reg, fp);
  3314. I915_WRITE(dpll_reg, dpll);
  3315. I915_READ(dpll_reg);
  3316. /* Wait for the clocks to stabilize. */
  3317. udelay(150);
  3318. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
  3319. if (is_sdvo) {
  3320. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3321. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  3322. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  3323. } else
  3324. I915_WRITE(dpll_md_reg, 0);
  3325. } else {
  3326. /* write it again -- the BIOS does, after all */
  3327. I915_WRITE(dpll_reg, dpll);
  3328. }
  3329. I915_READ(dpll_reg);
  3330. /* Wait for the clocks to stabilize. */
  3331. udelay(150);
  3332. }
  3333. if (is_lvds && has_reduced_clock && i915_powersave) {
  3334. I915_WRITE(fp_reg + 4, fp2);
  3335. intel_crtc->lowfreq_avail = true;
  3336. if (HAS_PIPE_CXSR(dev)) {
  3337. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3338. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3339. }
  3340. } else {
  3341. I915_WRITE(fp_reg + 4, fp);
  3342. intel_crtc->lowfreq_avail = false;
  3343. if (HAS_PIPE_CXSR(dev)) {
  3344. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3345. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3346. }
  3347. }
  3348. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3349. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3350. /* the chip adds 2 halflines automatically */
  3351. adjusted_mode->crtc_vdisplay -= 1;
  3352. adjusted_mode->crtc_vtotal -= 1;
  3353. adjusted_mode->crtc_vblank_start -= 1;
  3354. adjusted_mode->crtc_vblank_end -= 1;
  3355. adjusted_mode->crtc_vsync_end -= 1;
  3356. adjusted_mode->crtc_vsync_start -= 1;
  3357. } else
  3358. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  3359. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  3360. ((adjusted_mode->crtc_htotal - 1) << 16));
  3361. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  3362. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3363. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  3364. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3365. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  3366. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3367. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  3368. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3369. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  3370. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3371. /* pipesrc and dspsize control the size that is scaled from, which should
  3372. * always be the user's requested size.
  3373. */
  3374. if (!HAS_PCH_SPLIT(dev)) {
  3375. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  3376. (mode->hdisplay - 1));
  3377. I915_WRITE(dsppos_reg, 0);
  3378. }
  3379. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3380. if (HAS_PCH_SPLIT(dev)) {
  3381. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  3382. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  3383. I915_WRITE(link_m1_reg, m_n.link_m);
  3384. I915_WRITE(link_n1_reg, m_n.link_n);
  3385. if (is_edp) {
  3386. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  3387. } else {
  3388. /* enable FDI RX PLL too */
  3389. temp = I915_READ(fdi_rx_reg);
  3390. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  3391. I915_READ(fdi_rx_reg);
  3392. udelay(200);
  3393. /* enable FDI TX PLL too */
  3394. temp = I915_READ(fdi_tx_reg);
  3395. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  3396. I915_READ(fdi_tx_reg);
  3397. /* enable FDI RX PCDCLK */
  3398. temp = I915_READ(fdi_rx_reg);
  3399. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  3400. I915_READ(fdi_rx_reg);
  3401. udelay(200);
  3402. }
  3403. }
  3404. I915_WRITE(pipeconf_reg, pipeconf);
  3405. I915_READ(pipeconf_reg);
  3406. intel_wait_for_vblank(dev);
  3407. if (IS_IRONLAKE(dev)) {
  3408. /* enable address swizzle for tiling buffer */
  3409. temp = I915_READ(DISP_ARB_CTL);
  3410. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  3411. }
  3412. I915_WRITE(dspcntr_reg, dspcntr);
  3413. /* Flush the plane changes */
  3414. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3415. if ((IS_I965G(dev) || plane == 0))
  3416. intel_update_fbc(crtc, &crtc->mode);
  3417. intel_update_watermarks(dev);
  3418. drm_vblank_post_modeset(dev, pipe);
  3419. return ret;
  3420. }
  3421. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  3422. void intel_crtc_load_lut(struct drm_crtc *crtc)
  3423. {
  3424. struct drm_device *dev = crtc->dev;
  3425. struct drm_i915_private *dev_priv = dev->dev_private;
  3426. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3427. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  3428. int i;
  3429. /* The clocks have to be on to load the palette. */
  3430. if (!crtc->enabled)
  3431. return;
  3432. /* use legacy palette for Ironlake */
  3433. if (HAS_PCH_SPLIT(dev))
  3434. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  3435. LGC_PALETTE_B;
  3436. for (i = 0; i < 256; i++) {
  3437. I915_WRITE(palreg + 4 * i,
  3438. (intel_crtc->lut_r[i] << 16) |
  3439. (intel_crtc->lut_g[i] << 8) |
  3440. intel_crtc->lut_b[i]);
  3441. }
  3442. }
  3443. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  3444. struct drm_file *file_priv,
  3445. uint32_t handle,
  3446. uint32_t width, uint32_t height)
  3447. {
  3448. struct drm_device *dev = crtc->dev;
  3449. struct drm_i915_private *dev_priv = dev->dev_private;
  3450. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3451. struct drm_gem_object *bo;
  3452. struct drm_i915_gem_object *obj_priv;
  3453. int pipe = intel_crtc->pipe;
  3454. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  3455. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  3456. uint32_t temp = I915_READ(control);
  3457. size_t addr;
  3458. int ret;
  3459. DRM_DEBUG_KMS("\n");
  3460. /* if we want to turn off the cursor ignore width and height */
  3461. if (!handle) {
  3462. DRM_DEBUG_KMS("cursor off\n");
  3463. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3464. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  3465. temp |= CURSOR_MODE_DISABLE;
  3466. } else {
  3467. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  3468. }
  3469. addr = 0;
  3470. bo = NULL;
  3471. mutex_lock(&dev->struct_mutex);
  3472. goto finish;
  3473. }
  3474. /* Currently we only support 64x64 cursors */
  3475. if (width != 64 || height != 64) {
  3476. DRM_ERROR("we currently only support 64x64 cursors\n");
  3477. return -EINVAL;
  3478. }
  3479. bo = drm_gem_object_lookup(dev, file_priv, handle);
  3480. if (!bo)
  3481. return -ENOENT;
  3482. obj_priv = to_intel_bo(bo);
  3483. if (bo->size < width * height * 4) {
  3484. DRM_ERROR("buffer is to small\n");
  3485. ret = -ENOMEM;
  3486. goto fail;
  3487. }
  3488. /* we only need to pin inside GTT if cursor is non-phy */
  3489. mutex_lock(&dev->struct_mutex);
  3490. if (!dev_priv->info->cursor_needs_physical) {
  3491. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  3492. if (ret) {
  3493. DRM_ERROR("failed to pin cursor bo\n");
  3494. goto fail_locked;
  3495. }
  3496. ret = i915_gem_object_set_to_gtt_domain(bo, 0);
  3497. if (ret) {
  3498. DRM_ERROR("failed to move cursor bo into the GTT\n");
  3499. goto fail_unpin;
  3500. }
  3501. addr = obj_priv->gtt_offset;
  3502. } else {
  3503. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  3504. if (ret) {
  3505. DRM_ERROR("failed to attach phys object\n");
  3506. goto fail_locked;
  3507. }
  3508. addr = obj_priv->phys_obj->handle->busaddr;
  3509. }
  3510. if (!IS_I9XX(dev))
  3511. I915_WRITE(CURSIZE, (height << 12) | width);
  3512. /* Hooray for CUR*CNTR differences */
  3513. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3514. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  3515. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  3516. temp |= (pipe << 28); /* Connect to correct pipe */
  3517. } else {
  3518. temp &= ~(CURSOR_FORMAT_MASK);
  3519. temp |= CURSOR_ENABLE;
  3520. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  3521. }
  3522. finish:
  3523. I915_WRITE(control, temp);
  3524. I915_WRITE(base, addr);
  3525. if (intel_crtc->cursor_bo) {
  3526. if (dev_priv->info->cursor_needs_physical) {
  3527. if (intel_crtc->cursor_bo != bo)
  3528. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  3529. } else
  3530. i915_gem_object_unpin(intel_crtc->cursor_bo);
  3531. drm_gem_object_unreference(intel_crtc->cursor_bo);
  3532. }
  3533. mutex_unlock(&dev->struct_mutex);
  3534. intel_crtc->cursor_addr = addr;
  3535. intel_crtc->cursor_bo = bo;
  3536. return 0;
  3537. fail_unpin:
  3538. i915_gem_object_unpin(bo);
  3539. fail_locked:
  3540. mutex_unlock(&dev->struct_mutex);
  3541. fail:
  3542. drm_gem_object_unreference_unlocked(bo);
  3543. return ret;
  3544. }
  3545. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  3546. {
  3547. struct drm_device *dev = crtc->dev;
  3548. struct drm_i915_private *dev_priv = dev->dev_private;
  3549. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3550. struct intel_framebuffer *intel_fb;
  3551. int pipe = intel_crtc->pipe;
  3552. uint32_t temp = 0;
  3553. uint32_t adder;
  3554. if (crtc->fb) {
  3555. intel_fb = to_intel_framebuffer(crtc->fb);
  3556. intel_mark_busy(dev, intel_fb->obj);
  3557. }
  3558. if (x < 0) {
  3559. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  3560. x = -x;
  3561. }
  3562. if (y < 0) {
  3563. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  3564. y = -y;
  3565. }
  3566. temp |= x << CURSOR_X_SHIFT;
  3567. temp |= y << CURSOR_Y_SHIFT;
  3568. adder = intel_crtc->cursor_addr;
  3569. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  3570. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  3571. return 0;
  3572. }
  3573. /** Sets the color ramps on behalf of RandR */
  3574. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3575. u16 blue, int regno)
  3576. {
  3577. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3578. intel_crtc->lut_r[regno] = red >> 8;
  3579. intel_crtc->lut_g[regno] = green >> 8;
  3580. intel_crtc->lut_b[regno] = blue >> 8;
  3581. }
  3582. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3583. u16 *blue, int regno)
  3584. {
  3585. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3586. *red = intel_crtc->lut_r[regno] << 8;
  3587. *green = intel_crtc->lut_g[regno] << 8;
  3588. *blue = intel_crtc->lut_b[regno] << 8;
  3589. }
  3590. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3591. u16 *blue, uint32_t size)
  3592. {
  3593. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3594. int i;
  3595. if (size != 256)
  3596. return;
  3597. for (i = 0; i < 256; i++) {
  3598. intel_crtc->lut_r[i] = red[i] >> 8;
  3599. intel_crtc->lut_g[i] = green[i] >> 8;
  3600. intel_crtc->lut_b[i] = blue[i] >> 8;
  3601. }
  3602. intel_crtc_load_lut(crtc);
  3603. }
  3604. /**
  3605. * Get a pipe with a simple mode set on it for doing load-based monitor
  3606. * detection.
  3607. *
  3608. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3609. * its requirements. The pipe will be connected to no other encoders.
  3610. *
  3611. * Currently this code will only succeed if there is a pipe with no encoders
  3612. * configured for it. In the future, it could choose to temporarily disable
  3613. * some outputs to free up a pipe for its use.
  3614. *
  3615. * \return crtc, or NULL if no pipes are available.
  3616. */
  3617. /* VESA 640x480x72Hz mode to set on the pipe */
  3618. static struct drm_display_mode load_detect_mode = {
  3619. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3620. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3621. };
  3622. struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  3623. struct drm_connector *connector,
  3624. struct drm_display_mode *mode,
  3625. int *dpms_mode)
  3626. {
  3627. struct intel_crtc *intel_crtc;
  3628. struct drm_crtc *possible_crtc;
  3629. struct drm_crtc *supported_crtc =NULL;
  3630. struct drm_encoder *encoder = &intel_encoder->enc;
  3631. struct drm_crtc *crtc = NULL;
  3632. struct drm_device *dev = encoder->dev;
  3633. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3634. struct drm_crtc_helper_funcs *crtc_funcs;
  3635. int i = -1;
  3636. /*
  3637. * Algorithm gets a little messy:
  3638. * - if the connector already has an assigned crtc, use it (but make
  3639. * sure it's on first)
  3640. * - try to find the first unused crtc that can drive this connector,
  3641. * and use that if we find one
  3642. * - if there are no unused crtcs available, try to use the first
  3643. * one we found that supports the connector
  3644. */
  3645. /* See if we already have a CRTC for this connector */
  3646. if (encoder->crtc) {
  3647. crtc = encoder->crtc;
  3648. /* Make sure the crtc and connector are running */
  3649. intel_crtc = to_intel_crtc(crtc);
  3650. *dpms_mode = intel_crtc->dpms_mode;
  3651. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3652. crtc_funcs = crtc->helper_private;
  3653. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3654. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3655. }
  3656. return crtc;
  3657. }
  3658. /* Find an unused one (if possible) */
  3659. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3660. i++;
  3661. if (!(encoder->possible_crtcs & (1 << i)))
  3662. continue;
  3663. if (!possible_crtc->enabled) {
  3664. crtc = possible_crtc;
  3665. break;
  3666. }
  3667. if (!supported_crtc)
  3668. supported_crtc = possible_crtc;
  3669. }
  3670. /*
  3671. * If we didn't find an unused CRTC, don't use any.
  3672. */
  3673. if (!crtc) {
  3674. return NULL;
  3675. }
  3676. encoder->crtc = crtc;
  3677. connector->encoder = encoder;
  3678. intel_encoder->load_detect_temp = true;
  3679. intel_crtc = to_intel_crtc(crtc);
  3680. *dpms_mode = intel_crtc->dpms_mode;
  3681. if (!crtc->enabled) {
  3682. if (!mode)
  3683. mode = &load_detect_mode;
  3684. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3685. } else {
  3686. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3687. crtc_funcs = crtc->helper_private;
  3688. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3689. }
  3690. /* Add this connector to the crtc */
  3691. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3692. encoder_funcs->commit(encoder);
  3693. }
  3694. /* let the connector get through one full cycle before testing */
  3695. intel_wait_for_vblank(dev);
  3696. return crtc;
  3697. }
  3698. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  3699. struct drm_connector *connector, int dpms_mode)
  3700. {
  3701. struct drm_encoder *encoder = &intel_encoder->enc;
  3702. struct drm_device *dev = encoder->dev;
  3703. struct drm_crtc *crtc = encoder->crtc;
  3704. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3705. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3706. if (intel_encoder->load_detect_temp) {
  3707. encoder->crtc = NULL;
  3708. connector->encoder = NULL;
  3709. intel_encoder->load_detect_temp = false;
  3710. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3711. drm_helper_disable_unused_functions(dev);
  3712. }
  3713. /* Switch crtc and encoder back off if necessary */
  3714. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3715. if (encoder->crtc == crtc)
  3716. encoder_funcs->dpms(encoder, dpms_mode);
  3717. crtc_funcs->dpms(crtc, dpms_mode);
  3718. }
  3719. }
  3720. /* Returns the clock of the currently programmed mode of the given pipe. */
  3721. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  3722. {
  3723. struct drm_i915_private *dev_priv = dev->dev_private;
  3724. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3725. int pipe = intel_crtc->pipe;
  3726. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  3727. u32 fp;
  3728. intel_clock_t clock;
  3729. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  3730. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  3731. else
  3732. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  3733. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  3734. if (IS_PINEVIEW(dev)) {
  3735. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  3736. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3737. } else {
  3738. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  3739. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3740. }
  3741. if (IS_I9XX(dev)) {
  3742. if (IS_PINEVIEW(dev))
  3743. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  3744. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  3745. else
  3746. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  3747. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3748. switch (dpll & DPLL_MODE_MASK) {
  3749. case DPLLB_MODE_DAC_SERIAL:
  3750. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  3751. 5 : 10;
  3752. break;
  3753. case DPLLB_MODE_LVDS:
  3754. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  3755. 7 : 14;
  3756. break;
  3757. default:
  3758. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  3759. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  3760. return 0;
  3761. }
  3762. /* XXX: Handle the 100Mhz refclk */
  3763. intel_clock(dev, 96000, &clock);
  3764. } else {
  3765. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  3766. if (is_lvds) {
  3767. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  3768. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3769. clock.p2 = 14;
  3770. if ((dpll & PLL_REF_INPUT_MASK) ==
  3771. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  3772. /* XXX: might not be 66MHz */
  3773. intel_clock(dev, 66000, &clock);
  3774. } else
  3775. intel_clock(dev, 48000, &clock);
  3776. } else {
  3777. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  3778. clock.p1 = 2;
  3779. else {
  3780. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  3781. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  3782. }
  3783. if (dpll & PLL_P2_DIVIDE_BY_4)
  3784. clock.p2 = 4;
  3785. else
  3786. clock.p2 = 2;
  3787. intel_clock(dev, 48000, &clock);
  3788. }
  3789. }
  3790. /* XXX: It would be nice to validate the clocks, but we can't reuse
  3791. * i830PllIsValid() because it relies on the xf86_config connector
  3792. * configuration being accurate, which it isn't necessarily.
  3793. */
  3794. return clock.dot;
  3795. }
  3796. /** Returns the currently programmed mode of the given pipe. */
  3797. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  3798. struct drm_crtc *crtc)
  3799. {
  3800. struct drm_i915_private *dev_priv = dev->dev_private;
  3801. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3802. int pipe = intel_crtc->pipe;
  3803. struct drm_display_mode *mode;
  3804. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  3805. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  3806. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  3807. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  3808. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  3809. if (!mode)
  3810. return NULL;
  3811. mode->clock = intel_crtc_clock_get(dev, crtc);
  3812. mode->hdisplay = (htot & 0xffff) + 1;
  3813. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  3814. mode->hsync_start = (hsync & 0xffff) + 1;
  3815. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  3816. mode->vdisplay = (vtot & 0xffff) + 1;
  3817. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  3818. mode->vsync_start = (vsync & 0xffff) + 1;
  3819. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  3820. drm_mode_set_name(mode);
  3821. drm_mode_set_crtcinfo(mode, 0);
  3822. return mode;
  3823. }
  3824. #define GPU_IDLE_TIMEOUT 500 /* ms */
  3825. /* When this timer fires, we've been idle for awhile */
  3826. static void intel_gpu_idle_timer(unsigned long arg)
  3827. {
  3828. struct drm_device *dev = (struct drm_device *)arg;
  3829. drm_i915_private_t *dev_priv = dev->dev_private;
  3830. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3831. dev_priv->busy = false;
  3832. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3833. }
  3834. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  3835. static void intel_crtc_idle_timer(unsigned long arg)
  3836. {
  3837. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  3838. struct drm_crtc *crtc = &intel_crtc->base;
  3839. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  3840. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3841. intel_crtc->busy = false;
  3842. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3843. }
  3844. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
  3845. {
  3846. struct drm_device *dev = crtc->dev;
  3847. drm_i915_private_t *dev_priv = dev->dev_private;
  3848. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3849. int pipe = intel_crtc->pipe;
  3850. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3851. int dpll = I915_READ(dpll_reg);
  3852. if (HAS_PCH_SPLIT(dev))
  3853. return;
  3854. if (!dev_priv->lvds_downclock_avail)
  3855. return;
  3856. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  3857. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  3858. /* Unlock panel regs */
  3859. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3860. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  3861. I915_WRITE(dpll_reg, dpll);
  3862. dpll = I915_READ(dpll_reg);
  3863. intel_wait_for_vblank(dev);
  3864. dpll = I915_READ(dpll_reg);
  3865. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  3866. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  3867. /* ...and lock them again */
  3868. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3869. }
  3870. /* Schedule downclock */
  3871. if (schedule)
  3872. mod_timer(&intel_crtc->idle_timer, jiffies +
  3873. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3874. }
  3875. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  3876. {
  3877. struct drm_device *dev = crtc->dev;
  3878. drm_i915_private_t *dev_priv = dev->dev_private;
  3879. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3880. int pipe = intel_crtc->pipe;
  3881. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3882. int dpll = I915_READ(dpll_reg);
  3883. if (HAS_PCH_SPLIT(dev))
  3884. return;
  3885. if (!dev_priv->lvds_downclock_avail)
  3886. return;
  3887. /*
  3888. * Since this is called by a timer, we should never get here in
  3889. * the manual case.
  3890. */
  3891. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  3892. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  3893. /* Unlock panel regs */
  3894. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3895. dpll |= DISPLAY_RATE_SELECT_FPA1;
  3896. I915_WRITE(dpll_reg, dpll);
  3897. dpll = I915_READ(dpll_reg);
  3898. intel_wait_for_vblank(dev);
  3899. dpll = I915_READ(dpll_reg);
  3900. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  3901. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  3902. /* ...and lock them again */
  3903. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3904. }
  3905. }
  3906. /**
  3907. * intel_idle_update - adjust clocks for idleness
  3908. * @work: work struct
  3909. *
  3910. * Either the GPU or display (or both) went idle. Check the busy status
  3911. * here and adjust the CRTC and GPU clocks as necessary.
  3912. */
  3913. static void intel_idle_update(struct work_struct *work)
  3914. {
  3915. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  3916. idle_work);
  3917. struct drm_device *dev = dev_priv->dev;
  3918. struct drm_crtc *crtc;
  3919. struct intel_crtc *intel_crtc;
  3920. int enabled = 0;
  3921. if (!i915_powersave)
  3922. return;
  3923. mutex_lock(&dev->struct_mutex);
  3924. i915_update_gfx_val(dev_priv);
  3925. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3926. /* Skip inactive CRTCs */
  3927. if (!crtc->fb)
  3928. continue;
  3929. enabled++;
  3930. intel_crtc = to_intel_crtc(crtc);
  3931. if (!intel_crtc->busy)
  3932. intel_decrease_pllclock(crtc);
  3933. }
  3934. if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
  3935. DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
  3936. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  3937. }
  3938. mutex_unlock(&dev->struct_mutex);
  3939. }
  3940. /**
  3941. * intel_mark_busy - mark the GPU and possibly the display busy
  3942. * @dev: drm device
  3943. * @obj: object we're operating on
  3944. *
  3945. * Callers can use this function to indicate that the GPU is busy processing
  3946. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  3947. * buffer), we'll also mark the display as busy, so we know to increase its
  3948. * clock frequency.
  3949. */
  3950. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  3951. {
  3952. drm_i915_private_t *dev_priv = dev->dev_private;
  3953. struct drm_crtc *crtc = NULL;
  3954. struct intel_framebuffer *intel_fb;
  3955. struct intel_crtc *intel_crtc;
  3956. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  3957. return;
  3958. if (!dev_priv->busy) {
  3959. if (IS_I945G(dev) || IS_I945GM(dev)) {
  3960. u32 fw_blc_self;
  3961. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  3962. fw_blc_self = I915_READ(FW_BLC_SELF);
  3963. fw_blc_self &= ~FW_BLC_SELF_EN;
  3964. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  3965. }
  3966. dev_priv->busy = true;
  3967. } else
  3968. mod_timer(&dev_priv->idle_timer, jiffies +
  3969. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  3970. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3971. if (!crtc->fb)
  3972. continue;
  3973. intel_crtc = to_intel_crtc(crtc);
  3974. intel_fb = to_intel_framebuffer(crtc->fb);
  3975. if (intel_fb->obj == obj) {
  3976. if (!intel_crtc->busy) {
  3977. if (IS_I945G(dev) || IS_I945GM(dev)) {
  3978. u32 fw_blc_self;
  3979. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  3980. fw_blc_self = I915_READ(FW_BLC_SELF);
  3981. fw_blc_self &= ~FW_BLC_SELF_EN;
  3982. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  3983. }
  3984. /* Non-busy -> busy, upclock */
  3985. intel_increase_pllclock(crtc, true);
  3986. intel_crtc->busy = true;
  3987. } else {
  3988. /* Busy -> busy, put off timer */
  3989. mod_timer(&intel_crtc->idle_timer, jiffies +
  3990. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3991. }
  3992. }
  3993. }
  3994. }
  3995. static void intel_crtc_destroy(struct drm_crtc *crtc)
  3996. {
  3997. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3998. drm_crtc_cleanup(crtc);
  3999. kfree(intel_crtc);
  4000. }
  4001. struct intel_unpin_work {
  4002. struct work_struct work;
  4003. struct drm_device *dev;
  4004. struct drm_gem_object *old_fb_obj;
  4005. struct drm_gem_object *pending_flip_obj;
  4006. struct drm_pending_vblank_event *event;
  4007. int pending;
  4008. };
  4009. static void intel_unpin_work_fn(struct work_struct *__work)
  4010. {
  4011. struct intel_unpin_work *work =
  4012. container_of(__work, struct intel_unpin_work, work);
  4013. mutex_lock(&work->dev->struct_mutex);
  4014. i915_gem_object_unpin(work->old_fb_obj);
  4015. drm_gem_object_unreference(work->pending_flip_obj);
  4016. drm_gem_object_unreference(work->old_fb_obj);
  4017. mutex_unlock(&work->dev->struct_mutex);
  4018. kfree(work);
  4019. }
  4020. static void do_intel_finish_page_flip(struct drm_device *dev,
  4021. struct drm_crtc *crtc)
  4022. {
  4023. drm_i915_private_t *dev_priv = dev->dev_private;
  4024. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4025. struct intel_unpin_work *work;
  4026. struct drm_i915_gem_object *obj_priv;
  4027. struct drm_pending_vblank_event *e;
  4028. struct timeval now;
  4029. unsigned long flags;
  4030. /* Ignore early vblank irqs */
  4031. if (intel_crtc == NULL)
  4032. return;
  4033. spin_lock_irqsave(&dev->event_lock, flags);
  4034. work = intel_crtc->unpin_work;
  4035. if (work == NULL || !work->pending) {
  4036. spin_unlock_irqrestore(&dev->event_lock, flags);
  4037. return;
  4038. }
  4039. intel_crtc->unpin_work = NULL;
  4040. drm_vblank_put(dev, intel_crtc->pipe);
  4041. if (work->event) {
  4042. e = work->event;
  4043. do_gettimeofday(&now);
  4044. e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
  4045. e->event.tv_sec = now.tv_sec;
  4046. e->event.tv_usec = now.tv_usec;
  4047. list_add_tail(&e->base.link,
  4048. &e->base.file_priv->event_list);
  4049. wake_up_interruptible(&e->base.file_priv->event_wait);
  4050. }
  4051. spin_unlock_irqrestore(&dev->event_lock, flags);
  4052. obj_priv = to_intel_bo(work->pending_flip_obj);
  4053. /* Initial scanout buffer will have a 0 pending flip count */
  4054. if ((atomic_read(&obj_priv->pending_flip) == 0) ||
  4055. atomic_dec_and_test(&obj_priv->pending_flip))
  4056. DRM_WAKEUP(&dev_priv->pending_flip_queue);
  4057. schedule_work(&work->work);
  4058. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  4059. }
  4060. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  4061. {
  4062. drm_i915_private_t *dev_priv = dev->dev_private;
  4063. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  4064. do_intel_finish_page_flip(dev, crtc);
  4065. }
  4066. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  4067. {
  4068. drm_i915_private_t *dev_priv = dev->dev_private;
  4069. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  4070. do_intel_finish_page_flip(dev, crtc);
  4071. }
  4072. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  4073. {
  4074. drm_i915_private_t *dev_priv = dev->dev_private;
  4075. struct intel_crtc *intel_crtc =
  4076. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  4077. unsigned long flags;
  4078. spin_lock_irqsave(&dev->event_lock, flags);
  4079. if (intel_crtc->unpin_work) {
  4080. intel_crtc->unpin_work->pending = 1;
  4081. } else {
  4082. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  4083. }
  4084. spin_unlock_irqrestore(&dev->event_lock, flags);
  4085. }
  4086. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  4087. struct drm_framebuffer *fb,
  4088. struct drm_pending_vblank_event *event)
  4089. {
  4090. struct drm_device *dev = crtc->dev;
  4091. struct drm_i915_private *dev_priv = dev->dev_private;
  4092. struct intel_framebuffer *intel_fb;
  4093. struct drm_i915_gem_object *obj_priv;
  4094. struct drm_gem_object *obj;
  4095. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4096. struct intel_unpin_work *work;
  4097. unsigned long flags;
  4098. int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
  4099. int ret, pipesrc;
  4100. u32 flip_mask;
  4101. work = kzalloc(sizeof *work, GFP_KERNEL);
  4102. if (work == NULL)
  4103. return -ENOMEM;
  4104. work->event = event;
  4105. work->dev = crtc->dev;
  4106. intel_fb = to_intel_framebuffer(crtc->fb);
  4107. work->old_fb_obj = intel_fb->obj;
  4108. INIT_WORK(&work->work, intel_unpin_work_fn);
  4109. /* We borrow the event spin lock for protecting unpin_work */
  4110. spin_lock_irqsave(&dev->event_lock, flags);
  4111. if (intel_crtc->unpin_work) {
  4112. spin_unlock_irqrestore(&dev->event_lock, flags);
  4113. kfree(work);
  4114. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  4115. return -EBUSY;
  4116. }
  4117. intel_crtc->unpin_work = work;
  4118. spin_unlock_irqrestore(&dev->event_lock, flags);
  4119. intel_fb = to_intel_framebuffer(fb);
  4120. obj = intel_fb->obj;
  4121. mutex_lock(&dev->struct_mutex);
  4122. ret = intel_pin_and_fence_fb_obj(dev, obj);
  4123. if (ret != 0) {
  4124. mutex_unlock(&dev->struct_mutex);
  4125. spin_lock_irqsave(&dev->event_lock, flags);
  4126. intel_crtc->unpin_work = NULL;
  4127. spin_unlock_irqrestore(&dev->event_lock, flags);
  4128. kfree(work);
  4129. DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
  4130. to_intel_bo(obj));
  4131. return ret;
  4132. }
  4133. /* Reference the objects for the scheduled work. */
  4134. drm_gem_object_reference(work->old_fb_obj);
  4135. drm_gem_object_reference(obj);
  4136. crtc->fb = fb;
  4137. i915_gem_object_flush_write_domain(obj);
  4138. drm_vblank_get(dev, intel_crtc->pipe);
  4139. obj_priv = to_intel_bo(obj);
  4140. atomic_inc(&obj_priv->pending_flip);
  4141. work->pending_flip_obj = obj;
  4142. if (intel_crtc->plane)
  4143. flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  4144. else
  4145. flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
  4146. /* Wait for any previous flip to finish */
  4147. if (IS_GEN3(dev))
  4148. while (I915_READ(ISR) & flip_mask)
  4149. ;
  4150. BEGIN_LP_RING(4);
  4151. if (IS_I965G(dev)) {
  4152. OUT_RING(MI_DISPLAY_FLIP |
  4153. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4154. OUT_RING(fb->pitch);
  4155. OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
  4156. pipesrc = I915_READ(pipesrc_reg);
  4157. OUT_RING(pipesrc & 0x0fff0fff);
  4158. } else {
  4159. OUT_RING(MI_DISPLAY_FLIP_I915 |
  4160. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4161. OUT_RING(fb->pitch);
  4162. OUT_RING(obj_priv->gtt_offset);
  4163. OUT_RING(MI_NOOP);
  4164. }
  4165. ADVANCE_LP_RING();
  4166. mutex_unlock(&dev->struct_mutex);
  4167. trace_i915_flip_request(intel_crtc->plane, obj);
  4168. return 0;
  4169. }
  4170. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  4171. .dpms = intel_crtc_dpms,
  4172. .mode_fixup = intel_crtc_mode_fixup,
  4173. .mode_set = intel_crtc_mode_set,
  4174. .mode_set_base = intel_pipe_set_base,
  4175. .prepare = intel_crtc_prepare,
  4176. .commit = intel_crtc_commit,
  4177. .load_lut = intel_crtc_load_lut,
  4178. };
  4179. static const struct drm_crtc_funcs intel_crtc_funcs = {
  4180. .cursor_set = intel_crtc_cursor_set,
  4181. .cursor_move = intel_crtc_cursor_move,
  4182. .gamma_set = intel_crtc_gamma_set,
  4183. .set_config = drm_crtc_helper_set_config,
  4184. .destroy = intel_crtc_destroy,
  4185. .page_flip = intel_crtc_page_flip,
  4186. };
  4187. static void intel_crtc_init(struct drm_device *dev, int pipe)
  4188. {
  4189. drm_i915_private_t *dev_priv = dev->dev_private;
  4190. struct intel_crtc *intel_crtc;
  4191. int i;
  4192. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  4193. if (intel_crtc == NULL)
  4194. return;
  4195. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  4196. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  4197. intel_crtc->pipe = pipe;
  4198. intel_crtc->plane = pipe;
  4199. for (i = 0; i < 256; i++) {
  4200. intel_crtc->lut_r[i] = i;
  4201. intel_crtc->lut_g[i] = i;
  4202. intel_crtc->lut_b[i] = i;
  4203. }
  4204. /* Swap pipes & planes for FBC on pre-965 */
  4205. intel_crtc->pipe = pipe;
  4206. intel_crtc->plane = pipe;
  4207. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  4208. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  4209. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  4210. }
  4211. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  4212. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  4213. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  4214. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  4215. intel_crtc->cursor_addr = 0;
  4216. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  4217. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  4218. intel_crtc->busy = false;
  4219. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  4220. (unsigned long)intel_crtc);
  4221. }
  4222. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  4223. struct drm_file *file_priv)
  4224. {
  4225. drm_i915_private_t *dev_priv = dev->dev_private;
  4226. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  4227. struct drm_mode_object *drmmode_obj;
  4228. struct intel_crtc *crtc;
  4229. if (!dev_priv) {
  4230. DRM_ERROR("called with no initialization\n");
  4231. return -EINVAL;
  4232. }
  4233. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  4234. DRM_MODE_OBJECT_CRTC);
  4235. if (!drmmode_obj) {
  4236. DRM_ERROR("no such CRTC id\n");
  4237. return -EINVAL;
  4238. }
  4239. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  4240. pipe_from_crtc_id->pipe = crtc->pipe;
  4241. return 0;
  4242. }
  4243. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  4244. {
  4245. struct drm_crtc *crtc = NULL;
  4246. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4247. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4248. if (intel_crtc->pipe == pipe)
  4249. break;
  4250. }
  4251. return crtc;
  4252. }
  4253. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  4254. {
  4255. int index_mask = 0;
  4256. struct drm_encoder *encoder;
  4257. int entry = 0;
  4258. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4259. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4260. if (type_mask & intel_encoder->clone_mask)
  4261. index_mask |= (1 << entry);
  4262. entry++;
  4263. }
  4264. return index_mask;
  4265. }
  4266. static void intel_setup_outputs(struct drm_device *dev)
  4267. {
  4268. struct drm_i915_private *dev_priv = dev->dev_private;
  4269. struct drm_encoder *encoder;
  4270. intel_crt_init(dev);
  4271. /* Set up integrated LVDS */
  4272. if (IS_MOBILE(dev) && !IS_I830(dev))
  4273. intel_lvds_init(dev);
  4274. if (HAS_PCH_SPLIT(dev)) {
  4275. int found;
  4276. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  4277. intel_dp_init(dev, DP_A);
  4278. if (I915_READ(HDMIB) & PORT_DETECTED) {
  4279. /* PCH SDVOB multiplex with HDMIB */
  4280. found = intel_sdvo_init(dev, PCH_SDVOB);
  4281. if (!found)
  4282. intel_hdmi_init(dev, HDMIB);
  4283. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  4284. intel_dp_init(dev, PCH_DP_B);
  4285. }
  4286. if (I915_READ(HDMIC) & PORT_DETECTED)
  4287. intel_hdmi_init(dev, HDMIC);
  4288. if (I915_READ(HDMID) & PORT_DETECTED)
  4289. intel_hdmi_init(dev, HDMID);
  4290. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  4291. intel_dp_init(dev, PCH_DP_C);
  4292. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  4293. intel_dp_init(dev, PCH_DP_D);
  4294. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  4295. bool found = false;
  4296. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4297. DRM_DEBUG_KMS("probing SDVOB\n");
  4298. found = intel_sdvo_init(dev, SDVOB);
  4299. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  4300. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  4301. intel_hdmi_init(dev, SDVOB);
  4302. }
  4303. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  4304. DRM_DEBUG_KMS("probing DP_B\n");
  4305. intel_dp_init(dev, DP_B);
  4306. }
  4307. }
  4308. /* Before G4X SDVOC doesn't have its own detect register */
  4309. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4310. DRM_DEBUG_KMS("probing SDVOC\n");
  4311. found = intel_sdvo_init(dev, SDVOC);
  4312. }
  4313. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  4314. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  4315. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  4316. intel_hdmi_init(dev, SDVOC);
  4317. }
  4318. if (SUPPORTS_INTEGRATED_DP(dev)) {
  4319. DRM_DEBUG_KMS("probing DP_C\n");
  4320. intel_dp_init(dev, DP_C);
  4321. }
  4322. }
  4323. if (SUPPORTS_INTEGRATED_DP(dev) &&
  4324. (I915_READ(DP_D) & DP_DETECTED)) {
  4325. DRM_DEBUG_KMS("probing DP_D\n");
  4326. intel_dp_init(dev, DP_D);
  4327. }
  4328. } else if (IS_GEN2(dev))
  4329. intel_dvo_init(dev);
  4330. if (SUPPORTS_TV(dev))
  4331. intel_tv_init(dev);
  4332. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4333. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4334. encoder->possible_crtcs = intel_encoder->crtc_mask;
  4335. encoder->possible_clones = intel_encoder_clones(dev,
  4336. intel_encoder->clone_mask);
  4337. }
  4338. }
  4339. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  4340. {
  4341. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4342. drm_framebuffer_cleanup(fb);
  4343. drm_gem_object_unreference_unlocked(intel_fb->obj);
  4344. kfree(intel_fb);
  4345. }
  4346. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  4347. struct drm_file *file_priv,
  4348. unsigned int *handle)
  4349. {
  4350. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4351. struct drm_gem_object *object = intel_fb->obj;
  4352. return drm_gem_handle_create(file_priv, object, handle);
  4353. }
  4354. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  4355. .destroy = intel_user_framebuffer_destroy,
  4356. .create_handle = intel_user_framebuffer_create_handle,
  4357. };
  4358. int intel_framebuffer_init(struct drm_device *dev,
  4359. struct intel_framebuffer *intel_fb,
  4360. struct drm_mode_fb_cmd *mode_cmd,
  4361. struct drm_gem_object *obj)
  4362. {
  4363. int ret;
  4364. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  4365. if (ret) {
  4366. DRM_ERROR("framebuffer init failed %d\n", ret);
  4367. return ret;
  4368. }
  4369. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  4370. intel_fb->obj = obj;
  4371. return 0;
  4372. }
  4373. static struct drm_framebuffer *
  4374. intel_user_framebuffer_create(struct drm_device *dev,
  4375. struct drm_file *filp,
  4376. struct drm_mode_fb_cmd *mode_cmd)
  4377. {
  4378. struct drm_gem_object *obj;
  4379. struct intel_framebuffer *intel_fb;
  4380. int ret;
  4381. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  4382. if (!obj)
  4383. return NULL;
  4384. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4385. if (!intel_fb)
  4386. return NULL;
  4387. ret = intel_framebuffer_init(dev, intel_fb,
  4388. mode_cmd, obj);
  4389. if (ret) {
  4390. drm_gem_object_unreference_unlocked(obj);
  4391. kfree(intel_fb);
  4392. return NULL;
  4393. }
  4394. return &intel_fb->base;
  4395. }
  4396. static const struct drm_mode_config_funcs intel_mode_funcs = {
  4397. .fb_create = intel_user_framebuffer_create,
  4398. .output_poll_changed = intel_fb_output_poll_changed,
  4399. };
  4400. static struct drm_gem_object *
  4401. intel_alloc_power_context(struct drm_device *dev)
  4402. {
  4403. struct drm_gem_object *pwrctx;
  4404. int ret;
  4405. pwrctx = i915_gem_alloc_object(dev, 4096);
  4406. if (!pwrctx) {
  4407. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  4408. return NULL;
  4409. }
  4410. mutex_lock(&dev->struct_mutex);
  4411. ret = i915_gem_object_pin(pwrctx, 4096);
  4412. if (ret) {
  4413. DRM_ERROR("failed to pin power context: %d\n", ret);
  4414. goto err_unref;
  4415. }
  4416. ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
  4417. if (ret) {
  4418. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  4419. goto err_unpin;
  4420. }
  4421. mutex_unlock(&dev->struct_mutex);
  4422. return pwrctx;
  4423. err_unpin:
  4424. i915_gem_object_unpin(pwrctx);
  4425. err_unref:
  4426. drm_gem_object_unreference(pwrctx);
  4427. mutex_unlock(&dev->struct_mutex);
  4428. return NULL;
  4429. }
  4430. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  4431. {
  4432. struct drm_i915_private *dev_priv = dev->dev_private;
  4433. u16 rgvswctl;
  4434. rgvswctl = I915_READ16(MEMSWCTL);
  4435. if (rgvswctl & MEMCTL_CMD_STS) {
  4436. DRM_DEBUG("gpu busy, RCS change rejected\n");
  4437. return false; /* still busy with another command */
  4438. }
  4439. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4440. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4441. I915_WRITE16(MEMSWCTL, rgvswctl);
  4442. POSTING_READ16(MEMSWCTL);
  4443. rgvswctl |= MEMCTL_CMD_STS;
  4444. I915_WRITE16(MEMSWCTL, rgvswctl);
  4445. return true;
  4446. }
  4447. void ironlake_enable_drps(struct drm_device *dev)
  4448. {
  4449. struct drm_i915_private *dev_priv = dev->dev_private;
  4450. u32 rgvmodectl = I915_READ(MEMMODECTL);
  4451. u8 fmax, fmin, fstart, vstart;
  4452. int i = 0;
  4453. /* 100ms RC evaluation intervals */
  4454. I915_WRITE(RCUPEI, 100000);
  4455. I915_WRITE(RCDNEI, 100000);
  4456. /* Set max/min thresholds to 90ms and 80ms respectively */
  4457. I915_WRITE(RCBMAXAVG, 90000);
  4458. I915_WRITE(RCBMINAVG, 80000);
  4459. I915_WRITE(MEMIHYST, 1);
  4460. /* Set up min, max, and cur for interrupt handling */
  4461. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  4462. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  4463. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  4464. MEMMODE_FSTART_SHIFT;
  4465. fstart = fmax;
  4466. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  4467. PXVFREQ_PX_SHIFT;
  4468. dev_priv->fmax = fstart; /* IPS callback will increase this */
  4469. dev_priv->fstart = fstart;
  4470. dev_priv->max_delay = fmax;
  4471. dev_priv->min_delay = fmin;
  4472. dev_priv->cur_delay = fstart;
  4473. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
  4474. fstart);
  4475. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  4476. /*
  4477. * Interrupts will be enabled in ironlake_irq_postinstall
  4478. */
  4479. I915_WRITE(VIDSTART, vstart);
  4480. POSTING_READ(VIDSTART);
  4481. rgvmodectl |= MEMMODE_SWMODE_EN;
  4482. I915_WRITE(MEMMODECTL, rgvmodectl);
  4483. while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
  4484. if (i++ > 100) {
  4485. DRM_ERROR("stuck trying to change perf mode\n");
  4486. break;
  4487. }
  4488. msleep(1);
  4489. }
  4490. msleep(1);
  4491. ironlake_set_drps(dev, fstart);
  4492. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  4493. I915_READ(0x112e0);
  4494. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  4495. dev_priv->last_count2 = I915_READ(0x112f4);
  4496. getrawmonotonic(&dev_priv->last_time2);
  4497. }
  4498. void ironlake_disable_drps(struct drm_device *dev)
  4499. {
  4500. struct drm_i915_private *dev_priv = dev->dev_private;
  4501. u16 rgvswctl = I915_READ16(MEMSWCTL);
  4502. /* Ack interrupts, disable EFC interrupt */
  4503. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  4504. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  4505. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  4506. I915_WRITE(DEIIR, DE_PCU_EVENT);
  4507. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  4508. /* Go back to the starting frequency */
  4509. ironlake_set_drps(dev, dev_priv->fstart);
  4510. msleep(1);
  4511. rgvswctl |= MEMCTL_CMD_STS;
  4512. I915_WRITE(MEMSWCTL, rgvswctl);
  4513. msleep(1);
  4514. }
  4515. static unsigned long intel_pxfreq(u32 vidfreq)
  4516. {
  4517. unsigned long freq;
  4518. int div = (vidfreq & 0x3f0000) >> 16;
  4519. int post = (vidfreq & 0x3000) >> 12;
  4520. int pre = (vidfreq & 0x7);
  4521. if (!pre)
  4522. return 0;
  4523. freq = ((div * 133333) / ((1<<post) * pre));
  4524. return freq;
  4525. }
  4526. void intel_init_emon(struct drm_device *dev)
  4527. {
  4528. struct drm_i915_private *dev_priv = dev->dev_private;
  4529. u32 lcfuse;
  4530. u8 pxw[16];
  4531. int i;
  4532. /* Disable to program */
  4533. I915_WRITE(ECR, 0);
  4534. POSTING_READ(ECR);
  4535. /* Program energy weights for various events */
  4536. I915_WRITE(SDEW, 0x15040d00);
  4537. I915_WRITE(CSIEW0, 0x007f0000);
  4538. I915_WRITE(CSIEW1, 0x1e220004);
  4539. I915_WRITE(CSIEW2, 0x04000004);
  4540. for (i = 0; i < 5; i++)
  4541. I915_WRITE(PEW + (i * 4), 0);
  4542. for (i = 0; i < 3; i++)
  4543. I915_WRITE(DEW + (i * 4), 0);
  4544. /* Program P-state weights to account for frequency power adjustment */
  4545. for (i = 0; i < 16; i++) {
  4546. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  4547. unsigned long freq = intel_pxfreq(pxvidfreq);
  4548. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  4549. PXVFREQ_PX_SHIFT;
  4550. unsigned long val;
  4551. val = vid * vid;
  4552. val *= (freq / 1000);
  4553. val *= 255;
  4554. val /= (127*127*900);
  4555. if (val > 0xff)
  4556. DRM_ERROR("bad pxval: %ld\n", val);
  4557. pxw[i] = val;
  4558. }
  4559. /* Render standby states get 0 weight */
  4560. pxw[14] = 0;
  4561. pxw[15] = 0;
  4562. for (i = 0; i < 4; i++) {
  4563. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  4564. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  4565. I915_WRITE(PXW + (i * 4), val);
  4566. }
  4567. /* Adjust magic regs to magic values (more experimental results) */
  4568. I915_WRITE(OGW0, 0);
  4569. I915_WRITE(OGW1, 0);
  4570. I915_WRITE(EG0, 0x00007f00);
  4571. I915_WRITE(EG1, 0x0000000e);
  4572. I915_WRITE(EG2, 0x000e0000);
  4573. I915_WRITE(EG3, 0x68000300);
  4574. I915_WRITE(EG4, 0x42000000);
  4575. I915_WRITE(EG5, 0x00140031);
  4576. I915_WRITE(EG6, 0);
  4577. I915_WRITE(EG7, 0);
  4578. for (i = 0; i < 8; i++)
  4579. I915_WRITE(PXWL + (i * 4), 0);
  4580. /* Enable PMON + select events */
  4581. I915_WRITE(ECR, 0x80000019);
  4582. lcfuse = I915_READ(LCFUSE02);
  4583. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  4584. }
  4585. void intel_init_clock_gating(struct drm_device *dev)
  4586. {
  4587. struct drm_i915_private *dev_priv = dev->dev_private;
  4588. /*
  4589. * Disable clock gating reported to work incorrectly according to the
  4590. * specs, but enable as much else as we can.
  4591. */
  4592. if (HAS_PCH_SPLIT(dev)) {
  4593. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  4594. if (IS_IRONLAKE(dev)) {
  4595. /* Required for FBC */
  4596. dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
  4597. /* Required for CxSR */
  4598. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  4599. I915_WRITE(PCH_3DCGDIS0,
  4600. MARIUNIT_CLOCK_GATE_DISABLE |
  4601. SVSMUNIT_CLOCK_GATE_DISABLE);
  4602. }
  4603. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  4604. /*
  4605. * According to the spec the following bits should be set in
  4606. * order to enable memory self-refresh
  4607. * The bit 22/21 of 0x42004
  4608. * The bit 5 of 0x42020
  4609. * The bit 15 of 0x45000
  4610. */
  4611. if (IS_IRONLAKE(dev)) {
  4612. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4613. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  4614. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  4615. I915_WRITE(ILK_DSPCLK_GATE,
  4616. (I915_READ(ILK_DSPCLK_GATE) |
  4617. ILK_DPARB_CLK_GATE));
  4618. I915_WRITE(DISP_ARB_CTL,
  4619. (I915_READ(DISP_ARB_CTL) |
  4620. DISP_FBC_WM_DIS));
  4621. }
  4622. return;
  4623. } else if (IS_G4X(dev)) {
  4624. uint32_t dspclk_gate;
  4625. I915_WRITE(RENCLK_GATE_D1, 0);
  4626. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4627. GS_UNIT_CLOCK_GATE_DISABLE |
  4628. CL_UNIT_CLOCK_GATE_DISABLE);
  4629. I915_WRITE(RAMCLK_GATE_D, 0);
  4630. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4631. OVRUNIT_CLOCK_GATE_DISABLE |
  4632. OVCUNIT_CLOCK_GATE_DISABLE;
  4633. if (IS_GM45(dev))
  4634. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4635. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4636. } else if (IS_I965GM(dev)) {
  4637. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4638. I915_WRITE(RENCLK_GATE_D2, 0);
  4639. I915_WRITE(DSPCLK_GATE_D, 0);
  4640. I915_WRITE(RAMCLK_GATE_D, 0);
  4641. I915_WRITE16(DEUC, 0);
  4642. } else if (IS_I965G(dev)) {
  4643. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4644. I965_RCC_CLOCK_GATE_DISABLE |
  4645. I965_RCPB_CLOCK_GATE_DISABLE |
  4646. I965_ISC_CLOCK_GATE_DISABLE |
  4647. I965_FBC_CLOCK_GATE_DISABLE);
  4648. I915_WRITE(RENCLK_GATE_D2, 0);
  4649. } else if (IS_I9XX(dev)) {
  4650. u32 dstate = I915_READ(D_STATE);
  4651. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4652. DSTATE_DOT_CLOCK_GATING;
  4653. I915_WRITE(D_STATE, dstate);
  4654. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  4655. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  4656. } else if (IS_I830(dev)) {
  4657. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  4658. }
  4659. /*
  4660. * GPU can automatically power down the render unit if given a page
  4661. * to save state.
  4662. */
  4663. if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
  4664. struct drm_i915_gem_object *obj_priv = NULL;
  4665. if (dev_priv->pwrctx) {
  4666. obj_priv = to_intel_bo(dev_priv->pwrctx);
  4667. } else {
  4668. struct drm_gem_object *pwrctx;
  4669. pwrctx = intel_alloc_power_context(dev);
  4670. if (pwrctx) {
  4671. dev_priv->pwrctx = pwrctx;
  4672. obj_priv = to_intel_bo(pwrctx);
  4673. }
  4674. }
  4675. if (obj_priv) {
  4676. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  4677. I915_WRITE(MCHBAR_RENDER_STANDBY,
  4678. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  4679. }
  4680. }
  4681. }
  4682. /* Set up chip specific display functions */
  4683. static void intel_init_display(struct drm_device *dev)
  4684. {
  4685. struct drm_i915_private *dev_priv = dev->dev_private;
  4686. /* We always want a DPMS function */
  4687. if (HAS_PCH_SPLIT(dev))
  4688. dev_priv->display.dpms = ironlake_crtc_dpms;
  4689. else
  4690. dev_priv->display.dpms = i9xx_crtc_dpms;
  4691. if (I915_HAS_FBC(dev)) {
  4692. if (IS_GM45(dev)) {
  4693. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  4694. dev_priv->display.enable_fbc = g4x_enable_fbc;
  4695. dev_priv->display.disable_fbc = g4x_disable_fbc;
  4696. } else if (IS_I965GM(dev)) {
  4697. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  4698. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  4699. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  4700. }
  4701. /* 855GM needs testing */
  4702. }
  4703. /* Returns the core display clock speed */
  4704. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  4705. dev_priv->display.get_display_clock_speed =
  4706. i945_get_display_clock_speed;
  4707. else if (IS_I915G(dev))
  4708. dev_priv->display.get_display_clock_speed =
  4709. i915_get_display_clock_speed;
  4710. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  4711. dev_priv->display.get_display_clock_speed =
  4712. i9xx_misc_get_display_clock_speed;
  4713. else if (IS_I915GM(dev))
  4714. dev_priv->display.get_display_clock_speed =
  4715. i915gm_get_display_clock_speed;
  4716. else if (IS_I865G(dev))
  4717. dev_priv->display.get_display_clock_speed =
  4718. i865_get_display_clock_speed;
  4719. else if (IS_I85X(dev))
  4720. dev_priv->display.get_display_clock_speed =
  4721. i855_get_display_clock_speed;
  4722. else /* 852, 830 */
  4723. dev_priv->display.get_display_clock_speed =
  4724. i830_get_display_clock_speed;
  4725. /* For FIFO watermark updates */
  4726. if (HAS_PCH_SPLIT(dev)) {
  4727. if (IS_IRONLAKE(dev)) {
  4728. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  4729. dev_priv->display.update_wm = ironlake_update_wm;
  4730. else {
  4731. DRM_DEBUG_KMS("Failed to get proper latency. "
  4732. "Disable CxSR\n");
  4733. dev_priv->display.update_wm = NULL;
  4734. }
  4735. } else
  4736. dev_priv->display.update_wm = NULL;
  4737. } else if (IS_PINEVIEW(dev)) {
  4738. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  4739. dev_priv->is_ddr3,
  4740. dev_priv->fsb_freq,
  4741. dev_priv->mem_freq)) {
  4742. DRM_INFO("failed to find known CxSR latency "
  4743. "(found ddr%s fsb freq %d, mem freq %d), "
  4744. "disabling CxSR\n",
  4745. (dev_priv->is_ddr3 == 1) ? "3": "2",
  4746. dev_priv->fsb_freq, dev_priv->mem_freq);
  4747. /* Disable CxSR and never update its watermark again */
  4748. pineview_disable_cxsr(dev);
  4749. dev_priv->display.update_wm = NULL;
  4750. } else
  4751. dev_priv->display.update_wm = pineview_update_wm;
  4752. } else if (IS_G4X(dev))
  4753. dev_priv->display.update_wm = g4x_update_wm;
  4754. else if (IS_I965G(dev))
  4755. dev_priv->display.update_wm = i965_update_wm;
  4756. else if (IS_I9XX(dev)) {
  4757. dev_priv->display.update_wm = i9xx_update_wm;
  4758. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  4759. } else if (IS_I85X(dev)) {
  4760. dev_priv->display.update_wm = i9xx_update_wm;
  4761. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  4762. } else {
  4763. dev_priv->display.update_wm = i830_update_wm;
  4764. if (IS_845G(dev))
  4765. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  4766. else
  4767. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4768. }
  4769. }
  4770. void intel_modeset_init(struct drm_device *dev)
  4771. {
  4772. struct drm_i915_private *dev_priv = dev->dev_private;
  4773. int i;
  4774. drm_mode_config_init(dev);
  4775. dev->mode_config.min_width = 0;
  4776. dev->mode_config.min_height = 0;
  4777. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  4778. intel_init_display(dev);
  4779. if (IS_I965G(dev)) {
  4780. dev->mode_config.max_width = 8192;
  4781. dev->mode_config.max_height = 8192;
  4782. } else if (IS_I9XX(dev)) {
  4783. dev->mode_config.max_width = 4096;
  4784. dev->mode_config.max_height = 4096;
  4785. } else {
  4786. dev->mode_config.max_width = 2048;
  4787. dev->mode_config.max_height = 2048;
  4788. }
  4789. /* set memory base */
  4790. if (IS_I9XX(dev))
  4791. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  4792. else
  4793. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  4794. if (IS_MOBILE(dev) || IS_I9XX(dev))
  4795. dev_priv->num_pipe = 2;
  4796. else
  4797. dev_priv->num_pipe = 1;
  4798. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  4799. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  4800. for (i = 0; i < dev_priv->num_pipe; i++) {
  4801. intel_crtc_init(dev, i);
  4802. }
  4803. intel_setup_outputs(dev);
  4804. intel_init_clock_gating(dev);
  4805. if (IS_IRONLAKE_M(dev)) {
  4806. ironlake_enable_drps(dev);
  4807. intel_init_emon(dev);
  4808. }
  4809. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  4810. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  4811. (unsigned long)dev);
  4812. intel_setup_overlay(dev);
  4813. }
  4814. void intel_modeset_cleanup(struct drm_device *dev)
  4815. {
  4816. struct drm_i915_private *dev_priv = dev->dev_private;
  4817. struct drm_crtc *crtc;
  4818. struct intel_crtc *intel_crtc;
  4819. mutex_lock(&dev->struct_mutex);
  4820. drm_kms_helper_poll_fini(dev);
  4821. intel_fbdev_fini(dev);
  4822. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4823. /* Skip inactive CRTCs */
  4824. if (!crtc->fb)
  4825. continue;
  4826. intel_crtc = to_intel_crtc(crtc);
  4827. intel_increase_pllclock(crtc, false);
  4828. del_timer_sync(&intel_crtc->idle_timer);
  4829. }
  4830. del_timer_sync(&dev_priv->idle_timer);
  4831. if (dev_priv->display.disable_fbc)
  4832. dev_priv->display.disable_fbc(dev);
  4833. if (dev_priv->pwrctx) {
  4834. struct drm_i915_gem_object *obj_priv;
  4835. obj_priv = to_intel_bo(dev_priv->pwrctx);
  4836. I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
  4837. I915_READ(PWRCTXA);
  4838. i915_gem_object_unpin(dev_priv->pwrctx);
  4839. drm_gem_object_unreference(dev_priv->pwrctx);
  4840. }
  4841. if (IS_IRONLAKE_M(dev))
  4842. ironlake_disable_drps(dev);
  4843. mutex_unlock(&dev->struct_mutex);
  4844. drm_mode_config_cleanup(dev);
  4845. }
  4846. /*
  4847. * Return which encoder is currently attached for connector.
  4848. */
  4849. struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
  4850. {
  4851. struct drm_mode_object *obj;
  4852. struct drm_encoder *encoder;
  4853. int i;
  4854. for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
  4855. if (connector->encoder_ids[i] == 0)
  4856. break;
  4857. obj = drm_mode_object_find(connector->dev,
  4858. connector->encoder_ids[i],
  4859. DRM_MODE_OBJECT_ENCODER);
  4860. if (!obj)
  4861. continue;
  4862. encoder = obj_to_encoder(obj);
  4863. return encoder;
  4864. }
  4865. return NULL;
  4866. }
  4867. /*
  4868. * set vga decode state - true == enable VGA decode
  4869. */
  4870. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  4871. {
  4872. struct drm_i915_private *dev_priv = dev->dev_private;
  4873. u16 gmch_ctrl;
  4874. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  4875. if (state)
  4876. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  4877. else
  4878. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  4879. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  4880. return 0;
  4881. }