mv_sas.c 55 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22. * USA
  23. */
  24. #include "mv_sas.h"
  25. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  26. {
  27. if (task->lldd_task) {
  28. struct mvs_slot_info *slot;
  29. slot = (struct mvs_slot_info *) task->lldd_task;
  30. *tag = slot->slot_tag;
  31. return 1;
  32. }
  33. return 0;
  34. }
  35. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  36. {
  37. void *bitmap = (void *) &mvi->tags;
  38. clear_bit(tag, bitmap);
  39. }
  40. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  41. {
  42. mvs_tag_clear(mvi, tag);
  43. }
  44. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  45. {
  46. void *bitmap = (void *) &mvi->tags;
  47. set_bit(tag, bitmap);
  48. }
  49. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  50. {
  51. unsigned int index, tag;
  52. void *bitmap = (void *) &mvi->tags;
  53. index = find_first_zero_bit(bitmap, mvi->tags_num);
  54. tag = index;
  55. if (tag >= mvi->tags_num)
  56. return -SAS_QUEUE_FULL;
  57. mvs_tag_set(mvi, tag);
  58. *tag_out = tag;
  59. return 0;
  60. }
  61. void mvs_tag_init(struct mvs_info *mvi)
  62. {
  63. int i;
  64. for (i = 0; i < mvi->tags_num; ++i)
  65. mvs_tag_clear(mvi, i);
  66. }
  67. void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
  68. {
  69. u32 i;
  70. u32 run;
  71. u32 offset;
  72. offset = 0;
  73. while (size) {
  74. printk(KERN_DEBUG"%08X : ", baseaddr + offset);
  75. if (size >= 16)
  76. run = 16;
  77. else
  78. run = size;
  79. size -= run;
  80. for (i = 0; i < 16; i++) {
  81. if (i < run)
  82. printk(KERN_DEBUG"%02X ", (u32)data[i]);
  83. else
  84. printk(KERN_DEBUG" ");
  85. }
  86. printk(KERN_DEBUG": ");
  87. for (i = 0; i < run; i++)
  88. printk(KERN_DEBUG"%c",
  89. isalnum(data[i]) ? data[i] : '.');
  90. printk(KERN_DEBUG"\n");
  91. data = &data[16];
  92. offset += run;
  93. }
  94. printk(KERN_DEBUG"\n");
  95. }
  96. #if (_MV_DUMP > 1)
  97. static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
  98. enum sas_protocol proto)
  99. {
  100. u32 offset;
  101. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  102. offset = slot->cmd_size + MVS_OAF_SZ +
  103. MVS_CHIP_DISP->prd_size() * slot->n_elem;
  104. dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
  105. tag);
  106. mvs_hexdump(32, (u8 *) slot->response,
  107. (u32) slot->buf_dma + offset);
  108. }
  109. #endif
  110. static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
  111. enum sas_protocol proto)
  112. {
  113. #if (_MV_DUMP > 1)
  114. u32 sz, w_ptr;
  115. u64 addr;
  116. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  117. /*Delivery Queue */
  118. sz = MVS_CHIP_SLOT_SZ;
  119. w_ptr = slot->tx;
  120. addr = mvi->tx_dma;
  121. dev_printk(KERN_DEBUG, mvi->dev,
  122. "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
  123. dev_printk(KERN_DEBUG, mvi->dev,
  124. "Delivery Queue Base Address=0x%llX (PA)"
  125. "(tx_dma=0x%llX), Entry=%04d\n",
  126. addr, (unsigned long long)mvi->tx_dma, w_ptr);
  127. mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
  128. (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
  129. /*Command List */
  130. addr = mvi->slot_dma;
  131. dev_printk(KERN_DEBUG, mvi->dev,
  132. "Command List Base Address=0x%llX (PA)"
  133. "(slot_dma=0x%llX), Header=%03d\n",
  134. addr, (unsigned long long)slot->buf_dma, tag);
  135. dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
  136. /*mvs_cmd_hdr */
  137. mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
  138. (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
  139. /*1.command table area */
  140. dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
  141. mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
  142. /*2.open address frame area */
  143. dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
  144. mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
  145. (u32) slot->buf_dma + slot->cmd_size);
  146. /*3.status buffer */
  147. mvs_hba_sb_dump(mvi, tag, proto);
  148. /*4.PRD table */
  149. dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
  150. mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
  151. (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
  152. (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
  153. #endif
  154. }
  155. static void mvs_hba_cq_dump(struct mvs_info *mvi)
  156. {
  157. #if (_MV_DUMP > 2)
  158. u64 addr;
  159. void __iomem *regs = mvi->regs;
  160. u32 entry = mvi->rx_cons + 1;
  161. u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
  162. /*Completion Queue */
  163. addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
  164. dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
  165. mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
  166. dev_printk(KERN_DEBUG, mvi->dev,
  167. "Completion List Base Address=0x%llX (PA), "
  168. "CQ_Entry=%04d, CQ_WP=0x%08X\n",
  169. addr, entry - 1, mvi->rx[0]);
  170. mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
  171. mvi->rx_dma + sizeof(u32) * entry);
  172. #endif
  173. }
  174. void mvs_get_sas_addr(void *buf, u32 buflen)
  175. {
  176. /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
  177. }
  178. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  179. {
  180. unsigned long i = 0, j = 0, hi = 0;
  181. struct sas_ha_struct *sha = dev->port->ha;
  182. struct mvs_info *mvi = NULL;
  183. struct asd_sas_phy *phy;
  184. while (sha->sas_port[i]) {
  185. if (sha->sas_port[i] == dev->port) {
  186. phy = container_of(sha->sas_port[i]->phy_list.next,
  187. struct asd_sas_phy, port_phy_el);
  188. j = 0;
  189. while (sha->sas_phy[j]) {
  190. if (sha->sas_phy[j] == phy)
  191. break;
  192. j++;
  193. }
  194. break;
  195. }
  196. i++;
  197. }
  198. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  199. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  200. return mvi;
  201. }
  202. /* FIXME */
  203. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  204. {
  205. unsigned long i = 0, j = 0, n = 0, num = 0;
  206. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  207. struct sas_ha_struct *sha = dev->port->ha;
  208. while (sha->sas_port[i]) {
  209. if (sha->sas_port[i] == dev->port) {
  210. struct asd_sas_phy *phy;
  211. list_for_each_entry(phy,
  212. &sha->sas_port[i]->phy_list, port_phy_el) {
  213. j = 0;
  214. while (sha->sas_phy[j]) {
  215. if (sha->sas_phy[j] == phy)
  216. break;
  217. j++;
  218. }
  219. phyno[n] = (j >= mvi->chip->n_phy) ?
  220. (j - mvi->chip->n_phy) : j;
  221. num++;
  222. n++;
  223. }
  224. break;
  225. }
  226. i++;
  227. }
  228. return num;
  229. }
  230. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  231. struct mvs_device *dev)
  232. {
  233. if (!dev) {
  234. mv_printk("device has been free.\n");
  235. return;
  236. }
  237. if (dev->runing_req != 0)
  238. return;
  239. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  240. return;
  241. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  242. }
  243. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  244. struct mvs_device *dev)
  245. {
  246. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  247. return 0;
  248. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  249. }
  250. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  251. {
  252. u32 no;
  253. for_each_phy(phy_mask, phy_mask, no) {
  254. if (!(phy_mask & 1))
  255. continue;
  256. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  257. }
  258. }
  259. /* FIXME: locking? */
  260. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  261. void *funcdata)
  262. {
  263. int rc = 0, phy_id = sas_phy->id;
  264. u32 tmp, i = 0, hi;
  265. struct sas_ha_struct *sha = sas_phy->ha;
  266. struct mvs_info *mvi = NULL;
  267. while (sha->sas_phy[i]) {
  268. if (sha->sas_phy[i] == sas_phy)
  269. break;
  270. i++;
  271. }
  272. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  273. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  274. switch (func) {
  275. case PHY_FUNC_SET_LINK_RATE:
  276. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  277. break;
  278. case PHY_FUNC_HARD_RESET:
  279. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  280. if (tmp & PHY_RST_HARD)
  281. break;
  282. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
  283. break;
  284. case PHY_FUNC_LINK_RESET:
  285. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  286. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
  287. break;
  288. case PHY_FUNC_DISABLE:
  289. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  290. break;
  291. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  292. default:
  293. rc = -EOPNOTSUPP;
  294. }
  295. msleep(200);
  296. return rc;
  297. }
  298. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  299. u32 off_lo, u32 off_hi, u64 sas_addr)
  300. {
  301. u32 lo = (u32)sas_addr;
  302. u32 hi = (u32)(sas_addr>>32);
  303. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  304. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  305. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  306. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  307. }
  308. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  309. {
  310. struct mvs_phy *phy = &mvi->phy[i];
  311. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  312. struct sas_ha_struct *sas_ha;
  313. if (!phy->phy_attached)
  314. return;
  315. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  316. && phy->phy_type & PORT_TYPE_SAS) {
  317. return;
  318. }
  319. sas_ha = mvi->sas;
  320. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  321. if (sas_phy->phy) {
  322. struct sas_phy *sphy = sas_phy->phy;
  323. sphy->negotiated_linkrate = sas_phy->linkrate;
  324. sphy->minimum_linkrate = phy->minimum_linkrate;
  325. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  326. sphy->maximum_linkrate = phy->maximum_linkrate;
  327. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  328. }
  329. if (phy->phy_type & PORT_TYPE_SAS) {
  330. struct sas_identify_frame *id;
  331. id = (struct sas_identify_frame *)phy->frame_rcvd;
  332. id->dev_type = phy->identify.device_type;
  333. id->initiator_bits = SAS_PROTOCOL_ALL;
  334. id->target_bits = phy->identify.target_port_protocols;
  335. } else if (phy->phy_type & PORT_TYPE_SATA) {
  336. /*Nothing*/
  337. }
  338. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  339. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  340. mvi->sas->notify_port_event(sas_phy,
  341. PORTE_BYTES_DMAED);
  342. }
  343. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  344. {
  345. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  346. if (dev_is_sata(dev)) {
  347. /* We don't need to rescan targets
  348. * if REPORT_LUNS request is failed
  349. */
  350. if (scsi_dev->lun > 0)
  351. return -ENXIO;
  352. scsi_dev->tagged_supported = 1;
  353. }
  354. return sas_slave_alloc(scsi_dev);
  355. }
  356. int mvs_slave_configure(struct scsi_device *sdev)
  357. {
  358. struct domain_device *dev = sdev_to_domain_dev(sdev);
  359. int ret = sas_slave_configure(sdev);
  360. if (ret)
  361. return ret;
  362. if (dev_is_sata(dev)) {
  363. /* may set PIO mode */
  364. #if MV_DISABLE_NCQ
  365. struct ata_port *ap = dev->sata_dev.ap;
  366. struct ata_device *adev = ap->link.device;
  367. adev->flags |= ATA_DFLAG_NCQ_OFF;
  368. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
  369. #endif
  370. }
  371. return 0;
  372. }
  373. void mvs_scan_start(struct Scsi_Host *shost)
  374. {
  375. int i, j;
  376. unsigned short core_nr;
  377. struct mvs_info *mvi;
  378. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  379. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  380. for (j = 0; j < core_nr; j++) {
  381. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  382. for (i = 0; i < mvi->chip->n_phy; ++i)
  383. mvs_bytes_dmaed(mvi, i);
  384. }
  385. }
  386. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  387. {
  388. /* give the phy enabling interrupt event time to come in (1s
  389. * is empirically about all it takes) */
  390. if (time < HZ)
  391. return 0;
  392. /* Wait for discovery to finish */
  393. scsi_flush_work(shost);
  394. return 1;
  395. }
  396. static int mvs_task_prep_smp(struct mvs_info *mvi,
  397. struct mvs_task_exec_info *tei)
  398. {
  399. int elem, rc, i;
  400. struct sas_task *task = tei->task;
  401. struct mvs_cmd_hdr *hdr = tei->hdr;
  402. struct domain_device *dev = task->dev;
  403. struct asd_sas_port *sas_port = dev->port;
  404. struct scatterlist *sg_req, *sg_resp;
  405. u32 req_len, resp_len, tag = tei->tag;
  406. void *buf_tmp;
  407. u8 *buf_oaf;
  408. dma_addr_t buf_tmp_dma;
  409. void *buf_prd;
  410. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  411. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  412. #if _MV_DUMP
  413. u8 *buf_cmd;
  414. void *from;
  415. #endif
  416. /*
  417. * DMA-map SMP request, response buffers
  418. */
  419. sg_req = &task->smp_task.smp_req;
  420. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  421. if (!elem)
  422. return -ENOMEM;
  423. req_len = sg_dma_len(sg_req);
  424. sg_resp = &task->smp_task.smp_resp;
  425. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  426. if (!elem) {
  427. rc = -ENOMEM;
  428. goto err_out;
  429. }
  430. resp_len = SB_RFB_MAX;
  431. /* must be in dwords */
  432. if ((req_len & 0x3) || (resp_len & 0x3)) {
  433. rc = -EINVAL;
  434. goto err_out_2;
  435. }
  436. /*
  437. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  438. */
  439. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  440. buf_tmp = slot->buf;
  441. buf_tmp_dma = slot->buf_dma;
  442. #if _MV_DUMP
  443. buf_cmd = buf_tmp;
  444. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  445. buf_tmp += req_len;
  446. buf_tmp_dma += req_len;
  447. slot->cmd_size = req_len;
  448. #else
  449. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  450. #endif
  451. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  452. buf_oaf = buf_tmp;
  453. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  454. buf_tmp += MVS_OAF_SZ;
  455. buf_tmp_dma += MVS_OAF_SZ;
  456. /* region 3: PRD table *********************************** */
  457. buf_prd = buf_tmp;
  458. if (tei->n_elem)
  459. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  460. else
  461. hdr->prd_tbl = 0;
  462. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  463. buf_tmp += i;
  464. buf_tmp_dma += i;
  465. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  466. slot->response = buf_tmp;
  467. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  468. if (mvi->flags & MVF_FLAG_SOC)
  469. hdr->reserved[0] = 0;
  470. /*
  471. * Fill in TX ring and command slot header
  472. */
  473. slot->tx = mvi->tx_prod;
  474. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  475. TXQ_MODE_I | tag |
  476. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  477. hdr->flags |= flags;
  478. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  479. hdr->tags = cpu_to_le32(tag);
  480. hdr->data_len = 0;
  481. /* generate open address frame hdr (first 12 bytes) */
  482. /* initiator, SMP, ftype 1h */
  483. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  484. buf_oaf[1] = dev->linkrate & 0xf;
  485. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  486. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  487. /* fill in PRD (scatter/gather) table, if any */
  488. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  489. #if _MV_DUMP
  490. /* copy cmd table */
  491. from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
  492. memcpy(buf_cmd, from + sg_req->offset, req_len);
  493. kunmap_atomic(from, KM_IRQ0);
  494. #endif
  495. return 0;
  496. err_out_2:
  497. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  498. PCI_DMA_FROMDEVICE);
  499. err_out:
  500. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  501. PCI_DMA_TODEVICE);
  502. return rc;
  503. }
  504. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  505. {
  506. struct ata_queued_cmd *qc = task->uldd_task;
  507. if (qc) {
  508. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  509. qc->tf.command == ATA_CMD_FPDMA_READ) {
  510. *tag = qc->tag;
  511. return 1;
  512. }
  513. }
  514. return 0;
  515. }
  516. static int mvs_task_prep_ata(struct mvs_info *mvi,
  517. struct mvs_task_exec_info *tei)
  518. {
  519. struct sas_task *task = tei->task;
  520. struct domain_device *dev = task->dev;
  521. struct mvs_device *mvi_dev =
  522. (struct mvs_device *)dev->lldd_dev;
  523. struct mvs_cmd_hdr *hdr = tei->hdr;
  524. struct asd_sas_port *sas_port = dev->port;
  525. struct mvs_slot_info *slot;
  526. void *buf_prd;
  527. u32 tag = tei->tag, hdr_tag;
  528. u32 flags, del_q;
  529. void *buf_tmp;
  530. u8 *buf_cmd, *buf_oaf;
  531. dma_addr_t buf_tmp_dma;
  532. u32 i, req_len, resp_len;
  533. const u32 max_resp_len = SB_RFB_MAX;
  534. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  535. mv_dprintk("Have not enough regiset for dev %d.\n",
  536. mvi_dev->device_id);
  537. return -EBUSY;
  538. }
  539. slot = &mvi->slot_info[tag];
  540. slot->tx = mvi->tx_prod;
  541. del_q = TXQ_MODE_I | tag |
  542. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  543. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  544. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  545. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  546. #ifndef DISABLE_HOTPLUG_DMA_FIX
  547. if (task->data_dir == DMA_FROM_DEVICE)
  548. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  549. else
  550. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  551. #else
  552. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  553. #endif
  554. if (task->ata_task.use_ncq)
  555. flags |= MCH_FPDMA;
  556. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  557. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  558. flags |= MCH_ATAPI;
  559. }
  560. /* FIXME: fill in port multiplier number */
  561. hdr->flags = cpu_to_le32(flags);
  562. /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
  563. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  564. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  565. else
  566. hdr_tag = tag;
  567. hdr->tags = cpu_to_le32(hdr_tag);
  568. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  569. /*
  570. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  571. */
  572. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  573. buf_cmd = buf_tmp = slot->buf;
  574. buf_tmp_dma = slot->buf_dma;
  575. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  576. buf_tmp += MVS_ATA_CMD_SZ;
  577. buf_tmp_dma += MVS_ATA_CMD_SZ;
  578. #if _MV_DUMP
  579. slot->cmd_size = MVS_ATA_CMD_SZ;
  580. #endif
  581. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  582. /* used for STP. unused for SATA? */
  583. buf_oaf = buf_tmp;
  584. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  585. buf_tmp += MVS_OAF_SZ;
  586. buf_tmp_dma += MVS_OAF_SZ;
  587. /* region 3: PRD table ********************************************* */
  588. buf_prd = buf_tmp;
  589. if (tei->n_elem)
  590. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  591. else
  592. hdr->prd_tbl = 0;
  593. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  594. buf_tmp += i;
  595. buf_tmp_dma += i;
  596. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  597. /* FIXME: probably unused, for SATA. kept here just in case
  598. * we get a STP/SATA error information record
  599. */
  600. slot->response = buf_tmp;
  601. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  602. if (mvi->flags & MVF_FLAG_SOC)
  603. hdr->reserved[0] = 0;
  604. req_len = sizeof(struct host_to_dev_fis);
  605. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  606. sizeof(struct mvs_err_info) - i;
  607. /* request, response lengths */
  608. resp_len = min(resp_len, max_resp_len);
  609. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  610. if (likely(!task->ata_task.device_control_reg_update))
  611. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  612. /* fill in command FIS and ATAPI CDB */
  613. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  614. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  615. memcpy(buf_cmd + STP_ATAPI_CMD,
  616. task->ata_task.atapi_packet, 16);
  617. /* generate open address frame hdr (first 12 bytes) */
  618. /* initiator, STP, ftype 1h */
  619. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  620. buf_oaf[1] = dev->linkrate & 0xf;
  621. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  622. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  623. /* fill in PRD (scatter/gather) table, if any */
  624. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  625. #ifndef DISABLE_HOTPLUG_DMA_FIX
  626. if (task->data_dir == DMA_FROM_DEVICE)
  627. MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
  628. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  629. #endif
  630. return 0;
  631. }
  632. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  633. struct mvs_task_exec_info *tei, int is_tmf,
  634. struct mvs_tmf_task *tmf)
  635. {
  636. struct sas_task *task = tei->task;
  637. struct mvs_cmd_hdr *hdr = tei->hdr;
  638. struct mvs_port *port = tei->port;
  639. struct domain_device *dev = task->dev;
  640. struct mvs_device *mvi_dev =
  641. (struct mvs_device *)dev->lldd_dev;
  642. struct asd_sas_port *sas_port = dev->port;
  643. struct mvs_slot_info *slot;
  644. void *buf_prd;
  645. struct ssp_frame_hdr *ssp_hdr;
  646. void *buf_tmp;
  647. u8 *buf_cmd, *buf_oaf, fburst = 0;
  648. dma_addr_t buf_tmp_dma;
  649. u32 flags;
  650. u32 resp_len, req_len, i, tag = tei->tag;
  651. const u32 max_resp_len = SB_RFB_MAX;
  652. u32 phy_mask;
  653. slot = &mvi->slot_info[tag];
  654. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  655. sas_port->phy_mask) & TXQ_PHY_MASK;
  656. slot->tx = mvi->tx_prod;
  657. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  658. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  659. (phy_mask << TXQ_PHY_SHIFT));
  660. flags = MCH_RETRY;
  661. if (task->ssp_task.enable_first_burst) {
  662. flags |= MCH_FBURST;
  663. fburst = (1 << 7);
  664. }
  665. if (is_tmf)
  666. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  667. else
  668. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  669. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  670. hdr->tags = cpu_to_le32(tag);
  671. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  672. /*
  673. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  674. */
  675. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  676. buf_cmd = buf_tmp = slot->buf;
  677. buf_tmp_dma = slot->buf_dma;
  678. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  679. buf_tmp += MVS_SSP_CMD_SZ;
  680. buf_tmp_dma += MVS_SSP_CMD_SZ;
  681. #if _MV_DUMP
  682. slot->cmd_size = MVS_SSP_CMD_SZ;
  683. #endif
  684. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  685. buf_oaf = buf_tmp;
  686. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  687. buf_tmp += MVS_OAF_SZ;
  688. buf_tmp_dma += MVS_OAF_SZ;
  689. /* region 3: PRD table ********************************************* */
  690. buf_prd = buf_tmp;
  691. if (tei->n_elem)
  692. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  693. else
  694. hdr->prd_tbl = 0;
  695. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  696. buf_tmp += i;
  697. buf_tmp_dma += i;
  698. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  699. slot->response = buf_tmp;
  700. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  701. if (mvi->flags & MVF_FLAG_SOC)
  702. hdr->reserved[0] = 0;
  703. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  704. sizeof(struct mvs_err_info) - i;
  705. resp_len = min(resp_len, max_resp_len);
  706. req_len = sizeof(struct ssp_frame_hdr) + 28;
  707. /* request, response lengths */
  708. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  709. /* generate open address frame hdr (first 12 bytes) */
  710. /* initiator, SSP, ftype 1h */
  711. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  712. buf_oaf[1] = dev->linkrate & 0xf;
  713. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  714. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  715. /* fill in SSP frame header (Command Table.SSP frame header) */
  716. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  717. if (is_tmf)
  718. ssp_hdr->frame_type = SSP_TASK;
  719. else
  720. ssp_hdr->frame_type = SSP_COMMAND;
  721. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  722. HASHED_SAS_ADDR_SIZE);
  723. memcpy(ssp_hdr->hashed_src_addr,
  724. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  725. ssp_hdr->tag = cpu_to_be16(tag);
  726. /* fill in IU for TASK and Command Frame */
  727. buf_cmd += sizeof(*ssp_hdr);
  728. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  729. if (ssp_hdr->frame_type != SSP_TASK) {
  730. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  731. (task->ssp_task.task_prio << 3);
  732. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  733. } else{
  734. buf_cmd[10] = tmf->tmf;
  735. switch (tmf->tmf) {
  736. case TMF_ABORT_TASK:
  737. case TMF_QUERY_TASK:
  738. buf_cmd[12] =
  739. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  740. buf_cmd[13] =
  741. tmf->tag_of_task_to_be_managed & 0xff;
  742. break;
  743. default:
  744. break;
  745. }
  746. }
  747. /* fill in PRD (scatter/gather) table, if any */
  748. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  749. return 0;
  750. }
  751. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  752. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  753. struct completion *completion,int is_tmf,
  754. struct mvs_tmf_task *tmf)
  755. {
  756. struct domain_device *dev = task->dev;
  757. struct mvs_info *mvi;
  758. struct mvs_device *mvi_dev;
  759. struct mvs_task_exec_info tei;
  760. struct sas_task *t = task;
  761. struct mvs_slot_info *slot;
  762. u32 tag = 0xdeadbeef, rc, n_elem = 0;
  763. u32 n = num, pass = 0;
  764. unsigned long flags = 0;
  765. if (!dev->port) {
  766. struct task_status_struct *tsm = &t->task_status;
  767. tsm->resp = SAS_TASK_UNDELIVERED;
  768. tsm->stat = SAS_PHY_DOWN;
  769. t->task_done(t);
  770. return 0;
  771. }
  772. mvi = mvs_find_dev_mvi(task->dev);
  773. spin_lock_irqsave(&mvi->lock, flags);
  774. do {
  775. dev = t->dev;
  776. mvi_dev = (struct mvs_device *)dev->lldd_dev;
  777. if (DEV_IS_GONE(mvi_dev)) {
  778. if (mvi_dev)
  779. mv_dprintk("device %d not ready.\n",
  780. mvi_dev->device_id);
  781. else
  782. mv_dprintk("device %016llx not ready.\n",
  783. SAS_ADDR(dev->sas_addr));
  784. rc = SAS_PHY_DOWN;
  785. goto out_done;
  786. }
  787. if (dev->port->id >= mvi->chip->n_phy)
  788. tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
  789. else
  790. tei.port = &mvi->port[dev->port->id];
  791. if (!tei.port->port_attached) {
  792. if (sas_protocol_ata(t->task_proto)) {
  793. mv_dprintk("port %d does not"
  794. "attached device.\n", dev->port->id);
  795. rc = SAS_PHY_DOWN;
  796. goto out_done;
  797. } else {
  798. struct task_status_struct *ts = &t->task_status;
  799. ts->resp = SAS_TASK_UNDELIVERED;
  800. ts->stat = SAS_PHY_DOWN;
  801. t->task_done(t);
  802. if (n > 1)
  803. t = list_entry(t->list.next,
  804. struct sas_task, list);
  805. continue;
  806. }
  807. }
  808. if (!sas_protocol_ata(t->task_proto)) {
  809. if (t->num_scatter) {
  810. n_elem = dma_map_sg(mvi->dev,
  811. t->scatter,
  812. t->num_scatter,
  813. t->data_dir);
  814. if (!n_elem) {
  815. rc = -ENOMEM;
  816. goto err_out;
  817. }
  818. }
  819. } else {
  820. n_elem = t->num_scatter;
  821. }
  822. rc = mvs_tag_alloc(mvi, &tag);
  823. if (rc)
  824. goto err_out;
  825. slot = &mvi->slot_info[tag];
  826. t->lldd_task = NULL;
  827. slot->n_elem = n_elem;
  828. slot->slot_tag = tag;
  829. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  830. tei.task = t;
  831. tei.hdr = &mvi->slot[tag];
  832. tei.tag = tag;
  833. tei.n_elem = n_elem;
  834. switch (t->task_proto) {
  835. case SAS_PROTOCOL_SMP:
  836. rc = mvs_task_prep_smp(mvi, &tei);
  837. break;
  838. case SAS_PROTOCOL_SSP:
  839. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  840. break;
  841. case SAS_PROTOCOL_SATA:
  842. case SAS_PROTOCOL_STP:
  843. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  844. rc = mvs_task_prep_ata(mvi, &tei);
  845. break;
  846. default:
  847. dev_printk(KERN_ERR, mvi->dev,
  848. "unknown sas_task proto: 0x%x\n",
  849. t->task_proto);
  850. rc = -EINVAL;
  851. break;
  852. }
  853. if (rc) {
  854. mv_dprintk("rc is %x\n", rc);
  855. goto err_out_tag;
  856. }
  857. slot->task = t;
  858. slot->port = tei.port;
  859. t->lldd_task = (void *) slot;
  860. list_add_tail(&slot->entry, &tei.port->list);
  861. /* TODO: select normal or high priority */
  862. spin_lock(&t->task_state_lock);
  863. t->task_state_flags |= SAS_TASK_AT_INITIATOR;
  864. spin_unlock(&t->task_state_lock);
  865. mvs_hba_memory_dump(mvi, tag, t->task_proto);
  866. mvi_dev->runing_req++;
  867. ++pass;
  868. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  869. if (n > 1)
  870. t = list_entry(t->list.next, struct sas_task, list);
  871. } while (--n);
  872. rc = 0;
  873. goto out_done;
  874. err_out_tag:
  875. mvs_tag_free(mvi, tag);
  876. err_out:
  877. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  878. if (!sas_protocol_ata(t->task_proto))
  879. if (n_elem)
  880. dma_unmap_sg(mvi->dev, t->scatter, n_elem,
  881. t->data_dir);
  882. out_done:
  883. if (likely(pass)) {
  884. MVS_CHIP_DISP->start_delivery(mvi,
  885. (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  886. }
  887. spin_unlock_irqrestore(&mvi->lock, flags);
  888. return rc;
  889. }
  890. int mvs_queue_command(struct sas_task *task, const int num,
  891. gfp_t gfp_flags)
  892. {
  893. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  894. }
  895. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  896. {
  897. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  898. mvs_tag_clear(mvi, slot_idx);
  899. }
  900. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  901. struct mvs_slot_info *slot, u32 slot_idx)
  902. {
  903. if (!slot->task)
  904. return;
  905. if (!sas_protocol_ata(task->task_proto))
  906. if (slot->n_elem)
  907. dma_unmap_sg(mvi->dev, task->scatter,
  908. slot->n_elem, task->data_dir);
  909. switch (task->task_proto) {
  910. case SAS_PROTOCOL_SMP:
  911. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  912. PCI_DMA_FROMDEVICE);
  913. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  914. PCI_DMA_TODEVICE);
  915. break;
  916. case SAS_PROTOCOL_SATA:
  917. case SAS_PROTOCOL_STP:
  918. case SAS_PROTOCOL_SSP:
  919. default:
  920. /* do nothing */
  921. break;
  922. }
  923. list_del_init(&slot->entry);
  924. task->lldd_task = NULL;
  925. slot->task = NULL;
  926. slot->port = NULL;
  927. slot->slot_tag = 0xFFFFFFFF;
  928. mvs_slot_free(mvi, slot_idx);
  929. }
  930. static void mvs_update_wideport(struct mvs_info *mvi, int i)
  931. {
  932. struct mvs_phy *phy = &mvi->phy[i];
  933. struct mvs_port *port = phy->port;
  934. int j, no;
  935. for_each_phy(port->wide_port_phymap, j, no) {
  936. if (j & 1) {
  937. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  938. PHYR_WIDE_PORT);
  939. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  940. port->wide_port_phymap);
  941. } else {
  942. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  943. PHYR_WIDE_PORT);
  944. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  945. 0);
  946. }
  947. }
  948. }
  949. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  950. {
  951. u32 tmp;
  952. struct mvs_phy *phy = &mvi->phy[i];
  953. struct mvs_port *port = phy->port;
  954. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  955. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  956. if (!port)
  957. phy->phy_attached = 1;
  958. return tmp;
  959. }
  960. if (port) {
  961. if (phy->phy_type & PORT_TYPE_SAS) {
  962. port->wide_port_phymap &= ~(1U << i);
  963. if (!port->wide_port_phymap)
  964. port->port_attached = 0;
  965. mvs_update_wideport(mvi, i);
  966. } else if (phy->phy_type & PORT_TYPE_SATA)
  967. port->port_attached = 0;
  968. phy->port = NULL;
  969. phy->phy_attached = 0;
  970. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  971. }
  972. return 0;
  973. }
  974. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  975. {
  976. u32 *s = (u32 *) buf;
  977. if (!s)
  978. return NULL;
  979. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  980. s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  981. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  982. s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  983. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  984. s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  985. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  986. s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  987. /* Workaround: take some ATAPI devices for ATA */
  988. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  989. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  990. return (void *)s;
  991. }
  992. static u32 mvs_is_sig_fis_received(u32 irq_status)
  993. {
  994. return irq_status & PHYEV_SIG_FIS;
  995. }
  996. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  997. {
  998. struct mvs_phy *phy = &mvi->phy[i];
  999. struct sas_identify_frame *id;
  1000. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1001. if (get_st) {
  1002. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  1003. phy->phy_status = mvs_is_phy_ready(mvi, i);
  1004. }
  1005. if (phy->phy_status) {
  1006. int oob_done = 0;
  1007. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  1008. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  1009. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  1010. if (phy->phy_type & PORT_TYPE_SATA) {
  1011. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  1012. if (mvs_is_sig_fis_received(phy->irq_status)) {
  1013. phy->phy_attached = 1;
  1014. phy->att_dev_sas_addr =
  1015. i + mvi->id * mvi->chip->n_phy;
  1016. if (oob_done)
  1017. sas_phy->oob_mode = SATA_OOB_MODE;
  1018. phy->frame_rcvd_size =
  1019. sizeof(struct dev_to_host_fis);
  1020. mvs_get_d2h_reg(mvi, i, (void *)id);
  1021. } else {
  1022. u32 tmp;
  1023. dev_printk(KERN_DEBUG, mvi->dev,
  1024. "Phy%d : No sig fis\n", i);
  1025. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  1026. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  1027. tmp | PHYEV_SIG_FIS);
  1028. phy->phy_attached = 0;
  1029. phy->phy_type &= ~PORT_TYPE_SATA;
  1030. MVS_CHIP_DISP->phy_reset(mvi, i, 0);
  1031. goto out_done;
  1032. }
  1033. } else if (phy->phy_type & PORT_TYPE_SAS
  1034. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  1035. phy->phy_attached = 1;
  1036. phy->identify.device_type =
  1037. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  1038. if (phy->identify.device_type == SAS_END_DEV)
  1039. phy->identify.target_port_protocols =
  1040. SAS_PROTOCOL_SSP;
  1041. else if (phy->identify.device_type != NO_DEVICE)
  1042. phy->identify.target_port_protocols =
  1043. SAS_PROTOCOL_SMP;
  1044. if (oob_done)
  1045. sas_phy->oob_mode = SAS_OOB_MODE;
  1046. phy->frame_rcvd_size =
  1047. sizeof(struct sas_identify_frame);
  1048. }
  1049. memcpy(sas_phy->attached_sas_addr,
  1050. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1051. if (MVS_CHIP_DISP->phy_work_around)
  1052. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1053. }
  1054. mv_dprintk("port %d attach dev info is %x\n",
  1055. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1056. mv_dprintk("port %d attach sas addr is %llx\n",
  1057. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1058. out_done:
  1059. if (get_st)
  1060. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1061. }
  1062. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1063. {
  1064. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1065. struct mvs_info *mvi = NULL; int i = 0, hi;
  1066. struct mvs_phy *phy = sas_phy->lldd_phy;
  1067. struct asd_sas_port *sas_port = sas_phy->port;
  1068. struct mvs_port *port;
  1069. unsigned long flags = 0;
  1070. if (!sas_port)
  1071. return;
  1072. while (sas_ha->sas_phy[i]) {
  1073. if (sas_ha->sas_phy[i] == sas_phy)
  1074. break;
  1075. i++;
  1076. }
  1077. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1078. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1079. if (sas_port->id >= mvi->chip->n_phy)
  1080. port = &mvi->port[sas_port->id - mvi->chip->n_phy];
  1081. else
  1082. port = &mvi->port[sas_port->id];
  1083. if (lock)
  1084. spin_lock_irqsave(&mvi->lock, flags);
  1085. port->port_attached = 1;
  1086. phy->port = port;
  1087. if (phy->phy_type & PORT_TYPE_SAS) {
  1088. port->wide_port_phymap = sas_port->phy_mask;
  1089. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1090. mvs_update_wideport(mvi, sas_phy->id);
  1091. }
  1092. if (lock)
  1093. spin_unlock_irqrestore(&mvi->lock, flags);
  1094. }
  1095. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1096. {
  1097. /*Nothing*/
  1098. }
  1099. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1100. {
  1101. mvs_port_notify_formed(sas_phy, 1);
  1102. }
  1103. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1104. {
  1105. mvs_port_notify_deformed(sas_phy, 1);
  1106. }
  1107. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1108. {
  1109. u32 dev;
  1110. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1111. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1112. mvi->devices[dev].device_id = dev;
  1113. return &mvi->devices[dev];
  1114. }
  1115. }
  1116. if (dev == MVS_MAX_DEVICES)
  1117. mv_printk("max support %d devices, ignore ..\n",
  1118. MVS_MAX_DEVICES);
  1119. return NULL;
  1120. }
  1121. void mvs_free_dev(struct mvs_device *mvi_dev)
  1122. {
  1123. u32 id = mvi_dev->device_id;
  1124. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1125. mvi_dev->device_id = id;
  1126. mvi_dev->dev_type = NO_DEVICE;
  1127. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1128. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1129. }
  1130. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1131. {
  1132. unsigned long flags = 0;
  1133. int res = 0;
  1134. struct mvs_info *mvi = NULL;
  1135. struct domain_device *parent_dev = dev->parent;
  1136. struct mvs_device *mvi_device;
  1137. mvi = mvs_find_dev_mvi(dev);
  1138. if (lock)
  1139. spin_lock_irqsave(&mvi->lock, flags);
  1140. mvi_device = mvs_alloc_dev(mvi);
  1141. if (!mvi_device) {
  1142. res = -1;
  1143. goto found_out;
  1144. }
  1145. dev->lldd_dev = (void *)mvi_device;
  1146. mvi_device->dev_type = dev->dev_type;
  1147. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1148. int phy_id;
  1149. u8 phy_num = parent_dev->ex_dev.num_phys;
  1150. struct ex_phy *phy;
  1151. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1152. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1153. if (SAS_ADDR(phy->attached_sas_addr) ==
  1154. SAS_ADDR(dev->sas_addr)) {
  1155. mvi_device->attached_phy = phy_id;
  1156. break;
  1157. }
  1158. }
  1159. if (phy_id == phy_num) {
  1160. mv_printk("Error: no attached dev:%016llx"
  1161. "at ex:%016llx.\n",
  1162. SAS_ADDR(dev->sas_addr),
  1163. SAS_ADDR(parent_dev->sas_addr));
  1164. res = -1;
  1165. }
  1166. }
  1167. found_out:
  1168. if (lock)
  1169. spin_unlock_irqrestore(&mvi->lock, flags);
  1170. return res;
  1171. }
  1172. int mvs_dev_found(struct domain_device *dev)
  1173. {
  1174. return mvs_dev_found_notify(dev, 1);
  1175. }
  1176. void mvs_dev_gone_notify(struct domain_device *dev, int lock)
  1177. {
  1178. unsigned long flags = 0;
  1179. struct mvs_info *mvi;
  1180. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1181. mvi = mvs_find_dev_mvi(dev);
  1182. if (lock)
  1183. spin_lock_irqsave(&mvi->lock, flags);
  1184. if (mvi_dev) {
  1185. mv_dprintk("found dev[%d:%x] is gone.\n",
  1186. mvi_dev->device_id, mvi_dev->dev_type);
  1187. mvs_free_reg_set(mvi, mvi_dev);
  1188. mvs_free_dev(mvi_dev);
  1189. } else {
  1190. mv_dprintk("found dev has gone.\n");
  1191. }
  1192. dev->lldd_dev = NULL;
  1193. if (lock)
  1194. spin_unlock_irqrestore(&mvi->lock, flags);
  1195. }
  1196. void mvs_dev_gone(struct domain_device *dev)
  1197. {
  1198. mvs_dev_gone_notify(dev, 1);
  1199. }
  1200. static struct sas_task *mvs_alloc_task(void)
  1201. {
  1202. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1203. if (task) {
  1204. INIT_LIST_HEAD(&task->list);
  1205. spin_lock_init(&task->task_state_lock);
  1206. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1207. init_timer(&task->timer);
  1208. init_completion(&task->completion);
  1209. }
  1210. return task;
  1211. }
  1212. static void mvs_free_task(struct sas_task *task)
  1213. {
  1214. if (task) {
  1215. BUG_ON(!list_empty(&task->list));
  1216. kfree(task);
  1217. }
  1218. }
  1219. static void mvs_task_done(struct sas_task *task)
  1220. {
  1221. if (!del_timer(&task->timer))
  1222. return;
  1223. complete(&task->completion);
  1224. }
  1225. static void mvs_tmf_timedout(unsigned long data)
  1226. {
  1227. struct sas_task *task = (struct sas_task *)data;
  1228. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1229. complete(&task->completion);
  1230. }
  1231. /* XXX */
  1232. #define MVS_TASK_TIMEOUT 20
  1233. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1234. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1235. {
  1236. int res, retry;
  1237. struct sas_task *task = NULL;
  1238. for (retry = 0; retry < 3; retry++) {
  1239. task = mvs_alloc_task();
  1240. if (!task)
  1241. return -ENOMEM;
  1242. task->dev = dev;
  1243. task->task_proto = dev->tproto;
  1244. memcpy(&task->ssp_task, parameter, para_len);
  1245. task->task_done = mvs_task_done;
  1246. task->timer.data = (unsigned long) task;
  1247. task->timer.function = mvs_tmf_timedout;
  1248. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1249. add_timer(&task->timer);
  1250. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1251. if (res) {
  1252. del_timer(&task->timer);
  1253. mv_printk("executing internel task failed:%d\n", res);
  1254. goto ex_err;
  1255. }
  1256. wait_for_completion(&task->completion);
  1257. res = -TMF_RESP_FUNC_FAILED;
  1258. /* Even TMF timed out, return direct. */
  1259. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1260. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1261. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1262. goto ex_err;
  1263. }
  1264. }
  1265. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1266. task->task_status.stat == SAM_GOOD) {
  1267. res = TMF_RESP_FUNC_COMPLETE;
  1268. break;
  1269. }
  1270. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1271. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1272. /* no error, but return the number of bytes of
  1273. * underrun */
  1274. res = task->task_status.residual;
  1275. break;
  1276. }
  1277. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1278. task->task_status.stat == SAS_DATA_OVERRUN) {
  1279. mv_dprintk("blocked task error.\n");
  1280. res = -EMSGSIZE;
  1281. break;
  1282. } else {
  1283. mv_dprintk(" task to dev %016llx response: 0x%x "
  1284. "status 0x%x\n",
  1285. SAS_ADDR(dev->sas_addr),
  1286. task->task_status.resp,
  1287. task->task_status.stat);
  1288. mvs_free_task(task);
  1289. task = NULL;
  1290. }
  1291. }
  1292. ex_err:
  1293. BUG_ON(retry == 3 && task != NULL);
  1294. if (task != NULL)
  1295. mvs_free_task(task);
  1296. return res;
  1297. }
  1298. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1299. u8 *lun, struct mvs_tmf_task *tmf)
  1300. {
  1301. struct sas_ssp_task ssp_task;
  1302. DECLARE_COMPLETION_ONSTACK(completion);
  1303. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1304. return TMF_RESP_FUNC_ESUPP;
  1305. strncpy((u8 *)&ssp_task.LUN, lun, 8);
  1306. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1307. sizeof(ssp_task), tmf);
  1308. }
  1309. /* Standard mandates link reset for ATA (type 0)
  1310. and hard reset for SSP (type 1) , only for RECOVERY */
  1311. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1312. {
  1313. int rc;
  1314. struct sas_phy *phy = sas_find_local_phy(dev);
  1315. int reset_type = (dev->dev_type == SATA_DEV ||
  1316. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1317. rc = sas_phy_reset(phy, reset_type);
  1318. msleep(2000);
  1319. return rc;
  1320. }
  1321. /* mandatory SAM-3 */
  1322. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1323. {
  1324. unsigned long flags;
  1325. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1326. struct mvs_tmf_task tmf_task;
  1327. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  1328. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1329. tmf_task.tmf = TMF_LU_RESET;
  1330. mvi_dev->dev_status = MVS_DEV_EH;
  1331. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1332. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1333. num = mvs_find_dev_phyno(dev, phyno);
  1334. spin_lock_irqsave(&mvi->lock, flags);
  1335. for (i = 0; i < num; i++)
  1336. mvs_release_task(mvi, phyno[i], dev);
  1337. spin_unlock_irqrestore(&mvi->lock, flags);
  1338. }
  1339. /* If failed, fall-through I_T_Nexus reset */
  1340. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1341. mvi_dev->device_id, rc);
  1342. return rc;
  1343. }
  1344. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1345. {
  1346. unsigned long flags;
  1347. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1348. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  1349. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1350. if (mvi_dev->dev_status != MVS_DEV_EH)
  1351. return TMF_RESP_FUNC_COMPLETE;
  1352. rc = mvs_debug_I_T_nexus_reset(dev);
  1353. mv_printk("%s for device[%x]:rc= %d\n",
  1354. __func__, mvi_dev->device_id, rc);
  1355. /* housekeeper */
  1356. num = mvs_find_dev_phyno(dev, phyno);
  1357. spin_lock_irqsave(&mvi->lock, flags);
  1358. for (i = 0; i < num; i++)
  1359. mvs_release_task(mvi, phyno[i], dev);
  1360. spin_unlock_irqrestore(&mvi->lock, flags);
  1361. return rc;
  1362. }
  1363. /* optional SAM-3 */
  1364. int mvs_query_task(struct sas_task *task)
  1365. {
  1366. u32 tag;
  1367. struct scsi_lun lun;
  1368. struct mvs_tmf_task tmf_task;
  1369. int rc = TMF_RESP_FUNC_FAILED;
  1370. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1371. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1372. struct domain_device *dev = task->dev;
  1373. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  1374. int_to_scsilun(cmnd->device->lun, &lun);
  1375. rc = mvs_find_tag(mvi, task, &tag);
  1376. if (rc == 0) {
  1377. rc = TMF_RESP_FUNC_FAILED;
  1378. return rc;
  1379. }
  1380. tmf_task.tmf = TMF_QUERY_TASK;
  1381. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1382. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1383. switch (rc) {
  1384. /* The task is still in Lun, release it then */
  1385. case TMF_RESP_FUNC_SUCC:
  1386. /* The task is not in Lun or failed, reset the phy */
  1387. case TMF_RESP_FUNC_FAILED:
  1388. case TMF_RESP_FUNC_COMPLETE:
  1389. break;
  1390. }
  1391. }
  1392. mv_printk("%s:rc= %d\n", __func__, rc);
  1393. return rc;
  1394. }
  1395. /* mandatory SAM-3, still need free task/slot info */
  1396. int mvs_abort_task(struct sas_task *task)
  1397. {
  1398. struct scsi_lun lun;
  1399. struct mvs_tmf_task tmf_task;
  1400. struct domain_device *dev = task->dev;
  1401. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  1402. int rc = TMF_RESP_FUNC_FAILED;
  1403. unsigned long flags;
  1404. u32 tag;
  1405. if (mvi->exp_req)
  1406. mvi->exp_req--;
  1407. spin_lock_irqsave(&task->task_state_lock, flags);
  1408. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1409. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1410. rc = TMF_RESP_FUNC_COMPLETE;
  1411. goto out;
  1412. }
  1413. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1414. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1415. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1416. int_to_scsilun(cmnd->device->lun, &lun);
  1417. rc = mvs_find_tag(mvi, task, &tag);
  1418. if (rc == 0) {
  1419. mv_printk("No such tag in %s\n", __func__);
  1420. rc = TMF_RESP_FUNC_FAILED;
  1421. return rc;
  1422. }
  1423. tmf_task.tmf = TMF_ABORT_TASK;
  1424. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1425. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1426. /* if successful, clear the task and callback forwards.*/
  1427. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1428. u32 slot_no;
  1429. struct mvs_slot_info *slot;
  1430. struct mvs_info *mvi = mvs_find_dev_mvi(dev);
  1431. if (task->lldd_task) {
  1432. slot = (struct mvs_slot_info *)task->lldd_task;
  1433. slot_no = (u32) (slot - mvi->slot_info);
  1434. mvs_slot_complete(mvi, slot_no, 1);
  1435. }
  1436. }
  1437. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1438. task->task_proto & SAS_PROTOCOL_STP) {
  1439. /* to do free register_set */
  1440. } else {
  1441. /* SMP */
  1442. }
  1443. out:
  1444. if (rc != TMF_RESP_FUNC_COMPLETE)
  1445. mv_printk("%s:rc= %d\n", __func__, rc);
  1446. return rc;
  1447. }
  1448. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1449. {
  1450. int rc = TMF_RESP_FUNC_FAILED;
  1451. struct mvs_tmf_task tmf_task;
  1452. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1453. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1454. return rc;
  1455. }
  1456. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1457. {
  1458. int rc = TMF_RESP_FUNC_FAILED;
  1459. struct mvs_tmf_task tmf_task;
  1460. tmf_task.tmf = TMF_CLEAR_ACA;
  1461. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1462. return rc;
  1463. }
  1464. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1465. {
  1466. int rc = TMF_RESP_FUNC_FAILED;
  1467. struct mvs_tmf_task tmf_task;
  1468. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1469. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1470. return rc;
  1471. }
  1472. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1473. u32 slot_idx, int err)
  1474. {
  1475. struct mvs_device *mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
  1476. struct task_status_struct *tstat = &task->task_status;
  1477. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1478. int stat = SAM_GOOD;
  1479. resp->frame_len = sizeof(struct dev_to_host_fis);
  1480. memcpy(&resp->ending_fis[0],
  1481. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1482. sizeof(struct dev_to_host_fis));
  1483. tstat->buf_valid_size = sizeof(*resp);
  1484. if (unlikely(err))
  1485. stat = SAS_PROTO_RESPONSE;
  1486. return stat;
  1487. }
  1488. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1489. u32 slot_idx)
  1490. {
  1491. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1492. int stat;
  1493. u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
  1494. u32 tfs = 0;
  1495. enum mvs_port_type type = PORT_TYPE_SAS;
  1496. if (err_dw0 & CMD_ISS_STPD)
  1497. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1498. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1499. stat = SAM_CHECK_COND;
  1500. switch (task->task_proto) {
  1501. case SAS_PROTOCOL_SSP:
  1502. stat = SAS_ABORTED_TASK;
  1503. break;
  1504. case SAS_PROTOCOL_SMP:
  1505. stat = SAM_CHECK_COND;
  1506. break;
  1507. case SAS_PROTOCOL_SATA:
  1508. case SAS_PROTOCOL_STP:
  1509. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1510. {
  1511. if (err_dw0 == 0x80400002)
  1512. mv_printk("find reserved error, why?\n");
  1513. task->ata_task.use_ncq = 0;
  1514. stat = SAS_PROTO_RESPONSE;
  1515. mvs_sata_done(mvi, task, slot_idx, 1);
  1516. }
  1517. break;
  1518. default:
  1519. break;
  1520. }
  1521. return stat;
  1522. }
  1523. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1524. {
  1525. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1526. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1527. struct sas_task *task = slot->task;
  1528. struct mvs_device *mvi_dev = NULL;
  1529. struct task_status_struct *tstat;
  1530. bool aborted;
  1531. void *to;
  1532. enum exec_status sts;
  1533. if (mvi->exp_req)
  1534. mvi->exp_req--;
  1535. if (unlikely(!task || !task->lldd_task))
  1536. return -1;
  1537. tstat = &task->task_status;
  1538. mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
  1539. mvs_hba_cq_dump(mvi);
  1540. spin_lock(&task->task_state_lock);
  1541. task->task_state_flags &=
  1542. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1543. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1544. /* race condition*/
  1545. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1546. spin_unlock(&task->task_state_lock);
  1547. memset(tstat, 0, sizeof(*tstat));
  1548. tstat->resp = SAS_TASK_COMPLETE;
  1549. if (unlikely(aborted)) {
  1550. tstat->stat = SAS_ABORTED_TASK;
  1551. if (mvi_dev)
  1552. mvi_dev->runing_req--;
  1553. if (sas_protocol_ata(task->task_proto))
  1554. mvs_free_reg_set(mvi, mvi_dev);
  1555. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1556. return -1;
  1557. }
  1558. if (unlikely(!mvi_dev || !slot->port->port_attached || flags)) {
  1559. mv_dprintk("port has not device.\n");
  1560. tstat->stat = SAS_PHY_DOWN;
  1561. goto out;
  1562. }
  1563. /*
  1564. if (unlikely((rx_desc & RXQ_ERR) || (*(u64 *) slot->response))) {
  1565. mv_dprintk("Find device[%016llx] RXQ_ERR %X,
  1566. err info:%016llx\n",
  1567. SAS_ADDR(task->dev->sas_addr),
  1568. rx_desc, (u64)(*(u64 *) slot->response));
  1569. }
  1570. */
  1571. /* error info record present */
  1572. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1573. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1574. goto out;
  1575. }
  1576. switch (task->task_proto) {
  1577. case SAS_PROTOCOL_SSP:
  1578. /* hw says status == 0, datapres == 0 */
  1579. if (rx_desc & RXQ_GOOD) {
  1580. tstat->stat = SAM_GOOD;
  1581. tstat->resp = SAS_TASK_COMPLETE;
  1582. }
  1583. /* response frame present */
  1584. else if (rx_desc & RXQ_RSP) {
  1585. struct ssp_response_iu *iu = slot->response +
  1586. sizeof(struct mvs_err_info);
  1587. sas_ssp_task_response(mvi->dev, task, iu);
  1588. } else
  1589. tstat->stat = SAM_CHECK_COND;
  1590. break;
  1591. case SAS_PROTOCOL_SMP: {
  1592. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1593. tstat->stat = SAM_GOOD;
  1594. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1595. memcpy(to + sg_resp->offset,
  1596. slot->response + sizeof(struct mvs_err_info),
  1597. sg_dma_len(sg_resp));
  1598. kunmap_atomic(to, KM_IRQ0);
  1599. break;
  1600. }
  1601. case SAS_PROTOCOL_SATA:
  1602. case SAS_PROTOCOL_STP:
  1603. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1604. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1605. break;
  1606. }
  1607. default:
  1608. tstat->stat = SAM_CHECK_COND;
  1609. break;
  1610. }
  1611. out:
  1612. if (mvi_dev) {
  1613. mvi_dev->runing_req--;
  1614. if (sas_protocol_ata(task->task_proto))
  1615. mvs_free_reg_set(mvi, mvi_dev);
  1616. }
  1617. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1618. sts = tstat->stat;
  1619. spin_unlock(&mvi->lock);
  1620. if (task->task_done)
  1621. task->task_done(task);
  1622. else
  1623. mv_dprintk("why has not task_done.\n");
  1624. spin_lock(&mvi->lock);
  1625. return sts;
  1626. }
  1627. void mvs_release_task(struct mvs_info *mvi,
  1628. int phy_no, struct domain_device *dev)
  1629. {
  1630. int i = 0; u32 slot_idx;
  1631. struct mvs_phy *phy;
  1632. struct mvs_port *port;
  1633. struct mvs_slot_info *slot, *slot2;
  1634. phy = &mvi->phy[phy_no];
  1635. port = phy->port;
  1636. if (!port)
  1637. return;
  1638. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1639. struct sas_task *task;
  1640. slot_idx = (u32) (slot - mvi->slot_info);
  1641. task = slot->task;
  1642. if (dev && task->dev != dev)
  1643. continue;
  1644. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1645. slot_idx, slot->slot_tag, task);
  1646. if (task->task_proto & SAS_PROTOCOL_SSP) {
  1647. mv_printk("attached with SSP task CDB[");
  1648. for (i = 0; i < 16; i++)
  1649. mv_printk(" %02x", task->ssp_task.cdb[i]);
  1650. mv_printk(" ]\n");
  1651. }
  1652. mvs_slot_complete(mvi, slot_idx, 1);
  1653. }
  1654. }
  1655. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1656. {
  1657. phy->phy_attached = 0;
  1658. phy->att_dev_info = 0;
  1659. phy->att_dev_sas_addr = 0;
  1660. }
  1661. static void mvs_work_queue(struct work_struct *work)
  1662. {
  1663. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1664. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1665. struct mvs_info *mvi = mwq->mvi;
  1666. unsigned long flags;
  1667. spin_lock_irqsave(&mvi->lock, flags);
  1668. if (mwq->handler & PHY_PLUG_EVENT) {
  1669. u32 phy_no = (unsigned long) mwq->data;
  1670. struct sas_ha_struct *sas_ha = mvi->sas;
  1671. struct mvs_phy *phy = &mvi->phy[phy_no];
  1672. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1673. if (phy->phy_event & PHY_PLUG_OUT) {
  1674. u32 tmp;
  1675. struct sas_identify_frame *id;
  1676. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1677. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1678. phy->phy_event &= ~PHY_PLUG_OUT;
  1679. if (!(tmp & PHY_READY_MASK)) {
  1680. sas_phy_disconnected(sas_phy);
  1681. mvs_phy_disconnected(phy);
  1682. sas_ha->notify_phy_event(sas_phy,
  1683. PHYE_LOSS_OF_SIGNAL);
  1684. mv_dprintk("phy%d Removed Device\n", phy_no);
  1685. } else {
  1686. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1687. mvs_update_phyinfo(mvi, phy_no, 1);
  1688. mvs_bytes_dmaed(mvi, phy_no);
  1689. mvs_port_notify_formed(sas_phy, 0);
  1690. mv_dprintk("phy%d Attached Device\n", phy_no);
  1691. }
  1692. }
  1693. }
  1694. list_del(&mwq->entry);
  1695. spin_unlock_irqrestore(&mvi->lock, flags);
  1696. kfree(mwq);
  1697. }
  1698. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1699. {
  1700. struct mvs_wq *mwq;
  1701. int ret = 0;
  1702. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1703. if (mwq) {
  1704. mwq->mvi = mvi;
  1705. mwq->data = data;
  1706. mwq->handler = handler;
  1707. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1708. list_add_tail(&mwq->entry, &mvi->wq_list);
  1709. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1710. } else
  1711. ret = -ENOMEM;
  1712. return ret;
  1713. }
  1714. static void mvs_sig_time_out(unsigned long tphy)
  1715. {
  1716. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1717. struct mvs_info *mvi = phy->mvi;
  1718. u8 phy_no;
  1719. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1720. if (&mvi->phy[phy_no] == phy) {
  1721. mv_dprintk("Get signature time out, reset phy %d\n",
  1722. phy_no+mvi->id*mvi->chip->n_phy);
  1723. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
  1724. }
  1725. }
  1726. }
  1727. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  1728. {
  1729. if (phy->timer.function)
  1730. del_timer(&phy->timer);
  1731. phy->timer.function = NULL;
  1732. }
  1733. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1734. {
  1735. u32 tmp;
  1736. struct sas_ha_struct *sas_ha = mvi->sas;
  1737. struct mvs_phy *phy = &mvi->phy[phy_no];
  1738. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1739. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1740. mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1741. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1742. mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1743. phy->irq_status);
  1744. /*
  1745. * events is port event now ,
  1746. * we need check the interrupt status which belongs to per port.
  1747. */
  1748. if (phy->irq_status & PHYEV_DCDR_ERR)
  1749. mv_dprintk("port %d STP decoding error.\n",
  1750. phy_no+mvi->id*mvi->chip->n_phy);
  1751. if (phy->irq_status & PHYEV_POOF) {
  1752. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1753. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1754. int ready;
  1755. mvs_release_task(mvi, phy_no, NULL);
  1756. phy->phy_event |= PHY_PLUG_OUT;
  1757. mvs_handle_event(mvi,
  1758. (void *)(unsigned long)phy_no,
  1759. PHY_PLUG_EVENT);
  1760. ready = mvs_is_phy_ready(mvi, phy_no);
  1761. if (!ready)
  1762. mv_dprintk("phy%d Unplug Notice\n",
  1763. phy_no +
  1764. mvi->id * mvi->chip->n_phy);
  1765. if (ready || dev_sata) {
  1766. if (MVS_CHIP_DISP->stp_reset)
  1767. MVS_CHIP_DISP->stp_reset(mvi,
  1768. phy_no);
  1769. else
  1770. MVS_CHIP_DISP->phy_reset(mvi,
  1771. phy_no, 0);
  1772. return;
  1773. }
  1774. }
  1775. }
  1776. if (phy->irq_status & PHYEV_COMWAKE) {
  1777. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1778. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1779. tmp | PHYEV_SIG_FIS);
  1780. if (phy->timer.function == NULL) {
  1781. phy->timer.data = (unsigned long)phy;
  1782. phy->timer.function = mvs_sig_time_out;
  1783. phy->timer.expires = jiffies + 10*HZ;
  1784. add_timer(&phy->timer);
  1785. }
  1786. }
  1787. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1788. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1789. mvs_sig_remove_timer(phy);
  1790. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1791. if (phy->phy_status) {
  1792. mdelay(10);
  1793. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1794. if (phy->phy_type & PORT_TYPE_SATA) {
  1795. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1796. mvi, phy_no);
  1797. tmp &= ~PHYEV_SIG_FIS;
  1798. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1799. phy_no, tmp);
  1800. }
  1801. mvs_update_phyinfo(mvi, phy_no, 0);
  1802. mvs_bytes_dmaed(mvi, phy_no);
  1803. /* whether driver is going to handle hot plug */
  1804. if (phy->phy_event & PHY_PLUG_OUT) {
  1805. mvs_port_notify_formed(sas_phy, 0);
  1806. phy->phy_event &= ~PHY_PLUG_OUT;
  1807. }
  1808. } else {
  1809. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1810. phy_no + mvi->id*mvi->chip->n_phy);
  1811. }
  1812. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1813. mv_dprintk("port %d broadcast change.\n",
  1814. phy_no + mvi->id*mvi->chip->n_phy);
  1815. /* exception for Samsung disk drive*/
  1816. mdelay(1000);
  1817. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1818. }
  1819. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1820. }
  1821. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1822. {
  1823. u32 rx_prod_idx, rx_desc;
  1824. bool attn = false;
  1825. /* the first dword in the RX ring is special: it contains
  1826. * a mirror of the hardware's RX producer index, so that
  1827. * we don't have to stall the CPU reading that register.
  1828. * The actual RX ring is offset by one dword, due to this.
  1829. */
  1830. rx_prod_idx = mvi->rx_cons;
  1831. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1832. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1833. return 0;
  1834. /* The CMPL_Q may come late, read from register and try again
  1835. * note: if coalescing is enabled,
  1836. * it will need to read from register every time for sure
  1837. */
  1838. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1839. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1840. if (mvi->rx_cons == rx_prod_idx)
  1841. return 0;
  1842. while (mvi->rx_cons != rx_prod_idx) {
  1843. /* increment our internal RX consumer pointer */
  1844. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1845. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1846. if (likely(rx_desc & RXQ_DONE))
  1847. mvs_slot_complete(mvi, rx_desc, 0);
  1848. if (rx_desc & RXQ_ATTN) {
  1849. attn = true;
  1850. } else if (rx_desc & RXQ_ERR) {
  1851. if (!(rx_desc & RXQ_DONE))
  1852. mvs_slot_complete(mvi, rx_desc, 0);
  1853. } else if (rx_desc & RXQ_SLOT_RESET) {
  1854. mvs_slot_free(mvi, rx_desc);
  1855. }
  1856. }
  1857. if (attn && self_clear)
  1858. MVS_CHIP_DISP->int_full(mvi);
  1859. return 0;
  1860. }