svm.c 40 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * AMD SVM support
  5. *
  6. * Copyright (C) 2006 Qumranet, Inc.
  7. *
  8. * Authors:
  9. * Yaniv Kamay <yaniv@qumranet.com>
  10. * Avi Kivity <avi@qumranet.com>
  11. *
  12. * This work is licensed under the terms of the GNU GPL, version 2. See
  13. * the COPYING file in the top-level directory.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/vmalloc.h>
  18. #include <linux/highmem.h>
  19. #include <asm/desc.h>
  20. #include "kvm_svm.h"
  21. #include "x86_emulate.h"
  22. MODULE_AUTHOR("Qumranet");
  23. MODULE_LICENSE("GPL");
  24. #define IOPM_ALLOC_ORDER 2
  25. #define MSRPM_ALLOC_ORDER 1
  26. #define DB_VECTOR 1
  27. #define UD_VECTOR 6
  28. #define GP_VECTOR 13
  29. #define DR7_GD_MASK (1 << 13)
  30. #define DR6_BD_MASK (1 << 13)
  31. #define CR4_DE_MASK (1UL << 3)
  32. #define SEG_TYPE_LDT 2
  33. #define SEG_TYPE_BUSY_TSS16 3
  34. #define KVM_EFER_LMA (1 << 10)
  35. #define KVM_EFER_LME (1 << 8)
  36. unsigned long iopm_base;
  37. unsigned long msrpm_base;
  38. struct kvm_ldttss_desc {
  39. u16 limit0;
  40. u16 base0;
  41. unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  42. unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  43. u32 base3;
  44. u32 zero1;
  45. } __attribute__((packed));
  46. struct svm_cpu_data {
  47. int cpu;
  48. uint64_t asid_generation;
  49. uint32_t max_asid;
  50. uint32_t next_asid;
  51. struct kvm_ldttss_desc *tss_desc;
  52. struct page *save_area;
  53. };
  54. static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  55. struct svm_init_data {
  56. int cpu;
  57. int r;
  58. };
  59. static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  60. #define NUM_MSR_MAPS (sizeof(msrpm_ranges) / sizeof(*msrpm_ranges))
  61. #define MSRS_RANGE_SIZE 2048
  62. #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  63. #define MAX_INST_SIZE 15
  64. static unsigned get_addr_size(struct kvm_vcpu *vcpu)
  65. {
  66. struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
  67. u16 cs_attrib;
  68. if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
  69. return 2;
  70. cs_attrib = sa->cs.attrib;
  71. return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
  72. (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
  73. }
  74. static inline u8 pop_irq(struct kvm_vcpu *vcpu)
  75. {
  76. int word_index = __ffs(vcpu->irq_summary);
  77. int bit_index = __ffs(vcpu->irq_pending[word_index]);
  78. int irq = word_index * BITS_PER_LONG + bit_index;
  79. clear_bit(bit_index, &vcpu->irq_pending[word_index]);
  80. if (!vcpu->irq_pending[word_index])
  81. clear_bit(word_index, &vcpu->irq_summary);
  82. return irq;
  83. }
  84. static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
  85. {
  86. set_bit(irq, vcpu->irq_pending);
  87. set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
  88. }
  89. static inline void clgi(void)
  90. {
  91. asm volatile (SVM_CLGI);
  92. }
  93. static inline void stgi(void)
  94. {
  95. asm volatile (SVM_STGI);
  96. }
  97. static inline void invlpga(unsigned long addr, u32 asid)
  98. {
  99. asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
  100. }
  101. static inline unsigned long kvm_read_cr2(void)
  102. {
  103. unsigned long cr2;
  104. asm volatile ("mov %%cr2, %0" : "=r" (cr2));
  105. return cr2;
  106. }
  107. static inline void kvm_write_cr2(unsigned long val)
  108. {
  109. asm volatile ("mov %0, %%cr2" :: "r" (val));
  110. }
  111. static inline unsigned long read_dr6(void)
  112. {
  113. unsigned long dr6;
  114. asm volatile ("mov %%dr6, %0" : "=r" (dr6));
  115. return dr6;
  116. }
  117. static inline void write_dr6(unsigned long val)
  118. {
  119. asm volatile ("mov %0, %%dr6" :: "r" (val));
  120. }
  121. static inline unsigned long read_dr7(void)
  122. {
  123. unsigned long dr7;
  124. asm volatile ("mov %%dr7, %0" : "=r" (dr7));
  125. return dr7;
  126. }
  127. static inline void write_dr7(unsigned long val)
  128. {
  129. asm volatile ("mov %0, %%dr7" :: "r" (val));
  130. }
  131. static inline int svm_is_long_mode(struct kvm_vcpu *vcpu)
  132. {
  133. return vcpu->svm->vmcb->save.efer & KVM_EFER_LMA;
  134. }
  135. static inline void force_new_asid(struct kvm_vcpu *vcpu)
  136. {
  137. vcpu->svm->asid_generation--;
  138. }
  139. static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
  140. {
  141. force_new_asid(vcpu);
  142. }
  143. static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
  144. {
  145. if (!(efer & KVM_EFER_LMA))
  146. efer &= ~KVM_EFER_LME;
  147. vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
  148. vcpu->shadow_efer = efer;
  149. }
  150. static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
  151. {
  152. vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
  153. SVM_EVTINJ_VALID_ERR |
  154. SVM_EVTINJ_TYPE_EXEPT |
  155. GP_VECTOR;
  156. vcpu->svm->vmcb->control.event_inj_err = error_code;
  157. }
  158. static void inject_ud(struct kvm_vcpu *vcpu)
  159. {
  160. vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
  161. SVM_EVTINJ_TYPE_EXEPT |
  162. UD_VECTOR;
  163. }
  164. static void inject_db(struct kvm_vcpu *vcpu)
  165. {
  166. vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
  167. SVM_EVTINJ_TYPE_EXEPT |
  168. DB_VECTOR;
  169. }
  170. static int is_page_fault(uint32_t info)
  171. {
  172. info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
  173. return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
  174. }
  175. static int is_external_interrupt(u32 info)
  176. {
  177. info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
  178. return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
  179. }
  180. static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
  181. {
  182. if (!vcpu->svm->next_rip) {
  183. printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
  184. return;
  185. }
  186. if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
  187. printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
  188. __FUNCTION__,
  189. vcpu->svm->vmcb->save.rip,
  190. vcpu->svm->next_rip);
  191. }
  192. vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
  193. vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
  194. }
  195. static int has_svm(void)
  196. {
  197. uint32_t eax, ebx, ecx, edx;
  198. if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) {
  199. printk(KERN_INFO "has_svm: not amd\n");
  200. return 0;
  201. }
  202. cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
  203. if (eax < SVM_CPUID_FUNC) {
  204. printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
  205. return 0;
  206. }
  207. cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
  208. if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
  209. printk(KERN_DEBUG "has_svm: svm not available\n");
  210. return 0;
  211. }
  212. return 1;
  213. }
  214. static void svm_hardware_disable(void *garbage)
  215. {
  216. struct svm_cpu_data *svm_data
  217. = per_cpu(svm_data, raw_smp_processor_id());
  218. if (svm_data) {
  219. uint64_t efer;
  220. wrmsrl(MSR_VM_HSAVE_PA, 0);
  221. rdmsrl(MSR_EFER, efer);
  222. wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
  223. per_cpu(svm_data, raw_smp_processor_id()) = 0;
  224. __free_page(svm_data->save_area);
  225. kfree(svm_data);
  226. }
  227. }
  228. static void svm_hardware_enable(void *garbage)
  229. {
  230. struct svm_cpu_data *svm_data;
  231. uint64_t efer;
  232. #ifdef CONFIG_X86_64
  233. struct desc_ptr gdt_descr;
  234. #else
  235. struct Xgt_desc_struct gdt_descr;
  236. #endif
  237. struct desc_struct *gdt;
  238. int me = raw_smp_processor_id();
  239. if (!has_svm()) {
  240. printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
  241. return;
  242. }
  243. svm_data = per_cpu(svm_data, me);
  244. if (!svm_data) {
  245. printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
  246. me);
  247. return;
  248. }
  249. svm_data->asid_generation = 1;
  250. svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
  251. svm_data->next_asid = svm_data->max_asid + 1;
  252. asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
  253. gdt = (struct desc_struct *)gdt_descr.address;
  254. svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
  255. rdmsrl(MSR_EFER, efer);
  256. wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
  257. wrmsrl(MSR_VM_HSAVE_PA,
  258. page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
  259. }
  260. static int svm_cpu_init(int cpu)
  261. {
  262. struct svm_cpu_data *svm_data;
  263. int r;
  264. svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
  265. if (!svm_data)
  266. return -ENOMEM;
  267. svm_data->cpu = cpu;
  268. svm_data->save_area = alloc_page(GFP_KERNEL);
  269. r = -ENOMEM;
  270. if (!svm_data->save_area)
  271. goto err_1;
  272. per_cpu(svm_data, cpu) = svm_data;
  273. return 0;
  274. err_1:
  275. kfree(svm_data);
  276. return r;
  277. }
  278. static int set_msr_interception(u32 *msrpm, unsigned msr,
  279. int read, int write)
  280. {
  281. int i;
  282. for (i = 0; i < NUM_MSR_MAPS; i++) {
  283. if (msr >= msrpm_ranges[i] &&
  284. msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
  285. u32 msr_offset = (i * MSRS_IN_RANGE + msr -
  286. msrpm_ranges[i]) * 2;
  287. u32 *base = msrpm + (msr_offset / 32);
  288. u32 msr_shift = msr_offset % 32;
  289. u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
  290. *base = (*base & ~(0x3 << msr_shift)) |
  291. (mask << msr_shift);
  292. return 1;
  293. }
  294. }
  295. printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
  296. return 0;
  297. }
  298. static __init int svm_hardware_setup(void)
  299. {
  300. int cpu;
  301. struct page *iopm_pages;
  302. struct page *msrpm_pages;
  303. void *msrpm_va;
  304. int r;
  305. kvm_emulator_want_group7_invlpg();
  306. iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
  307. if (!iopm_pages)
  308. return -ENOMEM;
  309. memset(page_address(iopm_pages), 0xff,
  310. PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
  311. iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
  312. msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
  313. r = -ENOMEM;
  314. if (!msrpm_pages)
  315. goto err_1;
  316. msrpm_va = page_address(msrpm_pages);
  317. memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
  318. msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
  319. #ifdef CONFIG_X86_64
  320. set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
  321. set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
  322. set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
  323. set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
  324. set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
  325. set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
  326. #endif
  327. set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
  328. set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
  329. set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
  330. set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
  331. for_each_online_cpu(cpu) {
  332. r = svm_cpu_init(cpu);
  333. if (r)
  334. goto err_2;
  335. }
  336. return 0;
  337. err_2:
  338. __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
  339. msrpm_base = 0;
  340. err_1:
  341. __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
  342. iopm_base = 0;
  343. return r;
  344. }
  345. static __exit void svm_hardware_unsetup(void)
  346. {
  347. __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
  348. __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
  349. iopm_base = msrpm_base = 0;
  350. }
  351. static void init_seg(struct vmcb_seg *seg)
  352. {
  353. seg->selector = 0;
  354. seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
  355. SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
  356. seg->limit = 0xffff;
  357. seg->base = 0;
  358. }
  359. static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
  360. {
  361. seg->selector = 0;
  362. seg->attrib = SVM_SELECTOR_P_MASK | type;
  363. seg->limit = 0xffff;
  364. seg->base = 0;
  365. }
  366. static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
  367. {
  368. return 0;
  369. }
  370. static void init_vmcb(struct vmcb *vmcb)
  371. {
  372. struct vmcb_control_area *control = &vmcb->control;
  373. struct vmcb_save_area *save = &vmcb->save;
  374. u64 tsc;
  375. control->intercept_cr_read = INTERCEPT_CR0_MASK |
  376. INTERCEPT_CR3_MASK |
  377. INTERCEPT_CR4_MASK;
  378. control->intercept_cr_write = INTERCEPT_CR0_MASK |
  379. INTERCEPT_CR3_MASK |
  380. INTERCEPT_CR4_MASK;
  381. control->intercept_dr_read = INTERCEPT_DR0_MASK |
  382. INTERCEPT_DR1_MASK |
  383. INTERCEPT_DR2_MASK |
  384. INTERCEPT_DR3_MASK;
  385. control->intercept_dr_write = INTERCEPT_DR0_MASK |
  386. INTERCEPT_DR1_MASK |
  387. INTERCEPT_DR2_MASK |
  388. INTERCEPT_DR3_MASK |
  389. INTERCEPT_DR5_MASK |
  390. INTERCEPT_DR7_MASK;
  391. control->intercept_exceptions = 1 << PF_VECTOR;
  392. control->intercept = (1ULL << INTERCEPT_INTR) |
  393. (1ULL << INTERCEPT_NMI) |
  394. /*
  395. * selective cr0 intercept bug?
  396. * 0: 0f 22 d8 mov %eax,%cr3
  397. * 3: 0f 20 c0 mov %cr0,%eax
  398. * 6: 0d 00 00 00 80 or $0x80000000,%eax
  399. * b: 0f 22 c0 mov %eax,%cr0
  400. * set cr3 ->interception
  401. * get cr0 ->interception
  402. * set cr0 -> no interception
  403. */
  404. /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
  405. (1ULL << INTERCEPT_CPUID) |
  406. (1ULL << INTERCEPT_HLT) |
  407. (1ULL << INTERCEPT_INVLPG) |
  408. (1ULL << INTERCEPT_INVLPGA) |
  409. (1ULL << INTERCEPT_IOIO_PROT) |
  410. (1ULL << INTERCEPT_MSR_PROT) |
  411. (1ULL << INTERCEPT_TASK_SWITCH) |
  412. (1ULL << INTERCEPT_VMRUN) |
  413. (1ULL << INTERCEPT_VMMCALL) |
  414. (1ULL << INTERCEPT_VMLOAD) |
  415. (1ULL << INTERCEPT_VMSAVE) |
  416. (1ULL << INTERCEPT_STGI) |
  417. (1ULL << INTERCEPT_CLGI) |
  418. (1ULL << INTERCEPT_SKINIT);
  419. control->iopm_base_pa = iopm_base;
  420. control->msrpm_base_pa = msrpm_base;
  421. rdtscll(tsc);
  422. control->tsc_offset = -tsc;
  423. control->int_ctl = V_INTR_MASKING_MASK;
  424. init_seg(&save->es);
  425. init_seg(&save->ss);
  426. init_seg(&save->ds);
  427. init_seg(&save->fs);
  428. init_seg(&save->gs);
  429. save->cs.selector = 0xf000;
  430. /* Executable/Readable Code Segment */
  431. save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
  432. SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
  433. save->cs.limit = 0xffff;
  434. save->cs.base = 0xffff0000;
  435. save->gdtr.limit = 0xffff;
  436. save->idtr.limit = 0xffff;
  437. init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
  438. init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
  439. save->efer = MSR_EFER_SVME_MASK;
  440. save->dr6 = 0xffff0ff0;
  441. save->dr7 = 0x400;
  442. save->rflags = 2;
  443. save->rip = 0x0000fff0;
  444. /*
  445. * cr0 val on cpu init should be 0x60000010, we enable cpu
  446. * cache by default. the orderly way is to enable cache in bios.
  447. */
  448. save->cr0 = 0x00000010 | CR0_PG_MASK;
  449. save->cr4 = CR4_PAE_MASK;
  450. /* rdx = ?? */
  451. }
  452. static int svm_create_vcpu(struct kvm_vcpu *vcpu)
  453. {
  454. struct page *page;
  455. int r;
  456. r = -ENOMEM;
  457. vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
  458. if (!vcpu->svm)
  459. goto out1;
  460. page = alloc_page(GFP_KERNEL);
  461. if (!page)
  462. goto out2;
  463. vcpu->svm->vmcb = page_address(page);
  464. memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
  465. vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
  466. vcpu->svm->cr0 = 0x00000010;
  467. vcpu->svm->asid_generation = 0;
  468. memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
  469. init_vmcb(vcpu->svm->vmcb);
  470. fx_init(vcpu);
  471. return 0;
  472. out2:
  473. kfree(vcpu->svm);
  474. out1:
  475. return r;
  476. }
  477. static void svm_free_vcpu(struct kvm_vcpu *vcpu)
  478. {
  479. if (!vcpu->svm)
  480. return;
  481. if (vcpu->svm->vmcb)
  482. __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
  483. kfree(vcpu->svm);
  484. }
  485. static struct kvm_vcpu *svm_vcpu_load(struct kvm_vcpu *vcpu)
  486. {
  487. get_cpu();
  488. return vcpu;
  489. }
  490. static void svm_vcpu_put(struct kvm_vcpu *vcpu)
  491. {
  492. put_cpu();
  493. }
  494. static void svm_cache_regs(struct kvm_vcpu *vcpu)
  495. {
  496. vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
  497. vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
  498. vcpu->rip = vcpu->svm->vmcb->save.rip;
  499. }
  500. static void svm_decache_regs(struct kvm_vcpu *vcpu)
  501. {
  502. vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
  503. vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
  504. vcpu->svm->vmcb->save.rip = vcpu->rip;
  505. }
  506. static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
  507. {
  508. return vcpu->svm->vmcb->save.rflags;
  509. }
  510. static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
  511. {
  512. vcpu->svm->vmcb->save.rflags = rflags;
  513. }
  514. static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
  515. {
  516. struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
  517. switch (seg) {
  518. case VCPU_SREG_CS: return &save->cs;
  519. case VCPU_SREG_DS: return &save->ds;
  520. case VCPU_SREG_ES: return &save->es;
  521. case VCPU_SREG_FS: return &save->fs;
  522. case VCPU_SREG_GS: return &save->gs;
  523. case VCPU_SREG_SS: return &save->ss;
  524. case VCPU_SREG_TR: return &save->tr;
  525. case VCPU_SREG_LDTR: return &save->ldtr;
  526. }
  527. BUG();
  528. return 0;
  529. }
  530. static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
  531. {
  532. struct vmcb_seg *s = svm_seg(vcpu, seg);
  533. return s->base;
  534. }
  535. static void svm_get_segment(struct kvm_vcpu *vcpu,
  536. struct kvm_segment *var, int seg)
  537. {
  538. struct vmcb_seg *s = svm_seg(vcpu, seg);
  539. var->base = s->base;
  540. var->limit = s->limit;
  541. var->selector = s->selector;
  542. var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
  543. var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
  544. var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
  545. var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
  546. var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
  547. var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
  548. var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
  549. var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
  550. var->unusable = !var->present;
  551. }
  552. static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
  553. {
  554. struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
  555. *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
  556. *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
  557. }
  558. static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
  559. {
  560. dt->limit = vcpu->svm->vmcb->save.ldtr.limit;
  561. dt->base = vcpu->svm->vmcb->save.ldtr.base;
  562. }
  563. static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
  564. {
  565. vcpu->svm->vmcb->save.ldtr.limit = dt->limit;
  566. vcpu->svm->vmcb->save.ldtr.base = dt->base ;
  567. }
  568. static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
  569. {
  570. dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
  571. dt->base = vcpu->svm->vmcb->save.gdtr.base;
  572. }
  573. static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
  574. {
  575. vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
  576. vcpu->svm->vmcb->save.gdtr.base = dt->base ;
  577. }
  578. static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
  579. {
  580. #ifdef CONFIG_X86_64
  581. if (vcpu->shadow_efer & KVM_EFER_LME) {
  582. if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
  583. vcpu->shadow_efer |= KVM_EFER_LMA;
  584. vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
  585. }
  586. if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
  587. vcpu->shadow_efer &= ~KVM_EFER_LMA;
  588. vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
  589. }
  590. }
  591. #endif
  592. vcpu->svm->cr0 = cr0;
  593. vcpu->svm->vmcb->save.cr0 = cr0 | CR0_PG_MASK;
  594. vcpu->cr0 = cr0;
  595. }
  596. static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
  597. {
  598. vcpu->cr4 = cr4;
  599. vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
  600. }
  601. static void svm_set_segment(struct kvm_vcpu *vcpu,
  602. struct kvm_segment *var, int seg)
  603. {
  604. struct vmcb_seg *s = svm_seg(vcpu, seg);
  605. s->base = var->base;
  606. s->limit = var->limit;
  607. s->selector = var->selector;
  608. if (var->unusable)
  609. s->attrib = 0;
  610. else {
  611. s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
  612. s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
  613. s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
  614. s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
  615. s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
  616. s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
  617. s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
  618. s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
  619. }
  620. if (seg == VCPU_SREG_CS)
  621. vcpu->svm->vmcb->save.cpl
  622. = (vcpu->svm->vmcb->save.cs.attrib
  623. >> SVM_SELECTOR_DPL_SHIFT) & 3;
  624. }
  625. /* FIXME:
  626. vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
  627. vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
  628. */
  629. static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
  630. {
  631. return -EOPNOTSUPP;
  632. }
  633. static void load_host_msrs(struct kvm_vcpu *vcpu)
  634. {
  635. int i;
  636. for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
  637. wrmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
  638. }
  639. static void save_host_msrs(struct kvm_vcpu *vcpu)
  640. {
  641. int i;
  642. for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
  643. rdmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
  644. }
  645. static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
  646. {
  647. if (svm_data->next_asid > svm_data->max_asid) {
  648. ++svm_data->asid_generation;
  649. svm_data->next_asid = 1;
  650. vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
  651. }
  652. vcpu->cpu = svm_data->cpu;
  653. vcpu->svm->asid_generation = svm_data->asid_generation;
  654. vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
  655. }
  656. static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
  657. {
  658. invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
  659. }
  660. static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
  661. {
  662. return vcpu->svm->db_regs[dr];
  663. }
  664. static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
  665. int *exception)
  666. {
  667. *exception = 0;
  668. if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
  669. vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
  670. vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
  671. *exception = DB_VECTOR;
  672. return;
  673. }
  674. switch (dr) {
  675. case 0 ... 3:
  676. vcpu->svm->db_regs[dr] = value;
  677. return;
  678. case 4 ... 5:
  679. if (vcpu->cr4 & CR4_DE_MASK) {
  680. *exception = UD_VECTOR;
  681. return;
  682. }
  683. case 7: {
  684. if (value & ~((1ULL << 32) - 1)) {
  685. *exception = GP_VECTOR;
  686. return;
  687. }
  688. vcpu->svm->vmcb->save.dr7 = value;
  689. return;
  690. }
  691. default:
  692. printk(KERN_DEBUG "%s: unexpected dr %u\n",
  693. __FUNCTION__, dr);
  694. *exception = UD_VECTOR;
  695. return;
  696. }
  697. }
  698. static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  699. {
  700. u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
  701. u64 fault_address;
  702. u32 error_code;
  703. enum emulation_result er;
  704. if (is_external_interrupt(exit_int_info))
  705. push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
  706. spin_lock(&vcpu->kvm->lock);
  707. fault_address = vcpu->svm->vmcb->control.exit_info_2;
  708. error_code = vcpu->svm->vmcb->control.exit_info_1;
  709. if (!vcpu->mmu.page_fault(vcpu, fault_address, error_code)) {
  710. spin_unlock(&vcpu->kvm->lock);
  711. return 1;
  712. }
  713. er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
  714. spin_unlock(&vcpu->kvm->lock);
  715. switch (er) {
  716. case EMULATE_DONE:
  717. return 1;
  718. case EMULATE_DO_MMIO:
  719. ++kvm_stat.mmio_exits;
  720. kvm_run->exit_reason = KVM_EXIT_MMIO;
  721. return 0;
  722. case EMULATE_FAIL:
  723. vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
  724. break;
  725. default:
  726. BUG();
  727. }
  728. kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
  729. return 0;
  730. }
  731. static int io_get_override(struct kvm_vcpu *vcpu,
  732. struct vmcb_seg **seg,
  733. int *addr_override)
  734. {
  735. u8 inst[MAX_INST_SIZE];
  736. unsigned ins_length;
  737. gva_t rip;
  738. int i;
  739. rip = vcpu->svm->vmcb->save.rip;
  740. ins_length = vcpu->svm->next_rip - rip;
  741. rip += vcpu->svm->vmcb->save.cs.base;
  742. if (ins_length > MAX_INST_SIZE)
  743. printk(KERN_DEBUG
  744. "%s: inst length err, cs base 0x%llx rip 0x%llx "
  745. "next rip 0x%llx ins_length %u\n",
  746. __FUNCTION__,
  747. vcpu->svm->vmcb->save.cs.base,
  748. vcpu->svm->vmcb->save.rip,
  749. vcpu->svm->vmcb->control.exit_info_2,
  750. ins_length);
  751. if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
  752. /* #PF */
  753. return 0;
  754. *addr_override = 0;
  755. *seg = 0;
  756. for (i = 0; i < ins_length; i++)
  757. switch (inst[i]) {
  758. case 0xf0:
  759. case 0xf2:
  760. case 0xf3:
  761. case 0x66:
  762. continue;
  763. case 0x67:
  764. *addr_override = 1;
  765. continue;
  766. case 0x2e:
  767. *seg = &vcpu->svm->vmcb->save.cs;
  768. continue;
  769. case 0x36:
  770. *seg = &vcpu->svm->vmcb->save.ss;
  771. continue;
  772. case 0x3e:
  773. *seg = &vcpu->svm->vmcb->save.ds;
  774. continue;
  775. case 0x26:
  776. *seg = &vcpu->svm->vmcb->save.es;
  777. continue;
  778. case 0x64:
  779. *seg = &vcpu->svm->vmcb->save.fs;
  780. continue;
  781. case 0x65:
  782. *seg = &vcpu->svm->vmcb->save.gs;
  783. continue;
  784. default:
  785. return 1;
  786. }
  787. printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
  788. return 0;
  789. }
  790. static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, u64 *address)
  791. {
  792. unsigned long addr_mask;
  793. unsigned long *reg;
  794. struct vmcb_seg *seg;
  795. int addr_override;
  796. struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
  797. u16 cs_attrib = save_area->cs.attrib;
  798. unsigned addr_size = get_addr_size(vcpu);
  799. if (!io_get_override(vcpu, &seg, &addr_override))
  800. return 0;
  801. if (addr_override)
  802. addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
  803. if (ins) {
  804. reg = &vcpu->regs[VCPU_REGS_RDI];
  805. seg = &vcpu->svm->vmcb->save.es;
  806. } else {
  807. reg = &vcpu->regs[VCPU_REGS_RSI];
  808. seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
  809. }
  810. addr_mask = ~0ULL >> (64 - (addr_size * 8));
  811. if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
  812. !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
  813. *address = (*reg & addr_mask);
  814. return addr_mask;
  815. }
  816. if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
  817. svm_inject_gp(vcpu, 0);
  818. return 0;
  819. }
  820. *address = (*reg & addr_mask) + seg->base;
  821. return addr_mask;
  822. }
  823. static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  824. {
  825. u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
  826. int _in = io_info & SVM_IOIO_TYPE_MASK;
  827. ++kvm_stat.io_exits;
  828. vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
  829. kvm_run->exit_reason = KVM_EXIT_IO;
  830. kvm_run->io.port = io_info >> 16;
  831. kvm_run->io.direction = (_in) ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
  832. kvm_run->io.size = ((io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT);
  833. kvm_run->io.string = (io_info & SVM_IOIO_STR_MASK) != 0;
  834. kvm_run->io.rep = (io_info & SVM_IOIO_REP_MASK) != 0;
  835. if (kvm_run->io.string) {
  836. unsigned addr_mask;
  837. addr_mask = io_adress(vcpu, _in, &kvm_run->io.address);
  838. if (!addr_mask) {
  839. printk(KERN_DEBUG "%s: get io address failed\n", __FUNCTION__);
  840. return 1;
  841. }
  842. if (kvm_run->io.rep) {
  843. kvm_run->io.count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
  844. kvm_run->io.string_down = (vcpu->svm->vmcb->save.rflags
  845. & X86_EFLAGS_DF) != 0;
  846. }
  847. } else {
  848. kvm_run->io.value = vcpu->svm->vmcb->save.rax;
  849. }
  850. return 0;
  851. }
  852. static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  853. {
  854. return 1;
  855. }
  856. static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  857. {
  858. vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
  859. skip_emulated_instruction(vcpu);
  860. if (vcpu->irq_summary && (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF))
  861. return 1;
  862. kvm_run->exit_reason = KVM_EXIT_HLT;
  863. return 0;
  864. }
  865. static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  866. {
  867. inject_ud(vcpu);
  868. return 1;
  869. }
  870. static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  871. {
  872. printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
  873. kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
  874. return 0;
  875. }
  876. static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  877. {
  878. vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
  879. kvm_run->exit_reason = KVM_EXIT_CPUID;
  880. return 0;
  881. }
  882. static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  883. {
  884. if (emulate_instruction(vcpu, 0, 0, 0) != EMULATE_DONE)
  885. printk(KERN_ERR "%s: failed\n", __FUNCTION__);
  886. return 1;
  887. }
  888. static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
  889. {
  890. switch (ecx) {
  891. case MSR_IA32_P5_MC_ADDR:
  892. case MSR_IA32_P5_MC_TYPE:
  893. case MSR_IA32_MC0_CTL:
  894. case MSR_IA32_MCG_STATUS:
  895. case MSR_IA32_MCG_CAP:
  896. case MSR_IA32_MC0_MISC:
  897. case MSR_IA32_MC0_MISC+4:
  898. case MSR_IA32_MC0_MISC+8:
  899. case MSR_IA32_MC0_MISC+12:
  900. case MSR_IA32_MC0_MISC+16:
  901. case MSR_IA32_UCODE_REV:
  902. /* MTRR registers */
  903. case 0xfe:
  904. case 0x200 ... 0x2ff:
  905. *data = 0;
  906. break;
  907. case MSR_IA32_TIME_STAMP_COUNTER: {
  908. u64 tsc;
  909. rdtscll(tsc);
  910. *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
  911. break;
  912. }
  913. case MSR_EFER:
  914. *data = vcpu->shadow_efer;
  915. break;
  916. case MSR_IA32_APICBASE:
  917. *data = vcpu->apic_base;
  918. break;
  919. case MSR_K6_STAR:
  920. *data = vcpu->svm->vmcb->save.star;
  921. break;
  922. #ifdef CONFIG_X86_64
  923. case MSR_LSTAR:
  924. *data = vcpu->svm->vmcb->save.lstar;
  925. break;
  926. case MSR_CSTAR:
  927. *data = vcpu->svm->vmcb->save.cstar;
  928. break;
  929. case MSR_KERNEL_GS_BASE:
  930. *data = vcpu->svm->vmcb->save.kernel_gs_base;
  931. break;
  932. case MSR_SYSCALL_MASK:
  933. *data = vcpu->svm->vmcb->save.sfmask;
  934. break;
  935. #endif
  936. case MSR_IA32_SYSENTER_CS:
  937. *data = vcpu->svm->vmcb->save.sysenter_cs;
  938. break;
  939. case MSR_IA32_SYSENTER_EIP:
  940. *data = vcpu->svm->vmcb->save.sysenter_eip;
  941. break;
  942. case MSR_IA32_SYSENTER_ESP:
  943. *data = vcpu->svm->vmcb->save.sysenter_esp;
  944. break;
  945. default:
  946. printk(KERN_ERR "kvm: unhandled rdmsr: 0x%x\n", ecx);
  947. return 1;
  948. }
  949. return 0;
  950. }
  951. static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  952. {
  953. u32 ecx = vcpu->regs[VCPU_REGS_RCX];
  954. u64 data;
  955. if (svm_get_msr(vcpu, ecx, &data))
  956. svm_inject_gp(vcpu, 0);
  957. else {
  958. vcpu->svm->vmcb->save.rax = data & 0xffffffff;
  959. vcpu->regs[VCPU_REGS_RDX] = data >> 32;
  960. vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
  961. skip_emulated_instruction(vcpu);
  962. }
  963. return 1;
  964. }
  965. static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
  966. {
  967. switch (ecx) {
  968. #ifdef CONFIG_X86_64
  969. case MSR_EFER:
  970. set_efer(vcpu, data);
  971. break;
  972. #endif
  973. case MSR_IA32_MC0_STATUS:
  974. printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
  975. , __FUNCTION__, data);
  976. break;
  977. case MSR_IA32_TIME_STAMP_COUNTER: {
  978. u64 tsc;
  979. rdtscll(tsc);
  980. vcpu->svm->vmcb->control.tsc_offset = data - tsc;
  981. break;
  982. }
  983. case MSR_IA32_UCODE_REV:
  984. case MSR_IA32_UCODE_WRITE:
  985. case 0x200 ... 0x2ff: /* MTRRs */
  986. break;
  987. case MSR_IA32_APICBASE:
  988. vcpu->apic_base = data;
  989. break;
  990. case MSR_K6_STAR:
  991. vcpu->svm->vmcb->save.star = data;
  992. break;
  993. #ifdef CONFIG_X86_64_
  994. case MSR_LSTAR:
  995. vcpu->svm->vmcb->save.lstar = data;
  996. break;
  997. case MSR_CSTAR:
  998. vcpu->svm->vmcb->save.cstar = data;
  999. break;
  1000. case MSR_KERNEL_GS_BASE:
  1001. vcpu->svm->vmcb->save.kernel_gs_base = data;
  1002. break;
  1003. case MSR_SYSCALL_MASK:
  1004. vcpu->svm->vmcb->save.sfmask = data;
  1005. break;
  1006. #endif
  1007. case MSR_IA32_SYSENTER_CS:
  1008. vcpu->svm->vmcb->save.sysenter_cs = data;
  1009. break;
  1010. case MSR_IA32_SYSENTER_EIP:
  1011. vcpu->svm->vmcb->save.sysenter_eip = data;
  1012. break;
  1013. case MSR_IA32_SYSENTER_ESP:
  1014. vcpu->svm->vmcb->save.sysenter_esp = data;
  1015. break;
  1016. default:
  1017. printk(KERN_ERR "kvm: unhandled wrmsr: %x\n", ecx);
  1018. return 1;
  1019. }
  1020. return 0;
  1021. }
  1022. static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  1023. {
  1024. u32 ecx = vcpu->regs[VCPU_REGS_RCX];
  1025. u64 data = (vcpu->svm->vmcb->save.rax & -1u)
  1026. | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
  1027. vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
  1028. if (svm_set_msr(vcpu, ecx, data))
  1029. svm_inject_gp(vcpu, 0);
  1030. else
  1031. skip_emulated_instruction(vcpu);
  1032. return 1;
  1033. }
  1034. static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  1035. {
  1036. if (vcpu->svm->vmcb->control.exit_info_1)
  1037. return wrmsr_interception(vcpu, kvm_run);
  1038. else
  1039. return rdmsr_interception(vcpu, kvm_run);
  1040. }
  1041. static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
  1042. struct kvm_run *kvm_run) = {
  1043. [SVM_EXIT_READ_CR0] = emulate_on_interception,
  1044. [SVM_EXIT_READ_CR3] = emulate_on_interception,
  1045. [SVM_EXIT_READ_CR4] = emulate_on_interception,
  1046. /* for now: */
  1047. [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
  1048. [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
  1049. [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
  1050. [SVM_EXIT_READ_DR0] = emulate_on_interception,
  1051. [SVM_EXIT_READ_DR1] = emulate_on_interception,
  1052. [SVM_EXIT_READ_DR2] = emulate_on_interception,
  1053. [SVM_EXIT_READ_DR3] = emulate_on_interception,
  1054. [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
  1055. [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
  1056. [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
  1057. [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
  1058. [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
  1059. [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
  1060. [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
  1061. [SVM_EXIT_INTR] = nop_on_interception,
  1062. [SVM_EXIT_NMI] = nop_on_interception,
  1063. [SVM_EXIT_SMI] = nop_on_interception,
  1064. [SVM_EXIT_INIT] = nop_on_interception,
  1065. /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
  1066. [SVM_EXIT_CPUID] = cpuid_interception,
  1067. [SVM_EXIT_HLT] = halt_interception,
  1068. [SVM_EXIT_INVLPG] = emulate_on_interception,
  1069. [SVM_EXIT_INVLPGA] = invalid_op_interception,
  1070. [SVM_EXIT_IOIO] = io_interception,
  1071. [SVM_EXIT_MSR] = msr_interception,
  1072. [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
  1073. [SVM_EXIT_VMRUN] = invalid_op_interception,
  1074. [SVM_EXIT_VMMCALL] = invalid_op_interception,
  1075. [SVM_EXIT_VMLOAD] = invalid_op_interception,
  1076. [SVM_EXIT_VMSAVE] = invalid_op_interception,
  1077. [SVM_EXIT_STGI] = invalid_op_interception,
  1078. [SVM_EXIT_CLGI] = invalid_op_interception,
  1079. [SVM_EXIT_SKINIT] = invalid_op_interception,
  1080. };
  1081. static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  1082. {
  1083. u32 exit_code = vcpu->svm->vmcb->control.exit_code;
  1084. kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
  1085. if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
  1086. exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
  1087. printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
  1088. "exit_code 0x%x\n",
  1089. __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
  1090. exit_code);
  1091. if (exit_code >= sizeof(svm_exit_handlers) / sizeof(*svm_exit_handlers)
  1092. || svm_exit_handlers[exit_code] == 0) {
  1093. kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
  1094. printk(KERN_ERR "%s: 0x%x @ 0x%llx cr0 0x%lx rflags 0x%llx\n",
  1095. __FUNCTION__,
  1096. exit_code,
  1097. vcpu->svm->vmcb->save.rip,
  1098. vcpu->cr0,
  1099. vcpu->svm->vmcb->save.rflags);
  1100. return 0;
  1101. }
  1102. return svm_exit_handlers[exit_code](vcpu, kvm_run);
  1103. }
  1104. static void reload_tss(struct kvm_vcpu *vcpu)
  1105. {
  1106. int cpu = raw_smp_processor_id();
  1107. struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
  1108. svm_data->tss_desc->type = 9; //available 32/64-bit TSS
  1109. load_TR_desc();
  1110. }
  1111. static void pre_svm_run(struct kvm_vcpu *vcpu)
  1112. {
  1113. int cpu = raw_smp_processor_id();
  1114. struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
  1115. vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
  1116. if (vcpu->cpu != cpu ||
  1117. vcpu->svm->asid_generation != svm_data->asid_generation)
  1118. new_asid(vcpu, svm_data);
  1119. }
  1120. static inline void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
  1121. {
  1122. struct vmcb_control_area *control;
  1123. if (!vcpu->irq_summary)
  1124. return;
  1125. control = &vcpu->svm->vmcb->control;
  1126. control->int_vector = pop_irq(vcpu);
  1127. control->int_ctl &= ~V_INTR_PRIO_MASK;
  1128. control->int_ctl |= V_IRQ_MASK |
  1129. ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
  1130. }
  1131. static void kvm_reput_irq(struct kvm_vcpu *vcpu)
  1132. {
  1133. struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
  1134. if (control->int_ctl & V_IRQ_MASK) {
  1135. control->int_ctl &= ~V_IRQ_MASK;
  1136. push_irq(vcpu, control->int_vector);
  1137. }
  1138. }
  1139. static void save_db_regs(unsigned long *db_regs)
  1140. {
  1141. asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
  1142. asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
  1143. asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
  1144. asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
  1145. }
  1146. static void load_db_regs(unsigned long *db_regs)
  1147. {
  1148. asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
  1149. asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
  1150. asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
  1151. asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
  1152. }
  1153. static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  1154. {
  1155. u16 fs_selector;
  1156. u16 gs_selector;
  1157. u16 ldt_selector;
  1158. again:
  1159. kvm_try_inject_irq(vcpu);
  1160. clgi();
  1161. pre_svm_run(vcpu);
  1162. save_host_msrs(vcpu);
  1163. fs_selector = read_fs();
  1164. gs_selector = read_gs();
  1165. ldt_selector = read_ldt();
  1166. vcpu->svm->host_cr2 = kvm_read_cr2();
  1167. vcpu->svm->host_dr6 = read_dr6();
  1168. vcpu->svm->host_dr7 = read_dr7();
  1169. vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
  1170. if (vcpu->svm->vmcb->save.dr7 & 0xff) {
  1171. write_dr7(0);
  1172. save_db_regs(vcpu->svm->host_db_regs);
  1173. load_db_regs(vcpu->svm->db_regs);
  1174. }
  1175. fx_save(vcpu->host_fx_image);
  1176. fx_restore(vcpu->guest_fx_image);
  1177. asm volatile (
  1178. #ifdef CONFIG_X86_64
  1179. "push %%rbx; push %%rcx; push %%rdx;"
  1180. "push %%rsi; push %%rdi; push %%rbp;"
  1181. "push %%r8; push %%r9; push %%r10; push %%r11;"
  1182. "push %%r12; push %%r13; push %%r14; push %%r15;"
  1183. #else
  1184. "push %%ebx; push %%ecx; push %%edx;"
  1185. "push %%esi; push %%edi; push %%ebp;"
  1186. #endif
  1187. #ifdef CONFIG_X86_64
  1188. "mov %c[rbx](%[vcpu]), %%rbx \n\t"
  1189. "mov %c[rcx](%[vcpu]), %%rcx \n\t"
  1190. "mov %c[rdx](%[vcpu]), %%rdx \n\t"
  1191. "mov %c[rsi](%[vcpu]), %%rsi \n\t"
  1192. "mov %c[rdi](%[vcpu]), %%rdi \n\t"
  1193. "mov %c[rbp](%[vcpu]), %%rbp \n\t"
  1194. "mov %c[r8](%[vcpu]), %%r8 \n\t"
  1195. "mov %c[r9](%[vcpu]), %%r9 \n\t"
  1196. "mov %c[r10](%[vcpu]), %%r10 \n\t"
  1197. "mov %c[r11](%[vcpu]), %%r11 \n\t"
  1198. "mov %c[r12](%[vcpu]), %%r12 \n\t"
  1199. "mov %c[r13](%[vcpu]), %%r13 \n\t"
  1200. "mov %c[r14](%[vcpu]), %%r14 \n\t"
  1201. "mov %c[r15](%[vcpu]), %%r15 \n\t"
  1202. #else
  1203. "mov %c[rbx](%[vcpu]), %%ebx \n\t"
  1204. "mov %c[rcx](%[vcpu]), %%ecx \n\t"
  1205. "mov %c[rdx](%[vcpu]), %%edx \n\t"
  1206. "mov %c[rsi](%[vcpu]), %%esi \n\t"
  1207. "mov %c[rdi](%[vcpu]), %%edi \n\t"
  1208. "mov %c[rbp](%[vcpu]), %%ebp \n\t"
  1209. #endif
  1210. #ifdef CONFIG_X86_64
  1211. /* Enter guest mode */
  1212. "push %%rax \n\t"
  1213. "mov %c[svm](%[vcpu]), %%rax \n\t"
  1214. "mov %c[vmcb](%%rax), %%rax \n\t"
  1215. SVM_VMLOAD "\n\t"
  1216. SVM_VMRUN "\n\t"
  1217. SVM_VMSAVE "\n\t"
  1218. "pop %%rax \n\t"
  1219. #else
  1220. /* Enter guest mode */
  1221. "push %%eax \n\t"
  1222. "mov %c[svm](%[vcpu]), %%eax \n\t"
  1223. "mov %c[vmcb](%%eax), %%eax \n\t"
  1224. SVM_VMLOAD "\n\t"
  1225. SVM_VMRUN "\n\t"
  1226. SVM_VMSAVE "\n\t"
  1227. "pop %%eax \n\t"
  1228. #endif
  1229. /* Save guest registers, load host registers */
  1230. #ifdef CONFIG_X86_64
  1231. "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
  1232. "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
  1233. "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
  1234. "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
  1235. "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
  1236. "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
  1237. "mov %%r8, %c[r8](%[vcpu]) \n\t"
  1238. "mov %%r9, %c[r9](%[vcpu]) \n\t"
  1239. "mov %%r10, %c[r10](%[vcpu]) \n\t"
  1240. "mov %%r11, %c[r11](%[vcpu]) \n\t"
  1241. "mov %%r12, %c[r12](%[vcpu]) \n\t"
  1242. "mov %%r13, %c[r13](%[vcpu]) \n\t"
  1243. "mov %%r14, %c[r14](%[vcpu]) \n\t"
  1244. "mov %%r15, %c[r15](%[vcpu]) \n\t"
  1245. "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
  1246. "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
  1247. "pop %%rbp; pop %%rdi; pop %%rsi;"
  1248. "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
  1249. #else
  1250. "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
  1251. "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
  1252. "mov %%edx, %c[rdx](%[vcpu]) \n\t"
  1253. "mov %%esi, %c[rsi](%[vcpu]) \n\t"
  1254. "mov %%edi, %c[rdi](%[vcpu]) \n\t"
  1255. "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
  1256. "pop %%ebp; pop %%edi; pop %%esi;"
  1257. "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
  1258. #endif
  1259. :
  1260. : [vcpu]"a"(vcpu),
  1261. [svm]"i"(offsetof(struct kvm_vcpu, svm)),
  1262. [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
  1263. [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
  1264. [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
  1265. [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
  1266. [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
  1267. [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
  1268. [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
  1269. #ifdef CONFIG_X86_64
  1270. ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
  1271. [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
  1272. [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
  1273. [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
  1274. [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
  1275. [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
  1276. [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
  1277. [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
  1278. #endif
  1279. : "cc", "memory" );
  1280. fx_save(vcpu->guest_fx_image);
  1281. fx_restore(vcpu->host_fx_image);
  1282. if ((vcpu->svm->vmcb->save.dr7 & 0xff))
  1283. load_db_regs(vcpu->svm->host_db_regs);
  1284. vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
  1285. write_dr6(vcpu->svm->host_dr6);
  1286. write_dr7(vcpu->svm->host_dr7);
  1287. kvm_write_cr2(vcpu->svm->host_cr2);
  1288. load_fs(fs_selector);
  1289. load_gs(gs_selector);
  1290. load_ldt(ldt_selector);
  1291. load_host_msrs(vcpu);
  1292. reload_tss(vcpu);
  1293. stgi();
  1294. kvm_reput_irq(vcpu);
  1295. vcpu->svm->next_rip = 0;
  1296. if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
  1297. kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
  1298. kvm_run->exit_reason = vcpu->svm->vmcb->control.exit_code;
  1299. return 0;
  1300. }
  1301. if (handle_exit(vcpu, kvm_run)) {
  1302. if (signal_pending(current)) {
  1303. ++kvm_stat.signal_exits;
  1304. return -EINTR;
  1305. }
  1306. kvm_resched(vcpu);
  1307. goto again;
  1308. }
  1309. return 0;
  1310. }
  1311. static void svm_flush_tlb(struct kvm_vcpu *vcpu)
  1312. {
  1313. force_new_asid(vcpu);
  1314. }
  1315. static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
  1316. {
  1317. vcpu->svm->vmcb->save.cr3 = root;
  1318. force_new_asid(vcpu);
  1319. }
  1320. static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
  1321. unsigned long addr,
  1322. uint32_t err_code)
  1323. {
  1324. uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
  1325. ++kvm_stat.pf_guest;
  1326. if (is_page_fault(exit_int_info)) {
  1327. vcpu->svm->vmcb->control.event_inj_err = 0;
  1328. vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
  1329. SVM_EVTINJ_VALID_ERR |
  1330. SVM_EVTINJ_TYPE_EXEPT |
  1331. DF_VECTOR;
  1332. return;
  1333. }
  1334. vcpu->cr2 = addr;
  1335. vcpu->svm->vmcb->save.cr2 = addr;
  1336. vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
  1337. SVM_EVTINJ_VALID_ERR |
  1338. SVM_EVTINJ_TYPE_EXEPT |
  1339. PF_VECTOR;
  1340. vcpu->svm->vmcb->control.event_inj_err = err_code;
  1341. }
  1342. static int is_disabled(void)
  1343. {
  1344. return 0;
  1345. }
  1346. static struct kvm_arch_ops svm_arch_ops = {
  1347. .cpu_has_kvm_support = has_svm,
  1348. .disabled_by_bios = is_disabled,
  1349. .hardware_setup = svm_hardware_setup,
  1350. .hardware_unsetup = svm_hardware_unsetup,
  1351. .hardware_enable = svm_hardware_enable,
  1352. .hardware_disable = svm_hardware_disable,
  1353. .vcpu_create = svm_create_vcpu,
  1354. .vcpu_free = svm_free_vcpu,
  1355. .vcpu_load = svm_vcpu_load,
  1356. .vcpu_put = svm_vcpu_put,
  1357. .set_guest_debug = svm_guest_debug,
  1358. .get_msr = svm_get_msr,
  1359. .set_msr = svm_set_msr,
  1360. .get_segment_base = svm_get_segment_base,
  1361. .get_segment = svm_get_segment,
  1362. .set_segment = svm_set_segment,
  1363. .is_long_mode = svm_is_long_mode,
  1364. .get_cs_db_l_bits = svm_get_cs_db_l_bits,
  1365. .set_cr0 = svm_set_cr0,
  1366. .set_cr0_no_modeswitch = svm_set_cr0,
  1367. .set_cr3 = svm_set_cr3,
  1368. .set_cr4 = svm_set_cr4,
  1369. .set_efer = svm_set_efer,
  1370. .get_idt = svm_get_idt,
  1371. .set_idt = svm_set_idt,
  1372. .get_gdt = svm_get_gdt,
  1373. .set_gdt = svm_set_gdt,
  1374. .get_dr = svm_get_dr,
  1375. .set_dr = svm_set_dr,
  1376. .cache_regs = svm_cache_regs,
  1377. .decache_regs = svm_decache_regs,
  1378. .get_rflags = svm_get_rflags,
  1379. .set_rflags = svm_set_rflags,
  1380. .invlpg = svm_invlpg,
  1381. .tlb_flush = svm_flush_tlb,
  1382. .inject_page_fault = svm_inject_page_fault,
  1383. .inject_gp = svm_inject_gp,
  1384. .run = svm_vcpu_run,
  1385. .skip_emulated_instruction = skip_emulated_instruction,
  1386. .vcpu_setup = svm_vcpu_setup,
  1387. };
  1388. static int __init svm_init(void)
  1389. {
  1390. return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
  1391. }
  1392. static void __exit svm_exit(void)
  1393. {
  1394. kvm_exit_arch();
  1395. }
  1396. module_init(svm_init)
  1397. module_exit(svm_exit)