fimc-lite.c 43 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/module.h>
  19. #include <linux/types.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-ioctl.h>
  26. #include <media/v4l2-mem2mem.h>
  27. #include <media/videobuf2-core.h>
  28. #include <media/videobuf2-dma-contig.h>
  29. #include <media/s5p_fimc.h>
  30. #include "fimc-mdevice.h"
  31. #include "fimc-core.h"
  32. #include "fimc-lite.h"
  33. #include "fimc-lite-reg.h"
  34. static int debug;
  35. module_param(debug, int, 0644);
  36. static const struct fimc_fmt fimc_lite_formats[] = {
  37. {
  38. .name = "YUV 4:2:2 packed, YCbYCr",
  39. .fourcc = V4L2_PIX_FMT_YUYV,
  40. .depth = { 16 },
  41. .color = FIMC_FMT_YCBYCR422,
  42. .memplanes = 1,
  43. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  44. }, {
  45. .name = "YUV 4:2:2 packed, CbYCrY",
  46. .fourcc = V4L2_PIX_FMT_UYVY,
  47. .depth = { 16 },
  48. .color = FIMC_FMT_CBYCRY422,
  49. .memplanes = 1,
  50. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  51. }, {
  52. .name = "YUV 4:2:2 packed, CrYCbY",
  53. .fourcc = V4L2_PIX_FMT_VYUY,
  54. .depth = { 16 },
  55. .color = FIMC_FMT_CRYCBY422,
  56. .memplanes = 1,
  57. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  58. }, {
  59. .name = "YUV 4:2:2 packed, YCrYCb",
  60. .fourcc = V4L2_PIX_FMT_YVYU,
  61. .depth = { 16 },
  62. .color = FIMC_FMT_YCRYCB422,
  63. .memplanes = 1,
  64. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  65. }, {
  66. .name = "RAW8 (GRBG)",
  67. .fourcc = V4L2_PIX_FMT_SGRBG8,
  68. .depth = { 8 },
  69. .color = FIMC_FMT_RAW8,
  70. .memplanes = 1,
  71. .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
  72. }, {
  73. .name = "RAW10 (GRBG)",
  74. .fourcc = V4L2_PIX_FMT_SGRBG10,
  75. .depth = { 10 },
  76. .color = FIMC_FMT_RAW10,
  77. .memplanes = 1,
  78. .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
  79. }, {
  80. .name = "RAW12 (GRBG)",
  81. .fourcc = V4L2_PIX_FMT_SGRBG12,
  82. .depth = { 12 },
  83. .color = FIMC_FMT_RAW12,
  84. .memplanes = 1,
  85. .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
  86. },
  87. };
  88. /**
  89. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  90. * @pixelformat: fourcc to match, ignored if null
  91. * @mbus_code: media bus code to match, ignored if null
  92. * @index: index to the fimc_lite_formats array, ignored if negative
  93. */
  94. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  95. const u32 *mbus_code, int index)
  96. {
  97. const struct fimc_fmt *fmt, *def_fmt = NULL;
  98. unsigned int i;
  99. int id = 0;
  100. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  101. return NULL;
  102. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  103. fmt = &fimc_lite_formats[i];
  104. if (pixelformat && fmt->fourcc == *pixelformat)
  105. return fmt;
  106. if (mbus_code && fmt->mbus_code == *mbus_code)
  107. return fmt;
  108. if (index == id)
  109. def_fmt = fmt;
  110. id++;
  111. }
  112. return def_fmt;
  113. }
  114. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  115. {
  116. struct fimc_pipeline *pipeline = &fimc->pipeline;
  117. struct v4l2_subdev *sensor;
  118. struct fimc_sensor_info *si;
  119. unsigned long flags;
  120. sensor = isp_output ? fimc->sensor : pipeline->subdevs[IDX_SENSOR];
  121. if (sensor == NULL)
  122. return -ENXIO;
  123. if (fimc->fmt == NULL)
  124. return -EINVAL;
  125. /* Get sensor configuration data from the sensor subdev */
  126. si = v4l2_get_subdev_hostdata(sensor);
  127. spin_lock_irqsave(&fimc->slock, flags);
  128. flite_hw_set_camera_bus(fimc, &si->pdata);
  129. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  130. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  131. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  132. flite_hw_set_interrupt_mask(fimc);
  133. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  134. if (debug > 0)
  135. flite_hw_dump_regs(fimc, __func__);
  136. spin_unlock_irqrestore(&fimc->slock, flags);
  137. return 0;
  138. }
  139. /*
  140. * Reinitialize the driver so it is ready to start the streaming again.
  141. * Set fimc->state to indicate stream off and the hardware shut down state.
  142. * If not suspending (@suspend is false), return any buffers to videobuf2.
  143. * Otherwise put any owned buffers onto the pending buffers queue, so they
  144. * can be re-spun when the device is being resumed. Also perform FIMC
  145. * software reset and disable streaming on the whole pipeline if required.
  146. */
  147. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  148. {
  149. struct flite_buffer *buf;
  150. unsigned long flags;
  151. bool streaming;
  152. spin_lock_irqsave(&fimc->slock, flags);
  153. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  154. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  155. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  156. if (suspend)
  157. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  158. else
  159. fimc->state &= ~(1 << ST_FLITE_PENDING |
  160. 1 << ST_FLITE_SUSPENDED);
  161. /* Release unused buffers */
  162. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  163. buf = fimc_lite_pending_queue_pop(fimc);
  164. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  165. }
  166. /* If suspending put unused buffers onto pending queue */
  167. while (!list_empty(&fimc->active_buf_q)) {
  168. buf = fimc_lite_active_queue_pop(fimc);
  169. if (suspend)
  170. fimc_lite_pending_queue_add(fimc, buf);
  171. else
  172. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  173. }
  174. spin_unlock_irqrestore(&fimc->slock, flags);
  175. flite_hw_reset(fimc);
  176. if (!streaming)
  177. return 0;
  178. return fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 0);
  179. }
  180. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  181. {
  182. unsigned long flags;
  183. if (!fimc_lite_active(fimc))
  184. return 0;
  185. spin_lock_irqsave(&fimc->slock, flags);
  186. set_bit(ST_FLITE_OFF, &fimc->state);
  187. flite_hw_capture_stop(fimc);
  188. spin_unlock_irqrestore(&fimc->slock, flags);
  189. wait_event_timeout(fimc->irq_queue,
  190. !test_bit(ST_FLITE_OFF, &fimc->state),
  191. (2*HZ/10)); /* 200 ms */
  192. return fimc_lite_reinit(fimc, suspend);
  193. }
  194. /* Must be called with fimc.slock spinlock held. */
  195. static void fimc_lite_config_update(struct fimc_lite *fimc)
  196. {
  197. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  198. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  199. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  200. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  201. }
  202. static irqreturn_t flite_irq_handler(int irq, void *priv)
  203. {
  204. struct fimc_lite *fimc = priv;
  205. struct flite_buffer *vbuf;
  206. unsigned long flags;
  207. struct timeval *tv;
  208. struct timespec ts;
  209. u32 intsrc;
  210. spin_lock_irqsave(&fimc->slock, flags);
  211. intsrc = flite_hw_get_interrupt_source(fimc);
  212. flite_hw_clear_pending_irq(fimc);
  213. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  214. wake_up(&fimc->irq_queue);
  215. goto done;
  216. }
  217. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  218. clear_bit(ST_FLITE_RUN, &fimc->state);
  219. fimc->events.data_overflow++;
  220. }
  221. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  222. flite_hw_clear_last_capture_end(fimc);
  223. clear_bit(ST_FLITE_STREAM, &fimc->state);
  224. wake_up(&fimc->irq_queue);
  225. }
  226. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  227. goto done;
  228. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  229. test_bit(ST_FLITE_RUN, &fimc->state) &&
  230. !list_empty(&fimc->active_buf_q) &&
  231. !list_empty(&fimc->pending_buf_q)) {
  232. vbuf = fimc_lite_active_queue_pop(fimc);
  233. ktime_get_ts(&ts);
  234. tv = &vbuf->vb.v4l2_buf.timestamp;
  235. tv->tv_sec = ts.tv_sec;
  236. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  237. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  238. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  239. vbuf = fimc_lite_pending_queue_pop(fimc);
  240. flite_hw_set_output_addr(fimc, vbuf->paddr);
  241. fimc_lite_active_queue_add(fimc, vbuf);
  242. }
  243. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  244. fimc_lite_config_update(fimc);
  245. if (list_empty(&fimc->pending_buf_q)) {
  246. flite_hw_capture_stop(fimc);
  247. clear_bit(ST_FLITE_STREAM, &fimc->state);
  248. }
  249. done:
  250. set_bit(ST_FLITE_RUN, &fimc->state);
  251. spin_unlock_irqrestore(&fimc->slock, flags);
  252. return IRQ_HANDLED;
  253. }
  254. static int start_streaming(struct vb2_queue *q, unsigned int count)
  255. {
  256. struct fimc_lite *fimc = q->drv_priv;
  257. int ret;
  258. fimc->frame_count = 0;
  259. ret = fimc_lite_hw_init(fimc, false);
  260. if (ret) {
  261. fimc_lite_reinit(fimc, false);
  262. return ret;
  263. }
  264. set_bit(ST_FLITE_PENDING, &fimc->state);
  265. if (!list_empty(&fimc->active_buf_q) &&
  266. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  267. flite_hw_capture_start(fimc);
  268. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  269. fimc_pipeline_call(fimc, set_stream,
  270. &fimc->pipeline, 1);
  271. }
  272. if (debug > 0)
  273. flite_hw_dump_regs(fimc, __func__);
  274. return 0;
  275. }
  276. static int stop_streaming(struct vb2_queue *q)
  277. {
  278. struct fimc_lite *fimc = q->drv_priv;
  279. if (!fimc_lite_active(fimc))
  280. return -EINVAL;
  281. return fimc_lite_stop_capture(fimc, false);
  282. }
  283. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  284. unsigned int *num_buffers, unsigned int *num_planes,
  285. unsigned int sizes[], void *allocators[])
  286. {
  287. const struct v4l2_pix_format_mplane *pixm = NULL;
  288. struct fimc_lite *fimc = vq->drv_priv;
  289. struct flite_frame *frame = &fimc->out_frame;
  290. const struct fimc_fmt *fmt = fimc->fmt;
  291. unsigned long wh;
  292. int i;
  293. if (pfmt) {
  294. pixm = &pfmt->fmt.pix_mp;
  295. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, -1);
  296. wh = pixm->width * pixm->height;
  297. } else {
  298. wh = frame->f_width * frame->f_height;
  299. }
  300. if (fmt == NULL)
  301. return -EINVAL;
  302. *num_planes = fmt->memplanes;
  303. for (i = 0; i < fmt->memplanes; i++) {
  304. unsigned int size = (wh * fmt->depth[i]) / 8;
  305. if (pixm)
  306. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  307. else
  308. sizes[i] = size;
  309. allocators[i] = fimc->alloc_ctx;
  310. }
  311. return 0;
  312. }
  313. static int buffer_prepare(struct vb2_buffer *vb)
  314. {
  315. struct vb2_queue *vq = vb->vb2_queue;
  316. struct fimc_lite *fimc = vq->drv_priv;
  317. int i;
  318. if (fimc->fmt == NULL)
  319. return -EINVAL;
  320. for (i = 0; i < fimc->fmt->memplanes; i++) {
  321. unsigned long size = fimc->payload[i];
  322. if (vb2_plane_size(vb, i) < size) {
  323. v4l2_err(&fimc->vfd,
  324. "User buffer too small (%ld < %ld)\n",
  325. vb2_plane_size(vb, i), size);
  326. return -EINVAL;
  327. }
  328. vb2_set_plane_payload(vb, i, size);
  329. }
  330. return 0;
  331. }
  332. static void buffer_queue(struct vb2_buffer *vb)
  333. {
  334. struct flite_buffer *buf
  335. = container_of(vb, struct flite_buffer, vb);
  336. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  337. unsigned long flags;
  338. spin_lock_irqsave(&fimc->slock, flags);
  339. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  340. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  341. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  342. list_empty(&fimc->active_buf_q)) {
  343. flite_hw_set_output_addr(fimc, buf->paddr);
  344. fimc_lite_active_queue_add(fimc, buf);
  345. } else {
  346. fimc_lite_pending_queue_add(fimc, buf);
  347. }
  348. if (vb2_is_streaming(&fimc->vb_queue) &&
  349. !list_empty(&fimc->pending_buf_q) &&
  350. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  351. flite_hw_capture_start(fimc);
  352. spin_unlock_irqrestore(&fimc->slock, flags);
  353. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  354. fimc_pipeline_call(fimc, set_stream,
  355. &fimc->pipeline, 1);
  356. return;
  357. }
  358. spin_unlock_irqrestore(&fimc->slock, flags);
  359. }
  360. static void fimc_lock(struct vb2_queue *vq)
  361. {
  362. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  363. mutex_lock(&fimc->lock);
  364. }
  365. static void fimc_unlock(struct vb2_queue *vq)
  366. {
  367. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  368. mutex_unlock(&fimc->lock);
  369. }
  370. static const struct vb2_ops fimc_lite_qops = {
  371. .queue_setup = queue_setup,
  372. .buf_prepare = buffer_prepare,
  373. .buf_queue = buffer_queue,
  374. .wait_prepare = fimc_unlock,
  375. .wait_finish = fimc_lock,
  376. .start_streaming = start_streaming,
  377. .stop_streaming = stop_streaming,
  378. };
  379. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  380. {
  381. unsigned long flags;
  382. spin_lock_irqsave(&fimc->slock, flags);
  383. memset(&fimc->events, 0, sizeof(fimc->events));
  384. spin_unlock_irqrestore(&fimc->slock, flags);
  385. }
  386. static int fimc_lite_open(struct file *file)
  387. {
  388. struct fimc_lite *fimc = video_drvdata(file);
  389. struct media_entity *me = &fimc->vfd.entity;
  390. int ret;
  391. mutex_lock(&me->parent->graph_mutex);
  392. mutex_lock(&fimc->lock);
  393. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
  394. ret = -EBUSY;
  395. goto done;
  396. }
  397. set_bit(ST_FLITE_IN_USE, &fimc->state);
  398. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  399. if (ret < 0)
  400. goto done;
  401. ret = v4l2_fh_open(file);
  402. if (ret < 0)
  403. goto done;
  404. if (++fimc->ref_count == 1 &&
  405. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  406. ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
  407. &fimc->vfd.entity, true);
  408. if (ret < 0) {
  409. pm_runtime_put_sync(&fimc->pdev->dev);
  410. fimc->ref_count--;
  411. v4l2_fh_release(file);
  412. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  413. }
  414. fimc_lite_clear_event_counters(fimc);
  415. }
  416. done:
  417. mutex_unlock(&fimc->lock);
  418. mutex_unlock(&me->parent->graph_mutex);
  419. return ret;
  420. }
  421. static int fimc_lite_close(struct file *file)
  422. {
  423. struct fimc_lite *fimc = video_drvdata(file);
  424. int ret;
  425. mutex_lock(&fimc->lock);
  426. if (--fimc->ref_count == 0 &&
  427. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  428. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  429. fimc_lite_stop_capture(fimc, false);
  430. fimc_pipeline_call(fimc, close, &fimc->pipeline);
  431. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  432. }
  433. pm_runtime_put(&fimc->pdev->dev);
  434. if (fimc->ref_count == 0)
  435. vb2_queue_release(&fimc->vb_queue);
  436. ret = v4l2_fh_release(file);
  437. mutex_unlock(&fimc->lock);
  438. return ret;
  439. }
  440. static unsigned int fimc_lite_poll(struct file *file,
  441. struct poll_table_struct *wait)
  442. {
  443. struct fimc_lite *fimc = video_drvdata(file);
  444. int ret;
  445. if (mutex_lock_interruptible(&fimc->lock))
  446. return POLL_ERR;
  447. ret = vb2_poll(&fimc->vb_queue, file, wait);
  448. mutex_unlock(&fimc->lock);
  449. return ret;
  450. }
  451. static int fimc_lite_mmap(struct file *file, struct vm_area_struct *vma)
  452. {
  453. struct fimc_lite *fimc = video_drvdata(file);
  454. int ret;
  455. if (mutex_lock_interruptible(&fimc->lock))
  456. return -ERESTARTSYS;
  457. ret = vb2_mmap(&fimc->vb_queue, vma);
  458. mutex_unlock(&fimc->lock);
  459. return ret;
  460. }
  461. static const struct v4l2_file_operations fimc_lite_fops = {
  462. .owner = THIS_MODULE,
  463. .open = fimc_lite_open,
  464. .release = fimc_lite_close,
  465. .poll = fimc_lite_poll,
  466. .unlocked_ioctl = video_ioctl2,
  467. .mmap = fimc_lite_mmap,
  468. };
  469. /*
  470. * Format and crop negotiation helpers
  471. */
  472. static const struct fimc_fmt *fimc_lite_try_format(struct fimc_lite *fimc,
  473. u32 *width, u32 *height,
  474. u32 *code, u32 *fourcc, int pad)
  475. {
  476. struct flite_variant *variant = fimc->variant;
  477. const struct fimc_fmt *fmt;
  478. fmt = fimc_lite_find_format(fourcc, code, 0);
  479. if (WARN_ON(!fmt))
  480. return NULL;
  481. if (code)
  482. *code = fmt->mbus_code;
  483. if (fourcc)
  484. *fourcc = fmt->fourcc;
  485. if (pad == FLITE_SD_PAD_SINK) {
  486. v4l_bound_align_image(width, 8, variant->max_width,
  487. ffs(variant->out_width_align) - 1,
  488. height, 0, variant->max_height, 0, 0);
  489. } else {
  490. v4l_bound_align_image(width, 8, fimc->inp_frame.rect.width,
  491. ffs(variant->out_width_align) - 1,
  492. height, 0, fimc->inp_frame.rect.height,
  493. 0, 0);
  494. }
  495. v4l2_dbg(1, debug, &fimc->subdev, "code: 0x%x, %dx%d\n",
  496. code ? *code : 0, *width, *height);
  497. return fmt;
  498. }
  499. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  500. {
  501. struct flite_frame *frame = &fimc->inp_frame;
  502. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  503. &r->height, 0, frame->f_height, 0, 0);
  504. /* Adjust left/top if cropping rectangle got out of bounds */
  505. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  506. r->left = round_down(r->left, fimc->variant->win_hor_offs_align);
  507. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  508. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
  509. r->left, r->top, r->width, r->height,
  510. frame->f_width, frame->f_height);
  511. }
  512. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  513. {
  514. struct flite_frame *frame = &fimc->out_frame;
  515. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  516. /* Scaling is not supported so we enforce compose rectangle size
  517. same as size of the sink crop rectangle. */
  518. r->width = crop_rect->width;
  519. r->height = crop_rect->height;
  520. /* Adjust left/top if the composing rectangle got out of bounds */
  521. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  522. r->left = round_down(r->left, fimc->variant->out_hor_offs_align);
  523. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  524. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
  525. r->left, r->top, r->width, r->height,
  526. frame->f_width, frame->f_height);
  527. }
  528. /*
  529. * Video node ioctl operations
  530. */
  531. static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
  532. struct v4l2_capability *cap)
  533. {
  534. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  535. cap->bus_info[0] = 0;
  536. cap->card[0] = 0;
  537. cap->capabilities = V4L2_CAP_STREAMING;
  538. return 0;
  539. }
  540. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  541. struct v4l2_fmtdesc *f)
  542. {
  543. const struct fimc_fmt *fmt;
  544. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  545. return -EINVAL;
  546. fmt = &fimc_lite_formats[f->index];
  547. strlcpy(f->description, fmt->name, sizeof(f->description));
  548. f->pixelformat = fmt->fourcc;
  549. return 0;
  550. }
  551. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  552. struct v4l2_format *f)
  553. {
  554. struct fimc_lite *fimc = video_drvdata(file);
  555. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  556. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  557. struct flite_frame *frame = &fimc->out_frame;
  558. const struct fimc_fmt *fmt = fimc->fmt;
  559. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  560. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  561. pixm->num_planes = fmt->memplanes;
  562. pixm->pixelformat = fmt->fourcc;
  563. pixm->width = frame->f_width;
  564. pixm->height = frame->f_height;
  565. pixm->field = V4L2_FIELD_NONE;
  566. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  567. return 0;
  568. }
  569. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  570. struct v4l2_pix_format_mplane *pixm,
  571. const struct fimc_fmt **ffmt)
  572. {
  573. struct flite_variant *variant = fimc->variant;
  574. u32 bpl = pixm->plane_fmt[0].bytesperline;
  575. const struct fimc_fmt *fmt;
  576. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0);
  577. if (WARN_ON(fmt == NULL))
  578. return -EINVAL;
  579. if (ffmt)
  580. *ffmt = fmt;
  581. v4l_bound_align_image(&pixm->width, 8, variant->max_width,
  582. ffs(variant->out_width_align) - 1,
  583. &pixm->height, 0, variant->max_height, 0, 0);
  584. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  585. pixm->plane_fmt[0].bytesperline = (pixm->width *
  586. fmt->depth[0]) / 8;
  587. if (pixm->plane_fmt[0].sizeimage == 0)
  588. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  589. fmt->depth[0]) / 8;
  590. pixm->num_planes = fmt->memplanes;
  591. pixm->pixelformat = fmt->fourcc;
  592. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  593. pixm->field = V4L2_FIELD_NONE;
  594. return 0;
  595. }
  596. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  597. struct v4l2_format *f)
  598. {
  599. struct fimc_lite *fimc = video_drvdata(file);
  600. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  601. }
  602. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  603. struct v4l2_format *f)
  604. {
  605. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  606. struct fimc_lite *fimc = video_drvdata(file);
  607. struct flite_frame *frame = &fimc->out_frame;
  608. const struct fimc_fmt *fmt = NULL;
  609. int ret;
  610. if (vb2_is_busy(&fimc->vb_queue))
  611. return -EBUSY;
  612. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  613. if (ret < 0)
  614. return ret;
  615. fimc->fmt = fmt;
  616. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  617. pixm->plane_fmt[0].sizeimage);
  618. frame->f_width = pixm->width;
  619. frame->f_height = pixm->height;
  620. return 0;
  621. }
  622. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  623. {
  624. struct v4l2_subdev *sd = &fimc->subdev;
  625. struct v4l2_subdev_format sink_fmt, src_fmt;
  626. struct media_pad *pad;
  627. int ret;
  628. while (1) {
  629. /* Retrieve format at the sink pad */
  630. pad = &sd->entity.pads[0];
  631. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  632. break;
  633. /* Don't call FIMC subdev operation to avoid nested locking */
  634. if (sd == &fimc->subdev) {
  635. struct flite_frame *ff = &fimc->out_frame;
  636. sink_fmt.format.width = ff->f_width;
  637. sink_fmt.format.height = ff->f_height;
  638. sink_fmt.format.code = fimc->fmt->mbus_code;
  639. } else {
  640. sink_fmt.pad = pad->index;
  641. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  642. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  643. &sink_fmt);
  644. if (ret < 0 && ret != -ENOIOCTLCMD)
  645. return -EPIPE;
  646. }
  647. /* Retrieve format at the source pad */
  648. pad = media_entity_remote_source(pad);
  649. if (pad == NULL ||
  650. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  651. break;
  652. sd = media_entity_to_v4l2_subdev(pad->entity);
  653. src_fmt.pad = pad->index;
  654. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  655. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  656. if (ret < 0 && ret != -ENOIOCTLCMD)
  657. return -EPIPE;
  658. if (src_fmt.format.width != sink_fmt.format.width ||
  659. src_fmt.format.height != sink_fmt.format.height ||
  660. src_fmt.format.code != sink_fmt.format.code)
  661. return -EPIPE;
  662. }
  663. return 0;
  664. }
  665. static int fimc_lite_streamon(struct file *file, void *priv,
  666. enum v4l2_buf_type type)
  667. {
  668. struct fimc_lite *fimc = video_drvdata(file);
  669. struct v4l2_subdev *sensor = fimc->pipeline.subdevs[IDX_SENSOR];
  670. struct fimc_pipeline *p = &fimc->pipeline;
  671. int ret;
  672. if (fimc_lite_active(fimc))
  673. return -EBUSY;
  674. ret = media_entity_pipeline_start(&sensor->entity, p->m_pipeline);
  675. if (ret < 0)
  676. return ret;
  677. ret = fimc_pipeline_validate(fimc);
  678. if (ret) {
  679. media_entity_pipeline_stop(&sensor->entity);
  680. return ret;
  681. }
  682. return vb2_streamon(&fimc->vb_queue, type);
  683. }
  684. static int fimc_lite_streamoff(struct file *file, void *priv,
  685. enum v4l2_buf_type type)
  686. {
  687. struct fimc_lite *fimc = video_drvdata(file);
  688. struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
  689. int ret;
  690. ret = vb2_streamoff(&fimc->vb_queue, type);
  691. if (ret == 0)
  692. media_entity_pipeline_stop(&sd->entity);
  693. return ret;
  694. }
  695. static int fimc_lite_reqbufs(struct file *file, void *priv,
  696. struct v4l2_requestbuffers *reqbufs)
  697. {
  698. struct fimc_lite *fimc = video_drvdata(file);
  699. int ret;
  700. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  701. ret = vb2_reqbufs(&fimc->vb_queue, reqbufs);
  702. if (!ret)
  703. fimc->reqbufs_count = reqbufs->count;
  704. return ret;
  705. }
  706. static int fimc_lite_querybuf(struct file *file, void *priv,
  707. struct v4l2_buffer *buf)
  708. {
  709. struct fimc_lite *fimc = video_drvdata(file);
  710. return vb2_querybuf(&fimc->vb_queue, buf);
  711. }
  712. static int fimc_lite_qbuf(struct file *file, void *priv,
  713. struct v4l2_buffer *buf)
  714. {
  715. struct fimc_lite *fimc = video_drvdata(file);
  716. return vb2_qbuf(&fimc->vb_queue, buf);
  717. }
  718. static int fimc_lite_dqbuf(struct file *file, void *priv,
  719. struct v4l2_buffer *buf)
  720. {
  721. struct fimc_lite *fimc = video_drvdata(file);
  722. return vb2_dqbuf(&fimc->vb_queue, buf, file->f_flags & O_NONBLOCK);
  723. }
  724. static int fimc_lite_create_bufs(struct file *file, void *priv,
  725. struct v4l2_create_buffers *create)
  726. {
  727. struct fimc_lite *fimc = video_drvdata(file);
  728. return vb2_create_bufs(&fimc->vb_queue, create);
  729. }
  730. static int fimc_lite_prepare_buf(struct file *file, void *priv,
  731. struct v4l2_buffer *b)
  732. {
  733. struct fimc_lite *fimc = video_drvdata(file);
  734. return vb2_prepare_buf(&fimc->vb_queue, b);
  735. }
  736. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  737. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  738. {
  739. if (a->left < b->left || a->top < b->top)
  740. return 0;
  741. if (a->left + a->width > b->left + b->width)
  742. return 0;
  743. if (a->top + a->height > b->top + b->height)
  744. return 0;
  745. return 1;
  746. }
  747. static int fimc_lite_g_selection(struct file *file, void *fh,
  748. struct v4l2_selection *sel)
  749. {
  750. struct fimc_lite *fimc = video_drvdata(file);
  751. struct flite_frame *f = &fimc->out_frame;
  752. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  753. return -EINVAL;
  754. switch (sel->target) {
  755. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  756. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  757. sel->r.left = 0;
  758. sel->r.top = 0;
  759. sel->r.width = f->f_width;
  760. sel->r.height = f->f_height;
  761. return 0;
  762. case V4L2_SEL_TGT_COMPOSE:
  763. sel->r = f->rect;
  764. return 0;
  765. }
  766. return -EINVAL;
  767. }
  768. static int fimc_lite_s_selection(struct file *file, void *fh,
  769. struct v4l2_selection *sel)
  770. {
  771. struct fimc_lite *fimc = video_drvdata(file);
  772. struct flite_frame *f = &fimc->out_frame;
  773. struct v4l2_rect rect = sel->r;
  774. unsigned long flags;
  775. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  776. sel->target != V4L2_SEL_TGT_COMPOSE)
  777. return -EINVAL;
  778. fimc_lite_try_compose(fimc, &rect);
  779. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  780. !enclosed_rectangle(&rect, &sel->r))
  781. return -ERANGE;
  782. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  783. !enclosed_rectangle(&sel->r, &rect))
  784. return -ERANGE;
  785. sel->r = rect;
  786. spin_lock_irqsave(&fimc->slock, flags);
  787. f->rect = rect;
  788. set_bit(ST_FLITE_CONFIG, &fimc->state);
  789. spin_unlock_irqrestore(&fimc->slock, flags);
  790. return 0;
  791. }
  792. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  793. .vidioc_querycap = fimc_vidioc_querycap_capture,
  794. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  795. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  796. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  797. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  798. .vidioc_g_selection = fimc_lite_g_selection,
  799. .vidioc_s_selection = fimc_lite_s_selection,
  800. .vidioc_reqbufs = fimc_lite_reqbufs,
  801. .vidioc_querybuf = fimc_lite_querybuf,
  802. .vidioc_prepare_buf = fimc_lite_prepare_buf,
  803. .vidioc_create_bufs = fimc_lite_create_bufs,
  804. .vidioc_qbuf = fimc_lite_qbuf,
  805. .vidioc_dqbuf = fimc_lite_dqbuf,
  806. .vidioc_streamon = fimc_lite_streamon,
  807. .vidioc_streamoff = fimc_lite_streamoff,
  808. };
  809. /* Called with the media graph mutex held */
  810. static struct v4l2_subdev *__find_remote_sensor(struct media_entity *me)
  811. {
  812. struct media_pad *pad = &me->pads[0];
  813. struct v4l2_subdev *sd;
  814. while (pad->flags & MEDIA_PAD_FL_SINK) {
  815. /* source pad */
  816. pad = media_entity_remote_source(pad);
  817. if (pad == NULL ||
  818. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  819. break;
  820. sd = media_entity_to_v4l2_subdev(pad->entity);
  821. if (sd->grp_id == GRP_ID_FIMC_IS_SENSOR)
  822. return sd;
  823. /* sink pad */
  824. pad = &sd->entity.pads[0];
  825. }
  826. return NULL;
  827. }
  828. /* Capture subdev media entity operations */
  829. static int fimc_lite_link_setup(struct media_entity *entity,
  830. const struct media_pad *local,
  831. const struct media_pad *remote, u32 flags)
  832. {
  833. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  834. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  835. unsigned int remote_ent_type = media_entity_type(remote->entity);
  836. int ret = 0;
  837. if (WARN_ON(fimc == NULL))
  838. return 0;
  839. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
  840. __func__, remote->entity->name, local->entity->name,
  841. flags, fimc->source_subdev_grp_id);
  842. mutex_lock(&fimc->lock);
  843. switch (local->index) {
  844. case FLITE_SD_PAD_SINK:
  845. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  846. ret = -EINVAL;
  847. break;
  848. }
  849. if (flags & MEDIA_LNK_FL_ENABLED) {
  850. if (fimc->source_subdev_grp_id == 0)
  851. fimc->source_subdev_grp_id = sd->grp_id;
  852. else
  853. ret = -EBUSY;
  854. } else {
  855. fimc->source_subdev_grp_id = 0;
  856. fimc->sensor = NULL;
  857. }
  858. break;
  859. case FLITE_SD_PAD_SOURCE_DMA:
  860. if (!(flags & MEDIA_LNK_FL_ENABLED))
  861. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  862. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  863. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  864. else
  865. ret = -EINVAL;
  866. break;
  867. case FLITE_SD_PAD_SOURCE_ISP:
  868. if (!(flags & MEDIA_LNK_FL_ENABLED))
  869. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  870. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  871. atomic_set(&fimc->out_path, FIMC_IO_ISP);
  872. else
  873. ret = -EINVAL;
  874. break;
  875. default:
  876. v4l2_err(sd, "Invalid pad index\n");
  877. ret = -EINVAL;
  878. }
  879. mb();
  880. mutex_unlock(&fimc->lock);
  881. return ret;
  882. }
  883. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  884. .link_setup = fimc_lite_link_setup,
  885. };
  886. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  887. struct v4l2_subdev_fh *fh,
  888. struct v4l2_subdev_mbus_code_enum *code)
  889. {
  890. const struct fimc_fmt *fmt;
  891. fmt = fimc_lite_find_format(NULL, NULL, code->index);
  892. if (!fmt)
  893. return -EINVAL;
  894. code->code = fmt->mbus_code;
  895. return 0;
  896. }
  897. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  898. struct v4l2_subdev_fh *fh,
  899. struct v4l2_subdev_format *fmt)
  900. {
  901. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  902. struct v4l2_mbus_framefmt *mf = &fmt->format;
  903. struct flite_frame *f = &fimc->out_frame;
  904. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  905. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  906. fmt->format = *mf;
  907. return 0;
  908. }
  909. mf->colorspace = V4L2_COLORSPACE_JPEG;
  910. mutex_lock(&fimc->lock);
  911. mf->code = fimc->fmt->mbus_code;
  912. if (fmt->pad == FLITE_SD_PAD_SINK) {
  913. /* full camera input frame size */
  914. mf->width = f->f_width;
  915. mf->height = f->f_height;
  916. } else {
  917. /* crop size */
  918. mf->width = f->rect.width;
  919. mf->height = f->rect.height;
  920. }
  921. mutex_unlock(&fimc->lock);
  922. return 0;
  923. }
  924. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  925. struct v4l2_subdev_fh *fh,
  926. struct v4l2_subdev_format *fmt)
  927. {
  928. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  929. struct v4l2_mbus_framefmt *mf = &fmt->format;
  930. struct flite_frame *sink = &fimc->inp_frame;
  931. struct flite_frame *source = &fimc->out_frame;
  932. const struct fimc_fmt *ffmt;
  933. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
  934. fmt->pad, mf->code, mf->width, mf->height);
  935. mf->colorspace = V4L2_COLORSPACE_JPEG;
  936. mutex_lock(&fimc->lock);
  937. if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
  938. sd->entity.stream_count > 0) ||
  939. (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
  940. vb2_is_busy(&fimc->vb_queue))) {
  941. mutex_unlock(&fimc->lock);
  942. return -EBUSY;
  943. }
  944. ffmt = fimc_lite_try_format(fimc, &mf->width, &mf->height,
  945. &mf->code, NULL, fmt->pad);
  946. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  947. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  948. *mf = fmt->format;
  949. mutex_unlock(&fimc->lock);
  950. return 0;
  951. }
  952. if (fmt->pad == FLITE_SD_PAD_SINK) {
  953. sink->f_width = mf->width;
  954. sink->f_height = mf->height;
  955. fimc->fmt = ffmt;
  956. /* Set sink crop rectangle */
  957. sink->rect.width = mf->width;
  958. sink->rect.height = mf->height;
  959. sink->rect.left = 0;
  960. sink->rect.top = 0;
  961. /* Reset source format and crop rectangle */
  962. source->rect = sink->rect;
  963. source->f_width = mf->width;
  964. source->f_height = mf->height;
  965. } else {
  966. /* Allow changing format only on sink pad */
  967. mf->code = fimc->fmt->mbus_code;
  968. mf->width = sink->rect.width;
  969. mf->height = sink->rect.height;
  970. }
  971. mutex_unlock(&fimc->lock);
  972. return 0;
  973. }
  974. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  975. struct v4l2_subdev_fh *fh,
  976. struct v4l2_subdev_selection *sel)
  977. {
  978. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  979. struct flite_frame *f = &fimc->inp_frame;
  980. if ((sel->target != V4L2_SEL_TGT_CROP &&
  981. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  982. sel->pad != FLITE_SD_PAD_SINK)
  983. return -EINVAL;
  984. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  985. sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
  986. return 0;
  987. }
  988. mutex_lock(&fimc->lock);
  989. if (sel->target == V4L2_SEL_TGT_CROP) {
  990. sel->r = f->rect;
  991. } else {
  992. sel->r.left = 0;
  993. sel->r.top = 0;
  994. sel->r.width = f->f_width;
  995. sel->r.height = f->f_height;
  996. }
  997. mutex_unlock(&fimc->lock);
  998. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  999. __func__, f->rect.left, f->rect.top, f->rect.width,
  1000. f->rect.height, f->f_width, f->f_height);
  1001. return 0;
  1002. }
  1003. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  1004. struct v4l2_subdev_fh *fh,
  1005. struct v4l2_subdev_selection *sel)
  1006. {
  1007. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1008. struct flite_frame *f = &fimc->inp_frame;
  1009. int ret = 0;
  1010. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  1011. return -EINVAL;
  1012. mutex_lock(&fimc->lock);
  1013. fimc_lite_try_crop(fimc, &sel->r);
  1014. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1015. *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r;
  1016. } else {
  1017. unsigned long flags;
  1018. spin_lock_irqsave(&fimc->slock, flags);
  1019. f->rect = sel->r;
  1020. /* Same crop rectangle on the source pad */
  1021. fimc->out_frame.rect = sel->r;
  1022. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1023. spin_unlock_irqrestore(&fimc->slock, flags);
  1024. }
  1025. mutex_unlock(&fimc->lock);
  1026. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  1027. __func__, f->rect.left, f->rect.top, f->rect.width,
  1028. f->rect.height, f->f_width, f->f_height);
  1029. return ret;
  1030. }
  1031. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1032. {
  1033. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1034. unsigned long flags;
  1035. int ret;
  1036. /*
  1037. * Find sensor subdev linked to FIMC-LITE directly or through
  1038. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1039. * is used as a subdev only and feeds data internally to FIMC-IS.
  1040. * The pipeline links are protected through entity.stream_count
  1041. * so there is no need to take the media graph mutex here.
  1042. */
  1043. fimc->sensor = __find_remote_sensor(&sd->entity);
  1044. if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
  1045. return -ENOIOCTLCMD;
  1046. mutex_lock(&fimc->lock);
  1047. if (on) {
  1048. flite_hw_reset(fimc);
  1049. ret = fimc_lite_hw_init(fimc, true);
  1050. if (!ret) {
  1051. spin_lock_irqsave(&fimc->slock, flags);
  1052. flite_hw_capture_start(fimc);
  1053. spin_unlock_irqrestore(&fimc->slock, flags);
  1054. }
  1055. } else {
  1056. set_bit(ST_FLITE_OFF, &fimc->state);
  1057. spin_lock_irqsave(&fimc->slock, flags);
  1058. flite_hw_capture_stop(fimc);
  1059. spin_unlock_irqrestore(&fimc->slock, flags);
  1060. ret = wait_event_timeout(fimc->irq_queue,
  1061. !test_bit(ST_FLITE_OFF, &fimc->state),
  1062. msecs_to_jiffies(200));
  1063. if (ret == 0)
  1064. v4l2_err(sd, "s_stream(0) timeout\n");
  1065. clear_bit(ST_FLITE_RUN, &fimc->state);
  1066. }
  1067. mutex_unlock(&fimc->lock);
  1068. return ret;
  1069. }
  1070. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1071. {
  1072. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1073. flite_hw_dump_regs(fimc, __func__);
  1074. return 0;
  1075. }
  1076. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1077. {
  1078. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1079. struct vb2_queue *q = &fimc->vb_queue;
  1080. struct video_device *vfd = &fimc->vfd;
  1081. int ret;
  1082. memset(vfd, 0, sizeof(*vfd));
  1083. fimc->fmt = &fimc_lite_formats[0];
  1084. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  1085. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1086. fimc->index);
  1087. vfd->fops = &fimc_lite_fops;
  1088. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1089. vfd->v4l2_dev = sd->v4l2_dev;
  1090. vfd->minor = -1;
  1091. vfd->release = video_device_release_empty;
  1092. vfd->lock = &fimc->lock;
  1093. fimc->ref_count = 0;
  1094. fimc->reqbufs_count = 0;
  1095. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1096. INIT_LIST_HEAD(&fimc->active_buf_q);
  1097. memset(q, 0, sizeof(*q));
  1098. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1099. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1100. q->ops = &fimc_lite_qops;
  1101. q->mem_ops = &vb2_dma_contig_memops;
  1102. q->buf_struct_size = sizeof(struct flite_buffer);
  1103. q->drv_priv = fimc;
  1104. ret = vb2_queue_init(q);
  1105. if (ret < 0)
  1106. return ret;
  1107. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1108. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1109. if (ret < 0)
  1110. return ret;
  1111. video_set_drvdata(vfd, fimc);
  1112. fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
  1113. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1114. if (ret < 0) {
  1115. media_entity_cleanup(&vfd->entity);
  1116. fimc->pipeline_ops = NULL;
  1117. return ret;
  1118. }
  1119. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1120. vfd->name, video_device_node_name(vfd));
  1121. return 0;
  1122. }
  1123. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1124. {
  1125. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1126. if (fimc == NULL)
  1127. return;
  1128. if (video_is_registered(&fimc->vfd)) {
  1129. video_unregister_device(&fimc->vfd);
  1130. media_entity_cleanup(&fimc->vfd.entity);
  1131. fimc->pipeline_ops = NULL;
  1132. }
  1133. }
  1134. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1135. .registered = fimc_lite_subdev_registered,
  1136. .unregistered = fimc_lite_subdev_unregistered,
  1137. };
  1138. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1139. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1140. .get_selection = fimc_lite_subdev_get_selection,
  1141. .set_selection = fimc_lite_subdev_set_selection,
  1142. .get_fmt = fimc_lite_subdev_get_fmt,
  1143. .set_fmt = fimc_lite_subdev_set_fmt,
  1144. };
  1145. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1146. .s_stream = fimc_lite_subdev_s_stream,
  1147. };
  1148. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1149. .log_status = fimc_lite_log_status,
  1150. };
  1151. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1152. .core = &fimc_lite_core_ops,
  1153. .video = &fimc_lite_subdev_video_ops,
  1154. .pad = &fimc_lite_subdev_pad_ops,
  1155. };
  1156. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1157. {
  1158. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1159. ctrl_handler);
  1160. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1161. return 0;
  1162. }
  1163. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1164. .s_ctrl = fimc_lite_s_ctrl,
  1165. };
  1166. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1167. .ops = &fimc_lite_ctrl_ops,
  1168. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1169. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1170. .name = "Test Pattern 640x480",
  1171. .step = 1,
  1172. };
  1173. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1174. {
  1175. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1176. struct v4l2_subdev *sd = &fimc->subdev;
  1177. int ret;
  1178. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1179. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
  1180. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1181. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1182. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1183. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1184. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1185. fimc->subdev_pads, 0);
  1186. if (ret)
  1187. return ret;
  1188. v4l2_ctrl_handler_init(handler, 1);
  1189. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1190. NULL);
  1191. if (handler->error) {
  1192. media_entity_cleanup(&sd->entity);
  1193. return handler->error;
  1194. }
  1195. sd->ctrl_handler = handler;
  1196. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1197. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1198. v4l2_set_subdevdata(sd, fimc);
  1199. return 0;
  1200. }
  1201. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1202. {
  1203. struct v4l2_subdev *sd = &fimc->subdev;
  1204. v4l2_device_unregister_subdev(sd);
  1205. media_entity_cleanup(&sd->entity);
  1206. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1207. v4l2_set_subdevdata(sd, NULL);
  1208. }
  1209. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1210. {
  1211. if (IS_ERR_OR_NULL(fimc->clock))
  1212. return;
  1213. clk_unprepare(fimc->clock);
  1214. clk_put(fimc->clock);
  1215. fimc->clock = NULL;
  1216. }
  1217. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1218. {
  1219. int ret;
  1220. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1221. if (IS_ERR(fimc->clock))
  1222. return PTR_ERR(fimc->clock);
  1223. ret = clk_prepare(fimc->clock);
  1224. if (ret < 0) {
  1225. clk_put(fimc->clock);
  1226. fimc->clock = NULL;
  1227. }
  1228. return ret;
  1229. }
  1230. static int fimc_lite_probe(struct platform_device *pdev)
  1231. {
  1232. struct flite_drvdata *drv_data = fimc_lite_get_drvdata(pdev);
  1233. struct fimc_lite *fimc;
  1234. struct resource *res;
  1235. int ret;
  1236. fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
  1237. if (!fimc)
  1238. return -ENOMEM;
  1239. fimc->index = pdev->id;
  1240. fimc->variant = drv_data->variant[fimc->index];
  1241. fimc->pdev = pdev;
  1242. init_waitqueue_head(&fimc->irq_queue);
  1243. spin_lock_init(&fimc->slock);
  1244. mutex_init(&fimc->lock);
  1245. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1246. fimc->regs = devm_ioremap_resource(&pdev->dev, res);
  1247. if (IS_ERR(fimc->regs))
  1248. return PTR_ERR(fimc->regs);
  1249. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1250. if (res == NULL) {
  1251. dev_err(&pdev->dev, "Failed to get IRQ resource\n");
  1252. return -ENXIO;
  1253. }
  1254. ret = fimc_lite_clk_get(fimc);
  1255. if (ret)
  1256. return ret;
  1257. ret = devm_request_irq(&pdev->dev, res->start, flite_irq_handler,
  1258. 0, dev_name(&pdev->dev), fimc);
  1259. if (ret) {
  1260. dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
  1261. goto err_clk;
  1262. }
  1263. /* The video node will be created within the subdev's registered() op */
  1264. ret = fimc_lite_create_capture_subdev(fimc);
  1265. if (ret)
  1266. goto err_clk;
  1267. platform_set_drvdata(pdev, fimc);
  1268. pm_runtime_enable(&pdev->dev);
  1269. ret = pm_runtime_get_sync(&pdev->dev);
  1270. if (ret < 0)
  1271. goto err_sd;
  1272. fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1273. if (IS_ERR(fimc->alloc_ctx)) {
  1274. ret = PTR_ERR(fimc->alloc_ctx);
  1275. goto err_pm;
  1276. }
  1277. pm_runtime_put(&pdev->dev);
  1278. dev_dbg(&pdev->dev, "FIMC-LITE.%d registered successfully\n",
  1279. fimc->index);
  1280. return 0;
  1281. err_pm:
  1282. pm_runtime_put(&pdev->dev);
  1283. err_sd:
  1284. fimc_lite_unregister_capture_subdev(fimc);
  1285. err_clk:
  1286. fimc_lite_clk_put(fimc);
  1287. return ret;
  1288. }
  1289. static int fimc_lite_runtime_resume(struct device *dev)
  1290. {
  1291. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1292. clk_enable(fimc->clock);
  1293. return 0;
  1294. }
  1295. static int fimc_lite_runtime_suspend(struct device *dev)
  1296. {
  1297. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1298. clk_disable(fimc->clock);
  1299. return 0;
  1300. }
  1301. #ifdef CONFIG_PM_SLEEP
  1302. static int fimc_lite_resume(struct device *dev)
  1303. {
  1304. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1305. struct flite_buffer *buf;
  1306. unsigned long flags;
  1307. int i;
  1308. spin_lock_irqsave(&fimc->slock, flags);
  1309. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1310. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1311. spin_unlock_irqrestore(&fimc->slock, flags);
  1312. return 0;
  1313. }
  1314. flite_hw_reset(fimc);
  1315. spin_unlock_irqrestore(&fimc->slock, flags);
  1316. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1317. return 0;
  1318. INIT_LIST_HEAD(&fimc->active_buf_q);
  1319. fimc_pipeline_call(fimc, open, &fimc->pipeline,
  1320. &fimc->vfd.entity, false);
  1321. fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
  1322. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1323. for (i = 0; i < fimc->reqbufs_count; i++) {
  1324. if (list_empty(&fimc->pending_buf_q))
  1325. break;
  1326. buf = fimc_lite_pending_queue_pop(fimc);
  1327. buffer_queue(&buf->vb);
  1328. }
  1329. return 0;
  1330. }
  1331. static int fimc_lite_suspend(struct device *dev)
  1332. {
  1333. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1334. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1335. int ret;
  1336. if (test_and_set_bit(ST_LPM, &fimc->state))
  1337. return 0;
  1338. ret = fimc_lite_stop_capture(fimc, suspend);
  1339. if (ret < 0 || !fimc_lite_active(fimc))
  1340. return ret;
  1341. return fimc_pipeline_call(fimc, close, &fimc->pipeline);
  1342. }
  1343. #endif /* CONFIG_PM_SLEEP */
  1344. static int fimc_lite_remove(struct platform_device *pdev)
  1345. {
  1346. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1347. struct device *dev = &pdev->dev;
  1348. pm_runtime_disable(dev);
  1349. pm_runtime_set_suspended(dev);
  1350. fimc_lite_unregister_capture_subdev(fimc);
  1351. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1352. fimc_lite_clk_put(fimc);
  1353. dev_info(dev, "Driver unloaded\n");
  1354. return 0;
  1355. }
  1356. static struct flite_variant fimc_lite0_variant_exynos4 = {
  1357. .max_width = 8192,
  1358. .max_height = 8192,
  1359. .out_width_align = 8,
  1360. .win_hor_offs_align = 2,
  1361. .out_hor_offs_align = 8,
  1362. };
  1363. /* EXYNOS4212, EXYNOS4412 */
  1364. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1365. .variant = {
  1366. [0] = &fimc_lite0_variant_exynos4,
  1367. [1] = &fimc_lite0_variant_exynos4,
  1368. },
  1369. };
  1370. static struct platform_device_id fimc_lite_driver_ids[] = {
  1371. {
  1372. .name = "exynos-fimc-lite",
  1373. .driver_data = (unsigned long)&fimc_lite_drvdata_exynos4,
  1374. },
  1375. { /* sentinel */ },
  1376. };
  1377. MODULE_DEVICE_TABLE(platform, fimc_lite_driver_ids);
  1378. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1379. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1380. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1381. NULL)
  1382. };
  1383. static struct platform_driver fimc_lite_driver = {
  1384. .probe = fimc_lite_probe,
  1385. .remove = fimc_lite_remove,
  1386. .id_table = fimc_lite_driver_ids,
  1387. .driver = {
  1388. .name = FIMC_LITE_DRV_NAME,
  1389. .owner = THIS_MODULE,
  1390. .pm = &fimc_lite_pm_ops,
  1391. }
  1392. };
  1393. module_platform_driver(fimc_lite_driver);
  1394. MODULE_LICENSE("GPL");
  1395. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);