mthca_main.c 32 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  148. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  149. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  150. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  151. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  152. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  153. /*
  154. * Subtract 1 from the limit because we need to allocate a
  155. * spare CQE so the HCA HW can tell the difference between an
  156. * empty CQ and a full CQ.
  157. */
  158. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  159. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  160. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  161. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  162. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  163. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  164. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  165. mdev->limits.port_width_cap = dev_lim->max_port_width;
  166. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  167. mdev->limits.flags = dev_lim->flags;
  168. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  169. May be doable since hardware supports it for SRQ.
  170. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  171. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  172. supported by driver. */
  173. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  174. IB_DEVICE_PORT_ACTIVE_EVENT |
  175. IB_DEVICE_SYS_IMAGE_GUID |
  176. IB_DEVICE_RC_RNR_NAK_GEN;
  177. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  178. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  179. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  180. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  181. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  182. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  183. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  184. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  185. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  186. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  187. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  188. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  189. return 0;
  190. }
  191. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  192. {
  193. u8 status;
  194. int err;
  195. struct mthca_dev_lim dev_lim;
  196. struct mthca_profile profile;
  197. struct mthca_init_hca_param init_hca;
  198. err = mthca_SYS_EN(mdev, &status);
  199. if (err) {
  200. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  201. return err;
  202. }
  203. if (status) {
  204. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  205. "aborting.\n", status);
  206. return -EINVAL;
  207. }
  208. err = mthca_QUERY_FW(mdev, &status);
  209. if (err) {
  210. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  211. goto err_disable;
  212. }
  213. if (status) {
  214. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  215. "aborting.\n", status);
  216. err = -EINVAL;
  217. goto err_disable;
  218. }
  219. err = mthca_QUERY_DDR(mdev, &status);
  220. if (err) {
  221. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  222. goto err_disable;
  223. }
  224. if (status) {
  225. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  226. "aborting.\n", status);
  227. err = -EINVAL;
  228. goto err_disable;
  229. }
  230. err = mthca_dev_lim(mdev, &dev_lim);
  231. profile = default_profile;
  232. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  233. profile.uarc_size = 0;
  234. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  235. profile.num_srq = dev_lim.max_srqs;
  236. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  237. if (err < 0)
  238. goto err_disable;
  239. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  240. if (err) {
  241. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  242. goto err_disable;
  243. }
  244. if (status) {
  245. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  246. "aborting.\n", status);
  247. err = -EINVAL;
  248. goto err_disable;
  249. }
  250. return 0;
  251. err_disable:
  252. mthca_SYS_DIS(mdev, &status);
  253. return err;
  254. }
  255. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  256. {
  257. u8 status;
  258. int err;
  259. /* FIXME: use HCA-attached memory for FW if present */
  260. mdev->fw.arbel.fw_icm =
  261. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  262. GFP_HIGHUSER | __GFP_NOWARN);
  263. if (!mdev->fw.arbel.fw_icm) {
  264. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  265. return -ENOMEM;
  266. }
  267. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  268. if (err) {
  269. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  270. goto err_free;
  271. }
  272. if (status) {
  273. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  274. err = -EINVAL;
  275. goto err_free;
  276. }
  277. err = mthca_RUN_FW(mdev, &status);
  278. if (err) {
  279. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  280. goto err_unmap_fa;
  281. }
  282. if (status) {
  283. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  284. err = -EINVAL;
  285. goto err_unmap_fa;
  286. }
  287. return 0;
  288. err_unmap_fa:
  289. mthca_UNMAP_FA(mdev, &status);
  290. err_free:
  291. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  292. return err;
  293. }
  294. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  295. struct mthca_dev_lim *dev_lim,
  296. struct mthca_init_hca_param *init_hca,
  297. u64 icm_size)
  298. {
  299. u64 aux_pages;
  300. u8 status;
  301. int err;
  302. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  303. if (err) {
  304. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  305. return err;
  306. }
  307. if (status) {
  308. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  309. "aborting.\n", status);
  310. return -EINVAL;
  311. }
  312. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  313. (unsigned long long) icm_size >> 10,
  314. (unsigned long long) aux_pages << 2);
  315. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  316. GFP_HIGHUSER | __GFP_NOWARN);
  317. if (!mdev->fw.arbel.aux_icm) {
  318. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  319. return -ENOMEM;
  320. }
  321. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  322. if (err) {
  323. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  324. goto err_free_aux;
  325. }
  326. if (status) {
  327. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  328. err = -EINVAL;
  329. goto err_free_aux;
  330. }
  331. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  332. if (err) {
  333. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  334. goto err_unmap_aux;
  335. }
  336. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  337. MTHCA_MTT_SEG_SIZE,
  338. mdev->limits.num_mtt_segs,
  339. mdev->limits.reserved_mtts, 1);
  340. if (!mdev->mr_table.mtt_table) {
  341. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  342. err = -ENOMEM;
  343. goto err_unmap_eq;
  344. }
  345. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  346. dev_lim->mpt_entry_sz,
  347. mdev->limits.num_mpts,
  348. mdev->limits.reserved_mrws, 1);
  349. if (!mdev->mr_table.mpt_table) {
  350. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  351. err = -ENOMEM;
  352. goto err_unmap_mtt;
  353. }
  354. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  355. dev_lim->qpc_entry_sz,
  356. mdev->limits.num_qps,
  357. mdev->limits.reserved_qps, 0);
  358. if (!mdev->qp_table.qp_table) {
  359. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  360. err = -ENOMEM;
  361. goto err_unmap_mpt;
  362. }
  363. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  364. dev_lim->eqpc_entry_sz,
  365. mdev->limits.num_qps,
  366. mdev->limits.reserved_qps, 0);
  367. if (!mdev->qp_table.eqp_table) {
  368. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  369. err = -ENOMEM;
  370. goto err_unmap_qp;
  371. }
  372. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  373. MTHCA_RDB_ENTRY_SIZE,
  374. mdev->limits.num_qps <<
  375. mdev->qp_table.rdb_shift,
  376. 0, 0);
  377. if (!mdev->qp_table.rdb_table) {
  378. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  379. err = -ENOMEM;
  380. goto err_unmap_eqp;
  381. }
  382. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  383. dev_lim->cqc_entry_sz,
  384. mdev->limits.num_cqs,
  385. mdev->limits.reserved_cqs, 0);
  386. if (!mdev->cq_table.table) {
  387. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  388. err = -ENOMEM;
  389. goto err_unmap_rdb;
  390. }
  391. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  392. mdev->srq_table.table =
  393. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  394. dev_lim->srq_entry_sz,
  395. mdev->limits.num_srqs,
  396. mdev->limits.reserved_srqs, 0);
  397. if (!mdev->srq_table.table) {
  398. mthca_err(mdev, "Failed to map SRQ context memory, "
  399. "aborting.\n");
  400. err = -ENOMEM;
  401. goto err_unmap_cq;
  402. }
  403. }
  404. /*
  405. * It's not strictly required, but for simplicity just map the
  406. * whole multicast group table now. The table isn't very big
  407. * and it's a lot easier than trying to track ref counts.
  408. */
  409. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  410. MTHCA_MGM_ENTRY_SIZE,
  411. mdev->limits.num_mgms +
  412. mdev->limits.num_amgms,
  413. mdev->limits.num_mgms +
  414. mdev->limits.num_amgms,
  415. 0);
  416. if (!mdev->mcg_table.table) {
  417. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  418. err = -ENOMEM;
  419. goto err_unmap_srq;
  420. }
  421. return 0;
  422. err_unmap_srq:
  423. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  424. mthca_free_icm_table(mdev, mdev->srq_table.table);
  425. err_unmap_cq:
  426. mthca_free_icm_table(mdev, mdev->cq_table.table);
  427. err_unmap_rdb:
  428. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  429. err_unmap_eqp:
  430. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  431. err_unmap_qp:
  432. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  433. err_unmap_mpt:
  434. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  435. err_unmap_mtt:
  436. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  437. err_unmap_eq:
  438. mthca_unmap_eq_icm(mdev);
  439. err_unmap_aux:
  440. mthca_UNMAP_ICM_AUX(mdev, &status);
  441. err_free_aux:
  442. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  443. return err;
  444. }
  445. static void mthca_free_icms(struct mthca_dev *mdev)
  446. {
  447. u8 status;
  448. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  449. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  450. mthca_free_icm_table(mdev, mdev->srq_table.table);
  451. mthca_free_icm_table(mdev, mdev->cq_table.table);
  452. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  453. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  454. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  455. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  456. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  457. mthca_unmap_eq_icm(mdev);
  458. mthca_UNMAP_ICM_AUX(mdev, &status);
  459. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  460. }
  461. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  462. {
  463. struct mthca_dev_lim dev_lim;
  464. struct mthca_profile profile;
  465. struct mthca_init_hca_param init_hca;
  466. u64 icm_size;
  467. u8 status;
  468. int err;
  469. err = mthca_QUERY_FW(mdev, &status);
  470. if (err) {
  471. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  472. return err;
  473. }
  474. if (status) {
  475. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  476. "aborting.\n", status);
  477. return -EINVAL;
  478. }
  479. err = mthca_ENABLE_LAM(mdev, &status);
  480. if (err) {
  481. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  482. return err;
  483. }
  484. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  485. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  486. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  487. } else if (status) {
  488. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  489. "aborting.\n", status);
  490. return -EINVAL;
  491. }
  492. err = mthca_load_fw(mdev);
  493. if (err) {
  494. mthca_err(mdev, "Failed to start FW, aborting.\n");
  495. goto err_disable;
  496. }
  497. err = mthca_dev_lim(mdev, &dev_lim);
  498. if (err) {
  499. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  500. goto err_stop_fw;
  501. }
  502. profile = default_profile;
  503. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  504. profile.num_udav = 0;
  505. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  506. profile.num_srq = dev_lim.max_srqs;
  507. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  508. if ((int) icm_size < 0) {
  509. err = icm_size;
  510. goto err_stop_fw;
  511. }
  512. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  513. if (err)
  514. goto err_stop_fw;
  515. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  516. if (err) {
  517. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  518. goto err_free_icm;
  519. }
  520. if (status) {
  521. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  522. "aborting.\n", status);
  523. err = -EINVAL;
  524. goto err_free_icm;
  525. }
  526. return 0;
  527. err_free_icm:
  528. mthca_free_icms(mdev);
  529. err_stop_fw:
  530. mthca_UNMAP_FA(mdev, &status);
  531. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  532. err_disable:
  533. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  534. mthca_DISABLE_LAM(mdev, &status);
  535. return err;
  536. }
  537. static void mthca_close_hca(struct mthca_dev *mdev)
  538. {
  539. u8 status;
  540. mthca_CLOSE_HCA(mdev, 0, &status);
  541. if (mthca_is_memfree(mdev)) {
  542. mthca_free_icms(mdev);
  543. mthca_UNMAP_FA(mdev, &status);
  544. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  545. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  546. mthca_DISABLE_LAM(mdev, &status);
  547. } else
  548. mthca_SYS_DIS(mdev, &status);
  549. }
  550. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  551. {
  552. u8 status;
  553. int err;
  554. struct mthca_adapter adapter;
  555. if (mthca_is_memfree(mdev))
  556. err = mthca_init_arbel(mdev);
  557. else
  558. err = mthca_init_tavor(mdev);
  559. if (err)
  560. return err;
  561. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  562. if (err) {
  563. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  564. goto err_close;
  565. }
  566. if (status) {
  567. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  568. "aborting.\n", status);
  569. err = -EINVAL;
  570. goto err_close;
  571. }
  572. mdev->eq_table.inta_pin = adapter.inta_pin;
  573. mdev->rev_id = adapter.revision_id;
  574. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  575. return 0;
  576. err_close:
  577. mthca_close_hca(mdev);
  578. return err;
  579. }
  580. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  581. {
  582. int err;
  583. u8 status;
  584. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  585. err = mthca_init_uar_table(dev);
  586. if (err) {
  587. mthca_err(dev, "Failed to initialize "
  588. "user access region table, aborting.\n");
  589. return err;
  590. }
  591. err = mthca_uar_alloc(dev, &dev->driver_uar);
  592. if (err) {
  593. mthca_err(dev, "Failed to allocate driver access region, "
  594. "aborting.\n");
  595. goto err_uar_table_free;
  596. }
  597. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  598. if (!dev->kar) {
  599. mthca_err(dev, "Couldn't map kernel access region, "
  600. "aborting.\n");
  601. err = -ENOMEM;
  602. goto err_uar_free;
  603. }
  604. err = mthca_init_pd_table(dev);
  605. if (err) {
  606. mthca_err(dev, "Failed to initialize "
  607. "protection domain table, aborting.\n");
  608. goto err_kar_unmap;
  609. }
  610. err = mthca_init_mr_table(dev);
  611. if (err) {
  612. mthca_err(dev, "Failed to initialize "
  613. "memory region table, aborting.\n");
  614. goto err_pd_table_free;
  615. }
  616. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  617. if (err) {
  618. mthca_err(dev, "Failed to create driver PD, "
  619. "aborting.\n");
  620. goto err_mr_table_free;
  621. }
  622. err = mthca_init_eq_table(dev);
  623. if (err) {
  624. mthca_err(dev, "Failed to initialize "
  625. "event queue table, aborting.\n");
  626. goto err_pd_free;
  627. }
  628. err = mthca_cmd_use_events(dev);
  629. if (err) {
  630. mthca_err(dev, "Failed to switch to event-driven "
  631. "firmware commands, aborting.\n");
  632. goto err_eq_table_free;
  633. }
  634. err = mthca_NOP(dev, &status);
  635. if (err || status) {
  636. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  637. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  638. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  639. dev->pdev->irq);
  640. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  641. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  642. else
  643. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  644. goto err_cmd_poll;
  645. }
  646. mthca_dbg(dev, "NOP command IRQ test passed\n");
  647. err = mthca_init_cq_table(dev);
  648. if (err) {
  649. mthca_err(dev, "Failed to initialize "
  650. "completion queue table, aborting.\n");
  651. goto err_cmd_poll;
  652. }
  653. err = mthca_init_srq_table(dev);
  654. if (err) {
  655. mthca_err(dev, "Failed to initialize "
  656. "shared receive queue table, aborting.\n");
  657. goto err_cq_table_free;
  658. }
  659. err = mthca_init_qp_table(dev);
  660. if (err) {
  661. mthca_err(dev, "Failed to initialize "
  662. "queue pair table, aborting.\n");
  663. goto err_srq_table_free;
  664. }
  665. err = mthca_init_av_table(dev);
  666. if (err) {
  667. mthca_err(dev, "Failed to initialize "
  668. "address vector table, aborting.\n");
  669. goto err_qp_table_free;
  670. }
  671. err = mthca_init_mcg_table(dev);
  672. if (err) {
  673. mthca_err(dev, "Failed to initialize "
  674. "multicast group table, aborting.\n");
  675. goto err_av_table_free;
  676. }
  677. return 0;
  678. err_av_table_free:
  679. mthca_cleanup_av_table(dev);
  680. err_qp_table_free:
  681. mthca_cleanup_qp_table(dev);
  682. err_srq_table_free:
  683. mthca_cleanup_srq_table(dev);
  684. err_cq_table_free:
  685. mthca_cleanup_cq_table(dev);
  686. err_cmd_poll:
  687. mthca_cmd_use_polling(dev);
  688. err_eq_table_free:
  689. mthca_cleanup_eq_table(dev);
  690. err_pd_free:
  691. mthca_pd_free(dev, &dev->driver_pd);
  692. err_mr_table_free:
  693. mthca_cleanup_mr_table(dev);
  694. err_pd_table_free:
  695. mthca_cleanup_pd_table(dev);
  696. err_kar_unmap:
  697. iounmap(dev->kar);
  698. err_uar_free:
  699. mthca_uar_free(dev, &dev->driver_uar);
  700. err_uar_table_free:
  701. mthca_cleanup_uar_table(dev);
  702. return err;
  703. }
  704. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  705. int ddr_hidden)
  706. {
  707. int err;
  708. /*
  709. * We can't just use pci_request_regions() because the MSI-X
  710. * table is right in the middle of the first BAR. If we did
  711. * pci_request_region and grab all of the first BAR, then
  712. * setting up MSI-X would fail, since the PCI core wants to do
  713. * request_mem_region on the MSI-X vector table.
  714. *
  715. * So just request what we need right now, and request any
  716. * other regions we need when setting up EQs.
  717. */
  718. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  719. MTHCA_HCR_SIZE, DRV_NAME))
  720. return -EBUSY;
  721. err = pci_request_region(pdev, 2, DRV_NAME);
  722. if (err)
  723. goto err_bar2_failed;
  724. if (!ddr_hidden) {
  725. err = pci_request_region(pdev, 4, DRV_NAME);
  726. if (err)
  727. goto err_bar4_failed;
  728. }
  729. return 0;
  730. err_bar4_failed:
  731. pci_release_region(pdev, 2);
  732. err_bar2_failed:
  733. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  734. MTHCA_HCR_SIZE);
  735. return err;
  736. }
  737. static void mthca_release_regions(struct pci_dev *pdev,
  738. int ddr_hidden)
  739. {
  740. if (!ddr_hidden)
  741. pci_release_region(pdev, 4);
  742. pci_release_region(pdev, 2);
  743. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  744. MTHCA_HCR_SIZE);
  745. }
  746. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  747. {
  748. struct msix_entry entries[3];
  749. int err;
  750. entries[0].entry = 0;
  751. entries[1].entry = 1;
  752. entries[2].entry = 2;
  753. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  754. if (err) {
  755. if (err > 0)
  756. mthca_info(mdev, "Only %d MSI-X vectors available, "
  757. "not using MSI-X\n", err);
  758. return err;
  759. }
  760. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  761. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  762. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  763. return 0;
  764. }
  765. /* Types of supported HCA */
  766. enum {
  767. TAVOR, /* MT23108 */
  768. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  769. ARBEL_NATIVE, /* MT25208 with extended features */
  770. SINAI /* MT25204 */
  771. };
  772. #define MTHCA_FW_VER(major, minor, subminor) \
  773. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  774. static struct {
  775. u64 latest_fw;
  776. int is_memfree;
  777. int is_pcie;
  778. } mthca_hca_table[] = {
  779. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  780. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  781. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  782. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  783. };
  784. static int __devinit mthca_init_one(struct pci_dev *pdev,
  785. const struct pci_device_id *id)
  786. {
  787. static int mthca_version_printed = 0;
  788. int ddr_hidden = 0;
  789. int err;
  790. struct mthca_dev *mdev;
  791. if (!mthca_version_printed) {
  792. printk(KERN_INFO "%s", mthca_version);
  793. ++mthca_version_printed;
  794. }
  795. printk(KERN_INFO PFX "Initializing %s\n",
  796. pci_name(pdev));
  797. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  798. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  799. pci_name(pdev), id->driver_data);
  800. return -ENODEV;
  801. }
  802. err = pci_enable_device(pdev);
  803. if (err) {
  804. dev_err(&pdev->dev, "Cannot enable PCI device, "
  805. "aborting.\n");
  806. return err;
  807. }
  808. /*
  809. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  810. * be present)
  811. */
  812. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  813. pci_resource_len(pdev, 0) != 1 << 20) {
  814. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  815. err = -ENODEV;
  816. goto err_disable_pdev;
  817. }
  818. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  819. pci_resource_len(pdev, 2) != 1 << 23) {
  820. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  821. err = -ENODEV;
  822. goto err_disable_pdev;
  823. }
  824. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  825. ddr_hidden = 1;
  826. err = mthca_request_regions(pdev, ddr_hidden);
  827. if (err) {
  828. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  829. "aborting.\n");
  830. goto err_disable_pdev;
  831. }
  832. pci_set_master(pdev);
  833. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  834. if (err) {
  835. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  836. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  837. if (err) {
  838. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  839. goto err_free_res;
  840. }
  841. }
  842. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  843. if (err) {
  844. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  845. "consistent PCI DMA mask.\n");
  846. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  847. if (err) {
  848. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  849. "aborting.\n");
  850. goto err_free_res;
  851. }
  852. }
  853. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  854. if (!mdev) {
  855. dev_err(&pdev->dev, "Device struct alloc failed, "
  856. "aborting.\n");
  857. err = -ENOMEM;
  858. goto err_free_res;
  859. }
  860. mdev->pdev = pdev;
  861. if (ddr_hidden)
  862. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  863. if (mthca_hca_table[id->driver_data].is_memfree)
  864. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  865. if (mthca_hca_table[id->driver_data].is_pcie)
  866. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  867. /*
  868. * Now reset the HCA before we touch the PCI capabilities or
  869. * attempt a firmware command, since a boot ROM may have left
  870. * the HCA in an undefined state.
  871. */
  872. err = mthca_reset(mdev);
  873. if (err) {
  874. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  875. goto err_free_dev;
  876. }
  877. if (msi_x && !mthca_enable_msi_x(mdev))
  878. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  879. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  880. !pci_enable_msi(pdev))
  881. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  882. if (mthca_cmd_init(mdev)) {
  883. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  884. goto err_free_dev;
  885. }
  886. err = mthca_tune_pci(mdev);
  887. if (err)
  888. goto err_cmd;
  889. err = mthca_init_hca(mdev);
  890. if (err)
  891. goto err_cmd;
  892. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  893. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  894. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  895. (int) (mdev->fw_ver & 0xffff),
  896. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  897. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  898. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  899. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  900. }
  901. err = mthca_setup_hca(mdev);
  902. if (err)
  903. goto err_close;
  904. err = mthca_register_device(mdev);
  905. if (err)
  906. goto err_cleanup;
  907. err = mthca_create_agents(mdev);
  908. if (err)
  909. goto err_unregister;
  910. pci_set_drvdata(pdev, mdev);
  911. return 0;
  912. err_unregister:
  913. mthca_unregister_device(mdev);
  914. err_cleanup:
  915. mthca_cleanup_mcg_table(mdev);
  916. mthca_cleanup_av_table(mdev);
  917. mthca_cleanup_qp_table(mdev);
  918. mthca_cleanup_srq_table(mdev);
  919. mthca_cleanup_cq_table(mdev);
  920. mthca_cmd_use_polling(mdev);
  921. mthca_cleanup_eq_table(mdev);
  922. mthca_pd_free(mdev, &mdev->driver_pd);
  923. mthca_cleanup_mr_table(mdev);
  924. mthca_cleanup_pd_table(mdev);
  925. mthca_cleanup_uar_table(mdev);
  926. err_close:
  927. mthca_close_hca(mdev);
  928. err_cmd:
  929. mthca_cmd_cleanup(mdev);
  930. err_free_dev:
  931. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  932. pci_disable_msix(pdev);
  933. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  934. pci_disable_msi(pdev);
  935. ib_dealloc_device(&mdev->ib_dev);
  936. err_free_res:
  937. mthca_release_regions(pdev, ddr_hidden);
  938. err_disable_pdev:
  939. pci_disable_device(pdev);
  940. pci_set_drvdata(pdev, NULL);
  941. return err;
  942. }
  943. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  944. {
  945. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  946. u8 status;
  947. int p;
  948. if (mdev) {
  949. mthca_free_agents(mdev);
  950. mthca_unregister_device(mdev);
  951. for (p = 1; p <= mdev->limits.num_ports; ++p)
  952. mthca_CLOSE_IB(mdev, p, &status);
  953. mthca_cleanup_mcg_table(mdev);
  954. mthca_cleanup_av_table(mdev);
  955. mthca_cleanup_qp_table(mdev);
  956. mthca_cleanup_srq_table(mdev);
  957. mthca_cleanup_cq_table(mdev);
  958. mthca_cmd_use_polling(mdev);
  959. mthca_cleanup_eq_table(mdev);
  960. mthca_pd_free(mdev, &mdev->driver_pd);
  961. mthca_cleanup_mr_table(mdev);
  962. mthca_cleanup_pd_table(mdev);
  963. iounmap(mdev->kar);
  964. mthca_uar_free(mdev, &mdev->driver_uar);
  965. mthca_cleanup_uar_table(mdev);
  966. mthca_close_hca(mdev);
  967. mthca_cmd_cleanup(mdev);
  968. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  969. pci_disable_msix(pdev);
  970. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  971. pci_disable_msi(pdev);
  972. ib_dealloc_device(&mdev->ib_dev);
  973. mthca_release_regions(pdev, mdev->mthca_flags &
  974. MTHCA_FLAG_DDR_HIDDEN);
  975. pci_disable_device(pdev);
  976. pci_set_drvdata(pdev, NULL);
  977. }
  978. }
  979. static struct pci_device_id mthca_pci_table[] = {
  980. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  981. .driver_data = TAVOR },
  982. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  983. .driver_data = TAVOR },
  984. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  985. .driver_data = ARBEL_COMPAT },
  986. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  987. .driver_data = ARBEL_COMPAT },
  988. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  989. .driver_data = ARBEL_NATIVE },
  990. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  991. .driver_data = ARBEL_NATIVE },
  992. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  993. .driver_data = SINAI },
  994. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  995. .driver_data = SINAI },
  996. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  997. .driver_data = SINAI },
  998. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  999. .driver_data = SINAI },
  1000. { 0, }
  1001. };
  1002. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1003. static struct pci_driver mthca_driver = {
  1004. .name = DRV_NAME,
  1005. .owner = THIS_MODULE,
  1006. .id_table = mthca_pci_table,
  1007. .probe = mthca_init_one,
  1008. .remove = __devexit_p(mthca_remove_one)
  1009. };
  1010. static int __init mthca_init(void)
  1011. {
  1012. int ret;
  1013. ret = pci_register_driver(&mthca_driver);
  1014. return ret < 0 ? ret : 0;
  1015. }
  1016. static void __exit mthca_cleanup(void)
  1017. {
  1018. pci_unregister_driver(&mthca_driver);
  1019. }
  1020. module_init(mthca_init);
  1021. module_exit(mthca_cleanup);