xhci-hcd.c 15 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/irq.h>
  23. #include <linux/module.h>
  24. #include "xhci.h"
  25. #define DRIVER_AUTHOR "Sarah Sharp"
  26. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  27. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  28. /*
  29. * handshake - spin reading hc until handshake completes or fails
  30. * @ptr: address of hc register to be read
  31. * @mask: bits to look at in result of read
  32. * @done: value of those bits when handshake succeeds
  33. * @usec: timeout in microseconds
  34. *
  35. * Returns negative errno, or zero on success
  36. *
  37. * Success happens when the "mask" bits have the specified value (hardware
  38. * handshake done). There are two failure modes: "usec" have passed (major
  39. * hardware flakeout), or the register reads as all-ones (hardware removed).
  40. */
  41. static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  42. u32 mask, u32 done, int usec)
  43. {
  44. u32 result;
  45. do {
  46. result = xhci_readl(xhci, ptr);
  47. if (result == ~(u32)0) /* card removed */
  48. return -ENODEV;
  49. result &= mask;
  50. if (result == done)
  51. return 0;
  52. udelay(1);
  53. usec--;
  54. } while (usec > 0);
  55. return -ETIMEDOUT;
  56. }
  57. /*
  58. * Force HC into halt state.
  59. *
  60. * Disable any IRQs and clear the run/stop bit.
  61. * HC will complete any current and actively pipelined transactions, and
  62. * should halt within 16 microframes of the run/stop bit being cleared.
  63. * Read HC Halted bit in the status register to see when the HC is finished.
  64. * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  65. */
  66. int xhci_halt(struct xhci_hcd *xhci)
  67. {
  68. u32 halted;
  69. u32 cmd;
  70. u32 mask;
  71. xhci_dbg(xhci, "// Halt the HC\n");
  72. /* Disable all interrupts from the host controller */
  73. mask = ~(XHCI_IRQS);
  74. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  75. if (!halted)
  76. mask &= ~CMD_RUN;
  77. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  78. cmd &= mask;
  79. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  80. return handshake(xhci, &xhci->op_regs->status,
  81. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  82. }
  83. /*
  84. * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
  85. *
  86. * This resets pipelines, timers, counters, state machines, etc.
  87. * Transactions will be terminated immediately, and operational registers
  88. * will be set to their defaults.
  89. */
  90. int xhci_reset(struct xhci_hcd *xhci)
  91. {
  92. u32 command;
  93. u32 state;
  94. state = xhci_readl(xhci, &xhci->op_regs->status);
  95. BUG_ON((state & STS_HALT) == 0);
  96. xhci_dbg(xhci, "// Reset the HC\n");
  97. command = xhci_readl(xhci, &xhci->op_regs->command);
  98. command |= CMD_RESET;
  99. xhci_writel(xhci, command, &xhci->op_regs->command);
  100. /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
  101. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  102. return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
  103. }
  104. /*
  105. * Stop the HC from processing the endpoint queues.
  106. */
  107. static void xhci_quiesce(struct xhci_hcd *xhci)
  108. {
  109. /*
  110. * Queues are per endpoint, so we need to disable an endpoint or slot.
  111. *
  112. * To disable a slot, we need to insert a disable slot command on the
  113. * command ring and ring the doorbell. This will also free any internal
  114. * resources associated with the slot (which might not be what we want).
  115. *
  116. * A Release Endpoint command sounds better - doesn't free internal HC
  117. * memory, but removes the endpoints from the schedule and releases the
  118. * bandwidth, disables the doorbells, and clears the endpoint enable
  119. * flag. Usually used prior to a set interface command.
  120. *
  121. * TODO: Implement after command ring code is done.
  122. */
  123. BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state));
  124. xhci_dbg(xhci, "Finished quiescing -- code not written yet\n");
  125. }
  126. #if 0
  127. /* Set up MSI-X table for entry 0 (may claim other entries later) */
  128. static int xhci_setup_msix(struct xhci_hcd *xhci)
  129. {
  130. int ret;
  131. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  132. xhci->msix_count = 0;
  133. /* XXX: did I do this right? ixgbe does kcalloc for more than one */
  134. xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
  135. if (!xhci->msix_entries) {
  136. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  137. return -ENOMEM;
  138. }
  139. xhci->msix_entries[0].entry = 0;
  140. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  141. if (ret) {
  142. xhci_err(xhci, "Failed to enable MSI-X\n");
  143. goto free_entries;
  144. }
  145. /*
  146. * Pass the xhci pointer value as the request_irq "cookie".
  147. * If more irqs are added, this will need to be unique for each one.
  148. */
  149. ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
  150. "xHCI", xhci_to_hcd(xhci));
  151. if (ret) {
  152. xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
  153. goto disable_msix;
  154. }
  155. xhci_dbg(xhci, "Finished setting up MSI-X\n");
  156. return 0;
  157. disable_msix:
  158. pci_disable_msix(pdev);
  159. free_entries:
  160. kfree(xhci->msix_entries);
  161. xhci->msix_entries = NULL;
  162. return ret;
  163. }
  164. /* XXX: code duplication; can xhci_setup_msix call this? */
  165. /* Free any IRQs and disable MSI-X */
  166. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  167. {
  168. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  169. if (!xhci->msix_entries)
  170. return;
  171. free_irq(xhci->msix_entries[0].vector, xhci);
  172. pci_disable_msix(pdev);
  173. kfree(xhci->msix_entries);
  174. xhci->msix_entries = NULL;
  175. xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
  176. }
  177. #endif
  178. /*
  179. * Initialize memory for HCD and xHC (one-time init).
  180. *
  181. * Program the PAGESIZE register, initialize the device context array, create
  182. * device contexts (?), set up a command ring segment (or two?), create event
  183. * ring (one for now).
  184. */
  185. int xhci_init(struct usb_hcd *hcd)
  186. {
  187. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  188. int retval = 0;
  189. xhci_dbg(xhci, "xhci_init\n");
  190. spin_lock_init(&xhci->lock);
  191. retval = xhci_mem_init(xhci, GFP_KERNEL);
  192. xhci_dbg(xhci, "Finished xhci_init\n");
  193. return retval;
  194. }
  195. /*
  196. * Called in interrupt context when there might be work
  197. * queued on the event ring
  198. *
  199. * xhci->lock must be held by caller.
  200. */
  201. static void xhci_work(struct xhci_hcd *xhci)
  202. {
  203. u32 temp;
  204. /*
  205. * Clear the op reg interrupt status first,
  206. * so we can receive interrupts from other MSI-X interrupters.
  207. * Write 1 to clear the interrupt status.
  208. */
  209. temp = xhci_readl(xhci, &xhci->op_regs->status);
  210. temp |= STS_EINT;
  211. xhci_writel(xhci, temp, &xhci->op_regs->status);
  212. /* FIXME when MSI-X is supported and there are multiple vectors */
  213. /* Clear the MSI-X event interrupt status */
  214. /* Acknowledge the interrupt */
  215. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  216. temp |= 0x3;
  217. xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
  218. /* Flush posted writes */
  219. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  220. /* FIXME this should be a delayed service routine that clears the EHB */
  221. handle_event(xhci);
  222. /* Clear the event handler busy flag; the event ring should be empty. */
  223. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  224. xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]);
  225. /* Flush posted writes -- FIXME is this necessary? */
  226. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  227. }
  228. /*-------------------------------------------------------------------------*/
  229. /*
  230. * xHCI spec says we can get an interrupt, and if the HC has an error condition,
  231. * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
  232. * indicators of an event TRB error, but we check the status *first* to be safe.
  233. */
  234. irqreturn_t xhci_irq(struct usb_hcd *hcd)
  235. {
  236. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  237. u32 temp, temp2;
  238. spin_lock(&xhci->lock);
  239. /* Check if the xHC generated the interrupt, or the irq is shared */
  240. temp = xhci_readl(xhci, &xhci->op_regs->status);
  241. temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  242. if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
  243. spin_unlock(&xhci->lock);
  244. return IRQ_NONE;
  245. }
  246. temp = xhci_readl(xhci, &xhci->op_regs->status);
  247. if (temp & STS_FATAL) {
  248. xhci_warn(xhci, "WARNING: Host System Error\n");
  249. xhci_halt(xhci);
  250. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  251. return -ESHUTDOWN;
  252. }
  253. xhci_work(xhci);
  254. spin_unlock(&xhci->lock);
  255. return IRQ_HANDLED;
  256. }
  257. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  258. void event_ring_work(unsigned long arg)
  259. {
  260. unsigned long flags;
  261. int temp;
  262. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  263. int i, j;
  264. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  265. spin_lock_irqsave(&xhci->lock, flags);
  266. temp = xhci_readl(xhci, &xhci->op_regs->status);
  267. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  268. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  269. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  270. xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
  271. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  272. xhci->error_bitmask = 0;
  273. xhci_dbg(xhci, "Event ring:\n");
  274. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  275. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  276. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  277. temp &= ERST_PTR_MASK;
  278. xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
  279. xhci_dbg(xhci, "Command ring:\n");
  280. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  281. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  282. xhci_dbg_cmd_ptrs(xhci);
  283. if (xhci->noops_submitted != NUM_TEST_NOOPS)
  284. if (setup_one_noop(xhci))
  285. ring_cmd_db(xhci);
  286. spin_unlock_irqrestore(&xhci->lock, flags);
  287. if (!xhci->zombie)
  288. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  289. else
  290. xhci_dbg(xhci, "Quit polling the event ring.\n");
  291. }
  292. #endif
  293. /*
  294. * Start the HC after it was halted.
  295. *
  296. * This function is called by the USB core when the HC driver is added.
  297. * Its opposite is xhci_stop().
  298. *
  299. * xhci_init() must be called once before this function can be called.
  300. * Reset the HC, enable device slot contexts, program DCBAAP, and
  301. * set command ring pointer and event ring pointer.
  302. *
  303. * Setup MSI-X vectors and enable interrupts.
  304. */
  305. int xhci_run(struct usb_hcd *hcd)
  306. {
  307. u32 temp;
  308. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  309. void (*doorbell)(struct xhci_hcd *) = NULL;
  310. hcd->uses_new_polling = 1;
  311. hcd->poll_rh = 0;
  312. xhci_dbg(xhci, "xhci_run\n");
  313. #if 0 /* FIXME: MSI not setup yet */
  314. /* Do this at the very last minute */
  315. ret = xhci_setup_msix(xhci);
  316. if (!ret)
  317. return ret;
  318. return -ENOSYS;
  319. #endif
  320. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  321. init_timer(&xhci->event_ring_timer);
  322. xhci->event_ring_timer.data = (unsigned long) xhci;
  323. xhci->event_ring_timer.function = event_ring_work;
  324. /* Poll the event ring */
  325. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  326. xhci->zombie = 0;
  327. xhci_dbg(xhci, "Setting event ring polling timer\n");
  328. add_timer(&xhci->event_ring_timer);
  329. #endif
  330. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  331. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  332. temp &= 0xffff;
  333. temp |= (u32) 160;
  334. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  335. /* Set the HCD state before we enable the irqs */
  336. hcd->state = HC_STATE_RUNNING;
  337. temp = xhci_readl(xhci, &xhci->op_regs->command);
  338. temp |= (CMD_EIE);
  339. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  340. temp);
  341. xhci_writel(xhci, temp, &xhci->op_regs->command);
  342. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  343. xhci_dbg(xhci, "// Enabling event ring interrupter 0x%x"
  344. " by writing 0x%x to irq_pending\n",
  345. (unsigned int) xhci->ir_set,
  346. (unsigned int) ER_IRQ_ENABLE(temp));
  347. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  348. &xhci->ir_set->irq_pending);
  349. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  350. if (NUM_TEST_NOOPS > 0)
  351. doorbell = setup_one_noop(xhci);
  352. xhci_dbg(xhci, "Command ring memory map follows:\n");
  353. xhci_debug_ring(xhci, xhci->cmd_ring);
  354. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  355. xhci_dbg_cmd_ptrs(xhci);
  356. xhci_dbg(xhci, "ERST memory map follows:\n");
  357. xhci_dbg_erst(xhci, &xhci->erst);
  358. xhci_dbg(xhci, "Event ring:\n");
  359. xhci_debug_ring(xhci, xhci->event_ring);
  360. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  361. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]);
  362. xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp);
  363. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  364. temp &= ERST_PTR_MASK;
  365. xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
  366. temp = xhci_readl(xhci, &xhci->op_regs->command);
  367. temp |= (CMD_RUN);
  368. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  369. temp);
  370. xhci_writel(xhci, temp, &xhci->op_regs->command);
  371. /* Flush PCI posted writes */
  372. temp = xhci_readl(xhci, &xhci->op_regs->command);
  373. xhci_dbg(xhci, "// @%x = 0x%x\n",
  374. (unsigned int) &xhci->op_regs->command, temp);
  375. if (doorbell)
  376. (*doorbell)(xhci);
  377. xhci_dbg(xhci, "Finished xhci_run\n");
  378. return 0;
  379. }
  380. /*
  381. * Stop xHCI driver.
  382. *
  383. * This function is called by the USB core when the HC driver is removed.
  384. * Its opposite is xhci_run().
  385. *
  386. * Disable device contexts, disable IRQs, and quiesce the HC.
  387. * Reset the HC, finish any completed transactions, and cleanup memory.
  388. */
  389. void xhci_stop(struct usb_hcd *hcd)
  390. {
  391. u32 temp;
  392. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  393. spin_lock_irq(&xhci->lock);
  394. if (HC_IS_RUNNING(hcd->state))
  395. xhci_quiesce(xhci);
  396. xhci_halt(xhci);
  397. xhci_reset(xhci);
  398. spin_unlock_irq(&xhci->lock);
  399. #if 0 /* No MSI yet */
  400. xhci_cleanup_msix(xhci);
  401. #endif
  402. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  403. /* Tell the event ring poll function not to reschedule */
  404. xhci->zombie = 1;
  405. del_timer_sync(&xhci->event_ring_timer);
  406. #endif
  407. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  408. temp = xhci_readl(xhci, &xhci->op_regs->status);
  409. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  410. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  411. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  412. &xhci->ir_set->irq_pending);
  413. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  414. xhci_dbg(xhci, "cleaning up memory\n");
  415. xhci_mem_cleanup(xhci);
  416. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  417. xhci_readl(xhci, &xhci->op_regs->status));
  418. }
  419. /*
  420. * Shutdown HC (not bus-specific)
  421. *
  422. * This is called when the machine is rebooting or halting. We assume that the
  423. * machine will be powered off, and the HC's internal state will be reset.
  424. * Don't bother to free memory.
  425. */
  426. void xhci_shutdown(struct usb_hcd *hcd)
  427. {
  428. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  429. spin_lock_irq(&xhci->lock);
  430. xhci_halt(xhci);
  431. spin_unlock_irq(&xhci->lock);
  432. #if 0
  433. xhci_cleanup_msix(xhci);
  434. #endif
  435. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  436. xhci_readl(xhci, &xhci->op_regs->status));
  437. }
  438. /*-------------------------------------------------------------------------*/
  439. int xhci_get_frame(struct usb_hcd *hcd)
  440. {
  441. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  442. /* EHCI mods by the periodic size. Why? */
  443. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  444. }
  445. MODULE_DESCRIPTION(DRIVER_DESC);
  446. MODULE_AUTHOR(DRIVER_AUTHOR);
  447. MODULE_LICENSE("GPL");
  448. static int __init xhci_hcd_init(void)
  449. {
  450. #ifdef CONFIG_PCI
  451. int retval = 0;
  452. retval = xhci_register_pci();
  453. if (retval < 0) {
  454. printk(KERN_DEBUG "Problem registering PCI driver.");
  455. return retval;
  456. }
  457. #endif
  458. return 0;
  459. }
  460. module_init(xhci_hcd_init);
  461. static void __exit xhci_hcd_cleanup(void)
  462. {
  463. #ifdef CONFIG_PCI
  464. xhci_unregister_pci();
  465. #endif
  466. }
  467. module_exit(xhci_hcd_cleanup);