ci13xxx_udc.c 75 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/module.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include "ci13xxx_udc.h"
  69. /******************************************************************************
  70. * DEFINE
  71. *****************************************************************************/
  72. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* UDC descriptor */
  91. static struct ci13xxx *_udc;
  92. /* Interrupt statistics */
  93. #define ISR_MASK 0x1F
  94. static struct {
  95. u32 test;
  96. u32 ui;
  97. u32 uei;
  98. u32 pci;
  99. u32 uri;
  100. u32 sli;
  101. u32 none;
  102. struct {
  103. u32 cnt;
  104. u32 buf[ISR_MASK+1];
  105. u32 idx;
  106. } hndl;
  107. } isr_statistics;
  108. /**
  109. * ffs_nr: find first (least significant) bit set
  110. * @x: the word to search
  111. *
  112. * This function returns bit number (instead of position)
  113. */
  114. static int ffs_nr(u32 x)
  115. {
  116. int n = ffs(x);
  117. return n ? n-1 : 32;
  118. }
  119. /******************************************************************************
  120. * HW block
  121. *****************************************************************************/
  122. /* MSM specific */
  123. #define ABS_AHBBURST (0x0090UL)
  124. #define ABS_AHBMODE (0x0098UL)
  125. /* UDC register map */
  126. static uintptr_t ci_regs_nolpm[] = {
  127. [CAP_CAPLENGTH] = 0x000UL,
  128. [CAP_HCCPARAMS] = 0x008UL,
  129. [CAP_DCCPARAMS] = 0x024UL,
  130. [CAP_TESTMODE] = 0x038UL,
  131. [OP_USBCMD] = 0x000UL,
  132. [OP_USBSTS] = 0x004UL,
  133. [OP_USBINTR] = 0x008UL,
  134. [OP_DEVICEADDR] = 0x014UL,
  135. [OP_ENDPTLISTADDR] = 0x018UL,
  136. [OP_PORTSC] = 0x044UL,
  137. [OP_DEVLC] = 0x084UL,
  138. [OP_USBMODE] = 0x068UL,
  139. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  140. [OP_ENDPTPRIME] = 0x070UL,
  141. [OP_ENDPTFLUSH] = 0x074UL,
  142. [OP_ENDPTSTAT] = 0x078UL,
  143. [OP_ENDPTCOMPLETE] = 0x07CUL,
  144. [OP_ENDPTCTRL] = 0x080UL,
  145. };
  146. static uintptr_t ci_regs_lpm[] = {
  147. [CAP_CAPLENGTH] = 0x000UL,
  148. [CAP_HCCPARAMS] = 0x008UL,
  149. [CAP_DCCPARAMS] = 0x024UL,
  150. [CAP_TESTMODE] = 0x0FCUL,
  151. [OP_USBCMD] = 0x000UL,
  152. [OP_USBSTS] = 0x004UL,
  153. [OP_USBINTR] = 0x008UL,
  154. [OP_DEVICEADDR] = 0x014UL,
  155. [OP_ENDPTLISTADDR] = 0x018UL,
  156. [OP_PORTSC] = 0x044UL,
  157. [OP_DEVLC] = 0x084UL,
  158. [OP_USBMODE] = 0x0C8UL,
  159. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  160. [OP_ENDPTPRIME] = 0x0DCUL,
  161. [OP_ENDPTFLUSH] = 0x0E0UL,
  162. [OP_ENDPTSTAT] = 0x0E4UL,
  163. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  164. [OP_ENDPTCTRL] = 0x0ECUL,
  165. };
  166. static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
  167. {
  168. int i;
  169. kfree(udc->hw_bank.regmap);
  170. udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  171. GFP_KERNEL);
  172. if (!udc->hw_bank.regmap)
  173. return -ENOMEM;
  174. for (i = 0; i < OP_ENDPTCTRL; i++)
  175. udc->hw_bank.regmap[i] =
  176. (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
  177. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  178. for (; i <= OP_LAST; i++)
  179. udc->hw_bank.regmap[i] = udc->hw_bank.op +
  180. 4 * (i - OP_ENDPTCTRL) +
  181. (is_lpm
  182. ? ci_regs_lpm[OP_ENDPTCTRL]
  183. : ci_regs_nolpm[OP_ENDPTCTRL]);
  184. return 0;
  185. }
  186. /**
  187. * hw_ep_bit: calculates the bit number
  188. * @num: endpoint number
  189. * @dir: endpoint direction
  190. *
  191. * This function returns bit number
  192. */
  193. static inline int hw_ep_bit(int num, int dir)
  194. {
  195. return num + (dir ? 16 : 0);
  196. }
  197. static int ep_to_bit(struct ci13xxx *udc, int n)
  198. {
  199. int fill = 16 - udc->hw_ep_max / 2;
  200. if (n >= udc->hw_ep_max / 2)
  201. n += fill;
  202. return n;
  203. }
  204. /**
  205. * hw_read: reads from a hw register
  206. * @reg: register index
  207. * @mask: bitfield mask
  208. *
  209. * This function returns register contents
  210. */
  211. static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
  212. {
  213. return ioread32(udc->hw_bank.regmap[reg]) & mask;
  214. }
  215. /**
  216. * hw_write: writes to a hw register
  217. * @reg: register index
  218. * @mask: bitfield mask
  219. * @data: new value
  220. */
  221. static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
  222. u32 data)
  223. {
  224. if (~mask)
  225. data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
  226. | (data & mask);
  227. iowrite32(data, udc->hw_bank.regmap[reg]);
  228. }
  229. /**
  230. * hw_test_and_clear: tests & clears a hw register
  231. * @reg: register index
  232. * @mask: bitfield mask
  233. *
  234. * This function returns register contents
  235. */
  236. static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
  237. u32 mask)
  238. {
  239. u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
  240. iowrite32(val, udc->hw_bank.regmap[reg]);
  241. return val;
  242. }
  243. /**
  244. * hw_test_and_write: tests & writes a hw register
  245. * @reg: register index
  246. * @mask: bitfield mask
  247. * @data: new value
  248. *
  249. * This function returns register contents
  250. */
  251. static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
  252. u32 mask, u32 data)
  253. {
  254. u32 val = hw_read(udc, reg, ~0);
  255. hw_write(udc, reg, mask, data);
  256. return (val & mask) >> ffs_nr(mask);
  257. }
  258. static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
  259. uintptr_t cap_offset)
  260. {
  261. u32 reg;
  262. /* bank is a module variable */
  263. udc->hw_bank.abs = base;
  264. udc->hw_bank.cap = udc->hw_bank.abs;
  265. udc->hw_bank.cap += cap_offset;
  266. udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
  267. hw_alloc_regmap(udc, false);
  268. reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  269. ffs_nr(HCCPARAMS_LEN);
  270. udc->hw_bank.lpm = reg;
  271. hw_alloc_regmap(udc, !!reg);
  272. udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
  273. udc->hw_bank.size += OP_LAST;
  274. udc->hw_bank.size /= sizeof(u32);
  275. reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  276. ffs_nr(DCCPARAMS_DEN);
  277. udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  278. if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
  279. return -ENODEV;
  280. /* setup lock mode ? */
  281. /* ENDPTSETUPSTAT is '0' by default */
  282. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  283. return 0;
  284. }
  285. /**
  286. * hw_device_reset: resets chip (execute without interruption)
  287. * @base: register base address
  288. *
  289. * This function returns an error code
  290. */
  291. static int hw_device_reset(struct ci13xxx *udc)
  292. {
  293. /* should flush & stop before reset */
  294. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  295. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  296. hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  297. while (hw_read(udc, OP_USBCMD, USBCMD_RST))
  298. udelay(10); /* not RTOS friendly */
  299. if (udc->udc_driver->notify_event)
  300. udc->udc_driver->notify_event(udc,
  301. CI13XXX_CONTROLLER_RESET_EVENT);
  302. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  303. hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  304. /* USBMODE should be configured step by step */
  305. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  306. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  307. /* HW >= 2.3 */
  308. hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  309. if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  310. pr_err("cannot enter in device mode");
  311. pr_err("lpm = %i", udc->hw_bank.lpm);
  312. return -ENODEV;
  313. }
  314. return 0;
  315. }
  316. /**
  317. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  318. * without interruption)
  319. * @dma: 0 => disable, !0 => enable and set dma engine
  320. *
  321. * This function returns an error code
  322. */
  323. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  324. {
  325. if (dma) {
  326. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  327. /* interrupt, error, port change, reset, sleep/suspend */
  328. hw_write(udc, OP_USBINTR, ~0,
  329. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  330. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  331. } else {
  332. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  333. hw_write(udc, OP_USBINTR, ~0, 0);
  334. }
  335. return 0;
  336. }
  337. /**
  338. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  339. * @num: endpoint number
  340. * @dir: endpoint direction
  341. *
  342. * This function returns an error code
  343. */
  344. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  345. {
  346. int n = hw_ep_bit(num, dir);
  347. do {
  348. /* flush any pending transfer */
  349. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  350. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  351. cpu_relax();
  352. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  353. return 0;
  354. }
  355. /**
  356. * hw_ep_disable: disables endpoint (execute without interruption)
  357. * @num: endpoint number
  358. * @dir: endpoint direction
  359. *
  360. * This function returns an error code
  361. */
  362. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  363. {
  364. hw_ep_flush(udc, num, dir);
  365. hw_write(udc, OP_ENDPTCTRL + num,
  366. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  367. return 0;
  368. }
  369. /**
  370. * hw_ep_enable: enables endpoint (execute without interruption)
  371. * @num: endpoint number
  372. * @dir: endpoint direction
  373. * @type: endpoint type
  374. *
  375. * This function returns an error code
  376. */
  377. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  378. {
  379. u32 mask, data;
  380. if (dir) {
  381. mask = ENDPTCTRL_TXT; /* type */
  382. data = type << ffs_nr(mask);
  383. mask |= ENDPTCTRL_TXS; /* unstall */
  384. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  385. data |= ENDPTCTRL_TXR;
  386. mask |= ENDPTCTRL_TXE; /* enable */
  387. data |= ENDPTCTRL_TXE;
  388. } else {
  389. mask = ENDPTCTRL_RXT; /* type */
  390. data = type << ffs_nr(mask);
  391. mask |= ENDPTCTRL_RXS; /* unstall */
  392. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  393. data |= ENDPTCTRL_RXR;
  394. mask |= ENDPTCTRL_RXE; /* enable */
  395. data |= ENDPTCTRL_RXE;
  396. }
  397. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  398. return 0;
  399. }
  400. /**
  401. * hw_ep_get_halt: return endpoint halt status
  402. * @num: endpoint number
  403. * @dir: endpoint direction
  404. *
  405. * This function returns 1 if endpoint halted
  406. */
  407. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  408. {
  409. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  410. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  411. }
  412. /**
  413. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  414. * interruption)
  415. * @n: endpoint number
  416. *
  417. * This function returns setup status
  418. */
  419. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  420. {
  421. n = ep_to_bit(udc, n);
  422. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  423. }
  424. /**
  425. * hw_ep_prime: primes endpoint (execute without interruption)
  426. * @num: endpoint number
  427. * @dir: endpoint direction
  428. * @is_ctrl: true if control endpoint
  429. *
  430. * This function returns an error code
  431. */
  432. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  433. {
  434. int n = hw_ep_bit(num, dir);
  435. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  436. return -EAGAIN;
  437. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  438. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  439. cpu_relax();
  440. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  441. return -EAGAIN;
  442. /* status shoult be tested according with manual but it doesn't work */
  443. return 0;
  444. }
  445. /**
  446. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  447. * without interruption)
  448. * @num: endpoint number
  449. * @dir: endpoint direction
  450. * @value: true => stall, false => unstall
  451. *
  452. * This function returns an error code
  453. */
  454. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  455. {
  456. if (value != 0 && value != 1)
  457. return -EINVAL;
  458. do {
  459. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  460. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  461. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  462. /* data toggle - reserved for EP0 but it's in ESS */
  463. hw_write(udc, reg, mask_xs|mask_xr,
  464. value ? mask_xs : mask_xr);
  465. } while (value != hw_ep_get_halt(udc, num, dir));
  466. return 0;
  467. }
  468. /**
  469. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  470. * interruption)
  471. * @n: interrupt bit
  472. *
  473. * This function returns an error code
  474. */
  475. static int hw_intr_clear(struct ci13xxx *udc, int n)
  476. {
  477. if (n >= REG_BITS)
  478. return -EINVAL;
  479. hw_write(udc, OP_USBINTR, BIT(n), 0);
  480. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  481. return 0;
  482. }
  483. /**
  484. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  485. * interruption)
  486. * @n: interrupt bit
  487. *
  488. * This function returns an error code
  489. */
  490. static int hw_intr_force(struct ci13xxx *udc, int n)
  491. {
  492. if (n >= REG_BITS)
  493. return -EINVAL;
  494. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  495. hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
  496. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  497. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
  498. return 0;
  499. }
  500. /**
  501. * hw_is_port_high_speed: test if port is high speed
  502. *
  503. * This function returns true if high speed port
  504. */
  505. static int hw_port_is_high_speed(struct ci13xxx *udc)
  506. {
  507. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  508. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  509. }
  510. /**
  511. * hw_port_test_get: reads port test mode value
  512. *
  513. * This function returns port test mode value
  514. */
  515. static u8 hw_port_test_get(struct ci13xxx *udc)
  516. {
  517. return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  518. }
  519. /**
  520. * hw_port_test_set: writes port test mode (execute without interruption)
  521. * @mode: new value
  522. *
  523. * This function returns an error code
  524. */
  525. static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
  526. {
  527. const u8 TEST_MODE_MAX = 7;
  528. if (mode > TEST_MODE_MAX)
  529. return -EINVAL;
  530. hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  531. return 0;
  532. }
  533. /**
  534. * hw_read_intr_enable: returns interrupt enable register
  535. *
  536. * This function returns register data
  537. */
  538. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  539. {
  540. return hw_read(udc, OP_USBINTR, ~0);
  541. }
  542. /**
  543. * hw_read_intr_status: returns interrupt status register
  544. *
  545. * This function returns register data
  546. */
  547. static u32 hw_read_intr_status(struct ci13xxx *udc)
  548. {
  549. return hw_read(udc, OP_USBSTS, ~0);
  550. }
  551. /**
  552. * hw_register_read: reads all device registers (execute without interruption)
  553. * @buf: destination buffer
  554. * @size: buffer size
  555. *
  556. * This function returns number of registers read
  557. */
  558. static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
  559. {
  560. unsigned i;
  561. if (size > udc->hw_bank.size)
  562. size = udc->hw_bank.size;
  563. for (i = 0; i < size; i++)
  564. buf[i] = hw_read(udc, i * sizeof(u32), ~0);
  565. return size;
  566. }
  567. /**
  568. * hw_register_write: writes to register
  569. * @addr: register address
  570. * @data: register value
  571. *
  572. * This function returns an error code
  573. */
  574. static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
  575. {
  576. /* align */
  577. addr /= sizeof(u32);
  578. if (addr >= udc->hw_bank.size)
  579. return -EINVAL;
  580. /* align */
  581. addr *= sizeof(u32);
  582. hw_write(udc, addr, ~0, data);
  583. return 0;
  584. }
  585. /**
  586. * hw_test_and_clear_complete: test & clear complete status (execute without
  587. * interruption)
  588. * @n: endpoint number
  589. *
  590. * This function returns complete status
  591. */
  592. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  593. {
  594. n = ep_to_bit(udc, n);
  595. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  596. }
  597. /**
  598. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  599. * without interruption)
  600. *
  601. * This function returns active interrutps
  602. */
  603. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  604. {
  605. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  606. hw_write(udc, OP_USBSTS, ~0, reg);
  607. return reg;
  608. }
  609. /**
  610. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  611. * interruption)
  612. *
  613. * This function returns guard value
  614. */
  615. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  616. {
  617. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  618. }
  619. /**
  620. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  621. * interruption)
  622. *
  623. * This function returns guard value
  624. */
  625. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  626. {
  627. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  628. }
  629. /**
  630. * hw_usb_set_address: configures USB address (execute without interruption)
  631. * @value: new USB address
  632. *
  633. * This function returns an error code
  634. */
  635. static int hw_usb_set_address(struct ci13xxx *udc, u8 value)
  636. {
  637. /* advance */
  638. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  639. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  640. return 0;
  641. }
  642. /**
  643. * hw_usb_reset: restart device after a bus reset (execute without
  644. * interruption)
  645. *
  646. * This function returns an error code
  647. */
  648. static int hw_usb_reset(struct ci13xxx *udc)
  649. {
  650. hw_usb_set_address(udc, 0);
  651. /* ESS flushes only at end?!? */
  652. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  653. /* clear setup token semaphores */
  654. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  655. /* clear complete status */
  656. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  657. /* wait until all bits cleared */
  658. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  659. udelay(10); /* not RTOS friendly */
  660. /* reset all endpoints ? */
  661. /* reset internal status and wait for further instructions
  662. no need to verify the port reset status (ESS does it) */
  663. return 0;
  664. }
  665. /******************************************************************************
  666. * DBG block
  667. *****************************************************************************/
  668. /**
  669. * show_device: prints information about device capabilities and status
  670. *
  671. * Check "device.h" for details
  672. */
  673. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  674. char *buf)
  675. {
  676. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  677. struct usb_gadget *gadget = &udc->gadget;
  678. int n = 0;
  679. trace(udc->dev, "%p\n", buf);
  680. if (attr == NULL || buf == NULL) {
  681. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  682. return 0;
  683. }
  684. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  685. gadget->speed);
  686. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  687. gadget->max_speed);
  688. /* TODO: Scheduled for removal in 3.8. */
  689. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  690. gadget_is_dualspeed(gadget));
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  692. gadget->is_otg);
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  694. gadget->is_a_peripheral);
  695. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  696. gadget->b_hnp_enable);
  697. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  698. gadget->a_hnp_support);
  699. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  700. gadget->a_alt_hnp_support);
  701. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  702. (gadget->name ? gadget->name : ""));
  703. return n;
  704. }
  705. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  706. /**
  707. * show_driver: prints information about attached gadget (if any)
  708. *
  709. * Check "device.h" for details
  710. */
  711. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  712. char *buf)
  713. {
  714. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  715. struct usb_gadget_driver *driver = udc->driver;
  716. int n = 0;
  717. trace(udc->dev, "%p\n", buf);
  718. if (attr == NULL || buf == NULL) {
  719. dev_err(dev, "[%s] EINVAL\n", __func__);
  720. return 0;
  721. }
  722. if (driver == NULL)
  723. return scnprintf(buf, PAGE_SIZE,
  724. "There is no gadget attached!\n");
  725. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  726. (driver->function ? driver->function : ""));
  727. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  728. driver->max_speed);
  729. return n;
  730. }
  731. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  732. /* Maximum event message length */
  733. #define DBG_DATA_MSG 64UL
  734. /* Maximum event messages */
  735. #define DBG_DATA_MAX 128UL
  736. /* Event buffer descriptor */
  737. static struct {
  738. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  739. unsigned idx; /* index */
  740. unsigned tty; /* print to console? */
  741. rwlock_t lck; /* lock */
  742. } dbg_data = {
  743. .idx = 0,
  744. .tty = 0,
  745. .lck = __RW_LOCK_UNLOCKED(lck)
  746. };
  747. /**
  748. * dbg_dec: decrements debug event index
  749. * @idx: buffer index
  750. */
  751. static void dbg_dec(unsigned *idx)
  752. {
  753. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  754. }
  755. /**
  756. * dbg_inc: increments debug event index
  757. * @idx: buffer index
  758. */
  759. static void dbg_inc(unsigned *idx)
  760. {
  761. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  762. }
  763. /**
  764. * dbg_print: prints the common part of the event
  765. * @addr: endpoint address
  766. * @name: event name
  767. * @status: status
  768. * @extra: extra information
  769. */
  770. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  771. {
  772. struct timeval tval;
  773. unsigned int stamp;
  774. unsigned long flags;
  775. write_lock_irqsave(&dbg_data.lck, flags);
  776. do_gettimeofday(&tval);
  777. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  778. stamp = stamp * 1000000 + tval.tv_usec;
  779. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  780. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  781. stamp, addr, name, status, extra);
  782. dbg_inc(&dbg_data.idx);
  783. write_unlock_irqrestore(&dbg_data.lck, flags);
  784. if (dbg_data.tty != 0)
  785. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  786. stamp, addr, name, status, extra);
  787. }
  788. /**
  789. * dbg_done: prints a DONE event
  790. * @addr: endpoint address
  791. * @td: transfer descriptor
  792. * @status: status
  793. */
  794. static void dbg_done(u8 addr, const u32 token, int status)
  795. {
  796. char msg[DBG_DATA_MSG];
  797. scnprintf(msg, sizeof(msg), "%d %02X",
  798. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  799. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  800. dbg_print(addr, "DONE", status, msg);
  801. }
  802. /**
  803. * dbg_event: prints a generic event
  804. * @addr: endpoint address
  805. * @name: event name
  806. * @status: status
  807. */
  808. static void dbg_event(u8 addr, const char *name, int status)
  809. {
  810. if (name != NULL)
  811. dbg_print(addr, name, status, "");
  812. }
  813. /*
  814. * dbg_queue: prints a QUEUE event
  815. * @addr: endpoint address
  816. * @req: USB request
  817. * @status: status
  818. */
  819. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  820. {
  821. char msg[DBG_DATA_MSG];
  822. if (req != NULL) {
  823. scnprintf(msg, sizeof(msg),
  824. "%d %d", !req->no_interrupt, req->length);
  825. dbg_print(addr, "QUEUE", status, msg);
  826. }
  827. }
  828. /**
  829. * dbg_setup: prints a SETUP event
  830. * @addr: endpoint address
  831. * @req: setup request
  832. */
  833. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  834. {
  835. char msg[DBG_DATA_MSG];
  836. if (req != NULL) {
  837. scnprintf(msg, sizeof(msg),
  838. "%02X %02X %04X %04X %d", req->bRequestType,
  839. req->bRequest, le16_to_cpu(req->wValue),
  840. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  841. dbg_print(addr, "SETUP", 0, msg);
  842. }
  843. }
  844. /**
  845. * show_events: displays the event buffer
  846. *
  847. * Check "device.h" for details
  848. */
  849. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  850. char *buf)
  851. {
  852. unsigned long flags;
  853. unsigned i, j, n = 0;
  854. trace(dev->parent, "%p\n", buf);
  855. if (attr == NULL || buf == NULL) {
  856. dev_err(dev->parent, "[%s] EINVAL\n", __func__);
  857. return 0;
  858. }
  859. read_lock_irqsave(&dbg_data.lck, flags);
  860. i = dbg_data.idx;
  861. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  862. n += strlen(dbg_data.buf[i]);
  863. if (n >= PAGE_SIZE) {
  864. n -= strlen(dbg_data.buf[i]);
  865. break;
  866. }
  867. }
  868. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  869. j += scnprintf(buf + j, PAGE_SIZE - j,
  870. "%s", dbg_data.buf[i]);
  871. read_unlock_irqrestore(&dbg_data.lck, flags);
  872. return n;
  873. }
  874. /**
  875. * store_events: configure if events are going to be also printed to console
  876. *
  877. * Check "device.h" for details
  878. */
  879. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  880. const char *buf, size_t count)
  881. {
  882. unsigned tty;
  883. trace(dev->parent, "[%s] %p, %d\n", __func__, buf, count);
  884. if (attr == NULL || buf == NULL) {
  885. dev_err(dev, "[%s] EINVAL\n", __func__);
  886. goto done;
  887. }
  888. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  889. dev_err(dev, "<1|0>: enable|disable console log\n");
  890. goto done;
  891. }
  892. dbg_data.tty = tty;
  893. dev_info(dev, "tty = %u", dbg_data.tty);
  894. done:
  895. return count;
  896. }
  897. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  898. /**
  899. * show_inters: interrupt status, enable status and historic
  900. *
  901. * Check "device.h" for details
  902. */
  903. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  904. char *buf)
  905. {
  906. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  907. unsigned long flags;
  908. u32 intr;
  909. unsigned i, j, n = 0;
  910. trace(udc->dev, "%p\n", buf);
  911. if (attr == NULL || buf == NULL) {
  912. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  913. return 0;
  914. }
  915. spin_lock_irqsave(&udc->lock, flags);
  916. n += scnprintf(buf + n, PAGE_SIZE - n,
  917. "status = %08x\n", hw_read_intr_status(udc));
  918. n += scnprintf(buf + n, PAGE_SIZE - n,
  919. "enable = %08x\n", hw_read_intr_enable(udc));
  920. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  921. isr_statistics.test);
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  923. isr_statistics.ui);
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  925. isr_statistics.uei);
  926. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  927. isr_statistics.pci);
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  929. isr_statistics.uri);
  930. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  931. isr_statistics.sli);
  932. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  933. isr_statistics.none);
  934. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  935. isr_statistics.hndl.cnt);
  936. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  937. i &= ISR_MASK;
  938. intr = isr_statistics.hndl.buf[i];
  939. if (USBi_UI & intr)
  940. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  941. intr &= ~USBi_UI;
  942. if (USBi_UEI & intr)
  943. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  944. intr &= ~USBi_UEI;
  945. if (USBi_PCI & intr)
  946. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  947. intr &= ~USBi_PCI;
  948. if (USBi_URI & intr)
  949. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  950. intr &= ~USBi_URI;
  951. if (USBi_SLI & intr)
  952. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  953. intr &= ~USBi_SLI;
  954. if (intr)
  955. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  956. if (isr_statistics.hndl.buf[i])
  957. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  958. }
  959. spin_unlock_irqrestore(&udc->lock, flags);
  960. return n;
  961. }
  962. /**
  963. * store_inters: enable & force or disable an individual interrutps
  964. * (to be used for test purposes only)
  965. *
  966. * Check "device.h" for details
  967. */
  968. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  969. const char *buf, size_t count)
  970. {
  971. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  972. unsigned long flags;
  973. unsigned en, bit;
  974. trace(udc->dev, "%p, %d\n", buf, count);
  975. if (attr == NULL || buf == NULL) {
  976. dev_err(udc->dev, "EINVAL\n");
  977. goto done;
  978. }
  979. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  980. dev_err(udc->dev, "<1|0> <bit>: enable|disable interrupt\n");
  981. goto done;
  982. }
  983. spin_lock_irqsave(&udc->lock, flags);
  984. if (en) {
  985. if (hw_intr_force(udc, bit))
  986. dev_err(dev, "invalid bit number\n");
  987. else
  988. isr_statistics.test++;
  989. } else {
  990. if (hw_intr_clear(udc, bit))
  991. dev_err(dev, "invalid bit number\n");
  992. }
  993. spin_unlock_irqrestore(&udc->lock, flags);
  994. done:
  995. return count;
  996. }
  997. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  998. /**
  999. * show_port_test: reads port test mode
  1000. *
  1001. * Check "device.h" for details
  1002. */
  1003. static ssize_t show_port_test(struct device *dev,
  1004. struct device_attribute *attr, char *buf)
  1005. {
  1006. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1007. unsigned long flags;
  1008. unsigned mode;
  1009. trace(udc->dev, "%p\n", buf);
  1010. if (attr == NULL || buf == NULL) {
  1011. dev_err(udc->dev, "EINVAL\n");
  1012. return 0;
  1013. }
  1014. spin_lock_irqsave(&udc->lock, flags);
  1015. mode = hw_port_test_get(udc);
  1016. spin_unlock_irqrestore(&udc->lock, flags);
  1017. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  1018. }
  1019. /**
  1020. * store_port_test: writes port test mode
  1021. *
  1022. * Check "device.h" for details
  1023. */
  1024. static ssize_t store_port_test(struct device *dev,
  1025. struct device_attribute *attr,
  1026. const char *buf, size_t count)
  1027. {
  1028. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1029. unsigned long flags;
  1030. unsigned mode;
  1031. trace(udc->dev, "%p, %d\n", buf, count);
  1032. if (attr == NULL || buf == NULL) {
  1033. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1034. goto done;
  1035. }
  1036. if (sscanf(buf, "%u", &mode) != 1) {
  1037. dev_err(udc->dev, "<mode>: set port test mode");
  1038. goto done;
  1039. }
  1040. spin_lock_irqsave(&udc->lock, flags);
  1041. if (hw_port_test_set(udc, mode))
  1042. dev_err(udc->dev, "invalid mode\n");
  1043. spin_unlock_irqrestore(&udc->lock, flags);
  1044. done:
  1045. return count;
  1046. }
  1047. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1048. show_port_test, store_port_test);
  1049. /**
  1050. * show_qheads: DMA contents of all queue heads
  1051. *
  1052. * Check "device.h" for details
  1053. */
  1054. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1055. char *buf)
  1056. {
  1057. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1058. unsigned long flags;
  1059. unsigned i, j, n = 0;
  1060. trace(udc->dev, "%p\n", buf);
  1061. if (attr == NULL || buf == NULL) {
  1062. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1063. return 0;
  1064. }
  1065. spin_lock_irqsave(&udc->lock, flags);
  1066. for (i = 0; i < udc->hw_ep_max/2; i++) {
  1067. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1068. struct ci13xxx_ep *mEpTx =
  1069. &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
  1070. n += scnprintf(buf + n, PAGE_SIZE - n,
  1071. "EP=%02i: RX=%08X TX=%08X\n",
  1072. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1073. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1074. n += scnprintf(buf + n, PAGE_SIZE - n,
  1075. " %04X: %08X %08X\n", j,
  1076. *((u32 *)mEpRx->qh.ptr + j),
  1077. *((u32 *)mEpTx->qh.ptr + j));
  1078. }
  1079. }
  1080. spin_unlock_irqrestore(&udc->lock, flags);
  1081. return n;
  1082. }
  1083. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1084. /**
  1085. * show_registers: dumps all registers
  1086. *
  1087. * Check "device.h" for details
  1088. */
  1089. #define DUMP_ENTRIES 512
  1090. static ssize_t show_registers(struct device *dev,
  1091. struct device_attribute *attr, char *buf)
  1092. {
  1093. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1094. unsigned long flags;
  1095. u32 *dump;
  1096. unsigned i, k, n = 0;
  1097. trace(udc->dev, "%p\n", buf);
  1098. if (attr == NULL || buf == NULL) {
  1099. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1100. return 0;
  1101. }
  1102. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1103. if (!dump) {
  1104. dev_err(udc->dev, "%s: out of memory\n", __func__);
  1105. return 0;
  1106. }
  1107. spin_lock_irqsave(&udc->lock, flags);
  1108. k = hw_register_read(udc, dump, DUMP_ENTRIES);
  1109. spin_unlock_irqrestore(&udc->lock, flags);
  1110. for (i = 0; i < k; i++) {
  1111. n += scnprintf(buf + n, PAGE_SIZE - n,
  1112. "reg[0x%04X] = 0x%08X\n",
  1113. i * (unsigned)sizeof(u32), dump[i]);
  1114. }
  1115. kfree(dump);
  1116. return n;
  1117. }
  1118. /**
  1119. * store_registers: writes value to register address
  1120. *
  1121. * Check "device.h" for details
  1122. */
  1123. static ssize_t store_registers(struct device *dev,
  1124. struct device_attribute *attr,
  1125. const char *buf, size_t count)
  1126. {
  1127. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1128. unsigned long addr, data, flags;
  1129. trace(udc->dev, "%p, %d\n", buf, count);
  1130. if (attr == NULL || buf == NULL) {
  1131. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1132. goto done;
  1133. }
  1134. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1135. dev_err(udc->dev,
  1136. "<addr> <data>: write data to register address\n");
  1137. goto done;
  1138. }
  1139. spin_lock_irqsave(&udc->lock, flags);
  1140. if (hw_register_write(udc, addr, data))
  1141. dev_err(udc->dev, "invalid address range\n");
  1142. spin_unlock_irqrestore(&udc->lock, flags);
  1143. done:
  1144. return count;
  1145. }
  1146. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1147. show_registers, store_registers);
  1148. /**
  1149. * show_requests: DMA contents of all requests currently queued (all endpts)
  1150. *
  1151. * Check "device.h" for details
  1152. */
  1153. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1154. char *buf)
  1155. {
  1156. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1157. unsigned long flags;
  1158. struct list_head *ptr = NULL;
  1159. struct ci13xxx_req *req = NULL;
  1160. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1161. trace(udc->dev, "%p\n", buf);
  1162. if (attr == NULL || buf == NULL) {
  1163. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1164. return 0;
  1165. }
  1166. spin_lock_irqsave(&udc->lock, flags);
  1167. for (i = 0; i < udc->hw_ep_max; i++)
  1168. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1169. {
  1170. req = list_entry(ptr, struct ci13xxx_req, queue);
  1171. n += scnprintf(buf + n, PAGE_SIZE - n,
  1172. "EP=%02i: TD=%08X %s\n",
  1173. i % udc->hw_ep_max/2, (u32)req->dma,
  1174. ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
  1175. for (j = 0; j < qSize; j++)
  1176. n += scnprintf(buf + n, PAGE_SIZE - n,
  1177. " %04X: %08X\n", j,
  1178. *((u32 *)req->ptr + j));
  1179. }
  1180. spin_unlock_irqrestore(&udc->lock, flags);
  1181. return n;
  1182. }
  1183. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1184. /**
  1185. * dbg_create_files: initializes the attribute interface
  1186. * @dev: device
  1187. *
  1188. * This function returns an error code
  1189. */
  1190. __maybe_unused static int dbg_create_files(struct device *dev)
  1191. {
  1192. int retval = 0;
  1193. if (dev == NULL)
  1194. return -EINVAL;
  1195. retval = device_create_file(dev, &dev_attr_device);
  1196. if (retval)
  1197. goto done;
  1198. retval = device_create_file(dev, &dev_attr_driver);
  1199. if (retval)
  1200. goto rm_device;
  1201. retval = device_create_file(dev, &dev_attr_events);
  1202. if (retval)
  1203. goto rm_driver;
  1204. retval = device_create_file(dev, &dev_attr_inters);
  1205. if (retval)
  1206. goto rm_events;
  1207. retval = device_create_file(dev, &dev_attr_port_test);
  1208. if (retval)
  1209. goto rm_inters;
  1210. retval = device_create_file(dev, &dev_attr_qheads);
  1211. if (retval)
  1212. goto rm_port_test;
  1213. retval = device_create_file(dev, &dev_attr_registers);
  1214. if (retval)
  1215. goto rm_qheads;
  1216. retval = device_create_file(dev, &dev_attr_requests);
  1217. if (retval)
  1218. goto rm_registers;
  1219. return 0;
  1220. rm_registers:
  1221. device_remove_file(dev, &dev_attr_registers);
  1222. rm_qheads:
  1223. device_remove_file(dev, &dev_attr_qheads);
  1224. rm_port_test:
  1225. device_remove_file(dev, &dev_attr_port_test);
  1226. rm_inters:
  1227. device_remove_file(dev, &dev_attr_inters);
  1228. rm_events:
  1229. device_remove_file(dev, &dev_attr_events);
  1230. rm_driver:
  1231. device_remove_file(dev, &dev_attr_driver);
  1232. rm_device:
  1233. device_remove_file(dev, &dev_attr_device);
  1234. done:
  1235. return retval;
  1236. }
  1237. /**
  1238. * dbg_remove_files: destroys the attribute interface
  1239. * @dev: device
  1240. *
  1241. * This function returns an error code
  1242. */
  1243. __maybe_unused static int dbg_remove_files(struct device *dev)
  1244. {
  1245. if (dev == NULL)
  1246. return -EINVAL;
  1247. device_remove_file(dev, &dev_attr_requests);
  1248. device_remove_file(dev, &dev_attr_registers);
  1249. device_remove_file(dev, &dev_attr_qheads);
  1250. device_remove_file(dev, &dev_attr_port_test);
  1251. device_remove_file(dev, &dev_attr_inters);
  1252. device_remove_file(dev, &dev_attr_events);
  1253. device_remove_file(dev, &dev_attr_driver);
  1254. device_remove_file(dev, &dev_attr_device);
  1255. return 0;
  1256. }
  1257. /******************************************************************************
  1258. * UTIL block
  1259. *****************************************************************************/
  1260. /**
  1261. * _usb_addr: calculates endpoint address from direction & number
  1262. * @ep: endpoint
  1263. */
  1264. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1265. {
  1266. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1267. }
  1268. /**
  1269. * _hardware_queue: configures a request at hardware level
  1270. * @gadget: gadget
  1271. * @mEp: endpoint
  1272. *
  1273. * This function returns an error code
  1274. */
  1275. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1276. {
  1277. struct ci13xxx *udc = mEp->udc;
  1278. unsigned i;
  1279. int ret = 0;
  1280. unsigned length = mReq->req.length;
  1281. trace(udc->dev, "%p, %p", mEp, mReq);
  1282. /* don't queue twice */
  1283. if (mReq->req.status == -EALREADY)
  1284. return -EALREADY;
  1285. mReq->req.status = -EALREADY;
  1286. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1287. mReq->req.dma = \
  1288. dma_map_single(mEp->device, mReq->req.buf,
  1289. length, mEp->dir ? DMA_TO_DEVICE :
  1290. DMA_FROM_DEVICE);
  1291. if (mReq->req.dma == 0)
  1292. return -ENOMEM;
  1293. mReq->map = 1;
  1294. }
  1295. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1296. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1297. &mReq->zdma);
  1298. if (mReq->zptr == NULL) {
  1299. if (mReq->map) {
  1300. dma_unmap_single(mEp->device, mReq->req.dma,
  1301. length, mEp->dir ? DMA_TO_DEVICE :
  1302. DMA_FROM_DEVICE);
  1303. mReq->req.dma = DMA_ADDR_INVALID;
  1304. mReq->map = 0;
  1305. }
  1306. return -ENOMEM;
  1307. }
  1308. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1309. mReq->zptr->next = TD_TERMINATE;
  1310. mReq->zptr->token = TD_STATUS_ACTIVE;
  1311. if (!mReq->req.no_interrupt)
  1312. mReq->zptr->token |= TD_IOC;
  1313. }
  1314. /*
  1315. * TD configuration
  1316. * TODO - handle requests which spawns into several TDs
  1317. */
  1318. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1319. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1320. mReq->ptr->token &= TD_TOTAL_BYTES;
  1321. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1322. if (mReq->zptr) {
  1323. mReq->ptr->next = mReq->zdma;
  1324. } else {
  1325. mReq->ptr->next = TD_TERMINATE;
  1326. if (!mReq->req.no_interrupt)
  1327. mReq->ptr->token |= TD_IOC;
  1328. }
  1329. mReq->ptr->page[0] = mReq->req.dma;
  1330. for (i = 1; i < 5; i++)
  1331. mReq->ptr->page[i] =
  1332. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1333. if (!list_empty(&mEp->qh.queue)) {
  1334. struct ci13xxx_req *mReqPrev;
  1335. int n = hw_ep_bit(mEp->num, mEp->dir);
  1336. int tmp_stat;
  1337. mReqPrev = list_entry(mEp->qh.queue.prev,
  1338. struct ci13xxx_req, queue);
  1339. if (mReqPrev->zptr)
  1340. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1341. else
  1342. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1343. wmb();
  1344. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  1345. goto done;
  1346. do {
  1347. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1348. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  1349. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  1350. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  1351. if (tmp_stat)
  1352. goto done;
  1353. }
  1354. /* QH configuration */
  1355. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1356. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1357. mEp->qh.ptr->cap |= QH_ZLT;
  1358. wmb(); /* synchronize before ep prime */
  1359. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  1360. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1361. done:
  1362. return ret;
  1363. }
  1364. /**
  1365. * _hardware_dequeue: handles a request at hardware level
  1366. * @gadget: gadget
  1367. * @mEp: endpoint
  1368. *
  1369. * This function returns an error code
  1370. */
  1371. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1372. {
  1373. trace(mEp->udc->dev, "%p, %p", mEp, mReq);
  1374. if (mReq->req.status != -EALREADY)
  1375. return -EINVAL;
  1376. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1377. return -EBUSY;
  1378. if (mReq->zptr) {
  1379. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1380. return -EBUSY;
  1381. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1382. mReq->zptr = NULL;
  1383. }
  1384. mReq->req.status = 0;
  1385. if (mReq->map) {
  1386. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1387. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1388. mReq->req.dma = DMA_ADDR_INVALID;
  1389. mReq->map = 0;
  1390. }
  1391. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1392. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1393. mReq->req.status = -1;
  1394. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1395. mReq->req.status = -1;
  1396. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1397. mReq->req.status = -1;
  1398. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1399. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1400. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1401. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1402. return mReq->req.actual;
  1403. }
  1404. /**
  1405. * _ep_nuke: dequeues all endpoint requests
  1406. * @mEp: endpoint
  1407. *
  1408. * This function returns an error code
  1409. * Caller must hold lock
  1410. */
  1411. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1412. __releases(mEp->lock)
  1413. __acquires(mEp->lock)
  1414. {
  1415. trace(mEp->udc->dev, "%p", mEp);
  1416. if (mEp == NULL)
  1417. return -EINVAL;
  1418. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1419. while (!list_empty(&mEp->qh.queue)) {
  1420. /* pop oldest request */
  1421. struct ci13xxx_req *mReq = \
  1422. list_entry(mEp->qh.queue.next,
  1423. struct ci13xxx_req, queue);
  1424. list_del_init(&mReq->queue);
  1425. mReq->req.status = -ESHUTDOWN;
  1426. if (mReq->req.complete != NULL) {
  1427. spin_unlock(mEp->lock);
  1428. mReq->req.complete(&mEp->ep, &mReq->req);
  1429. spin_lock(mEp->lock);
  1430. }
  1431. }
  1432. return 0;
  1433. }
  1434. /**
  1435. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1436. * @gadget: gadget
  1437. *
  1438. * This function returns an error code
  1439. */
  1440. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1441. {
  1442. struct usb_ep *ep;
  1443. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1444. unsigned long flags;
  1445. trace(udc->dev, "%p", gadget);
  1446. if (gadget == NULL)
  1447. return -EINVAL;
  1448. spin_lock_irqsave(&udc->lock, flags);
  1449. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1450. udc->remote_wakeup = 0;
  1451. udc->suspended = 0;
  1452. spin_unlock_irqrestore(&udc->lock, flags);
  1453. /* flush all endpoints */
  1454. gadget_for_each_ep(ep, gadget) {
  1455. usb_ep_fifo_flush(ep);
  1456. }
  1457. usb_ep_fifo_flush(&udc->ep0out->ep);
  1458. usb_ep_fifo_flush(&udc->ep0in->ep);
  1459. udc->driver->disconnect(gadget);
  1460. /* make sure to disable all endpoints */
  1461. gadget_for_each_ep(ep, gadget) {
  1462. usb_ep_disable(ep);
  1463. }
  1464. if (udc->status != NULL) {
  1465. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  1466. udc->status = NULL;
  1467. }
  1468. return 0;
  1469. }
  1470. /******************************************************************************
  1471. * ISR block
  1472. *****************************************************************************/
  1473. /**
  1474. * isr_reset_handler: USB reset interrupt handler
  1475. * @udc: UDC device
  1476. *
  1477. * This function resets USB engine after a bus reset occurred
  1478. */
  1479. static void isr_reset_handler(struct ci13xxx *udc)
  1480. __releases(udc->lock)
  1481. __acquires(udc->lock)
  1482. {
  1483. int retval;
  1484. trace(udc->dev, "%p", udc);
  1485. dbg_event(0xFF, "BUS RST", 0);
  1486. spin_unlock(&udc->lock);
  1487. retval = _gadget_stop_activity(&udc->gadget);
  1488. if (retval)
  1489. goto done;
  1490. retval = hw_usb_reset(udc);
  1491. if (retval)
  1492. goto done;
  1493. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  1494. if (udc->status == NULL)
  1495. retval = -ENOMEM;
  1496. spin_lock(&udc->lock);
  1497. done:
  1498. if (retval)
  1499. dev_err(udc->dev, "error: %i\n", retval);
  1500. }
  1501. /**
  1502. * isr_get_status_complete: get_status request complete function
  1503. * @ep: endpoint
  1504. * @req: request handled
  1505. *
  1506. * Caller must release lock
  1507. */
  1508. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1509. {
  1510. trace(NULL, "%p, %p", ep, req);
  1511. if (ep == NULL || req == NULL)
  1512. return;
  1513. kfree(req->buf);
  1514. usb_ep_free_request(ep, req);
  1515. }
  1516. /**
  1517. * isr_get_status_response: get_status request response
  1518. * @udc: udc struct
  1519. * @setup: setup request packet
  1520. *
  1521. * This function returns an error code
  1522. */
  1523. static int isr_get_status_response(struct ci13xxx *udc,
  1524. struct usb_ctrlrequest *setup)
  1525. __releases(mEp->lock)
  1526. __acquires(mEp->lock)
  1527. {
  1528. struct ci13xxx_ep *mEp = udc->ep0in;
  1529. struct usb_request *req = NULL;
  1530. gfp_t gfp_flags = GFP_ATOMIC;
  1531. int dir, num, retval;
  1532. trace(udc->dev, "%p, %p", mEp, setup);
  1533. if (mEp == NULL || setup == NULL)
  1534. return -EINVAL;
  1535. spin_unlock(mEp->lock);
  1536. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1537. spin_lock(mEp->lock);
  1538. if (req == NULL)
  1539. return -ENOMEM;
  1540. req->complete = isr_get_status_complete;
  1541. req->length = 2;
  1542. req->buf = kzalloc(req->length, gfp_flags);
  1543. if (req->buf == NULL) {
  1544. retval = -ENOMEM;
  1545. goto err_free_req;
  1546. }
  1547. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1548. /* Assume that device is bus powered for now. */
  1549. *(u16 *)req->buf = _udc->remote_wakeup << 1;
  1550. retval = 0;
  1551. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1552. == USB_RECIP_ENDPOINT) {
  1553. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1554. TX : RX;
  1555. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1556. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  1557. }
  1558. /* else do nothing; reserved for future use */
  1559. spin_unlock(mEp->lock);
  1560. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1561. spin_lock(mEp->lock);
  1562. if (retval)
  1563. goto err_free_buf;
  1564. return 0;
  1565. err_free_buf:
  1566. kfree(req->buf);
  1567. err_free_req:
  1568. spin_unlock(mEp->lock);
  1569. usb_ep_free_request(&mEp->ep, req);
  1570. spin_lock(mEp->lock);
  1571. return retval;
  1572. }
  1573. /**
  1574. * isr_setup_status_complete: setup_status request complete function
  1575. * @ep: endpoint
  1576. * @req: request handled
  1577. *
  1578. * Caller must release lock. Put the port in test mode if test mode
  1579. * feature is selected.
  1580. */
  1581. static void
  1582. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1583. {
  1584. struct ci13xxx *udc = req->context;
  1585. unsigned long flags;
  1586. trace(udc->dev, "%p, %p", ep, req);
  1587. spin_lock_irqsave(&udc->lock, flags);
  1588. if (udc->test_mode)
  1589. hw_port_test_set(udc, udc->test_mode);
  1590. spin_unlock_irqrestore(&udc->lock, flags);
  1591. }
  1592. /**
  1593. * isr_setup_status_phase: queues the status phase of a setup transation
  1594. * @udc: udc struct
  1595. *
  1596. * This function returns an error code
  1597. */
  1598. static int isr_setup_status_phase(struct ci13xxx *udc)
  1599. __releases(mEp->lock)
  1600. __acquires(mEp->lock)
  1601. {
  1602. int retval;
  1603. struct ci13xxx_ep *mEp;
  1604. trace(udc->dev, "%p", udc);
  1605. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  1606. udc->status->context = udc;
  1607. udc->status->complete = isr_setup_status_complete;
  1608. spin_unlock(mEp->lock);
  1609. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1610. spin_lock(mEp->lock);
  1611. return retval;
  1612. }
  1613. /**
  1614. * isr_tr_complete_low: transaction complete low level handler
  1615. * @mEp: endpoint
  1616. *
  1617. * This function returns an error code
  1618. * Caller must hold lock
  1619. */
  1620. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1621. __releases(mEp->lock)
  1622. __acquires(mEp->lock)
  1623. {
  1624. struct ci13xxx_req *mReq, *mReqTemp;
  1625. struct ci13xxx_ep *mEpTemp = mEp;
  1626. int uninitialized_var(retval);
  1627. trace(mEp->udc->dev, "%p", mEp);
  1628. if (list_empty(&mEp->qh.queue))
  1629. return -EINVAL;
  1630. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1631. queue) {
  1632. retval = _hardware_dequeue(mEp, mReq);
  1633. if (retval < 0)
  1634. break;
  1635. list_del_init(&mReq->queue);
  1636. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1637. if (mReq->req.complete != NULL) {
  1638. spin_unlock(mEp->lock);
  1639. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1640. mReq->req.length)
  1641. mEpTemp = _udc->ep0in;
  1642. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1643. spin_lock(mEp->lock);
  1644. }
  1645. }
  1646. if (retval == -EBUSY)
  1647. retval = 0;
  1648. if (retval < 0)
  1649. dbg_event(_usb_addr(mEp), "DONE", retval);
  1650. return retval;
  1651. }
  1652. /**
  1653. * isr_tr_complete_handler: transaction complete interrupt handler
  1654. * @udc: UDC descriptor
  1655. *
  1656. * This function handles traffic events
  1657. */
  1658. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1659. __releases(udc->lock)
  1660. __acquires(udc->lock)
  1661. {
  1662. unsigned i;
  1663. u8 tmode = 0;
  1664. trace(udc->dev, "%p", udc);
  1665. for (i = 0; i < udc->hw_ep_max; i++) {
  1666. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1667. int type, num, dir, err = -EINVAL;
  1668. struct usb_ctrlrequest req;
  1669. if (mEp->ep.desc == NULL)
  1670. continue; /* not configured */
  1671. if (hw_test_and_clear_complete(udc, i)) {
  1672. err = isr_tr_complete_low(mEp);
  1673. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1674. if (err > 0) /* needs status phase */
  1675. err = isr_setup_status_phase(udc);
  1676. if (err < 0) {
  1677. dbg_event(_usb_addr(mEp),
  1678. "ERROR", err);
  1679. spin_unlock(&udc->lock);
  1680. if (usb_ep_set_halt(&mEp->ep))
  1681. dev_err(udc->dev,
  1682. "error: ep_set_halt\n");
  1683. spin_lock(&udc->lock);
  1684. }
  1685. }
  1686. }
  1687. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1688. !hw_test_and_clear_setup_status(udc, i))
  1689. continue;
  1690. if (i != 0) {
  1691. dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
  1692. continue;
  1693. }
  1694. /*
  1695. * Flush data and handshake transactions of previous
  1696. * setup packet.
  1697. */
  1698. _ep_nuke(udc->ep0out);
  1699. _ep_nuke(udc->ep0in);
  1700. /* read_setup_packet */
  1701. do {
  1702. hw_test_and_set_setup_guard(udc);
  1703. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1704. } while (!hw_test_and_clear_setup_guard(udc));
  1705. type = req.bRequestType;
  1706. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1707. dbg_setup(_usb_addr(mEp), &req);
  1708. switch (req.bRequest) {
  1709. case USB_REQ_CLEAR_FEATURE:
  1710. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1711. le16_to_cpu(req.wValue) ==
  1712. USB_ENDPOINT_HALT) {
  1713. if (req.wLength != 0)
  1714. break;
  1715. num = le16_to_cpu(req.wIndex);
  1716. dir = num & USB_ENDPOINT_DIR_MASK;
  1717. num &= USB_ENDPOINT_NUMBER_MASK;
  1718. if (dir) /* TX */
  1719. num += udc->hw_ep_max/2;
  1720. if (!udc->ci13xxx_ep[num].wedge) {
  1721. spin_unlock(&udc->lock);
  1722. err = usb_ep_clear_halt(
  1723. &udc->ci13xxx_ep[num].ep);
  1724. spin_lock(&udc->lock);
  1725. if (err)
  1726. break;
  1727. }
  1728. err = isr_setup_status_phase(udc);
  1729. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1730. le16_to_cpu(req.wValue) ==
  1731. USB_DEVICE_REMOTE_WAKEUP) {
  1732. if (req.wLength != 0)
  1733. break;
  1734. udc->remote_wakeup = 0;
  1735. err = isr_setup_status_phase(udc);
  1736. } else {
  1737. goto delegate;
  1738. }
  1739. break;
  1740. case USB_REQ_GET_STATUS:
  1741. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1742. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1743. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1744. goto delegate;
  1745. if (le16_to_cpu(req.wLength) != 2 ||
  1746. le16_to_cpu(req.wValue) != 0)
  1747. break;
  1748. err = isr_get_status_response(udc, &req);
  1749. break;
  1750. case USB_REQ_SET_ADDRESS:
  1751. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1752. goto delegate;
  1753. if (le16_to_cpu(req.wLength) != 0 ||
  1754. le16_to_cpu(req.wIndex) != 0)
  1755. break;
  1756. err = hw_usb_set_address(udc,
  1757. (u8)le16_to_cpu(req.wValue));
  1758. if (err)
  1759. break;
  1760. err = isr_setup_status_phase(udc);
  1761. break;
  1762. case USB_REQ_SET_FEATURE:
  1763. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1764. le16_to_cpu(req.wValue) ==
  1765. USB_ENDPOINT_HALT) {
  1766. if (req.wLength != 0)
  1767. break;
  1768. num = le16_to_cpu(req.wIndex);
  1769. dir = num & USB_ENDPOINT_DIR_MASK;
  1770. num &= USB_ENDPOINT_NUMBER_MASK;
  1771. if (dir) /* TX */
  1772. num += udc->hw_ep_max/2;
  1773. spin_unlock(&udc->lock);
  1774. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1775. spin_lock(&udc->lock);
  1776. if (!err)
  1777. isr_setup_status_phase(udc);
  1778. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1779. if (req.wLength != 0)
  1780. break;
  1781. switch (le16_to_cpu(req.wValue)) {
  1782. case USB_DEVICE_REMOTE_WAKEUP:
  1783. udc->remote_wakeup = 1;
  1784. err = isr_setup_status_phase(udc);
  1785. break;
  1786. case USB_DEVICE_TEST_MODE:
  1787. tmode = le16_to_cpu(req.wIndex) >> 8;
  1788. switch (tmode) {
  1789. case TEST_J:
  1790. case TEST_K:
  1791. case TEST_SE0_NAK:
  1792. case TEST_PACKET:
  1793. case TEST_FORCE_EN:
  1794. udc->test_mode = tmode;
  1795. err = isr_setup_status_phase(
  1796. udc);
  1797. break;
  1798. default:
  1799. break;
  1800. }
  1801. default:
  1802. goto delegate;
  1803. }
  1804. } else {
  1805. goto delegate;
  1806. }
  1807. break;
  1808. default:
  1809. delegate:
  1810. if (req.wLength == 0) /* no data phase */
  1811. udc->ep0_dir = TX;
  1812. spin_unlock(&udc->lock);
  1813. err = udc->driver->setup(&udc->gadget, &req);
  1814. spin_lock(&udc->lock);
  1815. break;
  1816. }
  1817. if (err < 0) {
  1818. dbg_event(_usb_addr(mEp), "ERROR", err);
  1819. spin_unlock(&udc->lock);
  1820. if (usb_ep_set_halt(&mEp->ep))
  1821. dev_err(udc->dev, "error: ep_set_halt\n");
  1822. spin_lock(&udc->lock);
  1823. }
  1824. }
  1825. }
  1826. /******************************************************************************
  1827. * ENDPT block
  1828. *****************************************************************************/
  1829. /**
  1830. * ep_enable: configure endpoint, making it usable
  1831. *
  1832. * Check usb_ep_enable() at "usb_gadget.h" for details
  1833. */
  1834. static int ep_enable(struct usb_ep *ep,
  1835. const struct usb_endpoint_descriptor *desc)
  1836. {
  1837. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1838. int retval = 0;
  1839. unsigned long flags;
  1840. trace(mEp->udc->dev, "%p, %p", ep, desc);
  1841. if (ep == NULL || desc == NULL)
  1842. return -EINVAL;
  1843. spin_lock_irqsave(mEp->lock, flags);
  1844. /* only internal SW should enable ctrl endpts */
  1845. mEp->ep.desc = desc;
  1846. if (!list_empty(&mEp->qh.queue))
  1847. dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
  1848. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1849. mEp->num = usb_endpoint_num(desc);
  1850. mEp->type = usb_endpoint_type(desc);
  1851. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1852. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1853. mEp->qh.ptr->cap = 0;
  1854. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1855. mEp->qh.ptr->cap |= QH_IOS;
  1856. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1857. mEp->qh.ptr->cap &= ~QH_MULT;
  1858. else
  1859. mEp->qh.ptr->cap &= ~QH_ZLT;
  1860. mEp->qh.ptr->cap |=
  1861. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1862. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1863. /*
  1864. * Enable endpoints in the HW other than ep0 as ep0
  1865. * is always enabled
  1866. */
  1867. if (mEp->num)
  1868. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  1869. spin_unlock_irqrestore(mEp->lock, flags);
  1870. return retval;
  1871. }
  1872. /**
  1873. * ep_disable: endpoint is no longer usable
  1874. *
  1875. * Check usb_ep_disable() at "usb_gadget.h" for details
  1876. */
  1877. static int ep_disable(struct usb_ep *ep)
  1878. {
  1879. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1880. int direction, retval = 0;
  1881. unsigned long flags;
  1882. trace(mEp->udc->dev, "%p", ep);
  1883. if (ep == NULL)
  1884. return -EINVAL;
  1885. else if (mEp->ep.desc == NULL)
  1886. return -EBUSY;
  1887. spin_lock_irqsave(mEp->lock, flags);
  1888. /* only internal SW should disable ctrl endpts */
  1889. direction = mEp->dir;
  1890. do {
  1891. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1892. retval |= _ep_nuke(mEp);
  1893. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  1894. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1895. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1896. } while (mEp->dir != direction);
  1897. mEp->ep.desc = NULL;
  1898. spin_unlock_irqrestore(mEp->lock, flags);
  1899. return retval;
  1900. }
  1901. /**
  1902. * ep_alloc_request: allocate a request object to use with this endpoint
  1903. *
  1904. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1905. */
  1906. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1907. {
  1908. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1909. struct ci13xxx_req *mReq = NULL;
  1910. trace(mEp->udc->dev, "%p, %i", ep, gfp_flags);
  1911. if (ep == NULL)
  1912. return NULL;
  1913. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1914. if (mReq != NULL) {
  1915. INIT_LIST_HEAD(&mReq->queue);
  1916. mReq->req.dma = DMA_ADDR_INVALID;
  1917. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1918. &mReq->dma);
  1919. if (mReq->ptr == NULL) {
  1920. kfree(mReq);
  1921. mReq = NULL;
  1922. }
  1923. }
  1924. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1925. return (mReq == NULL) ? NULL : &mReq->req;
  1926. }
  1927. /**
  1928. * ep_free_request: frees a request object
  1929. *
  1930. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1931. */
  1932. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1933. {
  1934. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1935. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1936. unsigned long flags;
  1937. trace(mEp->udc->dev, "%p, %p", ep, req);
  1938. if (ep == NULL || req == NULL) {
  1939. return;
  1940. } else if (!list_empty(&mReq->queue)) {
  1941. dev_err(mEp->udc->dev, "freeing queued request\n");
  1942. return;
  1943. }
  1944. spin_lock_irqsave(mEp->lock, flags);
  1945. if (mReq->ptr)
  1946. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1947. kfree(mReq);
  1948. dbg_event(_usb_addr(mEp), "FREE", 0);
  1949. spin_unlock_irqrestore(mEp->lock, flags);
  1950. }
  1951. /**
  1952. * ep_queue: queues (submits) an I/O request to an endpoint
  1953. *
  1954. * Check usb_ep_queue()* at usb_gadget.h" for details
  1955. */
  1956. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1957. gfp_t __maybe_unused gfp_flags)
  1958. {
  1959. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1960. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1961. int retval = 0;
  1962. unsigned long flags;
  1963. trace(mEp->udc->dev, "%p, %p, %X", ep, req, gfp_flags);
  1964. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1965. return -EINVAL;
  1966. spin_lock_irqsave(mEp->lock, flags);
  1967. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1968. if (req->length)
  1969. mEp = (_udc->ep0_dir == RX) ?
  1970. _udc->ep0out : _udc->ep0in;
  1971. if (!list_empty(&mEp->qh.queue)) {
  1972. _ep_nuke(mEp);
  1973. retval = -EOVERFLOW;
  1974. dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
  1975. _usb_addr(mEp));
  1976. }
  1977. }
  1978. /* first nuke then test link, e.g. previous status has not sent */
  1979. if (!list_empty(&mReq->queue)) {
  1980. retval = -EBUSY;
  1981. dev_err(mEp->udc->dev, "request already in queue\n");
  1982. goto done;
  1983. }
  1984. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1985. req->length = 4 * CI13XXX_PAGE_SIZE;
  1986. retval = -EMSGSIZE;
  1987. dev_warn(mEp->udc->dev, "request length truncated\n");
  1988. }
  1989. dbg_queue(_usb_addr(mEp), req, retval);
  1990. /* push request */
  1991. mReq->req.status = -EINPROGRESS;
  1992. mReq->req.actual = 0;
  1993. retval = _hardware_enqueue(mEp, mReq);
  1994. if (retval == -EALREADY) {
  1995. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1996. retval = 0;
  1997. }
  1998. if (!retval)
  1999. list_add_tail(&mReq->queue, &mEp->qh.queue);
  2000. done:
  2001. spin_unlock_irqrestore(mEp->lock, flags);
  2002. return retval;
  2003. }
  2004. /**
  2005. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  2006. *
  2007. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  2008. */
  2009. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  2010. {
  2011. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2012. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  2013. unsigned long flags;
  2014. trace(mEp->udc->dev, "%p, %p", ep, req);
  2015. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  2016. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  2017. list_empty(&mEp->qh.queue))
  2018. return -EINVAL;
  2019. spin_lock_irqsave(mEp->lock, flags);
  2020. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  2021. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2022. /* pop request */
  2023. list_del_init(&mReq->queue);
  2024. if (mReq->map) {
  2025. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2026. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2027. mReq->req.dma = DMA_ADDR_INVALID;
  2028. mReq->map = 0;
  2029. }
  2030. req->status = -ECONNRESET;
  2031. if (mReq->req.complete != NULL) {
  2032. spin_unlock(mEp->lock);
  2033. mReq->req.complete(&mEp->ep, &mReq->req);
  2034. spin_lock(mEp->lock);
  2035. }
  2036. spin_unlock_irqrestore(mEp->lock, flags);
  2037. return 0;
  2038. }
  2039. /**
  2040. * ep_set_halt: sets the endpoint halt feature
  2041. *
  2042. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2043. */
  2044. static int ep_set_halt(struct usb_ep *ep, int value)
  2045. {
  2046. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2047. int direction, retval = 0;
  2048. unsigned long flags;
  2049. trace(mEp->udc->dev, "%p, %i", ep, value);
  2050. if (ep == NULL || mEp->ep.desc == NULL)
  2051. return -EINVAL;
  2052. spin_lock_irqsave(mEp->lock, flags);
  2053. #ifndef STALL_IN
  2054. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2055. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2056. !list_empty(&mEp->qh.queue)) {
  2057. spin_unlock_irqrestore(mEp->lock, flags);
  2058. return -EAGAIN;
  2059. }
  2060. #endif
  2061. direction = mEp->dir;
  2062. do {
  2063. dbg_event(_usb_addr(mEp), "HALT", value);
  2064. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  2065. if (!value)
  2066. mEp->wedge = 0;
  2067. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2068. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2069. } while (mEp->dir != direction);
  2070. spin_unlock_irqrestore(mEp->lock, flags);
  2071. return retval;
  2072. }
  2073. /**
  2074. * ep_set_wedge: sets the halt feature and ignores clear requests
  2075. *
  2076. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2077. */
  2078. static int ep_set_wedge(struct usb_ep *ep)
  2079. {
  2080. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2081. unsigned long flags;
  2082. trace(mEp->udc->dev, "%p", ep);
  2083. if (ep == NULL || mEp->ep.desc == NULL)
  2084. return -EINVAL;
  2085. spin_lock_irqsave(mEp->lock, flags);
  2086. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2087. mEp->wedge = 1;
  2088. spin_unlock_irqrestore(mEp->lock, flags);
  2089. return usb_ep_set_halt(ep);
  2090. }
  2091. /**
  2092. * ep_fifo_flush: flushes contents of a fifo
  2093. *
  2094. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2095. */
  2096. static void ep_fifo_flush(struct usb_ep *ep)
  2097. {
  2098. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2099. unsigned long flags;
  2100. trace(mEp->udc->dev, "%p", ep);
  2101. if (ep == NULL) {
  2102. dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
  2103. return;
  2104. }
  2105. spin_lock_irqsave(mEp->lock, flags);
  2106. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2107. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2108. spin_unlock_irqrestore(mEp->lock, flags);
  2109. }
  2110. /**
  2111. * Endpoint-specific part of the API to the USB controller hardware
  2112. * Check "usb_gadget.h" for details
  2113. */
  2114. static const struct usb_ep_ops usb_ep_ops = {
  2115. .enable = ep_enable,
  2116. .disable = ep_disable,
  2117. .alloc_request = ep_alloc_request,
  2118. .free_request = ep_free_request,
  2119. .queue = ep_queue,
  2120. .dequeue = ep_dequeue,
  2121. .set_halt = ep_set_halt,
  2122. .set_wedge = ep_set_wedge,
  2123. .fifo_flush = ep_fifo_flush,
  2124. };
  2125. /******************************************************************************
  2126. * GADGET block
  2127. *****************************************************************************/
  2128. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2129. {
  2130. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2131. unsigned long flags;
  2132. int gadget_ready = 0;
  2133. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2134. return -EOPNOTSUPP;
  2135. spin_lock_irqsave(&udc->lock, flags);
  2136. udc->vbus_active = is_active;
  2137. if (udc->driver)
  2138. gadget_ready = 1;
  2139. spin_unlock_irqrestore(&udc->lock, flags);
  2140. if (gadget_ready) {
  2141. if (is_active) {
  2142. pm_runtime_get_sync(&_gadget->dev);
  2143. hw_device_reset(udc);
  2144. hw_device_state(udc, udc->ep0out->qh.dma);
  2145. } else {
  2146. hw_device_state(udc, 0);
  2147. if (udc->udc_driver->notify_event)
  2148. udc->udc_driver->notify_event(udc,
  2149. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2150. _gadget_stop_activity(&udc->gadget);
  2151. pm_runtime_put_sync(&_gadget->dev);
  2152. }
  2153. }
  2154. return 0;
  2155. }
  2156. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2157. {
  2158. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2159. unsigned long flags;
  2160. int ret = 0;
  2161. trace(udc->dev, "");
  2162. spin_lock_irqsave(&udc->lock, flags);
  2163. if (!udc->remote_wakeup) {
  2164. ret = -EOPNOTSUPP;
  2165. trace(udc->dev, "remote wakeup feature is not enabled\n");
  2166. goto out;
  2167. }
  2168. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  2169. ret = -EINVAL;
  2170. trace(udc->dev, "port is not suspended\n");
  2171. goto out;
  2172. }
  2173. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2174. out:
  2175. spin_unlock_irqrestore(&udc->lock, flags);
  2176. return ret;
  2177. }
  2178. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2179. {
  2180. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2181. if (udc->transceiver)
  2182. return usb_phy_set_power(udc->transceiver, mA);
  2183. return -ENOTSUPP;
  2184. }
  2185. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2186. int (*bind)(struct usb_gadget *));
  2187. static int ci13xxx_stop(struct usb_gadget_driver *driver);
  2188. /**
  2189. * Device operations part of the API to the USB controller hardware,
  2190. * which don't involve endpoints (or i/o)
  2191. * Check "usb_gadget.h" for details
  2192. */
  2193. static const struct usb_gadget_ops usb_gadget_ops = {
  2194. .vbus_session = ci13xxx_vbus_session,
  2195. .wakeup = ci13xxx_wakeup,
  2196. .vbus_draw = ci13xxx_vbus_draw,
  2197. .start = ci13xxx_start,
  2198. .stop = ci13xxx_stop,
  2199. };
  2200. /**
  2201. * ci13xxx_start: register a gadget driver
  2202. * @driver: the driver being registered
  2203. * @bind: the driver's bind callback
  2204. *
  2205. * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
  2206. * Interrupts are enabled here.
  2207. */
  2208. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2209. int (*bind)(struct usb_gadget *))
  2210. {
  2211. struct ci13xxx *udc = _udc;
  2212. unsigned long flags;
  2213. int i, j;
  2214. int retval = -ENOMEM;
  2215. trace(udc->dev, "%p", driver);
  2216. if (driver == NULL ||
  2217. bind == NULL ||
  2218. driver->setup == NULL ||
  2219. driver->disconnect == NULL)
  2220. return -EINVAL;
  2221. else if (udc == NULL)
  2222. return -ENODEV;
  2223. else if (udc->driver != NULL)
  2224. return -EBUSY;
  2225. /* alloc resources */
  2226. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2227. sizeof(struct ci13xxx_qh),
  2228. 64, CI13XXX_PAGE_SIZE);
  2229. if (udc->qh_pool == NULL)
  2230. return -ENOMEM;
  2231. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2232. sizeof(struct ci13xxx_td),
  2233. 64, CI13XXX_PAGE_SIZE);
  2234. if (udc->td_pool == NULL) {
  2235. dma_pool_destroy(udc->qh_pool);
  2236. udc->qh_pool = NULL;
  2237. return -ENOMEM;
  2238. }
  2239. spin_lock_irqsave(&udc->lock, flags);
  2240. dev_info(udc->dev, "hw_ep_max = %d\n", udc->hw_ep_max);
  2241. udc->gadget.dev.driver = NULL;
  2242. retval = 0;
  2243. for (i = 0; i < udc->hw_ep_max/2; i++) {
  2244. for (j = RX; j <= TX; j++) {
  2245. int k = i + j * udc->hw_ep_max/2;
  2246. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2247. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2248. (j == TX) ? "in" : "out");
  2249. mEp->udc = udc;
  2250. mEp->lock = &udc->lock;
  2251. mEp->device = &udc->gadget.dev;
  2252. mEp->td_pool = udc->td_pool;
  2253. mEp->ep.name = mEp->name;
  2254. mEp->ep.ops = &usb_ep_ops;
  2255. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2256. INIT_LIST_HEAD(&mEp->qh.queue);
  2257. spin_unlock_irqrestore(&udc->lock, flags);
  2258. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2259. &mEp->qh.dma);
  2260. spin_lock_irqsave(&udc->lock, flags);
  2261. if (mEp->qh.ptr == NULL)
  2262. retval = -ENOMEM;
  2263. else
  2264. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2265. /*
  2266. * set up shorthands for ep0 out and in endpoints,
  2267. * don't add to gadget's ep_list
  2268. */
  2269. if (i == 0) {
  2270. if (j == RX)
  2271. udc->ep0out = mEp;
  2272. else
  2273. udc->ep0in = mEp;
  2274. continue;
  2275. }
  2276. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2277. }
  2278. }
  2279. if (retval)
  2280. goto done;
  2281. spin_unlock_irqrestore(&udc->lock, flags);
  2282. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  2283. retval = usb_ep_enable(&udc->ep0out->ep);
  2284. if (retval)
  2285. return retval;
  2286. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  2287. retval = usb_ep_enable(&udc->ep0in->ep);
  2288. if (retval)
  2289. return retval;
  2290. spin_lock_irqsave(&udc->lock, flags);
  2291. udc->gadget.ep0 = &udc->ep0in->ep;
  2292. /* bind gadget */
  2293. driver->driver.bus = NULL;
  2294. udc->gadget.dev.driver = &driver->driver;
  2295. spin_unlock_irqrestore(&udc->lock, flags);
  2296. retval = bind(&udc->gadget); /* MAY SLEEP */
  2297. spin_lock_irqsave(&udc->lock, flags);
  2298. if (retval) {
  2299. udc->gadget.dev.driver = NULL;
  2300. goto done;
  2301. }
  2302. udc->driver = driver;
  2303. pm_runtime_get_sync(&udc->gadget.dev);
  2304. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2305. if (udc->vbus_active) {
  2306. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2307. hw_device_reset(udc);
  2308. } else {
  2309. pm_runtime_put_sync(&udc->gadget.dev);
  2310. goto done;
  2311. }
  2312. }
  2313. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  2314. if (retval)
  2315. pm_runtime_put_sync(&udc->gadget.dev);
  2316. done:
  2317. spin_unlock_irqrestore(&udc->lock, flags);
  2318. return retval;
  2319. }
  2320. /**
  2321. * ci13xxx_stop: unregister a gadget driver
  2322. *
  2323. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2324. */
  2325. static int ci13xxx_stop(struct usb_gadget_driver *driver)
  2326. {
  2327. struct ci13xxx *udc = _udc;
  2328. unsigned long i, flags;
  2329. trace(udc->dev, "%p", driver);
  2330. if (driver == NULL ||
  2331. driver->unbind == NULL ||
  2332. driver->setup == NULL ||
  2333. driver->disconnect == NULL ||
  2334. driver != udc->driver)
  2335. return -EINVAL;
  2336. spin_lock_irqsave(&udc->lock, flags);
  2337. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2338. udc->vbus_active) {
  2339. hw_device_state(udc, 0);
  2340. if (udc->udc_driver->notify_event)
  2341. udc->udc_driver->notify_event(udc,
  2342. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2343. spin_unlock_irqrestore(&udc->lock, flags);
  2344. _gadget_stop_activity(&udc->gadget);
  2345. spin_lock_irqsave(&udc->lock, flags);
  2346. pm_runtime_put(&udc->gadget.dev);
  2347. }
  2348. /* unbind gadget */
  2349. spin_unlock_irqrestore(&udc->lock, flags);
  2350. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2351. spin_lock_irqsave(&udc->lock, flags);
  2352. udc->gadget.dev.driver = NULL;
  2353. /* free resources */
  2354. for (i = 0; i < udc->hw_ep_max; i++) {
  2355. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2356. if (mEp->num)
  2357. list_del_init(&mEp->ep.ep_list);
  2358. if (mEp->qh.ptr != NULL)
  2359. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2360. }
  2361. udc->gadget.ep0 = NULL;
  2362. udc->driver = NULL;
  2363. spin_unlock_irqrestore(&udc->lock, flags);
  2364. if (udc->td_pool != NULL) {
  2365. dma_pool_destroy(udc->td_pool);
  2366. udc->td_pool = NULL;
  2367. }
  2368. if (udc->qh_pool != NULL) {
  2369. dma_pool_destroy(udc->qh_pool);
  2370. udc->qh_pool = NULL;
  2371. }
  2372. return 0;
  2373. }
  2374. /******************************************************************************
  2375. * BUS block
  2376. *****************************************************************************/
  2377. /**
  2378. * udc_irq: global interrupt handler
  2379. *
  2380. * This function returns IRQ_HANDLED if the IRQ has been handled
  2381. * It locks access to registers
  2382. */
  2383. static irqreturn_t udc_irq(int irq, void *data)
  2384. {
  2385. struct ci13xxx *udc = _udc;
  2386. irqreturn_t retval;
  2387. u32 intr;
  2388. trace(udc ? udc->dev : NULL, "");
  2389. if (udc == NULL) {
  2390. dev_err(udc->dev, "ENODEV");
  2391. return IRQ_HANDLED;
  2392. }
  2393. spin_lock(&udc->lock);
  2394. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2395. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  2396. USBMODE_CM_DEVICE) {
  2397. spin_unlock(&udc->lock);
  2398. return IRQ_NONE;
  2399. }
  2400. }
  2401. intr = hw_test_and_clear_intr_active(udc);
  2402. if (intr) {
  2403. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2404. isr_statistics.hndl.idx &= ISR_MASK;
  2405. isr_statistics.hndl.cnt++;
  2406. /* order defines priority - do NOT change it */
  2407. if (USBi_URI & intr) {
  2408. isr_statistics.uri++;
  2409. isr_reset_handler(udc);
  2410. }
  2411. if (USBi_PCI & intr) {
  2412. isr_statistics.pci++;
  2413. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  2414. USB_SPEED_HIGH : USB_SPEED_FULL;
  2415. if (udc->suspended && udc->driver->resume) {
  2416. spin_unlock(&udc->lock);
  2417. udc->driver->resume(&udc->gadget);
  2418. spin_lock(&udc->lock);
  2419. udc->suspended = 0;
  2420. }
  2421. }
  2422. if (USBi_UEI & intr)
  2423. isr_statistics.uei++;
  2424. if (USBi_UI & intr) {
  2425. isr_statistics.ui++;
  2426. isr_tr_complete_handler(udc);
  2427. }
  2428. if (USBi_SLI & intr) {
  2429. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2430. udc->driver->suspend) {
  2431. udc->suspended = 1;
  2432. spin_unlock(&udc->lock);
  2433. udc->driver->suspend(&udc->gadget);
  2434. spin_lock(&udc->lock);
  2435. }
  2436. isr_statistics.sli++;
  2437. }
  2438. retval = IRQ_HANDLED;
  2439. } else {
  2440. isr_statistics.none++;
  2441. retval = IRQ_NONE;
  2442. }
  2443. spin_unlock(&udc->lock);
  2444. return retval;
  2445. }
  2446. /**
  2447. * udc_release: driver release function
  2448. * @dev: device
  2449. *
  2450. * Currently does nothing
  2451. */
  2452. static void udc_release(struct device *dev)
  2453. {
  2454. trace(dev->parent, "%p", dev);
  2455. }
  2456. /**
  2457. * udc_probe: parent probe must call this to initialize UDC
  2458. * @dev: parent device
  2459. * @regs: registers base address
  2460. * @name: driver name
  2461. *
  2462. * This function returns an error code
  2463. * No interrupts active, the IRQ has not been requested yet
  2464. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2465. */
  2466. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2467. void __iomem *regs)
  2468. {
  2469. struct ci13xxx *udc;
  2470. int retval = 0;
  2471. trace(dev, "%p, %p, %p", dev, regs, driver->name);
  2472. if (dev == NULL || regs == NULL || driver == NULL ||
  2473. driver->name == NULL)
  2474. return -EINVAL;
  2475. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2476. if (udc == NULL)
  2477. return -ENOMEM;
  2478. spin_lock_init(&udc->lock);
  2479. udc->regs = regs;
  2480. udc->udc_driver = driver;
  2481. udc->gadget.ops = &usb_gadget_ops;
  2482. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2483. udc->gadget.max_speed = USB_SPEED_HIGH;
  2484. udc->gadget.is_otg = 0;
  2485. udc->gadget.name = driver->name;
  2486. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2487. udc->gadget.ep0 = NULL;
  2488. dev_set_name(&udc->gadget.dev, "gadget");
  2489. udc->gadget.dev.dma_mask = dev->dma_mask;
  2490. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2491. udc->gadget.dev.parent = dev;
  2492. udc->gadget.dev.release = udc_release;
  2493. udc->dev = dev;
  2494. retval = hw_device_init(udc, regs, driver->capoffset);
  2495. if (retval < 0)
  2496. goto free_udc;
  2497. udc->transceiver = usb_get_transceiver();
  2498. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2499. if (udc->transceiver == NULL) {
  2500. retval = -ENODEV;
  2501. goto free_udc;
  2502. }
  2503. }
  2504. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2505. retval = hw_device_reset(udc);
  2506. if (retval)
  2507. goto put_transceiver;
  2508. }
  2509. retval = device_register(&udc->gadget.dev);
  2510. if (retval) {
  2511. put_device(&udc->gadget.dev);
  2512. goto put_transceiver;
  2513. }
  2514. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2515. retval = dbg_create_files(&udc->gadget.dev);
  2516. #endif
  2517. if (retval)
  2518. goto unreg_device;
  2519. if (udc->transceiver) {
  2520. retval = otg_set_peripheral(udc->transceiver->otg,
  2521. &udc->gadget);
  2522. if (retval)
  2523. goto remove_dbg;
  2524. }
  2525. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2526. if (retval)
  2527. goto remove_trans;
  2528. pm_runtime_no_callbacks(&udc->gadget.dev);
  2529. pm_runtime_enable(&udc->gadget.dev);
  2530. _udc = udc;
  2531. return retval;
  2532. remove_trans:
  2533. if (udc->transceiver) {
  2534. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2535. usb_put_transceiver(udc->transceiver);
  2536. }
  2537. dev_err(dev, "error = %i\n", retval);
  2538. remove_dbg:
  2539. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2540. dbg_remove_files(&udc->gadget.dev);
  2541. #endif
  2542. unreg_device:
  2543. device_unregister(&udc->gadget.dev);
  2544. put_transceiver:
  2545. if (udc->transceiver)
  2546. usb_put_transceiver(udc->transceiver);
  2547. free_udc:
  2548. kfree(udc);
  2549. _udc = NULL;
  2550. return retval;
  2551. }
  2552. /**
  2553. * udc_remove: parent remove must call this to remove UDC
  2554. *
  2555. * No interrupts active, the IRQ has been released
  2556. */
  2557. static void udc_remove(void)
  2558. {
  2559. struct ci13xxx *udc = _udc;
  2560. if (udc == NULL)
  2561. return;
  2562. usb_del_gadget_udc(&udc->gadget);
  2563. if (udc->transceiver) {
  2564. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2565. usb_put_transceiver(udc->transceiver);
  2566. }
  2567. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2568. dbg_remove_files(&udc->gadget.dev);
  2569. #endif
  2570. device_unregister(&udc->gadget.dev);
  2571. kfree(udc->hw_bank.regmap);
  2572. kfree(udc);
  2573. _udc = NULL;
  2574. }
  2575. static int __devinit ci_udc_probe(struct platform_device *pdev)
  2576. {
  2577. struct device *dev = &pdev->dev;
  2578. struct ci13xxx_udc_driver *driver = dev->platform_data;
  2579. struct resource *res;
  2580. void __iomem *base;
  2581. int ret;
  2582. if (!driver) {
  2583. dev_err(dev, "platform data missing\n");
  2584. return -ENODEV;
  2585. }
  2586. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2587. if (!res) {
  2588. dev_err(dev, "missing resource\n");
  2589. return -ENODEV;
  2590. }
  2591. base = devm_request_and_ioremap(dev, res);
  2592. if (!res) {
  2593. dev_err(dev, "can't request and ioremap resource\n");
  2594. return -ENOMEM;
  2595. }
  2596. ret = udc_probe(driver, dev, base);
  2597. if (ret)
  2598. return ret;
  2599. _udc->irq = platform_get_irq(pdev, 0);
  2600. if (_udc->irq < 0) {
  2601. dev_err(dev, "missing IRQ\n");
  2602. ret = -ENODEV;
  2603. goto out;
  2604. }
  2605. ret = request_irq(_udc->irq, udc_irq, IRQF_SHARED, driver->name, _udc);
  2606. out:
  2607. if (ret)
  2608. udc_remove();
  2609. return ret;
  2610. }
  2611. static int __devexit ci_udc_remove(struct platform_device *pdev)
  2612. {
  2613. free_irq(_udc->irq, _udc);
  2614. udc_remove();
  2615. return 0;
  2616. }
  2617. static struct platform_driver ci_udc_driver = {
  2618. .probe = ci_udc_probe,
  2619. .remove = __devexit_p(ci_udc_remove),
  2620. .driver = {
  2621. .name = "ci_udc",
  2622. },
  2623. };
  2624. module_platform_driver(ci_udc_driver);
  2625. MODULE_ALIAS("platform:ci_udc");
  2626. MODULE_ALIAS("platform:ci13xxx");
  2627. MODULE_LICENSE("GPL v2");
  2628. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  2629. MODULE_DESCRIPTION("ChipIdea UDC Driver");