pci.c 56 KB

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  1. /*
  2. * PCI Bus Services, see include/linux/pci.h for further explanation.
  3. *
  4. * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
  5. * David Mosberger-Tang
  6. *
  7. * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/pci.h>
  13. #include <linux/pm.h>
  14. #include <linux/module.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/string.h>
  17. #include <linux/log2.h>
  18. #include <linux/pci-aspm.h>
  19. #include <linux/pm_wakeup.h>
  20. #include <linux/interrupt.h>
  21. #include <asm/dma.h> /* isa_dma_bridge_buggy */
  22. #include "pci.h"
  23. unsigned int pci_pm_d3_delay = 10;
  24. #ifdef CONFIG_PCI_DOMAINS
  25. int pci_domains_supported = 1;
  26. #endif
  27. #define DEFAULT_CARDBUS_IO_SIZE (256)
  28. #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
  29. /* pci=cbmemsize=nnM,cbiosize=nn can override this */
  30. unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
  31. unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
  32. /**
  33. * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  34. * @bus: pointer to PCI bus structure to search
  35. *
  36. * Given a PCI bus, returns the highest PCI bus number present in the set
  37. * including the given PCI bus and its list of child PCI buses.
  38. */
  39. unsigned char pci_bus_max_busnr(struct pci_bus* bus)
  40. {
  41. struct list_head *tmp;
  42. unsigned char max, n;
  43. max = bus->subordinate;
  44. list_for_each(tmp, &bus->children) {
  45. n = pci_bus_max_busnr(pci_bus_b(tmp));
  46. if(n > max)
  47. max = n;
  48. }
  49. return max;
  50. }
  51. EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
  52. #if 0
  53. /**
  54. * pci_max_busnr - returns maximum PCI bus number
  55. *
  56. * Returns the highest PCI bus number present in the system global list of
  57. * PCI buses.
  58. */
  59. unsigned char __devinit
  60. pci_max_busnr(void)
  61. {
  62. struct pci_bus *bus = NULL;
  63. unsigned char max, n;
  64. max = 0;
  65. while ((bus = pci_find_next_bus(bus)) != NULL) {
  66. n = pci_bus_max_busnr(bus);
  67. if(n > max)
  68. max = n;
  69. }
  70. return max;
  71. }
  72. #endif /* 0 */
  73. #define PCI_FIND_CAP_TTL 48
  74. static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
  75. u8 pos, int cap, int *ttl)
  76. {
  77. u8 id;
  78. while ((*ttl)--) {
  79. pci_bus_read_config_byte(bus, devfn, pos, &pos);
  80. if (pos < 0x40)
  81. break;
  82. pos &= ~3;
  83. pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
  84. &id);
  85. if (id == 0xff)
  86. break;
  87. if (id == cap)
  88. return pos;
  89. pos += PCI_CAP_LIST_NEXT;
  90. }
  91. return 0;
  92. }
  93. static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
  94. u8 pos, int cap)
  95. {
  96. int ttl = PCI_FIND_CAP_TTL;
  97. return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
  98. }
  99. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
  100. {
  101. return __pci_find_next_cap(dev->bus, dev->devfn,
  102. pos + PCI_CAP_LIST_NEXT, cap);
  103. }
  104. EXPORT_SYMBOL_GPL(pci_find_next_capability);
  105. static int __pci_bus_find_cap_start(struct pci_bus *bus,
  106. unsigned int devfn, u8 hdr_type)
  107. {
  108. u16 status;
  109. pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
  110. if (!(status & PCI_STATUS_CAP_LIST))
  111. return 0;
  112. switch (hdr_type) {
  113. case PCI_HEADER_TYPE_NORMAL:
  114. case PCI_HEADER_TYPE_BRIDGE:
  115. return PCI_CAPABILITY_LIST;
  116. case PCI_HEADER_TYPE_CARDBUS:
  117. return PCI_CB_CAPABILITY_LIST;
  118. default:
  119. return 0;
  120. }
  121. return 0;
  122. }
  123. /**
  124. * pci_find_capability - query for devices' capabilities
  125. * @dev: PCI device to query
  126. * @cap: capability code
  127. *
  128. * Tell if a device supports a given PCI capability.
  129. * Returns the address of the requested capability structure within the
  130. * device's PCI configuration space or 0 in case the device does not
  131. * support it. Possible values for @cap:
  132. *
  133. * %PCI_CAP_ID_PM Power Management
  134. * %PCI_CAP_ID_AGP Accelerated Graphics Port
  135. * %PCI_CAP_ID_VPD Vital Product Data
  136. * %PCI_CAP_ID_SLOTID Slot Identification
  137. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  138. * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
  139. * %PCI_CAP_ID_PCIX PCI-X
  140. * %PCI_CAP_ID_EXP PCI Express
  141. */
  142. int pci_find_capability(struct pci_dev *dev, int cap)
  143. {
  144. int pos;
  145. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  146. if (pos)
  147. pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
  148. return pos;
  149. }
  150. /**
  151. * pci_bus_find_capability - query for devices' capabilities
  152. * @bus: the PCI bus to query
  153. * @devfn: PCI device to query
  154. * @cap: capability code
  155. *
  156. * Like pci_find_capability() but works for pci devices that do not have a
  157. * pci_dev structure set up yet.
  158. *
  159. * Returns the address of the requested capability structure within the
  160. * device's PCI configuration space or 0 in case the device does not
  161. * support it.
  162. */
  163. int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
  164. {
  165. int pos;
  166. u8 hdr_type;
  167. pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
  168. pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
  169. if (pos)
  170. pos = __pci_find_next_cap(bus, devfn, pos, cap);
  171. return pos;
  172. }
  173. /**
  174. * pci_find_ext_capability - Find an extended capability
  175. * @dev: PCI device to query
  176. * @cap: capability code
  177. *
  178. * Returns the address of the requested extended capability structure
  179. * within the device's PCI configuration space or 0 if the device does
  180. * not support it. Possible values for @cap:
  181. *
  182. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  183. * %PCI_EXT_CAP_ID_VC Virtual Channel
  184. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  185. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  186. */
  187. int pci_find_ext_capability(struct pci_dev *dev, int cap)
  188. {
  189. u32 header;
  190. int ttl;
  191. int pos = PCI_CFG_SPACE_SIZE;
  192. /* minimum 8 bytes per capability */
  193. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  194. if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
  195. return 0;
  196. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  197. return 0;
  198. /*
  199. * If we have no capabilities, this is indicated by cap ID,
  200. * cap version and next pointer all being 0.
  201. */
  202. if (header == 0)
  203. return 0;
  204. while (ttl-- > 0) {
  205. if (PCI_EXT_CAP_ID(header) == cap)
  206. return pos;
  207. pos = PCI_EXT_CAP_NEXT(header);
  208. if (pos < PCI_CFG_SPACE_SIZE)
  209. break;
  210. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  211. break;
  212. }
  213. return 0;
  214. }
  215. EXPORT_SYMBOL_GPL(pci_find_ext_capability);
  216. static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
  217. {
  218. int rc, ttl = PCI_FIND_CAP_TTL;
  219. u8 cap, mask;
  220. if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
  221. mask = HT_3BIT_CAP_MASK;
  222. else
  223. mask = HT_5BIT_CAP_MASK;
  224. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
  225. PCI_CAP_ID_HT, &ttl);
  226. while (pos) {
  227. rc = pci_read_config_byte(dev, pos + 3, &cap);
  228. if (rc != PCIBIOS_SUCCESSFUL)
  229. return 0;
  230. if ((cap & mask) == ht_cap)
  231. return pos;
  232. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
  233. pos + PCI_CAP_LIST_NEXT,
  234. PCI_CAP_ID_HT, &ttl);
  235. }
  236. return 0;
  237. }
  238. /**
  239. * pci_find_next_ht_capability - query a device's Hypertransport capabilities
  240. * @dev: PCI device to query
  241. * @pos: Position from which to continue searching
  242. * @ht_cap: Hypertransport capability code
  243. *
  244. * To be used in conjunction with pci_find_ht_capability() to search for
  245. * all capabilities matching @ht_cap. @pos should always be a value returned
  246. * from pci_find_ht_capability().
  247. *
  248. * NB. To be 100% safe against broken PCI devices, the caller should take
  249. * steps to avoid an infinite loop.
  250. */
  251. int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
  252. {
  253. return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
  254. }
  255. EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
  256. /**
  257. * pci_find_ht_capability - query a device's Hypertransport capabilities
  258. * @dev: PCI device to query
  259. * @ht_cap: Hypertransport capability code
  260. *
  261. * Tell if a device supports a given Hypertransport capability.
  262. * Returns an address within the device's PCI configuration space
  263. * or 0 in case the device does not support the request capability.
  264. * The address points to the PCI capability, of type PCI_CAP_ID_HT,
  265. * which has a Hypertransport capability matching @ht_cap.
  266. */
  267. int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
  268. {
  269. int pos;
  270. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  271. if (pos)
  272. pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
  273. return pos;
  274. }
  275. EXPORT_SYMBOL_GPL(pci_find_ht_capability);
  276. /**
  277. * pci_find_parent_resource - return resource region of parent bus of given region
  278. * @dev: PCI device structure contains resources to be searched
  279. * @res: child resource record for which parent is sought
  280. *
  281. * For given resource region of given device, return the resource
  282. * region of parent bus the given region is contained in or where
  283. * it should be allocated from.
  284. */
  285. struct resource *
  286. pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
  287. {
  288. const struct pci_bus *bus = dev->bus;
  289. int i;
  290. struct resource *best = NULL;
  291. for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
  292. struct resource *r = bus->resource[i];
  293. if (!r)
  294. continue;
  295. if (res->start && !(res->start >= r->start && res->end <= r->end))
  296. continue; /* Not contained */
  297. if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
  298. continue; /* Wrong type */
  299. if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
  300. return r; /* Exact match */
  301. if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
  302. best = r; /* Approximating prefetchable by non-prefetchable */
  303. }
  304. return best;
  305. }
  306. /**
  307. * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
  308. * @dev: PCI device to have its BARs restored
  309. *
  310. * Restore the BAR values for a given device, so as to make it
  311. * accessible by its driver.
  312. */
  313. static void
  314. pci_restore_bars(struct pci_dev *dev)
  315. {
  316. int i, numres;
  317. switch (dev->hdr_type) {
  318. case PCI_HEADER_TYPE_NORMAL:
  319. numres = 6;
  320. break;
  321. case PCI_HEADER_TYPE_BRIDGE:
  322. numres = 2;
  323. break;
  324. case PCI_HEADER_TYPE_CARDBUS:
  325. numres = 1;
  326. break;
  327. default:
  328. /* Should never get here, but just in case... */
  329. return;
  330. }
  331. for (i = 0; i < numres; i ++)
  332. pci_update_resource(dev, &dev->resource[i], i);
  333. }
  334. static struct pci_platform_pm_ops *pci_platform_pm;
  335. int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
  336. {
  337. if (!ops->is_manageable || !ops->set_state || !ops->choose_state
  338. || !ops->sleep_wake || !ops->can_wakeup)
  339. return -EINVAL;
  340. pci_platform_pm = ops;
  341. return 0;
  342. }
  343. static inline bool platform_pci_power_manageable(struct pci_dev *dev)
  344. {
  345. return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
  346. }
  347. static inline int platform_pci_set_power_state(struct pci_dev *dev,
  348. pci_power_t t)
  349. {
  350. return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
  351. }
  352. static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
  353. {
  354. return pci_platform_pm ?
  355. pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
  356. }
  357. static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
  358. {
  359. return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
  360. }
  361. static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
  362. {
  363. return pci_platform_pm ?
  364. pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
  365. }
  366. /**
  367. * pci_raw_set_power_state - Use PCI PM registers to set the power state of
  368. * given PCI device
  369. * @dev: PCI device to handle.
  370. * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
  371. *
  372. * RETURN VALUE:
  373. * -EINVAL if the requested state is invalid.
  374. * -EIO if device does not support PCI PM or its PM capabilities register has a
  375. * wrong version, or device doesn't support the requested state.
  376. * 0 if device already is in the requested state.
  377. * 0 if device's power state has been successfully changed.
  378. */
  379. static int
  380. pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
  381. {
  382. u16 pmcsr;
  383. bool need_restore = false;
  384. if (!dev->pm_cap)
  385. return -EIO;
  386. if (state < PCI_D0 || state > PCI_D3hot)
  387. return -EINVAL;
  388. /* Validate current state:
  389. * Can enter D0 from any state, but if we can only go deeper
  390. * to sleep if we're already in a low power state
  391. */
  392. if (dev->current_state == state) {
  393. /* we're already there */
  394. return 0;
  395. } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
  396. && dev->current_state > state) {
  397. dev_err(&dev->dev, "invalid power transition "
  398. "(from state %d to %d)\n", dev->current_state, state);
  399. return -EINVAL;
  400. }
  401. /* check if this device supports the desired state */
  402. if ((state == PCI_D1 && !dev->d1_support)
  403. || (state == PCI_D2 && !dev->d2_support))
  404. return -EIO;
  405. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  406. /* If we're (effectively) in D3, force entire word to 0.
  407. * This doesn't affect PME_Status, disables PME_En, and
  408. * sets PowerState to 0.
  409. */
  410. switch (dev->current_state) {
  411. case PCI_D0:
  412. case PCI_D1:
  413. case PCI_D2:
  414. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  415. pmcsr |= state;
  416. break;
  417. case PCI_UNKNOWN: /* Boot-up */
  418. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
  419. && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
  420. need_restore = true;
  421. /* Fall-through: force to D0 */
  422. default:
  423. pmcsr = 0;
  424. break;
  425. }
  426. /* enter specified state */
  427. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
  428. /* Mandatory power management transition delays */
  429. /* see PCI PM 1.1 5.6.1 table 18 */
  430. if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
  431. msleep(pci_pm_d3_delay);
  432. else if (state == PCI_D2 || dev->current_state == PCI_D2)
  433. udelay(200);
  434. dev->current_state = state;
  435. /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
  436. * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
  437. * from D3hot to D0 _may_ perform an internal reset, thereby
  438. * going to "D0 Uninitialized" rather than "D0 Initialized".
  439. * For example, at least some versions of the 3c905B and the
  440. * 3c556B exhibit this behaviour.
  441. *
  442. * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
  443. * devices in a D3hot state at boot. Consequently, we need to
  444. * restore at least the BARs so that the device will be
  445. * accessible to its driver.
  446. */
  447. if (need_restore)
  448. pci_restore_bars(dev);
  449. if (dev->bus->self)
  450. pcie_aspm_pm_state_change(dev->bus->self);
  451. return 0;
  452. }
  453. /**
  454. * pci_update_current_state - Read PCI power state of given device from its
  455. * PCI PM registers and cache it
  456. * @dev: PCI device to handle.
  457. */
  458. static void pci_update_current_state(struct pci_dev *dev)
  459. {
  460. if (dev->pm_cap) {
  461. u16 pmcsr;
  462. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  463. dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
  464. }
  465. }
  466. /**
  467. * pci_set_power_state - Set the power state of a PCI device
  468. * @dev: PCI device to handle.
  469. * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
  470. *
  471. * Transition a device to a new power state, using the platform formware and/or
  472. * the device's PCI PM registers.
  473. *
  474. * RETURN VALUE:
  475. * -EINVAL if the requested state is invalid.
  476. * -EIO if device does not support PCI PM or its PM capabilities register has a
  477. * wrong version, or device doesn't support the requested state.
  478. * 0 if device already is in the requested state.
  479. * 0 if device's power state has been successfully changed.
  480. */
  481. int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  482. {
  483. int error;
  484. /* bound the state we're entering */
  485. if (state > PCI_D3hot)
  486. state = PCI_D3hot;
  487. else if (state < PCI_D0)
  488. state = PCI_D0;
  489. else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
  490. /*
  491. * If the device or the parent bridge do not support PCI PM,
  492. * ignore the request if we're doing anything other than putting
  493. * it into D0 (which would only happen on boot).
  494. */
  495. return 0;
  496. if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
  497. /*
  498. * Allow the platform to change the state, for example via ACPI
  499. * _PR0, _PS0 and some such, but do not trust it.
  500. */
  501. int ret = platform_pci_set_power_state(dev, PCI_D0);
  502. if (!ret)
  503. pci_update_current_state(dev);
  504. }
  505. /* This device is quirked not to be put into D3, so
  506. don't put it in D3 */
  507. if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
  508. return 0;
  509. error = pci_raw_set_power_state(dev, state);
  510. if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
  511. /* Allow the platform to finalize the transition */
  512. int ret = platform_pci_set_power_state(dev, state);
  513. if (!ret) {
  514. pci_update_current_state(dev);
  515. error = 0;
  516. }
  517. }
  518. return error;
  519. }
  520. /**
  521. * pci_choose_state - Choose the power state of a PCI device
  522. * @dev: PCI device to be suspended
  523. * @state: target sleep state for the whole system. This is the value
  524. * that is passed to suspend() function.
  525. *
  526. * Returns PCI power state suitable for given device and given system
  527. * message.
  528. */
  529. pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
  530. {
  531. pci_power_t ret;
  532. if (!pci_find_capability(dev, PCI_CAP_ID_PM))
  533. return PCI_D0;
  534. ret = platform_pci_choose_state(dev);
  535. if (ret != PCI_POWER_ERROR)
  536. return ret;
  537. switch (state.event) {
  538. case PM_EVENT_ON:
  539. return PCI_D0;
  540. case PM_EVENT_FREEZE:
  541. case PM_EVENT_PRETHAW:
  542. /* REVISIT both freeze and pre-thaw "should" use D0 */
  543. case PM_EVENT_SUSPEND:
  544. case PM_EVENT_HIBERNATE:
  545. return PCI_D3hot;
  546. default:
  547. dev_info(&dev->dev, "unrecognized suspend event %d\n",
  548. state.event);
  549. BUG();
  550. }
  551. return PCI_D0;
  552. }
  553. EXPORT_SYMBOL(pci_choose_state);
  554. static int pci_save_pcie_state(struct pci_dev *dev)
  555. {
  556. int pos, i = 0;
  557. struct pci_cap_saved_state *save_state;
  558. u16 *cap;
  559. int found = 0;
  560. pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  561. if (pos <= 0)
  562. return 0;
  563. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  564. if (!save_state)
  565. save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
  566. else
  567. found = 1;
  568. if (!save_state) {
  569. dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
  570. return -ENOMEM;
  571. }
  572. cap = (u16 *)&save_state->data[0];
  573. pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
  574. pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
  575. pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
  576. pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
  577. save_state->cap_nr = PCI_CAP_ID_EXP;
  578. if (!found)
  579. pci_add_saved_cap(dev, save_state);
  580. return 0;
  581. }
  582. static void pci_restore_pcie_state(struct pci_dev *dev)
  583. {
  584. int i = 0, pos;
  585. struct pci_cap_saved_state *save_state;
  586. u16 *cap;
  587. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  588. pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  589. if (!save_state || pos <= 0)
  590. return;
  591. cap = (u16 *)&save_state->data[0];
  592. pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
  593. pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
  594. pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
  595. pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
  596. }
  597. static int pci_save_pcix_state(struct pci_dev *dev)
  598. {
  599. int pos, i = 0;
  600. struct pci_cap_saved_state *save_state;
  601. u16 *cap;
  602. int found = 0;
  603. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  604. if (pos <= 0)
  605. return 0;
  606. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
  607. if (!save_state)
  608. save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
  609. else
  610. found = 1;
  611. if (!save_state) {
  612. dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
  613. return -ENOMEM;
  614. }
  615. cap = (u16 *)&save_state->data[0];
  616. pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
  617. save_state->cap_nr = PCI_CAP_ID_PCIX;
  618. if (!found)
  619. pci_add_saved_cap(dev, save_state);
  620. return 0;
  621. }
  622. static void pci_restore_pcix_state(struct pci_dev *dev)
  623. {
  624. int i = 0, pos;
  625. struct pci_cap_saved_state *save_state;
  626. u16 *cap;
  627. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
  628. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  629. if (!save_state || pos <= 0)
  630. return;
  631. cap = (u16 *)&save_state->data[0];
  632. pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
  633. }
  634. /**
  635. * pci_save_state - save the PCI configuration space of a device before suspending
  636. * @dev: - PCI device that we're dealing with
  637. */
  638. int
  639. pci_save_state(struct pci_dev *dev)
  640. {
  641. int i;
  642. /* XXX: 100% dword access ok here? */
  643. for (i = 0; i < 16; i++)
  644. pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
  645. if ((i = pci_save_pcie_state(dev)) != 0)
  646. return i;
  647. if ((i = pci_save_pcix_state(dev)) != 0)
  648. return i;
  649. return 0;
  650. }
  651. /**
  652. * pci_restore_state - Restore the saved state of a PCI device
  653. * @dev: - PCI device that we're dealing with
  654. */
  655. int
  656. pci_restore_state(struct pci_dev *dev)
  657. {
  658. int i;
  659. u32 val;
  660. /* PCI Express register must be restored first */
  661. pci_restore_pcie_state(dev);
  662. /*
  663. * The Base Address register should be programmed before the command
  664. * register(s)
  665. */
  666. for (i = 15; i >= 0; i--) {
  667. pci_read_config_dword(dev, i * 4, &val);
  668. if (val != dev->saved_config_space[i]) {
  669. dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
  670. "space at offset %#x (was %#x, writing %#x)\n",
  671. i, val, (int)dev->saved_config_space[i]);
  672. pci_write_config_dword(dev,i * 4,
  673. dev->saved_config_space[i]);
  674. }
  675. }
  676. pci_restore_pcix_state(dev);
  677. pci_restore_msi_state(dev);
  678. return 0;
  679. }
  680. static int do_pci_enable_device(struct pci_dev *dev, int bars)
  681. {
  682. int err;
  683. err = pci_set_power_state(dev, PCI_D0);
  684. if (err < 0 && err != -EIO)
  685. return err;
  686. err = pcibios_enable_device(dev, bars);
  687. if (err < 0)
  688. return err;
  689. pci_fixup_device(pci_fixup_enable, dev);
  690. return 0;
  691. }
  692. /**
  693. * pci_reenable_device - Resume abandoned device
  694. * @dev: PCI device to be resumed
  695. *
  696. * Note this function is a backend of pci_default_resume and is not supposed
  697. * to be called by normal code, write proper resume handler and use it instead.
  698. */
  699. int pci_reenable_device(struct pci_dev *dev)
  700. {
  701. if (atomic_read(&dev->enable_cnt))
  702. return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
  703. return 0;
  704. }
  705. static int __pci_enable_device_flags(struct pci_dev *dev,
  706. resource_size_t flags)
  707. {
  708. int err;
  709. int i, bars = 0;
  710. if (atomic_add_return(1, &dev->enable_cnt) > 1)
  711. return 0; /* already enabled */
  712. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  713. if (dev->resource[i].flags & flags)
  714. bars |= (1 << i);
  715. err = do_pci_enable_device(dev, bars);
  716. if (err < 0)
  717. atomic_dec(&dev->enable_cnt);
  718. return err;
  719. }
  720. /**
  721. * pci_enable_device_io - Initialize a device for use with IO space
  722. * @dev: PCI device to be initialized
  723. *
  724. * Initialize device before it's used by a driver. Ask low-level code
  725. * to enable I/O resources. Wake up the device if it was suspended.
  726. * Beware, this function can fail.
  727. */
  728. int pci_enable_device_io(struct pci_dev *dev)
  729. {
  730. return __pci_enable_device_flags(dev, IORESOURCE_IO);
  731. }
  732. /**
  733. * pci_enable_device_mem - Initialize a device for use with Memory space
  734. * @dev: PCI device to be initialized
  735. *
  736. * Initialize device before it's used by a driver. Ask low-level code
  737. * to enable Memory resources. Wake up the device if it was suspended.
  738. * Beware, this function can fail.
  739. */
  740. int pci_enable_device_mem(struct pci_dev *dev)
  741. {
  742. return __pci_enable_device_flags(dev, IORESOURCE_MEM);
  743. }
  744. /**
  745. * pci_enable_device - Initialize device before it's used by a driver.
  746. * @dev: PCI device to be initialized
  747. *
  748. * Initialize device before it's used by a driver. Ask low-level code
  749. * to enable I/O and memory. Wake up the device if it was suspended.
  750. * Beware, this function can fail.
  751. *
  752. * Note we don't actually enable the device many times if we call
  753. * this function repeatedly (we just increment the count).
  754. */
  755. int pci_enable_device(struct pci_dev *dev)
  756. {
  757. return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
  758. }
  759. /*
  760. * Managed PCI resources. This manages device on/off, intx/msi/msix
  761. * on/off and BAR regions. pci_dev itself records msi/msix status, so
  762. * there's no need to track it separately. pci_devres is initialized
  763. * when a device is enabled using managed PCI device enable interface.
  764. */
  765. struct pci_devres {
  766. unsigned int enabled:1;
  767. unsigned int pinned:1;
  768. unsigned int orig_intx:1;
  769. unsigned int restore_intx:1;
  770. u32 region_mask;
  771. };
  772. static void pcim_release(struct device *gendev, void *res)
  773. {
  774. struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
  775. struct pci_devres *this = res;
  776. int i;
  777. if (dev->msi_enabled)
  778. pci_disable_msi(dev);
  779. if (dev->msix_enabled)
  780. pci_disable_msix(dev);
  781. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  782. if (this->region_mask & (1 << i))
  783. pci_release_region(dev, i);
  784. if (this->restore_intx)
  785. pci_intx(dev, this->orig_intx);
  786. if (this->enabled && !this->pinned)
  787. pci_disable_device(dev);
  788. }
  789. static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
  790. {
  791. struct pci_devres *dr, *new_dr;
  792. dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
  793. if (dr)
  794. return dr;
  795. new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
  796. if (!new_dr)
  797. return NULL;
  798. return devres_get(&pdev->dev, new_dr, NULL, NULL);
  799. }
  800. static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
  801. {
  802. if (pci_is_managed(pdev))
  803. return devres_find(&pdev->dev, pcim_release, NULL, NULL);
  804. return NULL;
  805. }
  806. /**
  807. * pcim_enable_device - Managed pci_enable_device()
  808. * @pdev: PCI device to be initialized
  809. *
  810. * Managed pci_enable_device().
  811. */
  812. int pcim_enable_device(struct pci_dev *pdev)
  813. {
  814. struct pci_devres *dr;
  815. int rc;
  816. dr = get_pci_dr(pdev);
  817. if (unlikely(!dr))
  818. return -ENOMEM;
  819. if (dr->enabled)
  820. return 0;
  821. rc = pci_enable_device(pdev);
  822. if (!rc) {
  823. pdev->is_managed = 1;
  824. dr->enabled = 1;
  825. }
  826. return rc;
  827. }
  828. /**
  829. * pcim_pin_device - Pin managed PCI device
  830. * @pdev: PCI device to pin
  831. *
  832. * Pin managed PCI device @pdev. Pinned device won't be disabled on
  833. * driver detach. @pdev must have been enabled with
  834. * pcim_enable_device().
  835. */
  836. void pcim_pin_device(struct pci_dev *pdev)
  837. {
  838. struct pci_devres *dr;
  839. dr = find_pci_dr(pdev);
  840. WARN_ON(!dr || !dr->enabled);
  841. if (dr)
  842. dr->pinned = 1;
  843. }
  844. /**
  845. * pcibios_disable_device - disable arch specific PCI resources for device dev
  846. * @dev: the PCI device to disable
  847. *
  848. * Disables architecture specific PCI resources for the device. This
  849. * is the default implementation. Architecture implementations can
  850. * override this.
  851. */
  852. void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
  853. /**
  854. * pci_disable_device - Disable PCI device after use
  855. * @dev: PCI device to be disabled
  856. *
  857. * Signal to the system that the PCI device is not in use by the system
  858. * anymore. This only involves disabling PCI bus-mastering, if active.
  859. *
  860. * Note we don't actually disable the device until all callers of
  861. * pci_device_enable() have called pci_device_disable().
  862. */
  863. void
  864. pci_disable_device(struct pci_dev *dev)
  865. {
  866. struct pci_devres *dr;
  867. u16 pci_command;
  868. dr = find_pci_dr(dev);
  869. if (dr)
  870. dr->enabled = 0;
  871. if (atomic_sub_return(1, &dev->enable_cnt) != 0)
  872. return;
  873. pci_read_config_word(dev, PCI_COMMAND, &pci_command);
  874. if (pci_command & PCI_COMMAND_MASTER) {
  875. pci_command &= ~PCI_COMMAND_MASTER;
  876. pci_write_config_word(dev, PCI_COMMAND, pci_command);
  877. }
  878. dev->is_busmaster = 0;
  879. pcibios_disable_device(dev);
  880. }
  881. /**
  882. * pcibios_set_pcie_reset_state - set reset state for device dev
  883. * @dev: the PCI-E device reset
  884. * @state: Reset state to enter into
  885. *
  886. *
  887. * Sets the PCI-E reset state for the device. This is the default
  888. * implementation. Architecture implementations can override this.
  889. */
  890. int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
  891. enum pcie_reset_state state)
  892. {
  893. return -EINVAL;
  894. }
  895. /**
  896. * pci_set_pcie_reset_state - set reset state for device dev
  897. * @dev: the PCI-E device reset
  898. * @state: Reset state to enter into
  899. *
  900. *
  901. * Sets the PCI reset state for the device.
  902. */
  903. int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  904. {
  905. return pcibios_set_pcie_reset_state(dev, state);
  906. }
  907. /**
  908. * pci_pme_capable - check the capability of PCI device to generate PME#
  909. * @dev: PCI device to handle.
  910. * @state: PCI state from which device will issue PME#.
  911. */
  912. bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
  913. {
  914. if (!dev->pm_cap)
  915. return false;
  916. return !!(dev->pme_support & (1 << state));
  917. }
  918. /**
  919. * pci_pme_active - enable or disable PCI device's PME# function
  920. * @dev: PCI device to handle.
  921. * @enable: 'true' to enable PME# generation; 'false' to disable it.
  922. *
  923. * The caller must verify that the device is capable of generating PME# before
  924. * calling this function with @enable equal to 'true'.
  925. */
  926. void pci_pme_active(struct pci_dev *dev, bool enable)
  927. {
  928. u16 pmcsr;
  929. if (!dev->pm_cap)
  930. return;
  931. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  932. /* Clear PME_Status by writing 1 to it and enable PME# */
  933. pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
  934. if (!enable)
  935. pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
  936. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
  937. dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
  938. enable ? "enabled" : "disabled");
  939. }
  940. /**
  941. * pci_enable_wake - enable PCI device as wakeup event source
  942. * @dev: PCI device affected
  943. * @state: PCI state from which device will issue wakeup events
  944. * @enable: True to enable event generation; false to disable
  945. *
  946. * This enables the device as a wakeup event source, or disables it.
  947. * When such events involves platform-specific hooks, those hooks are
  948. * called automatically by this routine.
  949. *
  950. * Devices with legacy power management (no standard PCI PM capabilities)
  951. * always require such platform hooks.
  952. *
  953. * RETURN VALUE:
  954. * 0 is returned on success
  955. * -EINVAL is returned if device is not supposed to wake up the system
  956. * Error code depending on the platform is returned if both the platform and
  957. * the native mechanism fail to enable the generation of wake-up events
  958. */
  959. int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
  960. {
  961. int error = 0;
  962. bool pme_done = false;
  963. if (!device_may_wakeup(&dev->dev))
  964. return -EINVAL;
  965. /*
  966. * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
  967. * Anderson we should be doing PME# wake enable followed by ACPI wake
  968. * enable. To disable wake-up we call the platform first, for symmetry.
  969. */
  970. if (!enable && platform_pci_can_wakeup(dev))
  971. error = platform_pci_sleep_wake(dev, false);
  972. if (!enable || pci_pme_capable(dev, state)) {
  973. pci_pme_active(dev, enable);
  974. pme_done = true;
  975. }
  976. if (enable && platform_pci_can_wakeup(dev))
  977. error = platform_pci_sleep_wake(dev, true);
  978. return pme_done ? 0 : error;
  979. }
  980. /**
  981. * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
  982. * @dev: PCI device to prepare
  983. * @enable: True to enable wake-up event generation; false to disable
  984. *
  985. * Many drivers want the device to wake up the system from D3_hot or D3_cold
  986. * and this function allows them to set that up cleanly - pci_enable_wake()
  987. * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
  988. * ordering constraints.
  989. *
  990. * This function only returns error code if the device is not capable of
  991. * generating PME# from both D3_hot and D3_cold, and the platform is unable to
  992. * enable wake-up power for it.
  993. */
  994. int pci_wake_from_d3(struct pci_dev *dev, bool enable)
  995. {
  996. return pci_pme_capable(dev, PCI_D3cold) ?
  997. pci_enable_wake(dev, PCI_D3cold, enable) :
  998. pci_enable_wake(dev, PCI_D3hot, enable);
  999. }
  1000. /**
  1001. * pci_target_state - find an appropriate low power state for a given PCI dev
  1002. * @dev: PCI device
  1003. *
  1004. * Use underlying platform code to find a supported low power state for @dev.
  1005. * If the platform can't manage @dev, return the deepest state from which it
  1006. * can generate wake events, based on any available PME info.
  1007. */
  1008. pci_power_t pci_target_state(struct pci_dev *dev)
  1009. {
  1010. pci_power_t target_state = PCI_D3hot;
  1011. if (platform_pci_power_manageable(dev)) {
  1012. /*
  1013. * Call the platform to choose the target state of the device
  1014. * and enable wake-up from this state if supported.
  1015. */
  1016. pci_power_t state = platform_pci_choose_state(dev);
  1017. switch (state) {
  1018. case PCI_POWER_ERROR:
  1019. case PCI_UNKNOWN:
  1020. break;
  1021. case PCI_D1:
  1022. case PCI_D2:
  1023. if (pci_no_d1d2(dev))
  1024. break;
  1025. default:
  1026. target_state = state;
  1027. }
  1028. } else if (device_may_wakeup(&dev->dev)) {
  1029. /*
  1030. * Find the deepest state from which the device can generate
  1031. * wake-up events, make it the target state and enable device
  1032. * to generate PME#.
  1033. */
  1034. if (!dev->pm_cap)
  1035. return PCI_POWER_ERROR;
  1036. if (dev->pme_support) {
  1037. while (target_state
  1038. && !(dev->pme_support & (1 << target_state)))
  1039. target_state--;
  1040. }
  1041. }
  1042. return target_state;
  1043. }
  1044. /**
  1045. * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
  1046. * @dev: Device to handle.
  1047. *
  1048. * Choose the power state appropriate for the device depending on whether
  1049. * it can wake up the system and/or is power manageable by the platform
  1050. * (PCI_D3hot is the default) and put the device into that state.
  1051. */
  1052. int pci_prepare_to_sleep(struct pci_dev *dev)
  1053. {
  1054. pci_power_t target_state = pci_target_state(dev);
  1055. int error;
  1056. if (target_state == PCI_POWER_ERROR)
  1057. return -EIO;
  1058. pci_enable_wake(dev, target_state, true);
  1059. error = pci_set_power_state(dev, target_state);
  1060. if (error)
  1061. pci_enable_wake(dev, target_state, false);
  1062. return error;
  1063. }
  1064. /**
  1065. * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
  1066. * @dev: Device to handle.
  1067. *
  1068. * Disable device's sytem wake-up capability and put it into D0.
  1069. */
  1070. int pci_back_from_sleep(struct pci_dev *dev)
  1071. {
  1072. pci_enable_wake(dev, PCI_D0, false);
  1073. return pci_set_power_state(dev, PCI_D0);
  1074. }
  1075. /**
  1076. * pci_pm_init - Initialize PM functions of given PCI device
  1077. * @dev: PCI device to handle.
  1078. */
  1079. void pci_pm_init(struct pci_dev *dev)
  1080. {
  1081. int pm;
  1082. u16 pmc;
  1083. dev->pm_cap = 0;
  1084. /* find PCI PM capability in list */
  1085. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  1086. if (!pm)
  1087. return;
  1088. /* Check device's ability to generate PME# */
  1089. pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
  1090. if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
  1091. dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
  1092. pmc & PCI_PM_CAP_VER_MASK);
  1093. return;
  1094. }
  1095. dev->pm_cap = pm;
  1096. dev->d1_support = false;
  1097. dev->d2_support = false;
  1098. if (!pci_no_d1d2(dev)) {
  1099. if (pmc & PCI_PM_CAP_D1)
  1100. dev->d1_support = true;
  1101. if (pmc & PCI_PM_CAP_D2)
  1102. dev->d2_support = true;
  1103. if (dev->d1_support || dev->d2_support)
  1104. dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
  1105. dev->d1_support ? " D1" : "",
  1106. dev->d2_support ? " D2" : "");
  1107. }
  1108. pmc &= PCI_PM_CAP_PME_MASK;
  1109. if (pmc) {
  1110. dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
  1111. (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
  1112. (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
  1113. (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
  1114. (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
  1115. (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
  1116. dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
  1117. /*
  1118. * Make device's PM flags reflect the wake-up capability, but
  1119. * let the user space enable it to wake up the system as needed.
  1120. */
  1121. device_set_wakeup_capable(&dev->dev, true);
  1122. device_set_wakeup_enable(&dev->dev, false);
  1123. /* Disable the PME# generation functionality */
  1124. pci_pme_active(dev, false);
  1125. } else {
  1126. dev->pme_support = 0;
  1127. }
  1128. }
  1129. /**
  1130. * pci_enable_ari - enable ARI forwarding if hardware support it
  1131. * @dev: the PCI device
  1132. */
  1133. void pci_enable_ari(struct pci_dev *dev)
  1134. {
  1135. int pos;
  1136. u32 cap;
  1137. u16 ctrl;
  1138. struct pci_dev *bridge;
  1139. if (!dev->is_pcie || dev->devfn)
  1140. return;
  1141. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
  1142. if (!pos)
  1143. return;
  1144. bridge = dev->bus->self;
  1145. if (!bridge || !bridge->is_pcie)
  1146. return;
  1147. pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
  1148. if (!pos)
  1149. return;
  1150. pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
  1151. if (!(cap & PCI_EXP_DEVCAP2_ARI))
  1152. return;
  1153. pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
  1154. ctrl |= PCI_EXP_DEVCTL2_ARI;
  1155. pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
  1156. bridge->ari_enabled = 1;
  1157. }
  1158. int
  1159. pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
  1160. {
  1161. u8 pin;
  1162. pin = dev->pin;
  1163. if (!pin)
  1164. return -1;
  1165. pin--;
  1166. while (dev->bus->self) {
  1167. pin = (pin + PCI_SLOT(dev->devfn)) % 4;
  1168. dev = dev->bus->self;
  1169. }
  1170. *bridge = dev;
  1171. return pin;
  1172. }
  1173. /**
  1174. * pci_release_region - Release a PCI bar
  1175. * @pdev: PCI device whose resources were previously reserved by pci_request_region
  1176. * @bar: BAR to release
  1177. *
  1178. * Releases the PCI I/O and memory resources previously reserved by a
  1179. * successful call to pci_request_region. Call this function only
  1180. * after all use of the PCI regions has ceased.
  1181. */
  1182. void pci_release_region(struct pci_dev *pdev, int bar)
  1183. {
  1184. struct pci_devres *dr;
  1185. if (pci_resource_len(pdev, bar) == 0)
  1186. return;
  1187. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
  1188. release_region(pci_resource_start(pdev, bar),
  1189. pci_resource_len(pdev, bar));
  1190. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
  1191. release_mem_region(pci_resource_start(pdev, bar),
  1192. pci_resource_len(pdev, bar));
  1193. dr = find_pci_dr(pdev);
  1194. if (dr)
  1195. dr->region_mask &= ~(1 << bar);
  1196. }
  1197. /**
  1198. * pci_request_region - Reserved PCI I/O and memory resource
  1199. * @pdev: PCI device whose resources are to be reserved
  1200. * @bar: BAR to be reserved
  1201. * @res_name: Name to be associated with resource.
  1202. *
  1203. * Mark the PCI region associated with PCI device @pdev BR @bar as
  1204. * being reserved by owner @res_name. Do not access any
  1205. * address inside the PCI regions unless this call returns
  1206. * successfully.
  1207. *
  1208. * Returns 0 on success, or %EBUSY on error. A warning
  1209. * message is also printed on failure.
  1210. */
  1211. int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
  1212. {
  1213. struct pci_devres *dr;
  1214. if (pci_resource_len(pdev, bar) == 0)
  1215. return 0;
  1216. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
  1217. if (!request_region(pci_resource_start(pdev, bar),
  1218. pci_resource_len(pdev, bar), res_name))
  1219. goto err_out;
  1220. }
  1221. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
  1222. if (!request_mem_region(pci_resource_start(pdev, bar),
  1223. pci_resource_len(pdev, bar), res_name))
  1224. goto err_out;
  1225. }
  1226. dr = find_pci_dr(pdev);
  1227. if (dr)
  1228. dr->region_mask |= 1 << bar;
  1229. return 0;
  1230. err_out:
  1231. dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
  1232. bar,
  1233. pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
  1234. &pdev->resource[bar]);
  1235. return -EBUSY;
  1236. }
  1237. /**
  1238. * pci_release_selected_regions - Release selected PCI I/O and memory resources
  1239. * @pdev: PCI device whose resources were previously reserved
  1240. * @bars: Bitmask of BARs to be released
  1241. *
  1242. * Release selected PCI I/O and memory resources previously reserved.
  1243. * Call this function only after all use of the PCI regions has ceased.
  1244. */
  1245. void pci_release_selected_regions(struct pci_dev *pdev, int bars)
  1246. {
  1247. int i;
  1248. for (i = 0; i < 6; i++)
  1249. if (bars & (1 << i))
  1250. pci_release_region(pdev, i);
  1251. }
  1252. /**
  1253. * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
  1254. * @pdev: PCI device whose resources are to be reserved
  1255. * @bars: Bitmask of BARs to be requested
  1256. * @res_name: Name to be associated with resource
  1257. */
  1258. int pci_request_selected_regions(struct pci_dev *pdev, int bars,
  1259. const char *res_name)
  1260. {
  1261. int i;
  1262. for (i = 0; i < 6; i++)
  1263. if (bars & (1 << i))
  1264. if(pci_request_region(pdev, i, res_name))
  1265. goto err_out;
  1266. return 0;
  1267. err_out:
  1268. while(--i >= 0)
  1269. if (bars & (1 << i))
  1270. pci_release_region(pdev, i);
  1271. return -EBUSY;
  1272. }
  1273. /**
  1274. * pci_release_regions - Release reserved PCI I/O and memory resources
  1275. * @pdev: PCI device whose resources were previously reserved by pci_request_regions
  1276. *
  1277. * Releases all PCI I/O and memory resources previously reserved by a
  1278. * successful call to pci_request_regions. Call this function only
  1279. * after all use of the PCI regions has ceased.
  1280. */
  1281. void pci_release_regions(struct pci_dev *pdev)
  1282. {
  1283. pci_release_selected_regions(pdev, (1 << 6) - 1);
  1284. }
  1285. /**
  1286. * pci_request_regions - Reserved PCI I/O and memory resources
  1287. * @pdev: PCI device whose resources are to be reserved
  1288. * @res_name: Name to be associated with resource.
  1289. *
  1290. * Mark all PCI regions associated with PCI device @pdev as
  1291. * being reserved by owner @res_name. Do not access any
  1292. * address inside the PCI regions unless this call returns
  1293. * successfully.
  1294. *
  1295. * Returns 0 on success, or %EBUSY on error. A warning
  1296. * message is also printed on failure.
  1297. */
  1298. int pci_request_regions(struct pci_dev *pdev, const char *res_name)
  1299. {
  1300. return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
  1301. }
  1302. /**
  1303. * pci_set_master - enables bus-mastering for device dev
  1304. * @dev: the PCI device to enable
  1305. *
  1306. * Enables bus-mastering on the device and calls pcibios_set_master()
  1307. * to do the needed arch specific settings.
  1308. */
  1309. void
  1310. pci_set_master(struct pci_dev *dev)
  1311. {
  1312. u16 cmd;
  1313. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1314. if (! (cmd & PCI_COMMAND_MASTER)) {
  1315. dev_dbg(&dev->dev, "enabling bus mastering\n");
  1316. cmd |= PCI_COMMAND_MASTER;
  1317. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1318. }
  1319. dev->is_busmaster = 1;
  1320. pcibios_set_master(dev);
  1321. }
  1322. #ifdef PCI_DISABLE_MWI
  1323. int pci_set_mwi(struct pci_dev *dev)
  1324. {
  1325. return 0;
  1326. }
  1327. int pci_try_set_mwi(struct pci_dev *dev)
  1328. {
  1329. return 0;
  1330. }
  1331. void pci_clear_mwi(struct pci_dev *dev)
  1332. {
  1333. }
  1334. #else
  1335. #ifndef PCI_CACHE_LINE_BYTES
  1336. #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
  1337. #endif
  1338. /* This can be overridden by arch code. */
  1339. /* Don't forget this is measured in 32-bit words, not bytes */
  1340. u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
  1341. /**
  1342. * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
  1343. * @dev: the PCI device for which MWI is to be enabled
  1344. *
  1345. * Helper function for pci_set_mwi.
  1346. * Originally copied from drivers/net/acenic.c.
  1347. * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
  1348. *
  1349. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  1350. */
  1351. static int
  1352. pci_set_cacheline_size(struct pci_dev *dev)
  1353. {
  1354. u8 cacheline_size;
  1355. if (!pci_cache_line_size)
  1356. return -EINVAL; /* The system doesn't support MWI. */
  1357. /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
  1358. equal to or multiple of the right value. */
  1359. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  1360. if (cacheline_size >= pci_cache_line_size &&
  1361. (cacheline_size % pci_cache_line_size) == 0)
  1362. return 0;
  1363. /* Write the correct value. */
  1364. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
  1365. /* Read it back. */
  1366. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  1367. if (cacheline_size == pci_cache_line_size)
  1368. return 0;
  1369. dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
  1370. "supported\n", pci_cache_line_size << 2);
  1371. return -EINVAL;
  1372. }
  1373. /**
  1374. * pci_set_mwi - enables memory-write-invalidate PCI transaction
  1375. * @dev: the PCI device for which MWI is enabled
  1376. *
  1377. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
  1378. *
  1379. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  1380. */
  1381. int
  1382. pci_set_mwi(struct pci_dev *dev)
  1383. {
  1384. int rc;
  1385. u16 cmd;
  1386. rc = pci_set_cacheline_size(dev);
  1387. if (rc)
  1388. return rc;
  1389. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1390. if (! (cmd & PCI_COMMAND_INVALIDATE)) {
  1391. dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
  1392. cmd |= PCI_COMMAND_INVALIDATE;
  1393. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1394. }
  1395. return 0;
  1396. }
  1397. /**
  1398. * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
  1399. * @dev: the PCI device for which MWI is enabled
  1400. *
  1401. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
  1402. * Callers are not required to check the return value.
  1403. *
  1404. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  1405. */
  1406. int pci_try_set_mwi(struct pci_dev *dev)
  1407. {
  1408. int rc = pci_set_mwi(dev);
  1409. return rc;
  1410. }
  1411. /**
  1412. * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
  1413. * @dev: the PCI device to disable
  1414. *
  1415. * Disables PCI Memory-Write-Invalidate transaction on the device
  1416. */
  1417. void
  1418. pci_clear_mwi(struct pci_dev *dev)
  1419. {
  1420. u16 cmd;
  1421. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1422. if (cmd & PCI_COMMAND_INVALIDATE) {
  1423. cmd &= ~PCI_COMMAND_INVALIDATE;
  1424. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1425. }
  1426. }
  1427. #endif /* ! PCI_DISABLE_MWI */
  1428. /**
  1429. * pci_intx - enables/disables PCI INTx for device dev
  1430. * @pdev: the PCI device to operate on
  1431. * @enable: boolean: whether to enable or disable PCI INTx
  1432. *
  1433. * Enables/disables PCI INTx for device dev
  1434. */
  1435. void
  1436. pci_intx(struct pci_dev *pdev, int enable)
  1437. {
  1438. u16 pci_command, new;
  1439. pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
  1440. if (enable) {
  1441. new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
  1442. } else {
  1443. new = pci_command | PCI_COMMAND_INTX_DISABLE;
  1444. }
  1445. if (new != pci_command) {
  1446. struct pci_devres *dr;
  1447. pci_write_config_word(pdev, PCI_COMMAND, new);
  1448. dr = find_pci_dr(pdev);
  1449. if (dr && !dr->restore_intx) {
  1450. dr->restore_intx = 1;
  1451. dr->orig_intx = !enable;
  1452. }
  1453. }
  1454. }
  1455. /**
  1456. * pci_msi_off - disables any msi or msix capabilities
  1457. * @dev: the PCI device to operate on
  1458. *
  1459. * If you want to use msi see pci_enable_msi and friends.
  1460. * This is a lower level primitive that allows us to disable
  1461. * msi operation at the device level.
  1462. */
  1463. void pci_msi_off(struct pci_dev *dev)
  1464. {
  1465. int pos;
  1466. u16 control;
  1467. pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
  1468. if (pos) {
  1469. pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  1470. control &= ~PCI_MSI_FLAGS_ENABLE;
  1471. pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  1472. }
  1473. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  1474. if (pos) {
  1475. pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  1476. control &= ~PCI_MSIX_FLAGS_ENABLE;
  1477. pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
  1478. }
  1479. }
  1480. #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
  1481. /*
  1482. * These can be overridden by arch-specific implementations
  1483. */
  1484. int
  1485. pci_set_dma_mask(struct pci_dev *dev, u64 mask)
  1486. {
  1487. if (!pci_dma_supported(dev, mask))
  1488. return -EIO;
  1489. dev->dma_mask = mask;
  1490. return 0;
  1491. }
  1492. int
  1493. pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
  1494. {
  1495. if (!pci_dma_supported(dev, mask))
  1496. return -EIO;
  1497. dev->dev.coherent_dma_mask = mask;
  1498. return 0;
  1499. }
  1500. #endif
  1501. #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
  1502. int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
  1503. {
  1504. return dma_set_max_seg_size(&dev->dev, size);
  1505. }
  1506. EXPORT_SYMBOL(pci_set_dma_max_seg_size);
  1507. #endif
  1508. #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
  1509. int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
  1510. {
  1511. return dma_set_seg_boundary(&dev->dev, mask);
  1512. }
  1513. EXPORT_SYMBOL(pci_set_dma_seg_boundary);
  1514. #endif
  1515. static int __pcie_flr(struct pci_dev *dev, int probe)
  1516. {
  1517. u16 status;
  1518. u32 cap;
  1519. int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  1520. if (!exppos)
  1521. return -ENOTTY;
  1522. pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap);
  1523. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1524. return -ENOTTY;
  1525. if (probe)
  1526. return 0;
  1527. pci_block_user_cfg_access(dev);
  1528. /* Wait for Transaction Pending bit clean */
  1529. msleep(100);
  1530. pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
  1531. if (status & PCI_EXP_DEVSTA_TRPND) {
  1532. dev_info(&dev->dev, "Busy after 100ms while trying to reset; "
  1533. "sleeping for 1 second\n");
  1534. ssleep(1);
  1535. pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
  1536. if (status & PCI_EXP_DEVSTA_TRPND)
  1537. dev_info(&dev->dev, "Still busy after 1s; "
  1538. "proceeding with reset anyway\n");
  1539. }
  1540. pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL,
  1541. PCI_EXP_DEVCTL_BCR_FLR);
  1542. mdelay(100);
  1543. pci_unblock_user_cfg_access(dev);
  1544. return 0;
  1545. }
  1546. static int __pci_af_flr(struct pci_dev *dev, int probe)
  1547. {
  1548. int cappos = pci_find_capability(dev, PCI_CAP_ID_AF);
  1549. u8 status;
  1550. u8 cap;
  1551. if (!cappos)
  1552. return -ENOTTY;
  1553. pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap);
  1554. if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
  1555. return -ENOTTY;
  1556. if (probe)
  1557. return 0;
  1558. pci_block_user_cfg_access(dev);
  1559. /* Wait for Transaction Pending bit clean */
  1560. msleep(100);
  1561. pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
  1562. if (status & PCI_AF_STATUS_TP) {
  1563. dev_info(&dev->dev, "Busy after 100ms while trying to"
  1564. " reset; sleeping for 1 second\n");
  1565. ssleep(1);
  1566. pci_read_config_byte(dev,
  1567. cappos + PCI_AF_STATUS, &status);
  1568. if (status & PCI_AF_STATUS_TP)
  1569. dev_info(&dev->dev, "Still busy after 1s; "
  1570. "proceeding with reset anyway\n");
  1571. }
  1572. pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
  1573. mdelay(100);
  1574. pci_unblock_user_cfg_access(dev);
  1575. return 0;
  1576. }
  1577. static int __pci_reset_function(struct pci_dev *pdev, int probe)
  1578. {
  1579. int res;
  1580. res = __pcie_flr(pdev, probe);
  1581. if (res != -ENOTTY)
  1582. return res;
  1583. res = __pci_af_flr(pdev, probe);
  1584. if (res != -ENOTTY)
  1585. return res;
  1586. return res;
  1587. }
  1588. /**
  1589. * pci_execute_reset_function() - Reset a PCI device function
  1590. * @dev: Device function to reset
  1591. *
  1592. * Some devices allow an individual function to be reset without affecting
  1593. * other functions in the same device. The PCI device must be responsive
  1594. * to PCI config space in order to use this function.
  1595. *
  1596. * The device function is presumed to be unused when this function is called.
  1597. * Resetting the device will make the contents of PCI configuration space
  1598. * random, so any caller of this must be prepared to reinitialise the
  1599. * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
  1600. * etc.
  1601. *
  1602. * Returns 0 if the device function was successfully reset or -ENOTTY if the
  1603. * device doesn't support resetting a single function.
  1604. */
  1605. int pci_execute_reset_function(struct pci_dev *dev)
  1606. {
  1607. return __pci_reset_function(dev, 0);
  1608. }
  1609. EXPORT_SYMBOL_GPL(pci_execute_reset_function);
  1610. /**
  1611. * pci_reset_function() - quiesce and reset a PCI device function
  1612. * @dev: Device function to reset
  1613. *
  1614. * Some devices allow an individual function to be reset without affecting
  1615. * other functions in the same device. The PCI device must be responsive
  1616. * to PCI config space in order to use this function.
  1617. *
  1618. * This function does not just reset the PCI portion of a device, but
  1619. * clears all the state associated with the device. This function differs
  1620. * from pci_execute_reset_function in that it saves and restores device state
  1621. * over the reset.
  1622. *
  1623. * Returns 0 if the device function was successfully reset or -ENOTTY if the
  1624. * device doesn't support resetting a single function.
  1625. */
  1626. int pci_reset_function(struct pci_dev *dev)
  1627. {
  1628. int r = __pci_reset_function(dev, 1);
  1629. if (r < 0)
  1630. return r;
  1631. if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
  1632. disable_irq(dev->irq);
  1633. pci_save_state(dev);
  1634. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  1635. r = pci_execute_reset_function(dev);
  1636. pci_restore_state(dev);
  1637. if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
  1638. enable_irq(dev->irq);
  1639. return r;
  1640. }
  1641. EXPORT_SYMBOL_GPL(pci_reset_function);
  1642. /**
  1643. * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
  1644. * @dev: PCI device to query
  1645. *
  1646. * Returns mmrbc: maximum designed memory read count in bytes
  1647. * or appropriate error value.
  1648. */
  1649. int pcix_get_max_mmrbc(struct pci_dev *dev)
  1650. {
  1651. int err, cap;
  1652. u32 stat;
  1653. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  1654. if (!cap)
  1655. return -EINVAL;
  1656. err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
  1657. if (err)
  1658. return -EINVAL;
  1659. return (stat & PCI_X_STATUS_MAX_READ) >> 12;
  1660. }
  1661. EXPORT_SYMBOL(pcix_get_max_mmrbc);
  1662. /**
  1663. * pcix_get_mmrbc - get PCI-X maximum memory read byte count
  1664. * @dev: PCI device to query
  1665. *
  1666. * Returns mmrbc: maximum memory read count in bytes
  1667. * or appropriate error value.
  1668. */
  1669. int pcix_get_mmrbc(struct pci_dev *dev)
  1670. {
  1671. int ret, cap;
  1672. u32 cmd;
  1673. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  1674. if (!cap)
  1675. return -EINVAL;
  1676. ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
  1677. if (!ret)
  1678. ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
  1679. return ret;
  1680. }
  1681. EXPORT_SYMBOL(pcix_get_mmrbc);
  1682. /**
  1683. * pcix_set_mmrbc - set PCI-X maximum memory read byte count
  1684. * @dev: PCI device to query
  1685. * @mmrbc: maximum memory read count in bytes
  1686. * valid values are 512, 1024, 2048, 4096
  1687. *
  1688. * If possible sets maximum memory read byte count, some bridges have erratas
  1689. * that prevent this.
  1690. */
  1691. int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
  1692. {
  1693. int cap, err = -EINVAL;
  1694. u32 stat, cmd, v, o;
  1695. if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
  1696. goto out;
  1697. v = ffs(mmrbc) - 10;
  1698. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  1699. if (!cap)
  1700. goto out;
  1701. err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
  1702. if (err)
  1703. goto out;
  1704. if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
  1705. return -E2BIG;
  1706. err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
  1707. if (err)
  1708. goto out;
  1709. o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
  1710. if (o != v) {
  1711. if (v > o && dev->bus &&
  1712. (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
  1713. return -EIO;
  1714. cmd &= ~PCI_X_CMD_MAX_READ;
  1715. cmd |= v << 2;
  1716. err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
  1717. }
  1718. out:
  1719. return err;
  1720. }
  1721. EXPORT_SYMBOL(pcix_set_mmrbc);
  1722. /**
  1723. * pcie_get_readrq - get PCI Express read request size
  1724. * @dev: PCI device to query
  1725. *
  1726. * Returns maximum memory read request in bytes
  1727. * or appropriate error value.
  1728. */
  1729. int pcie_get_readrq(struct pci_dev *dev)
  1730. {
  1731. int ret, cap;
  1732. u16 ctl;
  1733. cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
  1734. if (!cap)
  1735. return -EINVAL;
  1736. ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
  1737. if (!ret)
  1738. ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
  1739. return ret;
  1740. }
  1741. EXPORT_SYMBOL(pcie_get_readrq);
  1742. /**
  1743. * pcie_set_readrq - set PCI Express maximum memory read request
  1744. * @dev: PCI device to query
  1745. * @rq: maximum memory read count in bytes
  1746. * valid values are 128, 256, 512, 1024, 2048, 4096
  1747. *
  1748. * If possible sets maximum read byte count
  1749. */
  1750. int pcie_set_readrq(struct pci_dev *dev, int rq)
  1751. {
  1752. int cap, err = -EINVAL;
  1753. u16 ctl, v;
  1754. if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
  1755. goto out;
  1756. v = (ffs(rq) - 8) << 12;
  1757. cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
  1758. if (!cap)
  1759. goto out;
  1760. err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
  1761. if (err)
  1762. goto out;
  1763. if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
  1764. ctl &= ~PCI_EXP_DEVCTL_READRQ;
  1765. ctl |= v;
  1766. err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
  1767. }
  1768. out:
  1769. return err;
  1770. }
  1771. EXPORT_SYMBOL(pcie_set_readrq);
  1772. /**
  1773. * pci_select_bars - Make BAR mask from the type of resource
  1774. * @dev: the PCI device for which BAR mask is made
  1775. * @flags: resource type mask to be selected
  1776. *
  1777. * This helper routine makes bar mask from the type of resource.
  1778. */
  1779. int pci_select_bars(struct pci_dev *dev, unsigned long flags)
  1780. {
  1781. int i, bars = 0;
  1782. for (i = 0; i < PCI_NUM_RESOURCES; i++)
  1783. if (pci_resource_flags(dev, i) & flags)
  1784. bars |= (1 << i);
  1785. return bars;
  1786. }
  1787. static void __devinit pci_no_domains(void)
  1788. {
  1789. #ifdef CONFIG_PCI_DOMAINS
  1790. pci_domains_supported = 0;
  1791. #endif
  1792. }
  1793. /**
  1794. * pci_ext_cfg_enabled - can we access extended PCI config space?
  1795. * @dev: The PCI device of the root bridge.
  1796. *
  1797. * Returns 1 if we can access PCI extended config space (offsets
  1798. * greater than 0xff). This is the default implementation. Architecture
  1799. * implementations can override this.
  1800. */
  1801. int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
  1802. {
  1803. return 1;
  1804. }
  1805. static int __devinit pci_init(void)
  1806. {
  1807. struct pci_dev *dev = NULL;
  1808. while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
  1809. pci_fixup_device(pci_fixup_final, dev);
  1810. }
  1811. msi_init();
  1812. return 0;
  1813. }
  1814. static int __init pci_setup(char *str)
  1815. {
  1816. while (str) {
  1817. char *k = strchr(str, ',');
  1818. if (k)
  1819. *k++ = 0;
  1820. if (*str && (str = pcibios_setup(str)) && *str) {
  1821. if (!strcmp(str, "nomsi")) {
  1822. pci_no_msi();
  1823. } else if (!strcmp(str, "noaer")) {
  1824. pci_no_aer();
  1825. } else if (!strcmp(str, "nodomains")) {
  1826. pci_no_domains();
  1827. } else if (!strncmp(str, "cbiosize=", 9)) {
  1828. pci_cardbus_io_size = memparse(str + 9, &str);
  1829. } else if (!strncmp(str, "cbmemsize=", 10)) {
  1830. pci_cardbus_mem_size = memparse(str + 10, &str);
  1831. } else {
  1832. printk(KERN_ERR "PCI: Unknown option `%s'\n",
  1833. str);
  1834. }
  1835. }
  1836. str = k;
  1837. }
  1838. return 0;
  1839. }
  1840. early_param("pci", pci_setup);
  1841. device_initcall(pci_init);
  1842. EXPORT_SYMBOL(pci_reenable_device);
  1843. EXPORT_SYMBOL(pci_enable_device_io);
  1844. EXPORT_SYMBOL(pci_enable_device_mem);
  1845. EXPORT_SYMBOL(pci_enable_device);
  1846. EXPORT_SYMBOL(pcim_enable_device);
  1847. EXPORT_SYMBOL(pcim_pin_device);
  1848. EXPORT_SYMBOL(pci_disable_device);
  1849. EXPORT_SYMBOL(pci_find_capability);
  1850. EXPORT_SYMBOL(pci_bus_find_capability);
  1851. EXPORT_SYMBOL(pci_release_regions);
  1852. EXPORT_SYMBOL(pci_request_regions);
  1853. EXPORT_SYMBOL(pci_release_region);
  1854. EXPORT_SYMBOL(pci_request_region);
  1855. EXPORT_SYMBOL(pci_release_selected_regions);
  1856. EXPORT_SYMBOL(pci_request_selected_regions);
  1857. EXPORT_SYMBOL(pci_set_master);
  1858. EXPORT_SYMBOL(pci_set_mwi);
  1859. EXPORT_SYMBOL(pci_try_set_mwi);
  1860. EXPORT_SYMBOL(pci_clear_mwi);
  1861. EXPORT_SYMBOL_GPL(pci_intx);
  1862. EXPORT_SYMBOL(pci_set_dma_mask);
  1863. EXPORT_SYMBOL(pci_set_consistent_dma_mask);
  1864. EXPORT_SYMBOL(pci_assign_resource);
  1865. EXPORT_SYMBOL(pci_find_parent_resource);
  1866. EXPORT_SYMBOL(pci_select_bars);
  1867. EXPORT_SYMBOL(pci_set_power_state);
  1868. EXPORT_SYMBOL(pci_save_state);
  1869. EXPORT_SYMBOL(pci_restore_state);
  1870. EXPORT_SYMBOL(pci_pme_capable);
  1871. EXPORT_SYMBOL(pci_pme_active);
  1872. EXPORT_SYMBOL(pci_enable_wake);
  1873. EXPORT_SYMBOL(pci_wake_from_d3);
  1874. EXPORT_SYMBOL(pci_target_state);
  1875. EXPORT_SYMBOL(pci_prepare_to_sleep);
  1876. EXPORT_SYMBOL(pci_back_from_sleep);
  1877. EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);