resource_tracker.c 67 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. u32 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. };
  70. enum res_qp_states {
  71. RES_QP_BUSY = RES_ANY_BUSY,
  72. /* QP number was allocated */
  73. RES_QP_RESERVED,
  74. /* ICM memory for QP context was mapped */
  75. RES_QP_MAPPED,
  76. /* QP is in hw ownership */
  77. RES_QP_HW
  78. };
  79. static inline const char *qp_states_str(enum res_qp_states state)
  80. {
  81. switch (state) {
  82. case RES_QP_BUSY: return "RES_QP_BUSY";
  83. case RES_QP_RESERVED: return "RES_QP_RESERVED";
  84. case RES_QP_MAPPED: return "RES_QP_MAPPED";
  85. case RES_QP_HW: return "RES_QP_HW";
  86. default: return "Unknown";
  87. }
  88. }
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. };
  99. enum res_mtt_states {
  100. RES_MTT_BUSY = RES_ANY_BUSY,
  101. RES_MTT_ALLOCATED,
  102. };
  103. static inline const char *mtt_states_str(enum res_mtt_states state)
  104. {
  105. switch (state) {
  106. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  107. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  108. default: return "Unknown";
  109. }
  110. }
  111. struct res_mtt {
  112. struct res_common com;
  113. int order;
  114. atomic_t ref_count;
  115. };
  116. enum res_mpt_states {
  117. RES_MPT_BUSY = RES_ANY_BUSY,
  118. RES_MPT_RESERVED,
  119. RES_MPT_MAPPED,
  120. RES_MPT_HW,
  121. };
  122. struct res_mpt {
  123. struct res_common com;
  124. struct res_mtt *mtt;
  125. int key;
  126. };
  127. enum res_eq_states {
  128. RES_EQ_BUSY = RES_ANY_BUSY,
  129. RES_EQ_RESERVED,
  130. RES_EQ_HW,
  131. };
  132. struct res_eq {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. };
  136. enum res_cq_states {
  137. RES_CQ_BUSY = RES_ANY_BUSY,
  138. RES_CQ_ALLOCATED,
  139. RES_CQ_HW,
  140. };
  141. struct res_cq {
  142. struct res_common com;
  143. struct res_mtt *mtt;
  144. atomic_t ref_count;
  145. };
  146. enum res_srq_states {
  147. RES_SRQ_BUSY = RES_ANY_BUSY,
  148. RES_SRQ_ALLOCATED,
  149. RES_SRQ_HW,
  150. };
  151. static inline const char *srq_states_str(enum res_srq_states state)
  152. {
  153. switch (state) {
  154. case RES_SRQ_BUSY: return "RES_SRQ_BUSY";
  155. case RES_SRQ_ALLOCATED: return "RES_SRQ_ALLOCATED";
  156. case RES_SRQ_HW: return "RES_SRQ_HW";
  157. default: return "Unknown";
  158. }
  159. }
  160. struct res_srq {
  161. struct res_common com;
  162. struct res_mtt *mtt;
  163. struct res_cq *cq;
  164. atomic_t ref_count;
  165. };
  166. enum res_counter_states {
  167. RES_COUNTER_BUSY = RES_ANY_BUSY,
  168. RES_COUNTER_ALLOCATED,
  169. };
  170. static inline const char *counter_states_str(enum res_counter_states state)
  171. {
  172. switch (state) {
  173. case RES_COUNTER_BUSY: return "RES_COUNTER_BUSY";
  174. case RES_COUNTER_ALLOCATED: return "RES_COUNTER_ALLOCATED";
  175. default: return "Unknown";
  176. }
  177. }
  178. struct res_counter {
  179. struct res_common com;
  180. int port;
  181. };
  182. /* For Debug uses */
  183. static const char *ResourceType(enum mlx4_resource rt)
  184. {
  185. switch (rt) {
  186. case RES_QP: return "RES_QP";
  187. case RES_CQ: return "RES_CQ";
  188. case RES_SRQ: return "RES_SRQ";
  189. case RES_MPT: return "RES_MPT";
  190. case RES_MTT: return "RES_MTT";
  191. case RES_MAC: return "RES_MAC";
  192. case RES_EQ: return "RES_EQ";
  193. case RES_COUNTER: return "RES_COUNTER";
  194. default: return "Unknown resource type !!!";
  195. };
  196. }
  197. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  198. {
  199. struct mlx4_priv *priv = mlx4_priv(dev);
  200. int i;
  201. int t;
  202. priv->mfunc.master.res_tracker.slave_list =
  203. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  204. GFP_KERNEL);
  205. if (!priv->mfunc.master.res_tracker.slave_list)
  206. return -ENOMEM;
  207. for (i = 0 ; i < dev->num_slaves; i++) {
  208. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  209. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  210. slave_list[i].res_list[t]);
  211. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  212. }
  213. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  214. dev->num_slaves);
  215. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  216. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  217. GFP_ATOMIC|__GFP_NOWARN);
  218. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  219. return 0 ;
  220. }
  221. void mlx4_free_resource_tracker(struct mlx4_dev *dev)
  222. {
  223. struct mlx4_priv *priv = mlx4_priv(dev);
  224. int i;
  225. if (priv->mfunc.master.res_tracker.slave_list) {
  226. for (i = 0 ; i < dev->num_slaves; i++)
  227. mlx4_delete_all_resources_for_slave(dev, i);
  228. kfree(priv->mfunc.master.res_tracker.slave_list);
  229. }
  230. }
  231. static void update_ud_gid(struct mlx4_dev *dev,
  232. struct mlx4_qp_context *qp_ctx, u8 slave)
  233. {
  234. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  235. if (MLX4_QP_ST_UD == ts)
  236. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  237. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  238. slave, qp_ctx->pri_path.mgid_index);
  239. }
  240. static int mpt_mask(struct mlx4_dev *dev)
  241. {
  242. return dev->caps.num_mpts - 1;
  243. }
  244. static void *find_res(struct mlx4_dev *dev, int res_id,
  245. enum mlx4_resource type)
  246. {
  247. struct mlx4_priv *priv = mlx4_priv(dev);
  248. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  249. res_id);
  250. }
  251. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  252. enum mlx4_resource type,
  253. void *res)
  254. {
  255. struct res_common *r;
  256. int err = 0;
  257. spin_lock_irq(mlx4_tlock(dev));
  258. r = find_res(dev, res_id, type);
  259. if (!r) {
  260. err = -ENONET;
  261. goto exit;
  262. }
  263. if (r->state == RES_ANY_BUSY) {
  264. err = -EBUSY;
  265. goto exit;
  266. }
  267. if (r->owner != slave) {
  268. err = -EPERM;
  269. goto exit;
  270. }
  271. r->from_state = r->state;
  272. r->state = RES_ANY_BUSY;
  273. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  274. ResourceType(type), r->res_id);
  275. if (res)
  276. *((struct res_common **)res) = r;
  277. exit:
  278. spin_unlock_irq(mlx4_tlock(dev));
  279. return err;
  280. }
  281. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  282. enum mlx4_resource type,
  283. int res_id, int *slave)
  284. {
  285. struct res_common *r;
  286. int err = -ENOENT;
  287. int id = res_id;
  288. if (type == RES_QP)
  289. id &= 0x7fffff;
  290. spin_lock(mlx4_tlock(dev));
  291. r = find_res(dev, id, type);
  292. if (r) {
  293. *slave = r->owner;
  294. err = 0;
  295. }
  296. spin_unlock(mlx4_tlock(dev));
  297. return err;
  298. }
  299. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  300. enum mlx4_resource type)
  301. {
  302. struct res_common *r;
  303. spin_lock_irq(mlx4_tlock(dev));
  304. r = find_res(dev, res_id, type);
  305. if (r)
  306. r->state = r->from_state;
  307. spin_unlock_irq(mlx4_tlock(dev));
  308. }
  309. static struct res_common *alloc_qp_tr(int id)
  310. {
  311. struct res_qp *ret;
  312. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  313. if (!ret)
  314. return NULL;
  315. ret->com.res_id = id;
  316. ret->com.state = RES_QP_RESERVED;
  317. ret->local_qpn = id;
  318. INIT_LIST_HEAD(&ret->mcg_list);
  319. spin_lock_init(&ret->mcg_spl);
  320. return &ret->com;
  321. }
  322. static struct res_common *alloc_mtt_tr(int id, int order)
  323. {
  324. struct res_mtt *ret;
  325. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  326. if (!ret)
  327. return NULL;
  328. ret->com.res_id = id;
  329. ret->order = order;
  330. ret->com.state = RES_MTT_ALLOCATED;
  331. atomic_set(&ret->ref_count, 0);
  332. return &ret->com;
  333. }
  334. static struct res_common *alloc_mpt_tr(int id, int key)
  335. {
  336. struct res_mpt *ret;
  337. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  338. if (!ret)
  339. return NULL;
  340. ret->com.res_id = id;
  341. ret->com.state = RES_MPT_RESERVED;
  342. ret->key = key;
  343. return &ret->com;
  344. }
  345. static struct res_common *alloc_eq_tr(int id)
  346. {
  347. struct res_eq *ret;
  348. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  349. if (!ret)
  350. return NULL;
  351. ret->com.res_id = id;
  352. ret->com.state = RES_EQ_RESERVED;
  353. return &ret->com;
  354. }
  355. static struct res_common *alloc_cq_tr(int id)
  356. {
  357. struct res_cq *ret;
  358. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  359. if (!ret)
  360. return NULL;
  361. ret->com.res_id = id;
  362. ret->com.state = RES_CQ_ALLOCATED;
  363. atomic_set(&ret->ref_count, 0);
  364. return &ret->com;
  365. }
  366. static struct res_common *alloc_srq_tr(int id)
  367. {
  368. struct res_srq *ret;
  369. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  370. if (!ret)
  371. return NULL;
  372. ret->com.res_id = id;
  373. ret->com.state = RES_SRQ_ALLOCATED;
  374. atomic_set(&ret->ref_count, 0);
  375. return &ret->com;
  376. }
  377. static struct res_common *alloc_counter_tr(int id)
  378. {
  379. struct res_counter *ret;
  380. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  381. if (!ret)
  382. return NULL;
  383. ret->com.res_id = id;
  384. ret->com.state = RES_COUNTER_ALLOCATED;
  385. return &ret->com;
  386. }
  387. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  388. int extra)
  389. {
  390. struct res_common *ret;
  391. switch (type) {
  392. case RES_QP:
  393. ret = alloc_qp_tr(id);
  394. break;
  395. case RES_MPT:
  396. ret = alloc_mpt_tr(id, extra);
  397. break;
  398. case RES_MTT:
  399. ret = alloc_mtt_tr(id, extra);
  400. break;
  401. case RES_EQ:
  402. ret = alloc_eq_tr(id);
  403. break;
  404. case RES_CQ:
  405. ret = alloc_cq_tr(id);
  406. break;
  407. case RES_SRQ:
  408. ret = alloc_srq_tr(id);
  409. break;
  410. case RES_MAC:
  411. printk(KERN_ERR "implementation missing\n");
  412. return NULL;
  413. case RES_COUNTER:
  414. ret = alloc_counter_tr(id);
  415. break;
  416. default:
  417. return NULL;
  418. }
  419. if (ret)
  420. ret->owner = slave;
  421. return ret;
  422. }
  423. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  424. enum mlx4_resource type, int extra)
  425. {
  426. int i;
  427. int err;
  428. struct mlx4_priv *priv = mlx4_priv(dev);
  429. struct res_common **res_arr;
  430. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  431. struct radix_tree_root *root = &tracker->res_tree[type];
  432. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  433. if (!res_arr)
  434. return -ENOMEM;
  435. for (i = 0; i < count; ++i) {
  436. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  437. if (!res_arr[i]) {
  438. for (--i; i >= 0; --i)
  439. kfree(res_arr[i]);
  440. kfree(res_arr);
  441. return -ENOMEM;
  442. }
  443. }
  444. spin_lock_irq(mlx4_tlock(dev));
  445. for (i = 0; i < count; ++i) {
  446. if (find_res(dev, base + i, type)) {
  447. err = -EEXIST;
  448. goto undo;
  449. }
  450. err = radix_tree_insert(root, base + i, res_arr[i]);
  451. if (err)
  452. goto undo;
  453. list_add_tail(&res_arr[i]->list,
  454. &tracker->slave_list[slave].res_list[type]);
  455. }
  456. spin_unlock_irq(mlx4_tlock(dev));
  457. kfree(res_arr);
  458. return 0;
  459. undo:
  460. for (--i; i >= base; --i)
  461. radix_tree_delete(&tracker->res_tree[type], i);
  462. spin_unlock_irq(mlx4_tlock(dev));
  463. for (i = 0; i < count; ++i)
  464. kfree(res_arr[i]);
  465. kfree(res_arr);
  466. return err;
  467. }
  468. static int remove_qp_ok(struct res_qp *res)
  469. {
  470. if (res->com.state == RES_QP_BUSY)
  471. return -EBUSY;
  472. else if (res->com.state != RES_QP_RESERVED)
  473. return -EPERM;
  474. return 0;
  475. }
  476. static int remove_mtt_ok(struct res_mtt *res, int order)
  477. {
  478. if (res->com.state == RES_MTT_BUSY ||
  479. atomic_read(&res->ref_count)) {
  480. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  481. __func__, __LINE__,
  482. mtt_states_str(res->com.state),
  483. atomic_read(&res->ref_count));
  484. return -EBUSY;
  485. } else if (res->com.state != RES_MTT_ALLOCATED)
  486. return -EPERM;
  487. else if (res->order != order)
  488. return -EINVAL;
  489. return 0;
  490. }
  491. static int remove_mpt_ok(struct res_mpt *res)
  492. {
  493. if (res->com.state == RES_MPT_BUSY)
  494. return -EBUSY;
  495. else if (res->com.state != RES_MPT_RESERVED)
  496. return -EPERM;
  497. return 0;
  498. }
  499. static int remove_eq_ok(struct res_eq *res)
  500. {
  501. if (res->com.state == RES_MPT_BUSY)
  502. return -EBUSY;
  503. else if (res->com.state != RES_MPT_RESERVED)
  504. return -EPERM;
  505. return 0;
  506. }
  507. static int remove_counter_ok(struct res_counter *res)
  508. {
  509. if (res->com.state == RES_COUNTER_BUSY)
  510. return -EBUSY;
  511. else if (res->com.state != RES_COUNTER_ALLOCATED)
  512. return -EPERM;
  513. return 0;
  514. }
  515. static int remove_cq_ok(struct res_cq *res)
  516. {
  517. if (res->com.state == RES_CQ_BUSY)
  518. return -EBUSY;
  519. else if (res->com.state != RES_CQ_ALLOCATED)
  520. return -EPERM;
  521. return 0;
  522. }
  523. static int remove_srq_ok(struct res_srq *res)
  524. {
  525. if (res->com.state == RES_SRQ_BUSY)
  526. return -EBUSY;
  527. else if (res->com.state != RES_SRQ_ALLOCATED)
  528. return -EPERM;
  529. return 0;
  530. }
  531. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  532. {
  533. switch (type) {
  534. case RES_QP:
  535. return remove_qp_ok((struct res_qp *)res);
  536. case RES_CQ:
  537. return remove_cq_ok((struct res_cq *)res);
  538. case RES_SRQ:
  539. return remove_srq_ok((struct res_srq *)res);
  540. case RES_MPT:
  541. return remove_mpt_ok((struct res_mpt *)res);
  542. case RES_MTT:
  543. return remove_mtt_ok((struct res_mtt *)res, extra);
  544. case RES_MAC:
  545. return -ENOSYS;
  546. case RES_EQ:
  547. return remove_eq_ok((struct res_eq *)res);
  548. case RES_COUNTER:
  549. return remove_counter_ok((struct res_counter *)res);
  550. default:
  551. return -EINVAL;
  552. }
  553. }
  554. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  555. enum mlx4_resource type, int extra)
  556. {
  557. int i;
  558. int err;
  559. struct mlx4_priv *priv = mlx4_priv(dev);
  560. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  561. struct res_common *r;
  562. spin_lock_irq(mlx4_tlock(dev));
  563. for (i = base; i < base + count; ++i) {
  564. r = radix_tree_lookup(&tracker->res_tree[type], i);
  565. if (!r) {
  566. err = -ENOENT;
  567. goto out;
  568. }
  569. if (r->owner != slave) {
  570. err = -EPERM;
  571. goto out;
  572. }
  573. err = remove_ok(r, type, extra);
  574. if (err)
  575. goto out;
  576. }
  577. for (i = base; i < base + count; ++i) {
  578. r = radix_tree_lookup(&tracker->res_tree[type], i);
  579. radix_tree_delete(&tracker->res_tree[type], i);
  580. list_del(&r->list);
  581. kfree(r);
  582. }
  583. err = 0;
  584. out:
  585. spin_unlock_irq(mlx4_tlock(dev));
  586. return err;
  587. }
  588. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  589. enum res_qp_states state, struct res_qp **qp,
  590. int alloc)
  591. {
  592. struct mlx4_priv *priv = mlx4_priv(dev);
  593. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  594. struct res_qp *r;
  595. int err = 0;
  596. spin_lock_irq(mlx4_tlock(dev));
  597. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  598. if (!r)
  599. err = -ENOENT;
  600. else if (r->com.owner != slave)
  601. err = -EPERM;
  602. else {
  603. switch (state) {
  604. case RES_QP_BUSY:
  605. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  606. __func__, r->com.res_id);
  607. err = -EBUSY;
  608. break;
  609. case RES_QP_RESERVED:
  610. if (r->com.state == RES_QP_MAPPED && !alloc)
  611. break;
  612. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  613. err = -EINVAL;
  614. break;
  615. case RES_QP_MAPPED:
  616. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  617. r->com.state == RES_QP_HW)
  618. break;
  619. else {
  620. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  621. r->com.res_id);
  622. err = -EINVAL;
  623. }
  624. break;
  625. case RES_QP_HW:
  626. if (r->com.state != RES_QP_MAPPED)
  627. err = -EINVAL;
  628. break;
  629. default:
  630. err = -EINVAL;
  631. }
  632. if (!err) {
  633. r->com.from_state = r->com.state;
  634. r->com.to_state = state;
  635. r->com.state = RES_QP_BUSY;
  636. if (qp)
  637. *qp = (struct res_qp *)r;
  638. }
  639. }
  640. spin_unlock_irq(mlx4_tlock(dev));
  641. return err;
  642. }
  643. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  644. enum res_mpt_states state, struct res_mpt **mpt)
  645. {
  646. struct mlx4_priv *priv = mlx4_priv(dev);
  647. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  648. struct res_mpt *r;
  649. int err = 0;
  650. spin_lock_irq(mlx4_tlock(dev));
  651. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  652. if (!r)
  653. err = -ENOENT;
  654. else if (r->com.owner != slave)
  655. err = -EPERM;
  656. else {
  657. switch (state) {
  658. case RES_MPT_BUSY:
  659. err = -EINVAL;
  660. break;
  661. case RES_MPT_RESERVED:
  662. if (r->com.state != RES_MPT_MAPPED)
  663. err = -EINVAL;
  664. break;
  665. case RES_MPT_MAPPED:
  666. if (r->com.state != RES_MPT_RESERVED &&
  667. r->com.state != RES_MPT_HW)
  668. err = -EINVAL;
  669. break;
  670. case RES_MPT_HW:
  671. if (r->com.state != RES_MPT_MAPPED)
  672. err = -EINVAL;
  673. break;
  674. default:
  675. err = -EINVAL;
  676. }
  677. if (!err) {
  678. r->com.from_state = r->com.state;
  679. r->com.to_state = state;
  680. r->com.state = RES_MPT_BUSY;
  681. if (mpt)
  682. *mpt = (struct res_mpt *)r;
  683. }
  684. }
  685. spin_unlock_irq(mlx4_tlock(dev));
  686. return err;
  687. }
  688. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  689. enum res_eq_states state, struct res_eq **eq)
  690. {
  691. struct mlx4_priv *priv = mlx4_priv(dev);
  692. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  693. struct res_eq *r;
  694. int err = 0;
  695. spin_lock_irq(mlx4_tlock(dev));
  696. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  697. if (!r)
  698. err = -ENOENT;
  699. else if (r->com.owner != slave)
  700. err = -EPERM;
  701. else {
  702. switch (state) {
  703. case RES_EQ_BUSY:
  704. err = -EINVAL;
  705. break;
  706. case RES_EQ_RESERVED:
  707. if (r->com.state != RES_EQ_HW)
  708. err = -EINVAL;
  709. break;
  710. case RES_EQ_HW:
  711. if (r->com.state != RES_EQ_RESERVED)
  712. err = -EINVAL;
  713. break;
  714. default:
  715. err = -EINVAL;
  716. }
  717. if (!err) {
  718. r->com.from_state = r->com.state;
  719. r->com.to_state = state;
  720. r->com.state = RES_EQ_BUSY;
  721. if (eq)
  722. *eq = r;
  723. }
  724. }
  725. spin_unlock_irq(mlx4_tlock(dev));
  726. return err;
  727. }
  728. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  729. enum res_cq_states state, struct res_cq **cq)
  730. {
  731. struct mlx4_priv *priv = mlx4_priv(dev);
  732. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  733. struct res_cq *r;
  734. int err;
  735. spin_lock_irq(mlx4_tlock(dev));
  736. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  737. if (!r)
  738. err = -ENOENT;
  739. else if (r->com.owner != slave)
  740. err = -EPERM;
  741. else {
  742. switch (state) {
  743. case RES_CQ_BUSY:
  744. err = -EBUSY;
  745. break;
  746. case RES_CQ_ALLOCATED:
  747. if (r->com.state != RES_CQ_HW)
  748. err = -EINVAL;
  749. else if (atomic_read(&r->ref_count))
  750. err = -EBUSY;
  751. else
  752. err = 0;
  753. break;
  754. case RES_CQ_HW:
  755. if (r->com.state != RES_CQ_ALLOCATED)
  756. err = -EINVAL;
  757. else
  758. err = 0;
  759. break;
  760. default:
  761. err = -EINVAL;
  762. }
  763. if (!err) {
  764. r->com.from_state = r->com.state;
  765. r->com.to_state = state;
  766. r->com.state = RES_CQ_BUSY;
  767. if (cq)
  768. *cq = r;
  769. }
  770. }
  771. spin_unlock_irq(mlx4_tlock(dev));
  772. return err;
  773. }
  774. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  775. enum res_cq_states state, struct res_srq **srq)
  776. {
  777. struct mlx4_priv *priv = mlx4_priv(dev);
  778. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  779. struct res_srq *r;
  780. int err = 0;
  781. spin_lock_irq(mlx4_tlock(dev));
  782. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  783. if (!r)
  784. err = -ENOENT;
  785. else if (r->com.owner != slave)
  786. err = -EPERM;
  787. else {
  788. switch (state) {
  789. case RES_SRQ_BUSY:
  790. err = -EINVAL;
  791. break;
  792. case RES_SRQ_ALLOCATED:
  793. if (r->com.state != RES_SRQ_HW)
  794. err = -EINVAL;
  795. else if (atomic_read(&r->ref_count))
  796. err = -EBUSY;
  797. break;
  798. case RES_SRQ_HW:
  799. if (r->com.state != RES_SRQ_ALLOCATED)
  800. err = -EINVAL;
  801. break;
  802. default:
  803. err = -EINVAL;
  804. }
  805. if (!err) {
  806. r->com.from_state = r->com.state;
  807. r->com.to_state = state;
  808. r->com.state = RES_SRQ_BUSY;
  809. if (srq)
  810. *srq = r;
  811. }
  812. }
  813. spin_unlock_irq(mlx4_tlock(dev));
  814. return err;
  815. }
  816. static void res_abort_move(struct mlx4_dev *dev, int slave,
  817. enum mlx4_resource type, int id)
  818. {
  819. struct mlx4_priv *priv = mlx4_priv(dev);
  820. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  821. struct res_common *r;
  822. spin_lock_irq(mlx4_tlock(dev));
  823. r = radix_tree_lookup(&tracker->res_tree[type], id);
  824. if (r && (r->owner == slave))
  825. r->state = r->from_state;
  826. spin_unlock_irq(mlx4_tlock(dev));
  827. }
  828. static void res_end_move(struct mlx4_dev *dev, int slave,
  829. enum mlx4_resource type, int id)
  830. {
  831. struct mlx4_priv *priv = mlx4_priv(dev);
  832. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  833. struct res_common *r;
  834. spin_lock_irq(mlx4_tlock(dev));
  835. r = radix_tree_lookup(&tracker->res_tree[type], id);
  836. if (r && (r->owner == slave))
  837. r->state = r->to_state;
  838. spin_unlock_irq(mlx4_tlock(dev));
  839. }
  840. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  841. {
  842. return mlx4_is_qp_reserved(dev, qpn);
  843. }
  844. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  845. u64 in_param, u64 *out_param)
  846. {
  847. int err;
  848. int count;
  849. int align;
  850. int base;
  851. int qpn;
  852. switch (op) {
  853. case RES_OP_RESERVE:
  854. count = get_param_l(&in_param);
  855. align = get_param_h(&in_param);
  856. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  857. if (err)
  858. return err;
  859. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  860. if (err) {
  861. __mlx4_qp_release_range(dev, base, count);
  862. return err;
  863. }
  864. set_param_l(out_param, base);
  865. break;
  866. case RES_OP_MAP_ICM:
  867. qpn = get_param_l(&in_param) & 0x7fffff;
  868. if (valid_reserved(dev, slave, qpn)) {
  869. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  870. if (err)
  871. return err;
  872. }
  873. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  874. NULL, 1);
  875. if (err)
  876. return err;
  877. if (!valid_reserved(dev, slave, qpn)) {
  878. err = __mlx4_qp_alloc_icm(dev, qpn);
  879. if (err) {
  880. res_abort_move(dev, slave, RES_QP, qpn);
  881. return err;
  882. }
  883. }
  884. res_end_move(dev, slave, RES_QP, qpn);
  885. break;
  886. default:
  887. err = -EINVAL;
  888. break;
  889. }
  890. return err;
  891. }
  892. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  893. u64 in_param, u64 *out_param)
  894. {
  895. int err = -EINVAL;
  896. int base;
  897. int order;
  898. if (op != RES_OP_RESERVE_AND_MAP)
  899. return err;
  900. order = get_param_l(&in_param);
  901. base = __mlx4_alloc_mtt_range(dev, order);
  902. if (base == -1)
  903. return -ENOMEM;
  904. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  905. if (err)
  906. __mlx4_free_mtt_range(dev, base, order);
  907. else
  908. set_param_l(out_param, base);
  909. return err;
  910. }
  911. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  912. u64 in_param, u64 *out_param)
  913. {
  914. int err = -EINVAL;
  915. int index;
  916. int id;
  917. struct res_mpt *mpt;
  918. switch (op) {
  919. case RES_OP_RESERVE:
  920. index = __mlx4_mr_reserve(dev);
  921. if (index == -1)
  922. break;
  923. id = index & mpt_mask(dev);
  924. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  925. if (err) {
  926. __mlx4_mr_release(dev, index);
  927. break;
  928. }
  929. set_param_l(out_param, index);
  930. break;
  931. case RES_OP_MAP_ICM:
  932. index = get_param_l(&in_param);
  933. id = index & mpt_mask(dev);
  934. err = mr_res_start_move_to(dev, slave, id,
  935. RES_MPT_MAPPED, &mpt);
  936. if (err)
  937. return err;
  938. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  939. if (err) {
  940. res_abort_move(dev, slave, RES_MPT, id);
  941. return err;
  942. }
  943. res_end_move(dev, slave, RES_MPT, id);
  944. break;
  945. }
  946. return err;
  947. }
  948. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  949. u64 in_param, u64 *out_param)
  950. {
  951. int cqn;
  952. int err;
  953. switch (op) {
  954. case RES_OP_RESERVE_AND_MAP:
  955. err = __mlx4_cq_alloc_icm(dev, &cqn);
  956. if (err)
  957. break;
  958. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  959. if (err) {
  960. __mlx4_cq_free_icm(dev, cqn);
  961. break;
  962. }
  963. set_param_l(out_param, cqn);
  964. break;
  965. default:
  966. err = -EINVAL;
  967. }
  968. return err;
  969. }
  970. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  971. u64 in_param, u64 *out_param)
  972. {
  973. int srqn;
  974. int err;
  975. switch (op) {
  976. case RES_OP_RESERVE_AND_MAP:
  977. err = __mlx4_srq_alloc_icm(dev, &srqn);
  978. if (err)
  979. break;
  980. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  981. if (err) {
  982. __mlx4_srq_free_icm(dev, srqn);
  983. break;
  984. }
  985. set_param_l(out_param, srqn);
  986. break;
  987. default:
  988. err = -EINVAL;
  989. }
  990. return err;
  991. }
  992. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  993. {
  994. struct mlx4_priv *priv = mlx4_priv(dev);
  995. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  996. struct mac_res *res;
  997. res = kzalloc(sizeof *res, GFP_KERNEL);
  998. if (!res)
  999. return -ENOMEM;
  1000. res->mac = mac;
  1001. res->port = (u8) port;
  1002. list_add_tail(&res->list,
  1003. &tracker->slave_list[slave].res_list[RES_MAC]);
  1004. return 0;
  1005. }
  1006. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1007. int port)
  1008. {
  1009. struct mlx4_priv *priv = mlx4_priv(dev);
  1010. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1011. struct list_head *mac_list =
  1012. &tracker->slave_list[slave].res_list[RES_MAC];
  1013. struct mac_res *res, *tmp;
  1014. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1015. if (res->mac == mac && res->port == (u8) port) {
  1016. list_del(&res->list);
  1017. kfree(res);
  1018. break;
  1019. }
  1020. }
  1021. }
  1022. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1023. {
  1024. struct mlx4_priv *priv = mlx4_priv(dev);
  1025. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1026. struct list_head *mac_list =
  1027. &tracker->slave_list[slave].res_list[RES_MAC];
  1028. struct mac_res *res, *tmp;
  1029. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1030. list_del(&res->list);
  1031. __mlx4_unregister_mac(dev, res->port, res->mac);
  1032. kfree(res);
  1033. }
  1034. }
  1035. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1036. u64 in_param, u64 *out_param)
  1037. {
  1038. int err = -EINVAL;
  1039. int port;
  1040. u64 mac;
  1041. if (op != RES_OP_RESERVE_AND_MAP)
  1042. return err;
  1043. port = get_param_l(out_param);
  1044. mac = in_param;
  1045. err = __mlx4_register_mac(dev, port, mac);
  1046. if (err >= 0) {
  1047. set_param_l(out_param, err);
  1048. err = 0;
  1049. }
  1050. if (!err) {
  1051. err = mac_add_to_slave(dev, slave, mac, port);
  1052. if (err)
  1053. __mlx4_unregister_mac(dev, port, mac);
  1054. }
  1055. return err;
  1056. }
  1057. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1058. u64 in_param, u64 *out_param)
  1059. {
  1060. return 0;
  1061. }
  1062. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1063. struct mlx4_vhcr *vhcr,
  1064. struct mlx4_cmd_mailbox *inbox,
  1065. struct mlx4_cmd_mailbox *outbox,
  1066. struct mlx4_cmd_info *cmd)
  1067. {
  1068. int err;
  1069. int alop = vhcr->op_modifier;
  1070. switch (vhcr->in_modifier) {
  1071. case RES_QP:
  1072. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1073. vhcr->in_param, &vhcr->out_param);
  1074. break;
  1075. case RES_MTT:
  1076. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1077. vhcr->in_param, &vhcr->out_param);
  1078. break;
  1079. case RES_MPT:
  1080. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1081. vhcr->in_param, &vhcr->out_param);
  1082. break;
  1083. case RES_CQ:
  1084. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1085. vhcr->in_param, &vhcr->out_param);
  1086. break;
  1087. case RES_SRQ:
  1088. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1089. vhcr->in_param, &vhcr->out_param);
  1090. break;
  1091. case RES_MAC:
  1092. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1093. vhcr->in_param, &vhcr->out_param);
  1094. break;
  1095. case RES_VLAN:
  1096. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1097. vhcr->in_param, &vhcr->out_param);
  1098. break;
  1099. default:
  1100. err = -EINVAL;
  1101. break;
  1102. }
  1103. return err;
  1104. }
  1105. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1106. u64 in_param)
  1107. {
  1108. int err;
  1109. int count;
  1110. int base;
  1111. int qpn;
  1112. switch (op) {
  1113. case RES_OP_RESERVE:
  1114. base = get_param_l(&in_param) & 0x7fffff;
  1115. count = get_param_h(&in_param);
  1116. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1117. if (err)
  1118. break;
  1119. __mlx4_qp_release_range(dev, base, count);
  1120. break;
  1121. case RES_OP_MAP_ICM:
  1122. qpn = get_param_l(&in_param) & 0x7fffff;
  1123. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1124. NULL, 0);
  1125. if (err)
  1126. return err;
  1127. if (!valid_reserved(dev, slave, qpn))
  1128. __mlx4_qp_free_icm(dev, qpn);
  1129. res_end_move(dev, slave, RES_QP, qpn);
  1130. if (valid_reserved(dev, slave, qpn))
  1131. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1132. break;
  1133. default:
  1134. err = -EINVAL;
  1135. break;
  1136. }
  1137. return err;
  1138. }
  1139. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1140. u64 in_param, u64 *out_param)
  1141. {
  1142. int err = -EINVAL;
  1143. int base;
  1144. int order;
  1145. if (op != RES_OP_RESERVE_AND_MAP)
  1146. return err;
  1147. base = get_param_l(&in_param);
  1148. order = get_param_h(&in_param);
  1149. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1150. if (!err)
  1151. __mlx4_free_mtt_range(dev, base, order);
  1152. return err;
  1153. }
  1154. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1155. u64 in_param)
  1156. {
  1157. int err = -EINVAL;
  1158. int index;
  1159. int id;
  1160. struct res_mpt *mpt;
  1161. switch (op) {
  1162. case RES_OP_RESERVE:
  1163. index = get_param_l(&in_param);
  1164. id = index & mpt_mask(dev);
  1165. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1166. if (err)
  1167. break;
  1168. index = mpt->key;
  1169. put_res(dev, slave, id, RES_MPT);
  1170. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1171. if (err)
  1172. break;
  1173. __mlx4_mr_release(dev, index);
  1174. break;
  1175. case RES_OP_MAP_ICM:
  1176. index = get_param_l(&in_param);
  1177. id = index & mpt_mask(dev);
  1178. err = mr_res_start_move_to(dev, slave, id,
  1179. RES_MPT_RESERVED, &mpt);
  1180. if (err)
  1181. return err;
  1182. __mlx4_mr_free_icm(dev, mpt->key);
  1183. res_end_move(dev, slave, RES_MPT, id);
  1184. return err;
  1185. break;
  1186. default:
  1187. err = -EINVAL;
  1188. break;
  1189. }
  1190. return err;
  1191. }
  1192. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1193. u64 in_param, u64 *out_param)
  1194. {
  1195. int cqn;
  1196. int err;
  1197. switch (op) {
  1198. case RES_OP_RESERVE_AND_MAP:
  1199. cqn = get_param_l(&in_param);
  1200. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1201. if (err)
  1202. break;
  1203. __mlx4_cq_free_icm(dev, cqn);
  1204. break;
  1205. default:
  1206. err = -EINVAL;
  1207. break;
  1208. }
  1209. return err;
  1210. }
  1211. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1212. u64 in_param, u64 *out_param)
  1213. {
  1214. int srqn;
  1215. int err;
  1216. switch (op) {
  1217. case RES_OP_RESERVE_AND_MAP:
  1218. srqn = get_param_l(&in_param);
  1219. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1220. if (err)
  1221. break;
  1222. __mlx4_srq_free_icm(dev, srqn);
  1223. break;
  1224. default:
  1225. err = -EINVAL;
  1226. break;
  1227. }
  1228. return err;
  1229. }
  1230. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1231. u64 in_param, u64 *out_param)
  1232. {
  1233. int port;
  1234. int err = 0;
  1235. switch (op) {
  1236. case RES_OP_RESERVE_AND_MAP:
  1237. port = get_param_l(out_param);
  1238. mac_del_from_slave(dev, slave, in_param, port);
  1239. __mlx4_unregister_mac(dev, port, in_param);
  1240. break;
  1241. default:
  1242. err = -EINVAL;
  1243. break;
  1244. }
  1245. return err;
  1246. }
  1247. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1248. u64 in_param, u64 *out_param)
  1249. {
  1250. return 0;
  1251. }
  1252. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1253. struct mlx4_vhcr *vhcr,
  1254. struct mlx4_cmd_mailbox *inbox,
  1255. struct mlx4_cmd_mailbox *outbox,
  1256. struct mlx4_cmd_info *cmd)
  1257. {
  1258. int err = -EINVAL;
  1259. int alop = vhcr->op_modifier;
  1260. switch (vhcr->in_modifier) {
  1261. case RES_QP:
  1262. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1263. vhcr->in_param);
  1264. break;
  1265. case RES_MTT:
  1266. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1267. vhcr->in_param, &vhcr->out_param);
  1268. break;
  1269. case RES_MPT:
  1270. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1271. vhcr->in_param);
  1272. break;
  1273. case RES_CQ:
  1274. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1275. vhcr->in_param, &vhcr->out_param);
  1276. break;
  1277. case RES_SRQ:
  1278. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1279. vhcr->in_param, &vhcr->out_param);
  1280. break;
  1281. case RES_MAC:
  1282. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1283. vhcr->in_param, &vhcr->out_param);
  1284. break;
  1285. case RES_VLAN:
  1286. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1287. vhcr->in_param, &vhcr->out_param);
  1288. break;
  1289. default:
  1290. break;
  1291. }
  1292. return err;
  1293. }
  1294. /* ugly but other choices are uglier */
  1295. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1296. {
  1297. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1298. }
  1299. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1300. {
  1301. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1302. }
  1303. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1304. {
  1305. return be32_to_cpu(mpt->mtt_sz);
  1306. }
  1307. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1308. {
  1309. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1310. }
  1311. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1312. {
  1313. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1314. }
  1315. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1316. {
  1317. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1318. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1319. int log_sq_sride = qpc->sq_size_stride & 7;
  1320. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1321. int log_rq_stride = qpc->rq_size_stride & 7;
  1322. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1323. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1324. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1325. int sq_size;
  1326. int rq_size;
  1327. int total_pages;
  1328. int total_mem;
  1329. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1330. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1331. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1332. total_mem = sq_size + rq_size;
  1333. total_pages =
  1334. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1335. page_shift);
  1336. return total_pages;
  1337. }
  1338. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1339. int size, struct res_mtt *mtt)
  1340. {
  1341. int res_start = mtt->com.res_id;
  1342. int res_size = (1 << mtt->order);
  1343. if (start < res_start || start + size > res_start + res_size)
  1344. return -EPERM;
  1345. return 0;
  1346. }
  1347. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1348. struct mlx4_vhcr *vhcr,
  1349. struct mlx4_cmd_mailbox *inbox,
  1350. struct mlx4_cmd_mailbox *outbox,
  1351. struct mlx4_cmd_info *cmd)
  1352. {
  1353. int err;
  1354. int index = vhcr->in_modifier;
  1355. struct res_mtt *mtt;
  1356. struct res_mpt *mpt;
  1357. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1358. int phys;
  1359. int id;
  1360. id = index & mpt_mask(dev);
  1361. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1362. if (err)
  1363. return err;
  1364. phys = mr_phys_mpt(inbox->buf);
  1365. if (!phys) {
  1366. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1367. if (err)
  1368. goto ex_abort;
  1369. err = check_mtt_range(dev, slave, mtt_base,
  1370. mr_get_mtt_size(inbox->buf), mtt);
  1371. if (err)
  1372. goto ex_put;
  1373. mpt->mtt = mtt;
  1374. }
  1375. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1376. if (err)
  1377. goto ex_put;
  1378. if (!phys) {
  1379. atomic_inc(&mtt->ref_count);
  1380. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1381. }
  1382. res_end_move(dev, slave, RES_MPT, id);
  1383. return 0;
  1384. ex_put:
  1385. if (!phys)
  1386. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1387. ex_abort:
  1388. res_abort_move(dev, slave, RES_MPT, id);
  1389. return err;
  1390. }
  1391. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1392. struct mlx4_vhcr *vhcr,
  1393. struct mlx4_cmd_mailbox *inbox,
  1394. struct mlx4_cmd_mailbox *outbox,
  1395. struct mlx4_cmd_info *cmd)
  1396. {
  1397. int err;
  1398. int index = vhcr->in_modifier;
  1399. struct res_mpt *mpt;
  1400. int id;
  1401. id = index & mpt_mask(dev);
  1402. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1403. if (err)
  1404. return err;
  1405. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1406. if (err)
  1407. goto ex_abort;
  1408. if (mpt->mtt)
  1409. atomic_dec(&mpt->mtt->ref_count);
  1410. res_end_move(dev, slave, RES_MPT, id);
  1411. return 0;
  1412. ex_abort:
  1413. res_abort_move(dev, slave, RES_MPT, id);
  1414. return err;
  1415. }
  1416. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1417. struct mlx4_vhcr *vhcr,
  1418. struct mlx4_cmd_mailbox *inbox,
  1419. struct mlx4_cmd_mailbox *outbox,
  1420. struct mlx4_cmd_info *cmd)
  1421. {
  1422. int err;
  1423. int index = vhcr->in_modifier;
  1424. struct res_mpt *mpt;
  1425. int id;
  1426. id = index & mpt_mask(dev);
  1427. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1428. if (err)
  1429. return err;
  1430. if (mpt->com.from_state != RES_MPT_HW) {
  1431. err = -EBUSY;
  1432. goto out;
  1433. }
  1434. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1435. out:
  1436. put_res(dev, slave, id, RES_MPT);
  1437. return err;
  1438. }
  1439. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1440. {
  1441. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1442. }
  1443. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1444. {
  1445. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1446. }
  1447. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1448. {
  1449. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1450. }
  1451. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1452. struct mlx4_vhcr *vhcr,
  1453. struct mlx4_cmd_mailbox *inbox,
  1454. struct mlx4_cmd_mailbox *outbox,
  1455. struct mlx4_cmd_info *cmd)
  1456. {
  1457. int err;
  1458. int qpn = vhcr->in_modifier & 0x7fffff;
  1459. struct res_mtt *mtt;
  1460. struct res_qp *qp;
  1461. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1462. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1463. int mtt_size = qp_get_mtt_size(qpc);
  1464. struct res_cq *rcq;
  1465. struct res_cq *scq;
  1466. int rcqn = qp_get_rcqn(qpc);
  1467. int scqn = qp_get_scqn(qpc);
  1468. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1469. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1470. struct res_srq *srq;
  1471. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1472. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1473. if (err)
  1474. return err;
  1475. qp->local_qpn = local_qpn;
  1476. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1477. if (err)
  1478. goto ex_abort;
  1479. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1480. if (err)
  1481. goto ex_put_mtt;
  1482. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1483. if (err)
  1484. goto ex_put_mtt;
  1485. if (scqn != rcqn) {
  1486. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1487. if (err)
  1488. goto ex_put_rcq;
  1489. } else
  1490. scq = rcq;
  1491. if (use_srq) {
  1492. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1493. if (err)
  1494. goto ex_put_scq;
  1495. }
  1496. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1497. if (err)
  1498. goto ex_put_srq;
  1499. atomic_inc(&mtt->ref_count);
  1500. qp->mtt = mtt;
  1501. atomic_inc(&rcq->ref_count);
  1502. qp->rcq = rcq;
  1503. atomic_inc(&scq->ref_count);
  1504. qp->scq = scq;
  1505. if (scqn != rcqn)
  1506. put_res(dev, slave, scqn, RES_CQ);
  1507. if (use_srq) {
  1508. atomic_inc(&srq->ref_count);
  1509. put_res(dev, slave, srqn, RES_SRQ);
  1510. qp->srq = srq;
  1511. }
  1512. put_res(dev, slave, rcqn, RES_CQ);
  1513. put_res(dev, slave, mtt_base, RES_MTT);
  1514. res_end_move(dev, slave, RES_QP, qpn);
  1515. return 0;
  1516. ex_put_srq:
  1517. if (use_srq)
  1518. put_res(dev, slave, srqn, RES_SRQ);
  1519. ex_put_scq:
  1520. if (scqn != rcqn)
  1521. put_res(dev, slave, scqn, RES_CQ);
  1522. ex_put_rcq:
  1523. put_res(dev, slave, rcqn, RES_CQ);
  1524. ex_put_mtt:
  1525. put_res(dev, slave, mtt_base, RES_MTT);
  1526. ex_abort:
  1527. res_abort_move(dev, slave, RES_QP, qpn);
  1528. return err;
  1529. }
  1530. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1531. {
  1532. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1533. }
  1534. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1535. {
  1536. int log_eq_size = eqc->log_eq_size & 0x1f;
  1537. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1538. if (log_eq_size + 5 < page_shift)
  1539. return 1;
  1540. return 1 << (log_eq_size + 5 - page_shift);
  1541. }
  1542. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1543. {
  1544. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1545. }
  1546. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1547. {
  1548. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1549. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1550. if (log_cq_size + 5 < page_shift)
  1551. return 1;
  1552. return 1 << (log_cq_size + 5 - page_shift);
  1553. }
  1554. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1555. struct mlx4_vhcr *vhcr,
  1556. struct mlx4_cmd_mailbox *inbox,
  1557. struct mlx4_cmd_mailbox *outbox,
  1558. struct mlx4_cmd_info *cmd)
  1559. {
  1560. int err;
  1561. int eqn = vhcr->in_modifier;
  1562. int res_id = (slave << 8) | eqn;
  1563. struct mlx4_eq_context *eqc = inbox->buf;
  1564. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1565. int mtt_size = eq_get_mtt_size(eqc);
  1566. struct res_eq *eq;
  1567. struct res_mtt *mtt;
  1568. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1569. if (err)
  1570. return err;
  1571. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1572. if (err)
  1573. goto out_add;
  1574. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1575. if (err)
  1576. goto out_move;
  1577. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1578. if (err)
  1579. goto out_put;
  1580. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1581. if (err)
  1582. goto out_put;
  1583. atomic_inc(&mtt->ref_count);
  1584. eq->mtt = mtt;
  1585. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1586. res_end_move(dev, slave, RES_EQ, res_id);
  1587. return 0;
  1588. out_put:
  1589. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1590. out_move:
  1591. res_abort_move(dev, slave, RES_EQ, res_id);
  1592. out_add:
  1593. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1594. return err;
  1595. }
  1596. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1597. int len, struct res_mtt **res)
  1598. {
  1599. struct mlx4_priv *priv = mlx4_priv(dev);
  1600. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1601. struct res_mtt *mtt;
  1602. int err = -EINVAL;
  1603. spin_lock_irq(mlx4_tlock(dev));
  1604. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1605. com.list) {
  1606. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1607. *res = mtt;
  1608. mtt->com.from_state = mtt->com.state;
  1609. mtt->com.state = RES_MTT_BUSY;
  1610. err = 0;
  1611. break;
  1612. }
  1613. }
  1614. spin_unlock_irq(mlx4_tlock(dev));
  1615. return err;
  1616. }
  1617. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1618. struct mlx4_vhcr *vhcr,
  1619. struct mlx4_cmd_mailbox *inbox,
  1620. struct mlx4_cmd_mailbox *outbox,
  1621. struct mlx4_cmd_info *cmd)
  1622. {
  1623. struct mlx4_mtt mtt;
  1624. __be64 *page_list = inbox->buf;
  1625. u64 *pg_list = (u64 *)page_list;
  1626. int i;
  1627. struct res_mtt *rmtt = NULL;
  1628. int start = be64_to_cpu(page_list[0]);
  1629. int npages = vhcr->in_modifier;
  1630. int err;
  1631. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1632. if (err)
  1633. return err;
  1634. /* Call the SW implementation of write_mtt:
  1635. * - Prepare a dummy mtt struct
  1636. * - Translate inbox contents to simple addresses in host endianess */
  1637. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1638. we don't really use it */
  1639. mtt.order = 0;
  1640. mtt.page_shift = 0;
  1641. for (i = 0; i < npages; ++i)
  1642. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1643. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1644. ((u64 *)page_list + 2));
  1645. if (rmtt)
  1646. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1647. return err;
  1648. }
  1649. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1650. struct mlx4_vhcr *vhcr,
  1651. struct mlx4_cmd_mailbox *inbox,
  1652. struct mlx4_cmd_mailbox *outbox,
  1653. struct mlx4_cmd_info *cmd)
  1654. {
  1655. int eqn = vhcr->in_modifier;
  1656. int res_id = eqn | (slave << 8);
  1657. struct res_eq *eq;
  1658. int err;
  1659. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1660. if (err)
  1661. return err;
  1662. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1663. if (err)
  1664. goto ex_abort;
  1665. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1666. if (err)
  1667. goto ex_put;
  1668. atomic_dec(&eq->mtt->ref_count);
  1669. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1670. res_end_move(dev, slave, RES_EQ, res_id);
  1671. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1672. return 0;
  1673. ex_put:
  1674. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1675. ex_abort:
  1676. res_abort_move(dev, slave, RES_EQ, res_id);
  1677. return err;
  1678. }
  1679. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1680. {
  1681. struct mlx4_priv *priv = mlx4_priv(dev);
  1682. struct mlx4_slave_event_eq_info *event_eq;
  1683. struct mlx4_cmd_mailbox *mailbox;
  1684. u32 in_modifier = 0;
  1685. int err;
  1686. int res_id;
  1687. struct res_eq *req;
  1688. if (!priv->mfunc.master.slave_state)
  1689. return -EINVAL;
  1690. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1691. /* Create the event only if the slave is registered */
  1692. if (event_eq->eqn < 0)
  1693. return 0;
  1694. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1695. res_id = (slave << 8) | event_eq->eqn;
  1696. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1697. if (err)
  1698. goto unlock;
  1699. if (req->com.from_state != RES_EQ_HW) {
  1700. err = -EINVAL;
  1701. goto put;
  1702. }
  1703. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1704. if (IS_ERR(mailbox)) {
  1705. err = PTR_ERR(mailbox);
  1706. goto put;
  1707. }
  1708. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1709. ++event_eq->token;
  1710. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1711. }
  1712. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1713. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1714. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1715. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1716. MLX4_CMD_NATIVE);
  1717. put_res(dev, slave, res_id, RES_EQ);
  1718. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1719. mlx4_free_cmd_mailbox(dev, mailbox);
  1720. return err;
  1721. put:
  1722. put_res(dev, slave, res_id, RES_EQ);
  1723. unlock:
  1724. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1725. return err;
  1726. }
  1727. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1728. struct mlx4_vhcr *vhcr,
  1729. struct mlx4_cmd_mailbox *inbox,
  1730. struct mlx4_cmd_mailbox *outbox,
  1731. struct mlx4_cmd_info *cmd)
  1732. {
  1733. int eqn = vhcr->in_modifier;
  1734. int res_id = eqn | (slave << 8);
  1735. struct res_eq *eq;
  1736. int err;
  1737. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1738. if (err)
  1739. return err;
  1740. if (eq->com.from_state != RES_EQ_HW) {
  1741. err = -EINVAL;
  1742. goto ex_put;
  1743. }
  1744. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1745. ex_put:
  1746. put_res(dev, slave, res_id, RES_EQ);
  1747. return err;
  1748. }
  1749. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1750. struct mlx4_vhcr *vhcr,
  1751. struct mlx4_cmd_mailbox *inbox,
  1752. struct mlx4_cmd_mailbox *outbox,
  1753. struct mlx4_cmd_info *cmd)
  1754. {
  1755. int err;
  1756. int cqn = vhcr->in_modifier;
  1757. struct mlx4_cq_context *cqc = inbox->buf;
  1758. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1759. struct res_cq *cq;
  1760. struct res_mtt *mtt;
  1761. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1762. if (err)
  1763. return err;
  1764. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1765. if (err)
  1766. goto out_move;
  1767. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1768. if (err)
  1769. goto out_put;
  1770. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1771. if (err)
  1772. goto out_put;
  1773. atomic_inc(&mtt->ref_count);
  1774. cq->mtt = mtt;
  1775. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1776. res_end_move(dev, slave, RES_CQ, cqn);
  1777. return 0;
  1778. out_put:
  1779. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1780. out_move:
  1781. res_abort_move(dev, slave, RES_CQ, cqn);
  1782. return err;
  1783. }
  1784. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1785. struct mlx4_vhcr *vhcr,
  1786. struct mlx4_cmd_mailbox *inbox,
  1787. struct mlx4_cmd_mailbox *outbox,
  1788. struct mlx4_cmd_info *cmd)
  1789. {
  1790. int err;
  1791. int cqn = vhcr->in_modifier;
  1792. struct res_cq *cq;
  1793. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1794. if (err)
  1795. return err;
  1796. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1797. if (err)
  1798. goto out_move;
  1799. atomic_dec(&cq->mtt->ref_count);
  1800. res_end_move(dev, slave, RES_CQ, cqn);
  1801. return 0;
  1802. out_move:
  1803. res_abort_move(dev, slave, RES_CQ, cqn);
  1804. return err;
  1805. }
  1806. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1807. struct mlx4_vhcr *vhcr,
  1808. struct mlx4_cmd_mailbox *inbox,
  1809. struct mlx4_cmd_mailbox *outbox,
  1810. struct mlx4_cmd_info *cmd)
  1811. {
  1812. int cqn = vhcr->in_modifier;
  1813. struct res_cq *cq;
  1814. int err;
  1815. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1816. if (err)
  1817. return err;
  1818. if (cq->com.from_state != RES_CQ_HW)
  1819. goto ex_put;
  1820. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1821. ex_put:
  1822. put_res(dev, slave, cqn, RES_CQ);
  1823. return err;
  1824. }
  1825. static int handle_resize(struct mlx4_dev *dev, int slave,
  1826. struct mlx4_vhcr *vhcr,
  1827. struct mlx4_cmd_mailbox *inbox,
  1828. struct mlx4_cmd_mailbox *outbox,
  1829. struct mlx4_cmd_info *cmd,
  1830. struct res_cq *cq)
  1831. {
  1832. int err;
  1833. struct res_mtt *orig_mtt;
  1834. struct res_mtt *mtt;
  1835. struct mlx4_cq_context *cqc = inbox->buf;
  1836. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1837. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1838. if (err)
  1839. return err;
  1840. if (orig_mtt != cq->mtt) {
  1841. err = -EINVAL;
  1842. goto ex_put;
  1843. }
  1844. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1845. if (err)
  1846. goto ex_put;
  1847. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1848. if (err)
  1849. goto ex_put1;
  1850. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1851. if (err)
  1852. goto ex_put1;
  1853. atomic_dec(&orig_mtt->ref_count);
  1854. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1855. atomic_inc(&mtt->ref_count);
  1856. cq->mtt = mtt;
  1857. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1858. return 0;
  1859. ex_put1:
  1860. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1861. ex_put:
  1862. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1863. return err;
  1864. }
  1865. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1866. struct mlx4_vhcr *vhcr,
  1867. struct mlx4_cmd_mailbox *inbox,
  1868. struct mlx4_cmd_mailbox *outbox,
  1869. struct mlx4_cmd_info *cmd)
  1870. {
  1871. int cqn = vhcr->in_modifier;
  1872. struct res_cq *cq;
  1873. int err;
  1874. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1875. if (err)
  1876. return err;
  1877. if (cq->com.from_state != RES_CQ_HW)
  1878. goto ex_put;
  1879. if (vhcr->op_modifier == 0) {
  1880. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1881. if (err)
  1882. goto ex_put;
  1883. }
  1884. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1885. ex_put:
  1886. put_res(dev, slave, cqn, RES_CQ);
  1887. return err;
  1888. }
  1889. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1890. {
  1891. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1892. int log_rq_stride = srqc->logstride & 7;
  1893. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1894. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1895. return 1;
  1896. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1897. }
  1898. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1899. struct mlx4_vhcr *vhcr,
  1900. struct mlx4_cmd_mailbox *inbox,
  1901. struct mlx4_cmd_mailbox *outbox,
  1902. struct mlx4_cmd_info *cmd)
  1903. {
  1904. int err;
  1905. int srqn = vhcr->in_modifier;
  1906. struct res_mtt *mtt;
  1907. struct res_srq *srq;
  1908. struct mlx4_srq_context *srqc = inbox->buf;
  1909. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1910. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  1911. return -EINVAL;
  1912. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  1913. if (err)
  1914. return err;
  1915. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1916. if (err)
  1917. goto ex_abort;
  1918. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  1919. mtt);
  1920. if (err)
  1921. goto ex_put_mtt;
  1922. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1923. if (err)
  1924. goto ex_put_mtt;
  1925. atomic_inc(&mtt->ref_count);
  1926. srq->mtt = mtt;
  1927. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1928. res_end_move(dev, slave, RES_SRQ, srqn);
  1929. return 0;
  1930. ex_put_mtt:
  1931. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1932. ex_abort:
  1933. res_abort_move(dev, slave, RES_SRQ, srqn);
  1934. return err;
  1935. }
  1936. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1937. struct mlx4_vhcr *vhcr,
  1938. struct mlx4_cmd_mailbox *inbox,
  1939. struct mlx4_cmd_mailbox *outbox,
  1940. struct mlx4_cmd_info *cmd)
  1941. {
  1942. int err;
  1943. int srqn = vhcr->in_modifier;
  1944. struct res_srq *srq;
  1945. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  1946. if (err)
  1947. return err;
  1948. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1949. if (err)
  1950. goto ex_abort;
  1951. atomic_dec(&srq->mtt->ref_count);
  1952. if (srq->cq)
  1953. atomic_dec(&srq->cq->ref_count);
  1954. res_end_move(dev, slave, RES_SRQ, srqn);
  1955. return 0;
  1956. ex_abort:
  1957. res_abort_move(dev, slave, RES_SRQ, srqn);
  1958. return err;
  1959. }
  1960. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1961. struct mlx4_vhcr *vhcr,
  1962. struct mlx4_cmd_mailbox *inbox,
  1963. struct mlx4_cmd_mailbox *outbox,
  1964. struct mlx4_cmd_info *cmd)
  1965. {
  1966. int err;
  1967. int srqn = vhcr->in_modifier;
  1968. struct res_srq *srq;
  1969. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1970. if (err)
  1971. return err;
  1972. if (srq->com.from_state != RES_SRQ_HW) {
  1973. err = -EBUSY;
  1974. goto out;
  1975. }
  1976. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1977. out:
  1978. put_res(dev, slave, srqn, RES_SRQ);
  1979. return err;
  1980. }
  1981. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1982. struct mlx4_vhcr *vhcr,
  1983. struct mlx4_cmd_mailbox *inbox,
  1984. struct mlx4_cmd_mailbox *outbox,
  1985. struct mlx4_cmd_info *cmd)
  1986. {
  1987. int err;
  1988. int srqn = vhcr->in_modifier;
  1989. struct res_srq *srq;
  1990. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1991. if (err)
  1992. return err;
  1993. if (srq->com.from_state != RES_SRQ_HW) {
  1994. err = -EBUSY;
  1995. goto out;
  1996. }
  1997. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1998. out:
  1999. put_res(dev, slave, srqn, RES_SRQ);
  2000. return err;
  2001. }
  2002. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2003. struct mlx4_vhcr *vhcr,
  2004. struct mlx4_cmd_mailbox *inbox,
  2005. struct mlx4_cmd_mailbox *outbox,
  2006. struct mlx4_cmd_info *cmd)
  2007. {
  2008. int err;
  2009. int qpn = vhcr->in_modifier & 0x7fffff;
  2010. struct res_qp *qp;
  2011. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2012. if (err)
  2013. return err;
  2014. if (qp->com.from_state != RES_QP_HW) {
  2015. err = -EBUSY;
  2016. goto out;
  2017. }
  2018. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2019. out:
  2020. put_res(dev, slave, qpn, RES_QP);
  2021. return err;
  2022. }
  2023. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2024. struct mlx4_vhcr *vhcr,
  2025. struct mlx4_cmd_mailbox *inbox,
  2026. struct mlx4_cmd_mailbox *outbox,
  2027. struct mlx4_cmd_info *cmd)
  2028. {
  2029. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2030. update_ud_gid(dev, qpc, (u8)slave);
  2031. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2032. }
  2033. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2034. struct mlx4_vhcr *vhcr,
  2035. struct mlx4_cmd_mailbox *inbox,
  2036. struct mlx4_cmd_mailbox *outbox,
  2037. struct mlx4_cmd_info *cmd)
  2038. {
  2039. int err;
  2040. int qpn = vhcr->in_modifier & 0x7fffff;
  2041. struct res_qp *qp;
  2042. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2043. if (err)
  2044. return err;
  2045. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2046. if (err)
  2047. goto ex_abort;
  2048. atomic_dec(&qp->mtt->ref_count);
  2049. atomic_dec(&qp->rcq->ref_count);
  2050. atomic_dec(&qp->scq->ref_count);
  2051. if (qp->srq)
  2052. atomic_dec(&qp->srq->ref_count);
  2053. res_end_move(dev, slave, RES_QP, qpn);
  2054. return 0;
  2055. ex_abort:
  2056. res_abort_move(dev, slave, RES_QP, qpn);
  2057. return err;
  2058. }
  2059. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2060. struct res_qp *rqp, u8 *gid)
  2061. {
  2062. struct res_gid *res;
  2063. list_for_each_entry(res, &rqp->mcg_list, list) {
  2064. if (!memcmp(res->gid, gid, 16))
  2065. return res;
  2066. }
  2067. return NULL;
  2068. }
  2069. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2070. u8 *gid, enum mlx4_protocol prot)
  2071. {
  2072. struct res_gid *res;
  2073. int err;
  2074. res = kzalloc(sizeof *res, GFP_KERNEL);
  2075. if (!res)
  2076. return -ENOMEM;
  2077. spin_lock_irq(&rqp->mcg_spl);
  2078. if (find_gid(dev, slave, rqp, gid)) {
  2079. kfree(res);
  2080. err = -EEXIST;
  2081. } else {
  2082. memcpy(res->gid, gid, 16);
  2083. res->prot = prot;
  2084. list_add_tail(&res->list, &rqp->mcg_list);
  2085. err = 0;
  2086. }
  2087. spin_unlock_irq(&rqp->mcg_spl);
  2088. return err;
  2089. }
  2090. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2091. u8 *gid, enum mlx4_protocol prot)
  2092. {
  2093. struct res_gid *res;
  2094. int err;
  2095. spin_lock_irq(&rqp->mcg_spl);
  2096. res = find_gid(dev, slave, rqp, gid);
  2097. if (!res || res->prot != prot)
  2098. err = -EINVAL;
  2099. else {
  2100. list_del(&res->list);
  2101. kfree(res);
  2102. err = 0;
  2103. }
  2104. spin_unlock_irq(&rqp->mcg_spl);
  2105. return err;
  2106. }
  2107. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2108. struct mlx4_vhcr *vhcr,
  2109. struct mlx4_cmd_mailbox *inbox,
  2110. struct mlx4_cmd_mailbox *outbox,
  2111. struct mlx4_cmd_info *cmd)
  2112. {
  2113. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2114. u8 *gid = inbox->buf;
  2115. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2116. int err, err1;
  2117. int qpn;
  2118. struct res_qp *rqp;
  2119. int attach = vhcr->op_modifier;
  2120. int block_loopback = vhcr->in_modifier >> 31;
  2121. u8 steer_type_mask = 2;
  2122. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2123. qpn = vhcr->in_modifier & 0xffffff;
  2124. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2125. if (err)
  2126. return err;
  2127. qp.qpn = qpn;
  2128. if (attach) {
  2129. err = add_mcg_res(dev, slave, rqp, gid, prot);
  2130. if (err)
  2131. goto ex_put;
  2132. err = mlx4_qp_attach_common(dev, &qp, gid,
  2133. block_loopback, prot, type);
  2134. if (err)
  2135. goto ex_rem;
  2136. } else {
  2137. err = rem_mcg_res(dev, slave, rqp, gid, prot);
  2138. if (err)
  2139. goto ex_put;
  2140. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2141. }
  2142. put_res(dev, slave, qpn, RES_QP);
  2143. return 0;
  2144. ex_rem:
  2145. /* ignore error return below, already in error */
  2146. err1 = rem_mcg_res(dev, slave, rqp, gid, prot);
  2147. ex_put:
  2148. put_res(dev, slave, qpn, RES_QP);
  2149. return err;
  2150. }
  2151. enum {
  2152. BUSY_MAX_RETRIES = 10
  2153. };
  2154. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2155. struct mlx4_vhcr *vhcr,
  2156. struct mlx4_cmd_mailbox *inbox,
  2157. struct mlx4_cmd_mailbox *outbox,
  2158. struct mlx4_cmd_info *cmd)
  2159. {
  2160. int err;
  2161. int index = vhcr->in_modifier & 0xffff;
  2162. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2163. if (err)
  2164. return err;
  2165. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2166. put_res(dev, slave, index, RES_COUNTER);
  2167. return err;
  2168. }
  2169. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2170. {
  2171. struct res_gid *rgid;
  2172. struct res_gid *tmp;
  2173. int err;
  2174. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2175. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2176. qp.qpn = rqp->local_qpn;
  2177. err = mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2178. MLX4_MC_STEER);
  2179. list_del(&rgid->list);
  2180. kfree(rgid);
  2181. }
  2182. }
  2183. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2184. enum mlx4_resource type, int print)
  2185. {
  2186. struct mlx4_priv *priv = mlx4_priv(dev);
  2187. struct mlx4_resource_tracker *tracker =
  2188. &priv->mfunc.master.res_tracker;
  2189. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2190. struct res_common *r;
  2191. struct res_common *tmp;
  2192. int busy;
  2193. busy = 0;
  2194. spin_lock_irq(mlx4_tlock(dev));
  2195. list_for_each_entry_safe(r, tmp, rlist, list) {
  2196. if (r->owner == slave) {
  2197. if (!r->removing) {
  2198. if (r->state == RES_ANY_BUSY) {
  2199. if (print)
  2200. mlx4_dbg(dev,
  2201. "%s id 0x%x is busy\n",
  2202. ResourceType(type),
  2203. r->res_id);
  2204. ++busy;
  2205. } else {
  2206. r->from_state = r->state;
  2207. r->state = RES_ANY_BUSY;
  2208. r->removing = 1;
  2209. }
  2210. }
  2211. }
  2212. }
  2213. spin_unlock_irq(mlx4_tlock(dev));
  2214. return busy;
  2215. }
  2216. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2217. enum mlx4_resource type)
  2218. {
  2219. unsigned long begin;
  2220. int busy;
  2221. begin = jiffies;
  2222. do {
  2223. busy = _move_all_busy(dev, slave, type, 0);
  2224. if (time_after(jiffies, begin + 5 * HZ))
  2225. break;
  2226. if (busy)
  2227. cond_resched();
  2228. } while (busy);
  2229. if (busy)
  2230. busy = _move_all_busy(dev, slave, type, 1);
  2231. return busy;
  2232. }
  2233. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2234. {
  2235. struct mlx4_priv *priv = mlx4_priv(dev);
  2236. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2237. struct list_head *qp_list =
  2238. &tracker->slave_list[slave].res_list[RES_QP];
  2239. struct res_qp *qp;
  2240. struct res_qp *tmp;
  2241. int state;
  2242. u64 in_param;
  2243. int qpn;
  2244. int err;
  2245. err = move_all_busy(dev, slave, RES_QP);
  2246. if (err)
  2247. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2248. "for slave %d\n", slave);
  2249. spin_lock_irq(mlx4_tlock(dev));
  2250. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2251. spin_unlock_irq(mlx4_tlock(dev));
  2252. if (qp->com.owner == slave) {
  2253. qpn = qp->com.res_id;
  2254. detach_qp(dev, slave, qp);
  2255. state = qp->com.from_state;
  2256. while (state != 0) {
  2257. switch (state) {
  2258. case RES_QP_RESERVED:
  2259. spin_lock_irq(mlx4_tlock(dev));
  2260. radix_tree_delete(&tracker->res_tree[RES_QP],
  2261. qp->com.res_id);
  2262. list_del(&qp->com.list);
  2263. spin_unlock_irq(mlx4_tlock(dev));
  2264. kfree(qp);
  2265. state = 0;
  2266. break;
  2267. case RES_QP_MAPPED:
  2268. if (!valid_reserved(dev, slave, qpn))
  2269. __mlx4_qp_free_icm(dev, qpn);
  2270. state = RES_QP_RESERVED;
  2271. break;
  2272. case RES_QP_HW:
  2273. in_param = slave;
  2274. err = mlx4_cmd(dev, in_param,
  2275. qp->local_qpn, 2,
  2276. MLX4_CMD_2RST_QP,
  2277. MLX4_CMD_TIME_CLASS_A,
  2278. MLX4_CMD_NATIVE);
  2279. if (err)
  2280. mlx4_dbg(dev, "rem_slave_qps: failed"
  2281. " to move slave %d qpn %d to"
  2282. " reset\n", slave,
  2283. qp->local_qpn);
  2284. atomic_dec(&qp->rcq->ref_count);
  2285. atomic_dec(&qp->scq->ref_count);
  2286. atomic_dec(&qp->mtt->ref_count);
  2287. if (qp->srq)
  2288. atomic_dec(&qp->srq->ref_count);
  2289. state = RES_QP_MAPPED;
  2290. break;
  2291. default:
  2292. state = 0;
  2293. }
  2294. }
  2295. }
  2296. spin_lock_irq(mlx4_tlock(dev));
  2297. }
  2298. spin_unlock_irq(mlx4_tlock(dev));
  2299. }
  2300. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2301. {
  2302. struct mlx4_priv *priv = mlx4_priv(dev);
  2303. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2304. struct list_head *srq_list =
  2305. &tracker->slave_list[slave].res_list[RES_SRQ];
  2306. struct res_srq *srq;
  2307. struct res_srq *tmp;
  2308. int state;
  2309. u64 in_param;
  2310. LIST_HEAD(tlist);
  2311. int srqn;
  2312. int err;
  2313. err = move_all_busy(dev, slave, RES_SRQ);
  2314. if (err)
  2315. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2316. "busy for slave %d\n", slave);
  2317. spin_lock_irq(mlx4_tlock(dev));
  2318. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2319. spin_unlock_irq(mlx4_tlock(dev));
  2320. if (srq->com.owner == slave) {
  2321. srqn = srq->com.res_id;
  2322. state = srq->com.from_state;
  2323. while (state != 0) {
  2324. switch (state) {
  2325. case RES_SRQ_ALLOCATED:
  2326. __mlx4_srq_free_icm(dev, srqn);
  2327. spin_lock_irq(mlx4_tlock(dev));
  2328. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2329. srqn);
  2330. list_del(&srq->com.list);
  2331. spin_unlock_irq(mlx4_tlock(dev));
  2332. kfree(srq);
  2333. state = 0;
  2334. break;
  2335. case RES_SRQ_HW:
  2336. in_param = slave;
  2337. err = mlx4_cmd(dev, in_param, srqn, 1,
  2338. MLX4_CMD_HW2SW_SRQ,
  2339. MLX4_CMD_TIME_CLASS_A,
  2340. MLX4_CMD_NATIVE);
  2341. if (err)
  2342. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2343. " to move slave %d srq %d to"
  2344. " SW ownership\n",
  2345. slave, srqn);
  2346. atomic_dec(&srq->mtt->ref_count);
  2347. if (srq->cq)
  2348. atomic_dec(&srq->cq->ref_count);
  2349. state = RES_SRQ_ALLOCATED;
  2350. break;
  2351. default:
  2352. state = 0;
  2353. }
  2354. }
  2355. }
  2356. spin_lock_irq(mlx4_tlock(dev));
  2357. }
  2358. spin_unlock_irq(mlx4_tlock(dev));
  2359. }
  2360. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2361. {
  2362. struct mlx4_priv *priv = mlx4_priv(dev);
  2363. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2364. struct list_head *cq_list =
  2365. &tracker->slave_list[slave].res_list[RES_CQ];
  2366. struct res_cq *cq;
  2367. struct res_cq *tmp;
  2368. int state;
  2369. u64 in_param;
  2370. LIST_HEAD(tlist);
  2371. int cqn;
  2372. int err;
  2373. err = move_all_busy(dev, slave, RES_CQ);
  2374. if (err)
  2375. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2376. "busy for slave %d\n", slave);
  2377. spin_lock_irq(mlx4_tlock(dev));
  2378. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2379. spin_unlock_irq(mlx4_tlock(dev));
  2380. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2381. cqn = cq->com.res_id;
  2382. state = cq->com.from_state;
  2383. while (state != 0) {
  2384. switch (state) {
  2385. case RES_CQ_ALLOCATED:
  2386. __mlx4_cq_free_icm(dev, cqn);
  2387. spin_lock_irq(mlx4_tlock(dev));
  2388. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2389. cqn);
  2390. list_del(&cq->com.list);
  2391. spin_unlock_irq(mlx4_tlock(dev));
  2392. kfree(cq);
  2393. state = 0;
  2394. break;
  2395. case RES_CQ_HW:
  2396. in_param = slave;
  2397. err = mlx4_cmd(dev, in_param, cqn, 1,
  2398. MLX4_CMD_HW2SW_CQ,
  2399. MLX4_CMD_TIME_CLASS_A,
  2400. MLX4_CMD_NATIVE);
  2401. if (err)
  2402. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2403. " to move slave %d cq %d to"
  2404. " SW ownership\n",
  2405. slave, cqn);
  2406. atomic_dec(&cq->mtt->ref_count);
  2407. state = RES_CQ_ALLOCATED;
  2408. break;
  2409. default:
  2410. state = 0;
  2411. }
  2412. }
  2413. }
  2414. spin_lock_irq(mlx4_tlock(dev));
  2415. }
  2416. spin_unlock_irq(mlx4_tlock(dev));
  2417. }
  2418. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2419. {
  2420. struct mlx4_priv *priv = mlx4_priv(dev);
  2421. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2422. struct list_head *mpt_list =
  2423. &tracker->slave_list[slave].res_list[RES_MPT];
  2424. struct res_mpt *mpt;
  2425. struct res_mpt *tmp;
  2426. int state;
  2427. u64 in_param;
  2428. LIST_HEAD(tlist);
  2429. int mptn;
  2430. int err;
  2431. err = move_all_busy(dev, slave, RES_MPT);
  2432. if (err)
  2433. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2434. "busy for slave %d\n", slave);
  2435. spin_lock_irq(mlx4_tlock(dev));
  2436. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2437. spin_unlock_irq(mlx4_tlock(dev));
  2438. if (mpt->com.owner == slave) {
  2439. mptn = mpt->com.res_id;
  2440. state = mpt->com.from_state;
  2441. while (state != 0) {
  2442. switch (state) {
  2443. case RES_MPT_RESERVED:
  2444. __mlx4_mr_release(dev, mpt->key);
  2445. spin_lock_irq(mlx4_tlock(dev));
  2446. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2447. mptn);
  2448. list_del(&mpt->com.list);
  2449. spin_unlock_irq(mlx4_tlock(dev));
  2450. kfree(mpt);
  2451. state = 0;
  2452. break;
  2453. case RES_MPT_MAPPED:
  2454. __mlx4_mr_free_icm(dev, mpt->key);
  2455. state = RES_MPT_RESERVED;
  2456. break;
  2457. case RES_MPT_HW:
  2458. in_param = slave;
  2459. err = mlx4_cmd(dev, in_param, mptn, 0,
  2460. MLX4_CMD_HW2SW_MPT,
  2461. MLX4_CMD_TIME_CLASS_A,
  2462. MLX4_CMD_NATIVE);
  2463. if (err)
  2464. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2465. " to move slave %d mpt %d to"
  2466. " SW ownership\n",
  2467. slave, mptn);
  2468. if (mpt->mtt)
  2469. atomic_dec(&mpt->mtt->ref_count);
  2470. state = RES_MPT_MAPPED;
  2471. break;
  2472. default:
  2473. state = 0;
  2474. }
  2475. }
  2476. }
  2477. spin_lock_irq(mlx4_tlock(dev));
  2478. }
  2479. spin_unlock_irq(mlx4_tlock(dev));
  2480. }
  2481. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2482. {
  2483. struct mlx4_priv *priv = mlx4_priv(dev);
  2484. struct mlx4_resource_tracker *tracker =
  2485. &priv->mfunc.master.res_tracker;
  2486. struct list_head *mtt_list =
  2487. &tracker->slave_list[slave].res_list[RES_MTT];
  2488. struct res_mtt *mtt;
  2489. struct res_mtt *tmp;
  2490. int state;
  2491. LIST_HEAD(tlist);
  2492. int base;
  2493. int err;
  2494. err = move_all_busy(dev, slave, RES_MTT);
  2495. if (err)
  2496. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2497. "busy for slave %d\n", slave);
  2498. spin_lock_irq(mlx4_tlock(dev));
  2499. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2500. spin_unlock_irq(mlx4_tlock(dev));
  2501. if (mtt->com.owner == slave) {
  2502. base = mtt->com.res_id;
  2503. state = mtt->com.from_state;
  2504. while (state != 0) {
  2505. switch (state) {
  2506. case RES_MTT_ALLOCATED:
  2507. __mlx4_free_mtt_range(dev, base,
  2508. mtt->order);
  2509. spin_lock_irq(mlx4_tlock(dev));
  2510. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2511. base);
  2512. list_del(&mtt->com.list);
  2513. spin_unlock_irq(mlx4_tlock(dev));
  2514. kfree(mtt);
  2515. state = 0;
  2516. break;
  2517. default:
  2518. state = 0;
  2519. }
  2520. }
  2521. }
  2522. spin_lock_irq(mlx4_tlock(dev));
  2523. }
  2524. spin_unlock_irq(mlx4_tlock(dev));
  2525. }
  2526. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2527. {
  2528. struct mlx4_priv *priv = mlx4_priv(dev);
  2529. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2530. struct list_head *eq_list =
  2531. &tracker->slave_list[slave].res_list[RES_EQ];
  2532. struct res_eq *eq;
  2533. struct res_eq *tmp;
  2534. int err;
  2535. int state;
  2536. LIST_HEAD(tlist);
  2537. int eqn;
  2538. struct mlx4_cmd_mailbox *mailbox;
  2539. err = move_all_busy(dev, slave, RES_EQ);
  2540. if (err)
  2541. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2542. "busy for slave %d\n", slave);
  2543. spin_lock_irq(mlx4_tlock(dev));
  2544. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2545. spin_unlock_irq(mlx4_tlock(dev));
  2546. if (eq->com.owner == slave) {
  2547. eqn = eq->com.res_id;
  2548. state = eq->com.from_state;
  2549. while (state != 0) {
  2550. switch (state) {
  2551. case RES_EQ_RESERVED:
  2552. spin_lock_irq(mlx4_tlock(dev));
  2553. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2554. eqn);
  2555. list_del(&eq->com.list);
  2556. spin_unlock_irq(mlx4_tlock(dev));
  2557. kfree(eq);
  2558. state = 0;
  2559. break;
  2560. case RES_EQ_HW:
  2561. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2562. if (IS_ERR(mailbox)) {
  2563. cond_resched();
  2564. continue;
  2565. }
  2566. err = mlx4_cmd_box(dev, slave, 0,
  2567. eqn & 0xff, 0,
  2568. MLX4_CMD_HW2SW_EQ,
  2569. MLX4_CMD_TIME_CLASS_A,
  2570. MLX4_CMD_NATIVE);
  2571. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2572. " to move slave %d eqs %d to"
  2573. " SW ownership\n", slave, eqn);
  2574. mlx4_free_cmd_mailbox(dev, mailbox);
  2575. if (!err) {
  2576. atomic_dec(&eq->mtt->ref_count);
  2577. state = RES_EQ_RESERVED;
  2578. }
  2579. break;
  2580. default:
  2581. state = 0;
  2582. }
  2583. }
  2584. }
  2585. spin_lock_irq(mlx4_tlock(dev));
  2586. }
  2587. spin_unlock_irq(mlx4_tlock(dev));
  2588. }
  2589. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2590. {
  2591. struct mlx4_priv *priv = mlx4_priv(dev);
  2592. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2593. /*VLAN*/
  2594. rem_slave_macs(dev, slave);
  2595. rem_slave_qps(dev, slave);
  2596. rem_slave_srqs(dev, slave);
  2597. rem_slave_cqs(dev, slave);
  2598. rem_slave_mrs(dev, slave);
  2599. rem_slave_eqs(dev, slave);
  2600. rem_slave_mtts(dev, slave);
  2601. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2602. }