ide-dma.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954
  1. /*
  2. * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000
  3. *
  4. * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  5. * May be copied or modified under the terms of the GNU General Public License
  6. */
  7. /*
  8. * Special Thanks to Mark for his Six years of work.
  9. *
  10. * Copyright (c) 1995-1998 Mark Lord
  11. * May be copied or modified under the terms of the GNU General Public License
  12. */
  13. /*
  14. * This module provides support for the bus-master IDE DMA functions
  15. * of various PCI chipsets, including the Intel PIIX (i82371FB for
  16. * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and
  17. * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset)
  18. * ("PIIX" stands for "PCI ISA IDE Xcellerator").
  19. *
  20. * Pretty much the same code works for other IDE PCI bus-mastering chipsets.
  21. *
  22. * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
  23. *
  24. * By default, DMA support is prepared for use, but is currently enabled only
  25. * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single),
  26. * or which are recognized as "good" (see table below). Drives with only mode0
  27. * or mode1 (multi/single) DMA should also work with this chipset/driver
  28. * (eg. MC2112A) but are not enabled by default.
  29. *
  30. * Use "hdparm -i" to view modes supported by a given drive.
  31. *
  32. * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling
  33. * DMA support, but must be (re-)compiled against this kernel version or later.
  34. *
  35. * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
  36. * If problems arise, ide.c will disable DMA operation after a few retries.
  37. * This error recovery mechanism works and has been extremely well exercised.
  38. *
  39. * IDE drives, depending on their vintage, may support several different modes
  40. * of DMA operation. The boot-time modes are indicated with a "*" in
  41. * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
  42. * the "hdparm -X" feature. There is seldom a need to do this, as drives
  43. * normally power-up with their "best" PIO/DMA modes enabled.
  44. *
  45. * Testing has been done with a rather extensive number of drives,
  46. * with Quantum & Western Digital models generally outperforming the pack,
  47. * and Fujitsu & Conner (and some Seagate which are really Conner) drives
  48. * showing more lackluster throughput.
  49. *
  50. * Keep an eye on /var/adm/messages for "DMA disabled" messages.
  51. *
  52. * Some people have reported trouble with Intel Zappa motherboards.
  53. * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
  54. * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
  55. * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
  56. *
  57. * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
  58. * fixing the problem with the BIOS on some Acer motherboards.
  59. *
  60. * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
  61. * "TX" chipset compatibility and for providing patches for the "TX" chipset.
  62. *
  63. * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
  64. * at generic DMA -- his patches were referred to when preparing this code.
  65. *
  66. * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
  67. * for supplying a Promise UDMA board & WD UDMA drive for this work!
  68. *
  69. * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports.
  70. *
  71. * ATA-66/100 and recovery functions, I forgot the rest......
  72. *
  73. */
  74. #include <linux/module.h>
  75. #include <linux/types.h>
  76. #include <linux/kernel.h>
  77. #include <linux/timer.h>
  78. #include <linux/mm.h>
  79. #include <linux/interrupt.h>
  80. #include <linux/pci.h>
  81. #include <linux/init.h>
  82. #include <linux/ide.h>
  83. #include <linux/delay.h>
  84. #include <linux/scatterlist.h>
  85. #include <asm/io.h>
  86. #include <asm/irq.h>
  87. static const struct drive_list_entry drive_whitelist [] = {
  88. { "Micropolis 2112A" , "ALL" },
  89. { "CONNER CTMA 4000" , "ALL" },
  90. { "CONNER CTT8000-A" , "ALL" },
  91. { "ST34342A" , "ALL" },
  92. { NULL , NULL }
  93. };
  94. static const struct drive_list_entry drive_blacklist [] = {
  95. { "WDC AC11000H" , "ALL" },
  96. { "WDC AC22100H" , "ALL" },
  97. { "WDC AC32500H" , "ALL" },
  98. { "WDC AC33100H" , "ALL" },
  99. { "WDC AC31600H" , "ALL" },
  100. { "WDC AC32100H" , "24.09P07" },
  101. { "WDC AC23200L" , "21.10N21" },
  102. { "Compaq CRD-8241B" , "ALL" },
  103. { "CRD-8400B" , "ALL" },
  104. { "CRD-8480B", "ALL" },
  105. { "CRD-8482B", "ALL" },
  106. { "CRD-84" , "ALL" },
  107. { "SanDisk SDP3B" , "ALL" },
  108. { "SanDisk SDP3B-64" , "ALL" },
  109. { "SANYO CD-ROM CRD" , "ALL" },
  110. { "HITACHI CDR-8" , "ALL" },
  111. { "HITACHI CDR-8335" , "ALL" },
  112. { "HITACHI CDR-8435" , "ALL" },
  113. { "Toshiba CD-ROM XM-6202B" , "ALL" },
  114. { "CD-532E-A" , "ALL" },
  115. { "E-IDE CD-ROM CR-840", "ALL" },
  116. { "CD-ROM Drive/F5A", "ALL" },
  117. { "WPI CDD-820", "ALL" },
  118. { "SAMSUNG CD-ROM SC-148C", "ALL" },
  119. { "SAMSUNG CD-ROM SC", "ALL" },
  120. { "SanDisk SDP3B-64" , "ALL" },
  121. { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
  122. { "_NEC DV5800A", "ALL" },
  123. { NULL , NULL }
  124. };
  125. /**
  126. * ide_in_drive_list - look for drive in black/white list
  127. * @id: drive identifier
  128. * @drive_table: list to inspect
  129. *
  130. * Look for a drive in the blacklist and the whitelist tables
  131. * Returns 1 if the drive is found in the table.
  132. */
  133. int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
  134. {
  135. for ( ; drive_table->id_model ; drive_table++)
  136. if ((!strcmp(drive_table->id_model, id->model)) &&
  137. ((strstr(id->fw_rev, drive_table->id_firmware)) ||
  138. (!strcmp(drive_table->id_firmware, "ALL"))))
  139. return 1;
  140. return 0;
  141. }
  142. /**
  143. * ide_dma_intr - IDE DMA interrupt handler
  144. * @drive: the drive the interrupt is for
  145. *
  146. * Handle an interrupt completing a read/write DMA transfer on an
  147. * IDE device
  148. */
  149. ide_startstop_t ide_dma_intr (ide_drive_t *drive)
  150. {
  151. u8 stat = 0, dma_stat = 0;
  152. dma_stat = HWIF(drive)->ide_dma_end(drive);
  153. stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
  154. if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
  155. if (!dma_stat) {
  156. struct request *rq = HWGROUP(drive)->rq;
  157. if (rq->rq_disk) {
  158. ide_driver_t *drv;
  159. drv = *(ide_driver_t **)rq->rq_disk->private_data;
  160. drv->end_request(drive, 1, rq->nr_sectors);
  161. } else
  162. ide_end_request(drive, 1, rq->nr_sectors);
  163. return ide_stopped;
  164. }
  165. printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
  166. drive->name, dma_stat);
  167. }
  168. return ide_error(drive, "dma_intr", stat);
  169. }
  170. EXPORT_SYMBOL_GPL(ide_dma_intr);
  171. #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
  172. /**
  173. * ide_build_sglist - map IDE scatter gather for DMA I/O
  174. * @drive: the drive to build the DMA table for
  175. * @rq: the request holding the sg list
  176. *
  177. * Perform the PCI mapping magic necessary to access the source or
  178. * target buffers of a request via PCI DMA. The lower layers of the
  179. * kernel provide the necessary cache management so that we can
  180. * operate in a portable fashion
  181. */
  182. int ide_build_sglist(ide_drive_t *drive, struct request *rq)
  183. {
  184. ide_hwif_t *hwif = HWIF(drive);
  185. struct scatterlist *sg = hwif->sg_table;
  186. BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256);
  187. ide_map_sg(drive, rq);
  188. if (rq_data_dir(rq) == READ)
  189. hwif->sg_dma_direction = PCI_DMA_FROMDEVICE;
  190. else
  191. hwif->sg_dma_direction = PCI_DMA_TODEVICE;
  192. return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
  193. }
  194. EXPORT_SYMBOL_GPL(ide_build_sglist);
  195. /**
  196. * ide_build_dmatable - build IDE DMA table
  197. *
  198. * ide_build_dmatable() prepares a dma request. We map the command
  199. * to get the pci bus addresses of the buffers and then build up
  200. * the PRD table that the IDE layer wants to be fed. The code
  201. * knows about the 64K wrap bug in the CS5530.
  202. *
  203. * Returns the number of built PRD entries if all went okay,
  204. * returns 0 otherwise.
  205. *
  206. * May also be invoked from trm290.c
  207. */
  208. int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
  209. {
  210. ide_hwif_t *hwif = HWIF(drive);
  211. unsigned int *table = hwif->dmatable_cpu;
  212. unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
  213. unsigned int count = 0;
  214. int i;
  215. struct scatterlist *sg;
  216. hwif->sg_nents = i = ide_build_sglist(drive, rq);
  217. if (!i)
  218. return 0;
  219. sg = hwif->sg_table;
  220. while (i) {
  221. u32 cur_addr;
  222. u32 cur_len;
  223. cur_addr = sg_dma_address(sg);
  224. cur_len = sg_dma_len(sg);
  225. /*
  226. * Fill in the dma table, without crossing any 64kB boundaries.
  227. * Most hardware requires 16-bit alignment of all blocks,
  228. * but the trm290 requires 32-bit alignment.
  229. */
  230. while (cur_len) {
  231. if (count++ >= PRD_ENTRIES) {
  232. printk(KERN_ERR "%s: DMA table too small\n", drive->name);
  233. goto use_pio_instead;
  234. } else {
  235. u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
  236. if (bcount > cur_len)
  237. bcount = cur_len;
  238. *table++ = cpu_to_le32(cur_addr);
  239. xcount = bcount & 0xffff;
  240. if (is_trm290)
  241. xcount = ((xcount >> 2) - 1) << 16;
  242. if (xcount == 0x0000) {
  243. /*
  244. * Most chipsets correctly interpret a length of 0x0000 as 64KB,
  245. * but at least one (e.g. CS5530) misinterprets it as zero (!).
  246. * So here we break the 64KB entry into two 32KB entries instead.
  247. */
  248. if (count++ >= PRD_ENTRIES) {
  249. printk(KERN_ERR "%s: DMA table too small\n", drive->name);
  250. goto use_pio_instead;
  251. }
  252. *table++ = cpu_to_le32(0x8000);
  253. *table++ = cpu_to_le32(cur_addr + 0x8000);
  254. xcount = 0x8000;
  255. }
  256. *table++ = cpu_to_le32(xcount);
  257. cur_addr += bcount;
  258. cur_len -= bcount;
  259. }
  260. }
  261. sg++;
  262. i--;
  263. }
  264. if (count) {
  265. if (!is_trm290)
  266. *--table |= cpu_to_le32(0x80000000);
  267. return count;
  268. }
  269. printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
  270. use_pio_instead:
  271. pci_unmap_sg(hwif->pci_dev,
  272. hwif->sg_table,
  273. hwif->sg_nents,
  274. hwif->sg_dma_direction);
  275. return 0; /* revert to PIO for this request */
  276. }
  277. EXPORT_SYMBOL_GPL(ide_build_dmatable);
  278. /**
  279. * ide_destroy_dmatable - clean up DMA mapping
  280. * @drive: The drive to unmap
  281. *
  282. * Teardown mappings after DMA has completed. This must be called
  283. * after the completion of each use of ide_build_dmatable and before
  284. * the next use of ide_build_dmatable. Failure to do so will cause
  285. * an oops as only one mapping can be live for each target at a given
  286. * time.
  287. */
  288. void ide_destroy_dmatable (ide_drive_t *drive)
  289. {
  290. struct pci_dev *dev = HWIF(drive)->pci_dev;
  291. struct scatterlist *sg = HWIF(drive)->sg_table;
  292. int nents = HWIF(drive)->sg_nents;
  293. pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction);
  294. }
  295. EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
  296. /**
  297. * config_drive_for_dma - attempt to activate IDE DMA
  298. * @drive: the drive to place in DMA mode
  299. *
  300. * If the drive supports at least mode 2 DMA or UDMA of any kind
  301. * then attempt to place it into DMA mode. Drives that are known to
  302. * support DMA but predate the DMA properties or that are known
  303. * to have DMA handling bugs are also set up appropriately based
  304. * on the good/bad drive lists.
  305. */
  306. static int config_drive_for_dma (ide_drive_t *drive)
  307. {
  308. struct hd_driveid *id = drive->id;
  309. ide_hwif_t *hwif = HWIF(drive);
  310. if ((id->capability & 1) && hwif->autodma) {
  311. /*
  312. * Enable DMA on any drive that has
  313. * UltraDMA (mode 0/1/2/3/4/5/6) enabled
  314. */
  315. if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
  316. return hwif->ide_dma_on(drive);
  317. /*
  318. * Enable DMA on any drive that has mode2 DMA
  319. * (multi or single) enabled
  320. */
  321. if (id->field_valid & 2) /* regular DMA */
  322. if ((id->dma_mword & 0x404) == 0x404 ||
  323. (id->dma_1word & 0x404) == 0x404)
  324. return hwif->ide_dma_on(drive);
  325. /* Consult the list of known "good" drives */
  326. if (__ide_dma_good_drive(drive))
  327. return hwif->ide_dma_on(drive);
  328. }
  329. // if (hwif->tuneproc != NULL) hwif->tuneproc(drive, 255);
  330. return hwif->ide_dma_off_quietly(drive);
  331. }
  332. /**
  333. * dma_timer_expiry - handle a DMA timeout
  334. * @drive: Drive that timed out
  335. *
  336. * An IDE DMA transfer timed out. In the event of an error we ask
  337. * the driver to resolve the problem, if a DMA transfer is still
  338. * in progress we continue to wait (arguably we need to add a
  339. * secondary 'I don't care what the drive thinks' timeout here)
  340. * Finally if we have an interrupt we let it complete the I/O.
  341. * But only one time - we clear expiry and if it's still not
  342. * completed after WAIT_CMD, we error and retry in PIO.
  343. * This can occur if an interrupt is lost or due to hang or bugs.
  344. */
  345. static int dma_timer_expiry (ide_drive_t *drive)
  346. {
  347. ide_hwif_t *hwif = HWIF(drive);
  348. u8 dma_stat = hwif->INB(hwif->dma_status);
  349. printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
  350. drive->name, dma_stat);
  351. if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
  352. return WAIT_CMD;
  353. HWGROUP(drive)->expiry = NULL; /* one free ride for now */
  354. /* 1 dmaing, 2 error, 4 intr */
  355. if (dma_stat & 2) /* ERROR */
  356. return -1;
  357. if (dma_stat & 1) /* DMAing */
  358. return WAIT_CMD;
  359. if (dma_stat & 4) /* Got an Interrupt */
  360. return WAIT_CMD;
  361. return 0; /* Status is unknown -- reset the bus */
  362. }
  363. /**
  364. * __ide_dma_host_off - Generic DMA kill
  365. * @drive: drive to control
  366. *
  367. * Perform the generic IDE controller DMA off operation. This
  368. * works for most IDE bus mastering controllers
  369. */
  370. int __ide_dma_host_off (ide_drive_t *drive)
  371. {
  372. ide_hwif_t *hwif = HWIF(drive);
  373. u8 unit = (drive->select.b.unit & 0x01);
  374. u8 dma_stat = hwif->INB(hwif->dma_status);
  375. hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status);
  376. return 0;
  377. }
  378. EXPORT_SYMBOL(__ide_dma_host_off);
  379. /**
  380. * __ide_dma_host_off_quietly - Generic DMA kill
  381. * @drive: drive to control
  382. *
  383. * Turn off the current DMA on this IDE controller.
  384. */
  385. int __ide_dma_off_quietly (ide_drive_t *drive)
  386. {
  387. drive->using_dma = 0;
  388. ide_toggle_bounce(drive, 0);
  389. if (HWIF(drive)->ide_dma_host_off(drive))
  390. return 1;
  391. return 0;
  392. }
  393. EXPORT_SYMBOL(__ide_dma_off_quietly);
  394. #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
  395. /**
  396. * __ide_dma_off - disable DMA on a device
  397. * @drive: drive to disable DMA on
  398. *
  399. * Disable IDE DMA for a device on this IDE controller.
  400. * Inform the user that DMA has been disabled.
  401. */
  402. int __ide_dma_off (ide_drive_t *drive)
  403. {
  404. printk(KERN_INFO "%s: DMA disabled\n", drive->name);
  405. return HWIF(drive)->ide_dma_off_quietly(drive);
  406. }
  407. EXPORT_SYMBOL(__ide_dma_off);
  408. #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
  409. /**
  410. * __ide_dma_host_on - Enable DMA on a host
  411. * @drive: drive to enable for DMA
  412. *
  413. * Enable DMA on an IDE controller following generic bus mastering
  414. * IDE controller behaviour
  415. */
  416. int __ide_dma_host_on (ide_drive_t *drive)
  417. {
  418. if (drive->using_dma) {
  419. ide_hwif_t *hwif = HWIF(drive);
  420. u8 unit = (drive->select.b.unit & 0x01);
  421. u8 dma_stat = hwif->INB(hwif->dma_status);
  422. hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status);
  423. return 0;
  424. }
  425. return 1;
  426. }
  427. EXPORT_SYMBOL(__ide_dma_host_on);
  428. /**
  429. * __ide_dma_on - Enable DMA on a device
  430. * @drive: drive to enable DMA on
  431. *
  432. * Enable IDE DMA for a device on this IDE controller.
  433. */
  434. int __ide_dma_on (ide_drive_t *drive)
  435. {
  436. /* consult the list of known "bad" drives */
  437. if (__ide_dma_bad_drive(drive))
  438. return 1;
  439. drive->using_dma = 1;
  440. ide_toggle_bounce(drive, 1);
  441. if (HWIF(drive)->ide_dma_host_on(drive))
  442. return 1;
  443. return 0;
  444. }
  445. EXPORT_SYMBOL(__ide_dma_on);
  446. /**
  447. * __ide_dma_check - check DMA setup
  448. * @drive: drive to check
  449. *
  450. * Don't use - due for extermination
  451. */
  452. int __ide_dma_check (ide_drive_t *drive)
  453. {
  454. return config_drive_for_dma(drive);
  455. }
  456. EXPORT_SYMBOL(__ide_dma_check);
  457. /**
  458. * ide_dma_setup - begin a DMA phase
  459. * @drive: target device
  460. *
  461. * Build an IDE DMA PRD (IDE speak for scatter gather table)
  462. * and then set up the DMA transfer registers for a device
  463. * that follows generic IDE PCI DMA behaviour. Controllers can
  464. * override this function if they need to
  465. *
  466. * Returns 0 on success. If a PIO fallback is required then 1
  467. * is returned.
  468. */
  469. int ide_dma_setup(ide_drive_t *drive)
  470. {
  471. ide_hwif_t *hwif = drive->hwif;
  472. struct request *rq = HWGROUP(drive)->rq;
  473. unsigned int reading;
  474. u8 dma_stat;
  475. if (rq_data_dir(rq))
  476. reading = 0;
  477. else
  478. reading = 1 << 3;
  479. /* fall back to pio! */
  480. if (!ide_build_dmatable(drive, rq)) {
  481. ide_map_sg(drive, rq);
  482. return 1;
  483. }
  484. /* PRD table */
  485. if (hwif->mmio == 2)
  486. writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable);
  487. else
  488. outl(hwif->dmatable_dma, hwif->dma_prdtable);
  489. /* specify r/w */
  490. hwif->OUTB(reading, hwif->dma_command);
  491. /* read dma_status for INTR & ERROR flags */
  492. dma_stat = hwif->INB(hwif->dma_status);
  493. /* clear INTR & ERROR flags */
  494. hwif->OUTB(dma_stat|6, hwif->dma_status);
  495. drive->waiting_for_dma = 1;
  496. return 0;
  497. }
  498. EXPORT_SYMBOL_GPL(ide_dma_setup);
  499. static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
  500. {
  501. /* issue cmd to drive */
  502. ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
  503. }
  504. void ide_dma_start(ide_drive_t *drive)
  505. {
  506. ide_hwif_t *hwif = HWIF(drive);
  507. u8 dma_cmd = hwif->INB(hwif->dma_command);
  508. /* Note that this is done *after* the cmd has
  509. * been issued to the drive, as per the BM-IDE spec.
  510. * The Promise Ultra33 doesn't work correctly when
  511. * we do this part before issuing the drive cmd.
  512. */
  513. /* start DMA */
  514. hwif->OUTB(dma_cmd|1, hwif->dma_command);
  515. hwif->dma = 1;
  516. wmb();
  517. }
  518. EXPORT_SYMBOL_GPL(ide_dma_start);
  519. /* returns 1 on error, 0 otherwise */
  520. int __ide_dma_end (ide_drive_t *drive)
  521. {
  522. ide_hwif_t *hwif = HWIF(drive);
  523. u8 dma_stat = 0, dma_cmd = 0;
  524. drive->waiting_for_dma = 0;
  525. /* get dma_command mode */
  526. dma_cmd = hwif->INB(hwif->dma_command);
  527. /* stop DMA */
  528. hwif->OUTB(dma_cmd&~1, hwif->dma_command);
  529. /* get DMA status */
  530. dma_stat = hwif->INB(hwif->dma_status);
  531. /* clear the INTR & ERROR bits */
  532. hwif->OUTB(dma_stat|6, hwif->dma_status);
  533. /* purge DMA mappings */
  534. ide_destroy_dmatable(drive);
  535. /* verify good DMA status */
  536. hwif->dma = 0;
  537. wmb();
  538. return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
  539. }
  540. EXPORT_SYMBOL(__ide_dma_end);
  541. /* returns 1 if dma irq issued, 0 otherwise */
  542. static int __ide_dma_test_irq(ide_drive_t *drive)
  543. {
  544. ide_hwif_t *hwif = HWIF(drive);
  545. u8 dma_stat = hwif->INB(hwif->dma_status);
  546. #if 0 /* do not set unless you know what you are doing */
  547. if (dma_stat & 4) {
  548. u8 stat = hwif->INB(IDE_STATUS_REG);
  549. hwif->OUTB(hwif->dma_status, dma_stat & 0xE4);
  550. }
  551. #endif
  552. /* return 1 if INTR asserted */
  553. if ((dma_stat & 4) == 4)
  554. return 1;
  555. if (!drive->waiting_for_dma)
  556. printk(KERN_WARNING "%s: (%s) called while not waiting\n",
  557. drive->name, __FUNCTION__);
  558. return 0;
  559. }
  560. #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
  561. int __ide_dma_bad_drive (ide_drive_t *drive)
  562. {
  563. struct hd_driveid *id = drive->id;
  564. int blacklist = ide_in_drive_list(id, drive_blacklist);
  565. if (blacklist) {
  566. printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
  567. drive->name, id->model);
  568. return blacklist;
  569. }
  570. return 0;
  571. }
  572. EXPORT_SYMBOL(__ide_dma_bad_drive);
  573. int __ide_dma_good_drive (ide_drive_t *drive)
  574. {
  575. struct hd_driveid *id = drive->id;
  576. return ide_in_drive_list(id, drive_whitelist);
  577. }
  578. EXPORT_SYMBOL(__ide_dma_good_drive);
  579. int ide_use_dma(ide_drive_t *drive)
  580. {
  581. struct hd_driveid *id = drive->id;
  582. ide_hwif_t *hwif = drive->hwif;
  583. if ((id->capability & 1) == 0 || drive->autodma == 0)
  584. return 0;
  585. /* consult the list of known "bad" drives */
  586. if (__ide_dma_bad_drive(drive))
  587. return 0;
  588. /* capable of UltraDMA modes */
  589. if (id->field_valid & 4) {
  590. if (hwif->ultra_mask & id->dma_ultra)
  591. return 1;
  592. }
  593. /* capable of regular DMA modes */
  594. if (id->field_valid & 2) {
  595. if (hwif->mwdma_mask & id->dma_mword)
  596. return 1;
  597. if (hwif->swdma_mask & id->dma_1word)
  598. return 1;
  599. }
  600. /* consult the list of known "good" drives */
  601. if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
  602. return 1;
  603. return 0;
  604. }
  605. EXPORT_SYMBOL_GPL(ide_use_dma);
  606. void ide_dma_verbose(ide_drive_t *drive)
  607. {
  608. struct hd_driveid *id = drive->id;
  609. ide_hwif_t *hwif = HWIF(drive);
  610. if (id->field_valid & 4) {
  611. if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
  612. goto bug_dma_off;
  613. if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) {
  614. if (((id->dma_ultra >> 11) & 0x1F) &&
  615. eighty_ninty_three(drive)) {
  616. if ((id->dma_ultra >> 15) & 1) {
  617. printk(", UDMA(mode 7)");
  618. } else if ((id->dma_ultra >> 14) & 1) {
  619. printk(", UDMA(133)");
  620. } else if ((id->dma_ultra >> 13) & 1) {
  621. printk(", UDMA(100)");
  622. } else if ((id->dma_ultra >> 12) & 1) {
  623. printk(", UDMA(66)");
  624. } else if ((id->dma_ultra >> 11) & 1) {
  625. printk(", UDMA(44)");
  626. } else
  627. goto mode_two;
  628. } else {
  629. mode_two:
  630. if ((id->dma_ultra >> 10) & 1) {
  631. printk(", UDMA(33)");
  632. } else if ((id->dma_ultra >> 9) & 1) {
  633. printk(", UDMA(25)");
  634. } else if ((id->dma_ultra >> 8) & 1) {
  635. printk(", UDMA(16)");
  636. }
  637. }
  638. } else {
  639. printk(", (U)DMA"); /* Can be BIOS-enabled! */
  640. }
  641. } else if (id->field_valid & 2) {
  642. if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
  643. goto bug_dma_off;
  644. printk(", DMA");
  645. } else if (id->field_valid & 1) {
  646. goto bug_dma_off;
  647. }
  648. return;
  649. bug_dma_off:
  650. printk(", BUG DMA OFF");
  651. hwif->ide_dma_off_quietly(drive);
  652. return;
  653. }
  654. EXPORT_SYMBOL(ide_dma_verbose);
  655. #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
  656. int __ide_dma_lostirq (ide_drive_t *drive)
  657. {
  658. printk("%s: DMA interrupt recovery\n", drive->name);
  659. return 1;
  660. }
  661. EXPORT_SYMBOL(__ide_dma_lostirq);
  662. int __ide_dma_timeout (ide_drive_t *drive)
  663. {
  664. printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
  665. if (HWIF(drive)->ide_dma_test_irq(drive))
  666. return 0;
  667. return HWIF(drive)->ide_dma_end(drive);
  668. }
  669. EXPORT_SYMBOL(__ide_dma_timeout);
  670. /*
  671. * Needed for allowing full modular support of ide-driver
  672. */
  673. static int ide_release_dma_engine(ide_hwif_t *hwif)
  674. {
  675. if (hwif->dmatable_cpu) {
  676. pci_free_consistent(hwif->pci_dev,
  677. PRD_ENTRIES * PRD_BYTES,
  678. hwif->dmatable_cpu,
  679. hwif->dmatable_dma);
  680. hwif->dmatable_cpu = NULL;
  681. }
  682. return 1;
  683. }
  684. static int ide_release_iomio_dma(ide_hwif_t *hwif)
  685. {
  686. release_region(hwif->dma_base, 8);
  687. if (hwif->extra_ports)
  688. release_region(hwif->extra_base, hwif->extra_ports);
  689. return 1;
  690. }
  691. /*
  692. * Needed for allowing full modular support of ide-driver
  693. */
  694. int ide_release_dma(ide_hwif_t *hwif)
  695. {
  696. ide_release_dma_engine(hwif);
  697. if (hwif->mmio == 2)
  698. return 1;
  699. else
  700. return ide_release_iomio_dma(hwif);
  701. }
  702. static int ide_allocate_dma_engine(ide_hwif_t *hwif)
  703. {
  704. hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
  705. PRD_ENTRIES * PRD_BYTES,
  706. &hwif->dmatable_dma);
  707. if (hwif->dmatable_cpu)
  708. return 0;
  709. printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n",
  710. hwif->cds->name);
  711. return 1;
  712. }
  713. static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
  714. {
  715. printk(KERN_INFO " %s: MMIO-DMA ", hwif->name);
  716. hwif->dma_base = base;
  717. if(hwif->mate)
  718. hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
  719. else
  720. hwif->dma_master = base;
  721. return 0;
  722. }
  723. static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
  724. {
  725. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
  726. hwif->name, base, base + ports - 1);
  727. if (!request_region(base, ports, hwif->name)) {
  728. printk(" -- Error, ports in use.\n");
  729. return 1;
  730. }
  731. hwif->dma_base = base;
  732. if (hwif->cds->extra) {
  733. hwif->extra_base = base + (hwif->channel ? 8 : 16);
  734. if (!hwif->mate || !hwif->mate->extra_ports) {
  735. if (!request_region(hwif->extra_base,
  736. hwif->cds->extra, hwif->cds->name)) {
  737. printk(" -- Error, extra ports in use.\n");
  738. release_region(base, ports);
  739. return 1;
  740. }
  741. hwif->extra_ports = hwif->cds->extra;
  742. }
  743. }
  744. if(hwif->mate)
  745. hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base;
  746. else
  747. hwif->dma_master = base;
  748. return 0;
  749. }
  750. static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
  751. {
  752. if (hwif->mmio == 2)
  753. return ide_mapped_mmio_dma(hwif, base,ports);
  754. BUG_ON(hwif->mmio == 1);
  755. return ide_iomio_dma(hwif, base, ports);
  756. }
  757. /*
  758. * This can be called for a dynamically installed interface. Don't __init it
  759. */
  760. void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports)
  761. {
  762. if (ide_dma_iobase(hwif, dma_base, num_ports))
  763. return;
  764. if (ide_allocate_dma_engine(hwif)) {
  765. ide_release_dma(hwif);
  766. return;
  767. }
  768. if (!(hwif->dma_command))
  769. hwif->dma_command = hwif->dma_base;
  770. if (!(hwif->dma_vendor1))
  771. hwif->dma_vendor1 = (hwif->dma_base + 1);
  772. if (!(hwif->dma_status))
  773. hwif->dma_status = (hwif->dma_base + 2);
  774. if (!(hwif->dma_vendor3))
  775. hwif->dma_vendor3 = (hwif->dma_base + 3);
  776. if (!(hwif->dma_prdtable))
  777. hwif->dma_prdtable = (hwif->dma_base + 4);
  778. if (!hwif->ide_dma_off_quietly)
  779. hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
  780. if (!hwif->ide_dma_host_off)
  781. hwif->ide_dma_host_off = &__ide_dma_host_off;
  782. if (!hwif->ide_dma_on)
  783. hwif->ide_dma_on = &__ide_dma_on;
  784. if (!hwif->ide_dma_host_on)
  785. hwif->ide_dma_host_on = &__ide_dma_host_on;
  786. if (!hwif->ide_dma_check)
  787. hwif->ide_dma_check = &__ide_dma_check;
  788. if (!hwif->dma_setup)
  789. hwif->dma_setup = &ide_dma_setup;
  790. if (!hwif->dma_exec_cmd)
  791. hwif->dma_exec_cmd = &ide_dma_exec_cmd;
  792. if (!hwif->dma_start)
  793. hwif->dma_start = &ide_dma_start;
  794. if (!hwif->ide_dma_end)
  795. hwif->ide_dma_end = &__ide_dma_end;
  796. if (!hwif->ide_dma_test_irq)
  797. hwif->ide_dma_test_irq = &__ide_dma_test_irq;
  798. if (!hwif->ide_dma_timeout)
  799. hwif->ide_dma_timeout = &__ide_dma_timeout;
  800. if (!hwif->ide_dma_lostirq)
  801. hwif->ide_dma_lostirq = &__ide_dma_lostirq;
  802. if (hwif->chipset != ide_trm290) {
  803. u8 dma_stat = hwif->INB(hwif->dma_status);
  804. printk(", BIOS settings: %s:%s, %s:%s",
  805. hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio",
  806. hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio");
  807. }
  808. printk("\n");
  809. BUG_ON(!hwif->dma_master);
  810. }
  811. EXPORT_SYMBOL_GPL(ide_setup_dma);
  812. #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */