devices.c 18 KB

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  1. /*
  2. * Author: MontaVista Software, Inc.
  3. * <source@mvista.com>
  4. *
  5. * Based on the OMAP devices.c
  6. *
  7. * 2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  15. * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  16. * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License
  20. * as published by the Free Software Foundation; either version 2
  21. * of the License, or (at your option) any later version.
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  30. * MA 02110-1301, USA.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/init.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/gpio.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/serial.h>
  39. #include <mach/irqs.h>
  40. #include <mach/hardware.h>
  41. #include <mach/common.h>
  42. #include <mach/mmc.h>
  43. #include "devices.h"
  44. #if defined(CONFIG_ARCH_MX1)
  45. static struct resource imx1_camera_resources[] = {
  46. {
  47. .start = 0x00224000,
  48. .end = 0x00224010,
  49. .flags = IORESOURCE_MEM,
  50. }, {
  51. .start = MX1_CSI_INT,
  52. .end = MX1_CSI_INT,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. };
  56. static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
  57. struct platform_device imx1_camera_device = {
  58. .name = "mx1-camera",
  59. .id = 0, /* This is used to put cameras on this interface */
  60. .dev = {
  61. .dma_mask = &imx1_camera_dmamask,
  62. .coherent_dma_mask = DMA_BIT_MASK(32),
  63. },
  64. .resource = imx1_camera_resources,
  65. .num_resources = ARRAY_SIZE(imx1_camera_resources),
  66. };
  67. static struct resource imx_i2c_resources[] = {
  68. {
  69. .start = 0x00217000,
  70. .end = 0x00217010,
  71. .flags = IORESOURCE_MEM,
  72. }, {
  73. .start = MX1_I2C_INT,
  74. .end = MX1_I2C_INT,
  75. .flags = IORESOURCE_IRQ,
  76. },
  77. };
  78. struct platform_device imx_i2c_device0 = {
  79. .name = "imx-i2c",
  80. .id = 0,
  81. .resource = imx_i2c_resources,
  82. .num_resources = ARRAY_SIZE(imx_i2c_resources),
  83. };
  84. #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
  85. static struct resource imx1_uart_resources ## n[] = { \
  86. { \
  87. .start = baseaddr, \
  88. .end = baseaddr + 0xd0, \
  89. .flags = IORESOURCE_MEM, \
  90. }, { \
  91. .start = irqrx, \
  92. .end = irqrx, \
  93. .flags = IORESOURCE_IRQ, \
  94. }, { \
  95. .start = irqtx, \
  96. .end = irqtx, \
  97. .flags = IORESOURCE_IRQ, \
  98. }, { \
  99. .start = irqrts, \
  100. .end = irqrts, \
  101. .flags = IORESOURCE_IRQ, \
  102. }, \
  103. }; \
  104. \
  105. struct platform_device imx1_uart_device ## n = { \
  106. .name = "imx-uart", \
  107. .id = n, \
  108. .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
  109. .resource = imx1_uart_resources ## n, \
  110. }
  111. DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
  112. DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
  113. static struct resource imx_rtc_resources[] = {
  114. {
  115. .start = 0x00204000,
  116. .end = 0x00204024,
  117. .flags = IORESOURCE_MEM,
  118. }, {
  119. .start = MX1_RTC_INT,
  120. .end = MX1_RTC_INT,
  121. .flags = IORESOURCE_IRQ,
  122. }, {
  123. .start = MX1_RTC_SAMINT,
  124. .end = MX1_RTC_SAMINT,
  125. .flags = IORESOURCE_IRQ,
  126. },
  127. };
  128. struct platform_device imx_rtc_device = {
  129. .name = "rtc-imx",
  130. .id = 0,
  131. .resource = imx_rtc_resources,
  132. .num_resources = ARRAY_SIZE(imx_rtc_resources),
  133. };
  134. static struct resource imx_wdt_resources[] = {
  135. {
  136. .start = 0x00201000,
  137. .end = 0x00201008,
  138. .flags = IORESOURCE_MEM,
  139. }, {
  140. .start = MX1_WDT_INT,
  141. .end = MX1_WDT_INT,
  142. .flags = IORESOURCE_IRQ,
  143. },
  144. };
  145. struct platform_device imx_wdt_device = {
  146. .name = "imx-wdt",
  147. .id = 0,
  148. .resource = imx_wdt_resources,
  149. .num_resources = ARRAY_SIZE(imx_wdt_resources),
  150. };
  151. static struct resource imx_usb_resources[] = {
  152. {
  153. .start = 0x00212000,
  154. .end = 0x00212148,
  155. .flags = IORESOURCE_MEM,
  156. }, {
  157. .start = MX1_USBD_INT0,
  158. .end = MX1_USBD_INT0,
  159. .flags = IORESOURCE_IRQ,
  160. }, {
  161. .start = MX1_USBD_INT1,
  162. .end = MX1_USBD_INT1,
  163. .flags = IORESOURCE_IRQ,
  164. }, {
  165. .start = MX1_USBD_INT2,
  166. .end = MX1_USBD_INT2,
  167. .flags = IORESOURCE_IRQ,
  168. }, {
  169. .start = MX1_USBD_INT3,
  170. .end = MX1_USBD_INT3,
  171. .flags = IORESOURCE_IRQ,
  172. }, {
  173. .start = MX1_USBD_INT4,
  174. .end = MX1_USBD_INT4,
  175. .flags = IORESOURCE_IRQ,
  176. }, {
  177. .start = MX1_USBD_INT5,
  178. .end = MX1_USBD_INT5,
  179. .flags = IORESOURCE_IRQ,
  180. }, {
  181. .start = MX1_USBD_INT6,
  182. .end = MX1_USBD_INT6,
  183. .flags = IORESOURCE_IRQ,
  184. },
  185. };
  186. struct platform_device imx_usb_device = {
  187. .name = "imx_udc",
  188. .id = 0,
  189. .num_resources = ARRAY_SIZE(imx_usb_resources),
  190. .resource = imx_usb_resources,
  191. };
  192. /* GPIO port description */
  193. static struct mxc_gpio_port imx_gpio_ports[] = {
  194. {
  195. .chip.label = "gpio-0",
  196. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
  197. .irq = MX1_GPIO_INT_PORTA,
  198. .virtual_irq_start = MXC_GPIO_IRQ_START,
  199. }, {
  200. .chip.label = "gpio-1",
  201. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
  202. .irq = MX1_GPIO_INT_PORTB,
  203. .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
  204. }, {
  205. .chip.label = "gpio-2",
  206. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
  207. .irq = MX1_GPIO_INT_PORTC,
  208. .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
  209. }, {
  210. .chip.label = "gpio-3",
  211. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
  212. .irq = MX1_GPIO_INT_PORTD,
  213. .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
  214. }
  215. };
  216. int __init imx1_register_gpios(void)
  217. {
  218. return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
  219. }
  220. #endif
  221. #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
  222. /*
  223. * SPI master controller
  224. *
  225. * - i.MX1: 2 channel (slighly different register setting)
  226. * - i.MX21: 2 channel
  227. * - i.MX27: 3 channel
  228. */
  229. #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
  230. static struct resource mxc_spi_resources ## n[] = { \
  231. { \
  232. .start = baseaddr, \
  233. .end = baseaddr + SZ_4K - 1, \
  234. .flags = IORESOURCE_MEM, \
  235. }, { \
  236. .start = irq, \
  237. .end = irq, \
  238. .flags = IORESOURCE_IRQ, \
  239. }, \
  240. }; \
  241. \
  242. struct platform_device mxc_spi_device ## n = { \
  243. .name = "spi_imx", \
  244. .id = n, \
  245. .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
  246. .resource = mxc_spi_resources ## n, \
  247. }
  248. DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
  249. DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
  250. #ifdef CONFIG_MACH_MX27
  251. DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
  252. #endif
  253. /*
  254. * General Purpose Timer
  255. * - i.MX21: 3 timers
  256. * - i.MX27: 6 timers
  257. */
  258. #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
  259. static struct resource timer ## n ##_resources[] = { \
  260. { \
  261. .start = baseaddr, \
  262. .end = baseaddr + SZ_4K - 1, \
  263. .flags = IORESOURCE_MEM, \
  264. }, { \
  265. .start = irq, \
  266. .end = irq, \
  267. .flags = IORESOURCE_IRQ, \
  268. } \
  269. }; \
  270. \
  271. struct platform_device mxc_gpt ## n = { \
  272. .name = "imx_gpt", \
  273. .id = n, \
  274. .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
  275. .resource = timer ## n ## _resources, \
  276. }
  277. /* We use gpt1 as system timer, so do not add a device for this one */
  278. DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
  279. DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
  280. #ifdef CONFIG_MACH_MX27
  281. DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
  282. DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
  283. DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
  284. #endif
  285. /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
  286. static struct resource mxc_wdt_resources[] = {
  287. {
  288. .start = MX2x_WDOG_BASE_ADDR,
  289. .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
  290. .flags = IORESOURCE_MEM,
  291. },
  292. };
  293. struct platform_device mxc_wdt = {
  294. .name = "imx2-wdt",
  295. .id = 0,
  296. .num_resources = ARRAY_SIZE(mxc_wdt_resources),
  297. .resource = mxc_wdt_resources,
  298. };
  299. static struct resource mxc_w1_master_resources[] = {
  300. {
  301. .start = MX2x_OWIRE_BASE_ADDR,
  302. .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
  303. .flags = IORESOURCE_MEM,
  304. },
  305. };
  306. struct platform_device mxc_w1_master_device = {
  307. .name = "mxc_w1",
  308. .id = 0,
  309. .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
  310. .resource = mxc_w1_master_resources,
  311. };
  312. /*
  313. * lcdc:
  314. * - i.MX1: the basic controller
  315. * - i.MX21: to be checked
  316. * - i.MX27: like i.MX1, with slightly variations
  317. */
  318. static struct resource mxc_fb[] = {
  319. {
  320. .start = MX2x_LCDC_BASE_ADDR,
  321. .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
  322. .flags = IORESOURCE_MEM,
  323. }, {
  324. .start = MX2x_INT_LCDC,
  325. .end = MX2x_INT_LCDC,
  326. .flags = IORESOURCE_IRQ,
  327. }
  328. };
  329. /* mxc lcd driver */
  330. struct platform_device mxc_fb_device = {
  331. .name = "imx-fb",
  332. .id = 0,
  333. .num_resources = ARRAY_SIZE(mxc_fb),
  334. .resource = mxc_fb,
  335. .dev = {
  336. .coherent_dma_mask = DMA_BIT_MASK(32),
  337. },
  338. };
  339. #ifdef CONFIG_MACH_MX27
  340. static struct resource mxc_fec_resources[] = {
  341. {
  342. .start = MX27_FEC_BASE_ADDR,
  343. .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
  344. .flags = IORESOURCE_MEM,
  345. }, {
  346. .start = MX27_INT_FEC,
  347. .end = MX27_INT_FEC,
  348. .flags = IORESOURCE_IRQ,
  349. },
  350. };
  351. struct platform_device mxc_fec_device = {
  352. .name = "fec",
  353. .id = 0,
  354. .num_resources = ARRAY_SIZE(mxc_fec_resources),
  355. .resource = mxc_fec_resources,
  356. };
  357. #endif
  358. #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
  359. static struct resource mxc_i2c_resources ## n[] = { \
  360. { \
  361. .start = baseaddr, \
  362. .end = baseaddr + SZ_4K - 1, \
  363. .flags = IORESOURCE_MEM, \
  364. }, { \
  365. .start = irq, \
  366. .end = irq, \
  367. .flags = IORESOURCE_IRQ, \
  368. } \
  369. }; \
  370. \
  371. struct platform_device mxc_i2c_device ## n = { \
  372. .name = "imx-i2c", \
  373. .id = n, \
  374. .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
  375. .resource = mxc_i2c_resources ## n, \
  376. }
  377. DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
  378. #ifdef CONFIG_MACH_MX27
  379. DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
  380. #endif
  381. static struct resource mxc_pwm_resources[] = {
  382. {
  383. .start = MX2x_PWM_BASE_ADDR,
  384. .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
  385. .flags = IORESOURCE_MEM,
  386. }, {
  387. .start = MX2x_INT_PWM,
  388. .end = MX2x_INT_PWM,
  389. .flags = IORESOURCE_IRQ,
  390. }
  391. };
  392. struct platform_device mxc_pwm_device = {
  393. .name = "mxc_pwm",
  394. .id = 0,
  395. .num_resources = ARRAY_SIZE(mxc_pwm_resources),
  396. .resource = mxc_pwm_resources,
  397. };
  398. #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
  399. static struct resource mxc_sdhc_resources ## n[] = { \
  400. { \
  401. .start = baseaddr, \
  402. .end = baseaddr + SZ_4K - 1, \
  403. .flags = IORESOURCE_MEM, \
  404. }, { \
  405. .start = irq, \
  406. .end = irq, \
  407. .flags = IORESOURCE_IRQ, \
  408. }, { \
  409. .start = dmareq, \
  410. .end = dmareq, \
  411. .flags = IORESOURCE_DMA, \
  412. }, \
  413. }; \
  414. \
  415. static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
  416. \
  417. struct platform_device mxc_sdhc_device ## n = { \
  418. .name = "mxc-mmc", \
  419. .id = n, \
  420. .dev = { \
  421. .dma_mask = &mxc_sdhc ## n ## _dmamask, \
  422. .coherent_dma_mask = DMA_BIT_MASK(32), \
  423. }, \
  424. .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
  425. .resource = mxc_sdhc_resources ## n, \
  426. }
  427. DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
  428. DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
  429. #ifdef CONFIG_MACH_MX27
  430. static struct resource otg_resources[] = {
  431. {
  432. .start = MX27_USBOTG_BASE_ADDR,
  433. .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
  434. .flags = IORESOURCE_MEM,
  435. }, {
  436. .start = MX27_INT_USB3,
  437. .end = MX27_INT_USB3,
  438. .flags = IORESOURCE_IRQ,
  439. },
  440. };
  441. static u64 otg_dmamask = DMA_BIT_MASK(32);
  442. /* OTG gadget device */
  443. struct platform_device mxc_otg_udc_device = {
  444. .name = "fsl-usb2-udc",
  445. .id = -1,
  446. .dev = {
  447. .dma_mask = &otg_dmamask,
  448. .coherent_dma_mask = DMA_BIT_MASK(32),
  449. },
  450. .resource = otg_resources,
  451. .num_resources = ARRAY_SIZE(otg_resources),
  452. };
  453. /* OTG host */
  454. struct platform_device mxc_otg_host = {
  455. .name = "mxc-ehci",
  456. .id = 0,
  457. .dev = {
  458. .coherent_dma_mask = DMA_BIT_MASK(32),
  459. .dma_mask = &otg_dmamask,
  460. },
  461. .resource = otg_resources,
  462. .num_resources = ARRAY_SIZE(otg_resources),
  463. };
  464. /* USB host 1 */
  465. static u64 usbh1_dmamask = DMA_BIT_MASK(32);
  466. static struct resource mxc_usbh1_resources[] = {
  467. {
  468. .start = MX27_USBOTG_BASE_ADDR + 0x200,
  469. .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
  470. .flags = IORESOURCE_MEM,
  471. }, {
  472. .start = MX27_INT_USB1,
  473. .end = MX27_INT_USB1,
  474. .flags = IORESOURCE_IRQ,
  475. },
  476. };
  477. struct platform_device mxc_usbh1 = {
  478. .name = "mxc-ehci",
  479. .id = 1,
  480. .dev = {
  481. .coherent_dma_mask = DMA_BIT_MASK(32),
  482. .dma_mask = &usbh1_dmamask,
  483. },
  484. .resource = mxc_usbh1_resources,
  485. .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
  486. };
  487. /* USB host 2 */
  488. static u64 usbh2_dmamask = DMA_BIT_MASK(32);
  489. static struct resource mxc_usbh2_resources[] = {
  490. {
  491. .start = MX27_USBOTG_BASE_ADDR + 0x400,
  492. .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
  493. .flags = IORESOURCE_MEM,
  494. }, {
  495. .start = MX27_INT_USB2,
  496. .end = MX27_INT_USB2,
  497. .flags = IORESOURCE_IRQ,
  498. },
  499. };
  500. struct platform_device mxc_usbh2 = {
  501. .name = "mxc-ehci",
  502. .id = 2,
  503. .dev = {
  504. .coherent_dma_mask = DMA_BIT_MASK(32),
  505. .dma_mask = &usbh2_dmamask,
  506. },
  507. .resource = mxc_usbh2_resources,
  508. .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
  509. };
  510. #endif
  511. #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
  512. { \
  513. .name = _name, \
  514. .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  515. .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  516. .flags = IORESOURCE_DMA, \
  517. }
  518. #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
  519. static struct resource imx_ssi_resources ## n[] = { \
  520. { \
  521. .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
  522. .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
  523. .flags = IORESOURCE_MEM, \
  524. }, { \
  525. .start = MX2x_INT_SSI1, \
  526. .end = MX2x_INT_SSI1, \
  527. .flags = IORESOURCE_IRQ, \
  528. }, \
  529. DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
  530. DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
  531. DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
  532. DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
  533. }; \
  534. \
  535. struct platform_device imx_ssi_device ## n = { \
  536. .name = "imx-ssi", \
  537. .id = n, \
  538. .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
  539. .resource = imx_ssi_resources ## n, \
  540. }
  541. DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  542. DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  543. #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
  544. static struct resource imx2x_uart_resources ## n[] = { \
  545. { \
  546. .start = baseaddr, \
  547. .end = baseaddr + 0xb5, \
  548. .flags = IORESOURCE_MEM, \
  549. }, { \
  550. .start = irq, \
  551. .end = irq, \
  552. .flags = IORESOURCE_IRQ, \
  553. }, \
  554. }; \
  555. \
  556. struct platform_device imx2x_uart_device ## n = { \
  557. .name = "imx-uart", \
  558. .id = n, \
  559. .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
  560. .resource = imx2x_uart_resources ## n, \
  561. }
  562. DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
  563. DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
  564. DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
  565. DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
  566. #ifdef CONFIG_MACH_MX27
  567. DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
  568. DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
  569. #endif
  570. /* GPIO port description */
  571. #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
  572. { \
  573. .chip.label = "gpio-" #n, \
  574. .irq = _irq, \
  575. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  576. n * 0x100), \
  577. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  578. }
  579. #define DEFINE_MXC_GPIO_PORT(SOC, n) \
  580. { \
  581. .chip.label = "gpio-" #n, \
  582. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  583. n * 0x100), \
  584. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  585. }
  586. #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
  587. static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
  588. DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
  589. DEFINE_MXC_GPIO_PORT(SOC, 1), \
  590. DEFINE_MXC_GPIO_PORT(SOC, 2), \
  591. DEFINE_MXC_GPIO_PORT(SOC, 3), \
  592. DEFINE_MXC_GPIO_PORT(SOC, 4), \
  593. DEFINE_MXC_GPIO_PORT(SOC, 5), \
  594. }
  595. #ifdef CONFIG_MACH_MX21
  596. DEFINE_MXC_GPIO_PORTS(MX21, imx21);
  597. int __init imx21_register_gpios(void)
  598. {
  599. return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
  600. }
  601. #endif
  602. #ifdef CONFIG_MACH_MX27
  603. DEFINE_MXC_GPIO_PORTS(MX27, imx27);
  604. int __init imx27_register_gpios(void)
  605. {
  606. return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
  607. }
  608. #endif
  609. #ifdef CONFIG_MACH_MX21
  610. static struct resource mx21_usbhc_resources[] = {
  611. {
  612. .start = MX21_USBOTG_BASE_ADDR,
  613. .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
  614. .flags = IORESOURCE_MEM,
  615. },
  616. {
  617. .start = MX21_INT_USBHOST,
  618. .end = MX21_INT_USBHOST,
  619. .flags = IORESOURCE_IRQ,
  620. },
  621. };
  622. struct platform_device mx21_usbhc_device = {
  623. .name = "imx21-hcd",
  624. .id = 0,
  625. .dev = {
  626. .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
  627. .coherent_dma_mask = DMA_BIT_MASK(32),
  628. },
  629. .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
  630. .resource = mx21_usbhc_resources,
  631. };
  632. #endif
  633. #endif