nvme-scsi.c 84 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. */
  18. /*
  19. * Refer to the SCSI-NVMe Translation spec for details on how
  20. * each command is translated.
  21. */
  22. #include <linux/nvme.h>
  23. #include <linux/bio.h>
  24. #include <linux/bitops.h>
  25. #include <linux/blkdev.h>
  26. #include <linux/delay.h>
  27. #include <linux/errno.h>
  28. #include <linux/fs.h>
  29. #include <linux/genhd.h>
  30. #include <linux/idr.h>
  31. #include <linux/init.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/kdev_t.h>
  35. #include <linux/kthread.h>
  36. #include <linux/kernel.h>
  37. #include <linux/mm.h>
  38. #include <linux/module.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/pci.h>
  41. #include <linux/poison.h>
  42. #include <linux/sched.h>
  43. #include <linux/slab.h>
  44. #include <linux/types.h>
  45. #include <scsi/sg.h>
  46. #include <scsi/scsi.h>
  47. static int sg_version_num = 30534; /* 2 digits for each component */
  48. #define SNTI_TRANSLATION_SUCCESS 0
  49. #define SNTI_INTERNAL_ERROR 1
  50. /* VPD Page Codes */
  51. #define VPD_SUPPORTED_PAGES 0x00
  52. #define VPD_SERIAL_NUMBER 0x80
  53. #define VPD_DEVICE_IDENTIFIERS 0x83
  54. #define VPD_EXTENDED_INQUIRY 0x86
  55. #define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1
  56. /* CDB offsets */
  57. #define REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET 6
  58. #define REPORT_LUNS_SR_OFFSET 2
  59. #define READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET 10
  60. #define REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET 4
  61. #define REQUEST_SENSE_DESC_OFFSET 1
  62. #define REQUEST_SENSE_DESC_MASK 0x01
  63. #define DESCRIPTOR_FORMAT_SENSE_DATA_TYPE 1
  64. #define INQUIRY_EVPD_BYTE_OFFSET 1
  65. #define INQUIRY_PAGE_CODE_BYTE_OFFSET 2
  66. #define INQUIRY_EVPD_BIT_MASK 1
  67. #define INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET 3
  68. #define START_STOP_UNIT_CDB_IMMED_OFFSET 1
  69. #define START_STOP_UNIT_CDB_IMMED_MASK 0x1
  70. #define START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET 3
  71. #define START_STOP_UNIT_CDB_POWER_COND_MOD_MASK 0xF
  72. #define START_STOP_UNIT_CDB_POWER_COND_OFFSET 4
  73. #define START_STOP_UNIT_CDB_POWER_COND_MASK 0xF0
  74. #define START_STOP_UNIT_CDB_NO_FLUSH_OFFSET 4
  75. #define START_STOP_UNIT_CDB_NO_FLUSH_MASK 0x4
  76. #define START_STOP_UNIT_CDB_START_OFFSET 4
  77. #define START_STOP_UNIT_CDB_START_MASK 0x1
  78. #define WRITE_BUFFER_CDB_MODE_OFFSET 1
  79. #define WRITE_BUFFER_CDB_MODE_MASK 0x1F
  80. #define WRITE_BUFFER_CDB_BUFFER_ID_OFFSET 2
  81. #define WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET 3
  82. #define WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET 6
  83. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET 1
  84. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK 0xC0
  85. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT 6
  86. #define FORMAT_UNIT_CDB_LONG_LIST_OFFSET 1
  87. #define FORMAT_UNIT_CDB_LONG_LIST_MASK 0x20
  88. #define FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET 1
  89. #define FORMAT_UNIT_CDB_FORMAT_DATA_MASK 0x10
  90. #define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4
  91. #define FORMAT_UNIT_LONG_PARM_LIST_LEN 8
  92. #define FORMAT_UNIT_PROT_INT_OFFSET 3
  93. #define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0
  94. #define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07
  95. #define UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET 7
  96. /* Misc. defines */
  97. #define NIBBLE_SHIFT 4
  98. #define FIXED_SENSE_DATA 0x70
  99. #define DESC_FORMAT_SENSE_DATA 0x72
  100. #define FIXED_SENSE_DATA_ADD_LENGTH 10
  101. #define LUN_ENTRY_SIZE 8
  102. #define LUN_DATA_HEADER_SIZE 8
  103. #define ALL_LUNS_RETURNED 0x02
  104. #define ALL_WELL_KNOWN_LUNS_RETURNED 0x01
  105. #define RESTRICTED_LUNS_RETURNED 0x00
  106. #define NVME_POWER_STATE_START_VALID 0x00
  107. #define NVME_POWER_STATE_ACTIVE 0x01
  108. #define NVME_POWER_STATE_IDLE 0x02
  109. #define NVME_POWER_STATE_STANDBY 0x03
  110. #define NVME_POWER_STATE_LU_CONTROL 0x07
  111. #define POWER_STATE_0 0
  112. #define POWER_STATE_1 1
  113. #define POWER_STATE_2 2
  114. #define POWER_STATE_3 3
  115. #define DOWNLOAD_SAVE_ACTIVATE 0x05
  116. #define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E
  117. #define ACTIVATE_DEFERRED_MICROCODE 0x0F
  118. #define FORMAT_UNIT_IMMED_MASK 0x2
  119. #define FORMAT_UNIT_IMMED_OFFSET 1
  120. #define KELVIN_TEMP_FACTOR 273
  121. #define FIXED_FMT_SENSE_DATA_SIZE 18
  122. #define DESC_FMT_SENSE_DATA_SIZE 8
  123. /* SCSI/NVMe defines and bit masks */
  124. #define INQ_STANDARD_INQUIRY_PAGE 0x00
  125. #define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00
  126. #define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80
  127. #define INQ_DEVICE_IDENTIFICATION_PAGE 0x83
  128. #define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86
  129. #define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1
  130. #define INQ_SERIAL_NUMBER_LENGTH 0x14
  131. #define INQ_NUM_SUPPORTED_VPD_PAGES 5
  132. #define VERSION_SPC_4 0x06
  133. #define ACA_UNSUPPORTED 0
  134. #define STANDARD_INQUIRY_LENGTH 36
  135. #define ADDITIONAL_STD_INQ_LENGTH 31
  136. #define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C
  137. #define RESERVED_FIELD 0
  138. /* SCSI READ/WRITE Defines */
  139. #define IO_CDB_WP_MASK 0xE0
  140. #define IO_CDB_WP_SHIFT 5
  141. #define IO_CDB_FUA_MASK 0x8
  142. #define IO_6_CDB_LBA_OFFSET 0
  143. #define IO_6_CDB_LBA_MASK 0x001FFFFF
  144. #define IO_6_CDB_TX_LEN_OFFSET 4
  145. #define IO_6_DEFAULT_TX_LEN 256
  146. #define IO_10_CDB_LBA_OFFSET 2
  147. #define IO_10_CDB_TX_LEN_OFFSET 7
  148. #define IO_10_CDB_WP_OFFSET 1
  149. #define IO_10_CDB_FUA_OFFSET 1
  150. #define IO_12_CDB_LBA_OFFSET 2
  151. #define IO_12_CDB_TX_LEN_OFFSET 6
  152. #define IO_12_CDB_WP_OFFSET 1
  153. #define IO_12_CDB_FUA_OFFSET 1
  154. #define IO_16_CDB_FUA_OFFSET 1
  155. #define IO_16_CDB_WP_OFFSET 1
  156. #define IO_16_CDB_LBA_OFFSET 2
  157. #define IO_16_CDB_TX_LEN_OFFSET 10
  158. /* Mode Sense/Select defines */
  159. #define MODE_PAGE_INFO_EXCEP 0x1C
  160. #define MODE_PAGE_CACHING 0x08
  161. #define MODE_PAGE_CONTROL 0x0A
  162. #define MODE_PAGE_POWER_CONDITION 0x1A
  163. #define MODE_PAGE_RETURN_ALL 0x3F
  164. #define MODE_PAGE_BLK_DES_LEN 0x08
  165. #define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10
  166. #define MODE_PAGE_CACHING_LEN 0x14
  167. #define MODE_PAGE_CONTROL_LEN 0x0C
  168. #define MODE_PAGE_POW_CND_LEN 0x28
  169. #define MODE_PAGE_INF_EXC_LEN 0x0C
  170. #define MODE_PAGE_ALL_LEN 0x54
  171. #define MODE_SENSE6_MPH_SIZE 4
  172. #define MODE_SENSE6_ALLOC_LEN_OFFSET 4
  173. #define MODE_SENSE_PAGE_CONTROL_OFFSET 2
  174. #define MODE_SENSE_PAGE_CONTROL_MASK 0xC0
  175. #define MODE_SENSE_PAGE_CODE_OFFSET 2
  176. #define MODE_SENSE_PAGE_CODE_MASK 0x3F
  177. #define MODE_SENSE_LLBAA_OFFSET 1
  178. #define MODE_SENSE_LLBAA_MASK 0x10
  179. #define MODE_SENSE_LLBAA_SHIFT 4
  180. #define MODE_SENSE_DBD_OFFSET 1
  181. #define MODE_SENSE_DBD_MASK 8
  182. #define MODE_SENSE_DBD_SHIFT 3
  183. #define MODE_SENSE10_MPH_SIZE 8
  184. #define MODE_SENSE10_ALLOC_LEN_OFFSET 7
  185. #define MODE_SELECT_CDB_PAGE_FORMAT_OFFSET 1
  186. #define MODE_SELECT_CDB_SAVE_PAGES_OFFSET 1
  187. #define MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET 4
  188. #define MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET 7
  189. #define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10
  190. #define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1
  191. #define MODE_SELECT_6_BD_OFFSET 3
  192. #define MODE_SELECT_10_BD_OFFSET 6
  193. #define MODE_SELECT_10_LLBAA_OFFSET 4
  194. #define MODE_SELECT_10_LLBAA_MASK 1
  195. #define MODE_SELECT_6_MPH_SIZE 4
  196. #define MODE_SELECT_10_MPH_SIZE 8
  197. #define CACHING_MODE_PAGE_WCE_MASK 0x04
  198. #define MODE_SENSE_BLK_DESC_ENABLED 0
  199. #define MODE_SENSE_BLK_DESC_COUNT 1
  200. #define MODE_SELECT_PAGE_CODE_MASK 0x3F
  201. #define SHORT_DESC_BLOCK 8
  202. #define LONG_DESC_BLOCK 16
  203. #define MODE_PAGE_POW_CND_LEN_FIELD 0x26
  204. #define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A
  205. #define MODE_PAGE_CACHING_LEN_FIELD 0x12
  206. #define MODE_PAGE_CONTROL_LEN_FIELD 0x0A
  207. #define MODE_SENSE_PC_CURRENT_VALUES 0
  208. /* Log Sense defines */
  209. #define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00
  210. #define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07
  211. #define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F
  212. #define LOG_PAGE_TEMPERATURE_PAGE 0x0D
  213. #define LOG_SENSE_CDB_SP_OFFSET 1
  214. #define LOG_SENSE_CDB_SP_NOT_ENABLED 0
  215. #define LOG_SENSE_CDB_PC_OFFSET 2
  216. #define LOG_SENSE_CDB_PC_MASK 0xC0
  217. #define LOG_SENSE_CDB_PC_SHIFT 6
  218. #define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1
  219. #define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F
  220. #define LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET 7
  221. #define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8
  222. #define LOG_INFO_EXCP_PAGE_LENGTH 0xC
  223. #define REMAINING_TEMP_PAGE_LENGTH 0xC
  224. #define LOG_TEMP_PAGE_LENGTH 0x10
  225. #define LOG_TEMP_UNKNOWN 0xFF
  226. #define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3
  227. /* Read Capacity defines */
  228. #define READ_CAP_10_RESP_SIZE 8
  229. #define READ_CAP_16_RESP_SIZE 32
  230. /* NVMe Namespace and Command Defines */
  231. #define NVME_GET_SMART_LOG_PAGE 0x02
  232. #define NVME_GET_FEAT_TEMP_THRESH 0x04
  233. #define BYTES_TO_DWORDS 4
  234. #define NVME_MAX_FIRMWARE_SLOT 7
  235. /* Report LUNs defines */
  236. #define REPORT_LUNS_FIRST_LUN_OFFSET 8
  237. /* SCSI ADDITIONAL SENSE Codes */
  238. #define SCSI_ASC_NO_SENSE 0x00
  239. #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
  240. #define SCSI_ASC_LUN_NOT_READY 0x04
  241. #define SCSI_ASC_WARNING 0x0B
  242. #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
  243. #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
  244. #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
  245. #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
  246. #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
  247. #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
  248. #define SCSI_ASC_ILLEGAL_COMMAND 0x20
  249. #define SCSI_ASC_ILLEGAL_BLOCK 0x21
  250. #define SCSI_ASC_INVALID_CDB 0x24
  251. #define SCSI_ASC_INVALID_LUN 0x25
  252. #define SCSI_ASC_INVALID_PARAMETER 0x26
  253. #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
  254. #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
  255. /* SCSI ADDITIONAL SENSE Code Qualifiers */
  256. #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
  257. #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
  258. #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
  259. #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
  260. #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
  261. #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
  262. #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
  263. #define SCSI_ASCQ_INVALID_LUN_ID 0x09
  264. /**
  265. * DEVICE_SPECIFIC_PARAMETER in mode parameter header (see sbc2r16) to
  266. * enable DPOFUA support type 0x10 value.
  267. */
  268. #define DEVICE_SPECIFIC_PARAMETER 0
  269. #define VPD_ID_DESCRIPTOR_LENGTH sizeof(VPD_IDENTIFICATION_DESCRIPTOR)
  270. /* MACROs to extract information from CDBs */
  271. #define GET_OPCODE(cdb) cdb[0]
  272. #define GET_U8_FROM_CDB(cdb, index) (cdb[index] << 0)
  273. #define GET_U16_FROM_CDB(cdb, index) ((cdb[index] << 8) | (cdb[index + 1] << 0))
  274. #define GET_U24_FROM_CDB(cdb, index) ((cdb[index] << 16) | \
  275. (cdb[index + 1] << 8) | \
  276. (cdb[index + 2] << 0))
  277. #define GET_U32_FROM_CDB(cdb, index) ((cdb[index] << 24) | \
  278. (cdb[index + 1] << 16) | \
  279. (cdb[index + 2] << 8) | \
  280. (cdb[index + 3] << 0))
  281. #define GET_U64_FROM_CDB(cdb, index) ((((u64)cdb[index]) << 56) | \
  282. (((u64)cdb[index + 1]) << 48) | \
  283. (((u64)cdb[index + 2]) << 40) | \
  284. (((u64)cdb[index + 3]) << 32) | \
  285. (((u64)cdb[index + 4]) << 24) | \
  286. (((u64)cdb[index + 5]) << 16) | \
  287. (((u64)cdb[index + 6]) << 8) | \
  288. (((u64)cdb[index + 7]) << 0))
  289. /* Inquiry Helper Macros */
  290. #define GET_INQ_EVPD_BIT(cdb) \
  291. ((GET_U8_FROM_CDB(cdb, INQUIRY_EVPD_BYTE_OFFSET) & \
  292. INQUIRY_EVPD_BIT_MASK) ? 1 : 0)
  293. #define GET_INQ_PAGE_CODE(cdb) \
  294. (GET_U8_FROM_CDB(cdb, INQUIRY_PAGE_CODE_BYTE_OFFSET))
  295. #define GET_INQ_ALLOC_LENGTH(cdb) \
  296. (GET_U16_FROM_CDB(cdb, INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET))
  297. /* Report LUNs Helper Macros */
  298. #define GET_REPORT_LUNS_ALLOC_LENGTH(cdb) \
  299. (GET_U32_FROM_CDB(cdb, REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET))
  300. /* Read Capacity Helper Macros */
  301. #define GET_READ_CAP_16_ALLOC_LENGTH(cdb) \
  302. (GET_U32_FROM_CDB(cdb, READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET))
  303. #define IS_READ_CAP_16(cdb) \
  304. ((cdb[0] == SERVICE_ACTION_IN && cdb[1] == SAI_READ_CAPACITY_16) ? 1 : 0)
  305. /* Request Sense Helper Macros */
  306. #define GET_REQUEST_SENSE_ALLOC_LENGTH(cdb) \
  307. (GET_U8_FROM_CDB(cdb, REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET))
  308. /* Mode Sense Helper Macros */
  309. #define GET_MODE_SENSE_DBD(cdb) \
  310. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_DBD_OFFSET) & MODE_SENSE_DBD_MASK) >> \
  311. MODE_SENSE_DBD_SHIFT)
  312. #define GET_MODE_SENSE_LLBAA(cdb) \
  313. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_LLBAA_OFFSET) & \
  314. MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT)
  315. #define GET_MODE_SENSE_MPH_SIZE(cdb10) \
  316. (cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE)
  317. /* Struct to gather data that needs to be extracted from a SCSI CDB.
  318. Not conforming to any particular CDB variant, but compatible with all. */
  319. struct nvme_trans_io_cdb {
  320. u8 fua;
  321. u8 prot_info;
  322. u64 lba;
  323. u32 xfer_len;
  324. };
  325. /* Internal Helper Functions */
  326. /* Copy data to userspace memory */
  327. static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from,
  328. unsigned long n)
  329. {
  330. int res = SNTI_TRANSLATION_SUCCESS;
  331. unsigned long not_copied;
  332. int i;
  333. void *index = from;
  334. size_t remaining = n;
  335. size_t xfer_len;
  336. if (hdr->iovec_count > 0) {
  337. struct sg_iovec sgl;
  338. for (i = 0; i < hdr->iovec_count; i++) {
  339. not_copied = copy_from_user(&sgl, hdr->dxferp +
  340. i * sizeof(struct sg_iovec),
  341. sizeof(struct sg_iovec));
  342. if (not_copied)
  343. return -EFAULT;
  344. xfer_len = min(remaining, sgl.iov_len);
  345. not_copied = copy_to_user(sgl.iov_base, index,
  346. xfer_len);
  347. if (not_copied) {
  348. res = -EFAULT;
  349. break;
  350. }
  351. index += xfer_len;
  352. remaining -= xfer_len;
  353. if (remaining == 0)
  354. break;
  355. }
  356. return res;
  357. }
  358. not_copied = copy_to_user(hdr->dxferp, from, n);
  359. if (not_copied)
  360. res = -EFAULT;
  361. return res;
  362. }
  363. /* Copy data from userspace memory */
  364. static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to,
  365. unsigned long n)
  366. {
  367. int res = SNTI_TRANSLATION_SUCCESS;
  368. unsigned long not_copied;
  369. int i;
  370. void *index = to;
  371. size_t remaining = n;
  372. size_t xfer_len;
  373. if (hdr->iovec_count > 0) {
  374. struct sg_iovec sgl;
  375. for (i = 0; i < hdr->iovec_count; i++) {
  376. not_copied = copy_from_user(&sgl, hdr->dxferp +
  377. i * sizeof(struct sg_iovec),
  378. sizeof(struct sg_iovec));
  379. if (not_copied)
  380. return -EFAULT;
  381. xfer_len = min(remaining, sgl.iov_len);
  382. not_copied = copy_from_user(index, sgl.iov_base,
  383. xfer_len);
  384. if (not_copied) {
  385. res = -EFAULT;
  386. break;
  387. }
  388. index += xfer_len;
  389. remaining -= xfer_len;
  390. if (remaining == 0)
  391. break;
  392. }
  393. return res;
  394. }
  395. not_copied = copy_from_user(to, hdr->dxferp, n);
  396. if (not_copied)
  397. res = -EFAULT;
  398. return res;
  399. }
  400. /* Status/Sense Buffer Writeback */
  401. static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key,
  402. u8 asc, u8 ascq)
  403. {
  404. int res = SNTI_TRANSLATION_SUCCESS;
  405. u8 xfer_len;
  406. u8 resp[DESC_FMT_SENSE_DATA_SIZE];
  407. if (scsi_status_is_good(status)) {
  408. hdr->status = SAM_STAT_GOOD;
  409. hdr->masked_status = GOOD;
  410. hdr->host_status = DID_OK;
  411. hdr->driver_status = DRIVER_OK;
  412. hdr->sb_len_wr = 0;
  413. } else {
  414. hdr->status = status;
  415. hdr->masked_status = status >> 1;
  416. hdr->host_status = DID_OK;
  417. hdr->driver_status = DRIVER_OK;
  418. memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE);
  419. resp[0] = DESC_FORMAT_SENSE_DATA;
  420. resp[1] = sense_key;
  421. resp[2] = asc;
  422. resp[3] = ascq;
  423. xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE);
  424. hdr->sb_len_wr = xfer_len;
  425. if (copy_to_user(hdr->sbp, resp, xfer_len) > 0)
  426. res = -EFAULT;
  427. }
  428. return res;
  429. }
  430. static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc)
  431. {
  432. u8 status, sense_key, asc, ascq;
  433. int res = SNTI_TRANSLATION_SUCCESS;
  434. /* For non-nvme (Linux) errors, simply return the error code */
  435. if (nvme_sc < 0)
  436. return nvme_sc;
  437. /* Mask DNR, More, and reserved fields */
  438. nvme_sc &= 0x7FF;
  439. switch (nvme_sc) {
  440. /* Generic Command Status */
  441. case NVME_SC_SUCCESS:
  442. status = SAM_STAT_GOOD;
  443. sense_key = NO_SENSE;
  444. asc = SCSI_ASC_NO_SENSE;
  445. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  446. break;
  447. case NVME_SC_INVALID_OPCODE:
  448. status = SAM_STAT_CHECK_CONDITION;
  449. sense_key = ILLEGAL_REQUEST;
  450. asc = SCSI_ASC_ILLEGAL_COMMAND;
  451. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  452. break;
  453. case NVME_SC_INVALID_FIELD:
  454. status = SAM_STAT_CHECK_CONDITION;
  455. sense_key = ILLEGAL_REQUEST;
  456. asc = SCSI_ASC_INVALID_CDB;
  457. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  458. break;
  459. case NVME_SC_DATA_XFER_ERROR:
  460. status = SAM_STAT_CHECK_CONDITION;
  461. sense_key = MEDIUM_ERROR;
  462. asc = SCSI_ASC_NO_SENSE;
  463. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  464. break;
  465. case NVME_SC_POWER_LOSS:
  466. status = SAM_STAT_TASK_ABORTED;
  467. sense_key = ABORTED_COMMAND;
  468. asc = SCSI_ASC_WARNING;
  469. ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED;
  470. break;
  471. case NVME_SC_INTERNAL:
  472. status = SAM_STAT_CHECK_CONDITION;
  473. sense_key = HARDWARE_ERROR;
  474. asc = SCSI_ASC_INTERNAL_TARGET_FAILURE;
  475. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  476. break;
  477. case NVME_SC_ABORT_REQ:
  478. status = SAM_STAT_TASK_ABORTED;
  479. sense_key = ABORTED_COMMAND;
  480. asc = SCSI_ASC_NO_SENSE;
  481. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  482. break;
  483. case NVME_SC_ABORT_QUEUE:
  484. status = SAM_STAT_TASK_ABORTED;
  485. sense_key = ABORTED_COMMAND;
  486. asc = SCSI_ASC_NO_SENSE;
  487. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  488. break;
  489. case NVME_SC_FUSED_FAIL:
  490. status = SAM_STAT_TASK_ABORTED;
  491. sense_key = ABORTED_COMMAND;
  492. asc = SCSI_ASC_NO_SENSE;
  493. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  494. break;
  495. case NVME_SC_FUSED_MISSING:
  496. status = SAM_STAT_TASK_ABORTED;
  497. sense_key = ABORTED_COMMAND;
  498. asc = SCSI_ASC_NO_SENSE;
  499. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  500. break;
  501. case NVME_SC_INVALID_NS:
  502. status = SAM_STAT_CHECK_CONDITION;
  503. sense_key = ILLEGAL_REQUEST;
  504. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  505. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  506. break;
  507. case NVME_SC_LBA_RANGE:
  508. status = SAM_STAT_CHECK_CONDITION;
  509. sense_key = ILLEGAL_REQUEST;
  510. asc = SCSI_ASC_ILLEGAL_BLOCK;
  511. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  512. break;
  513. case NVME_SC_CAP_EXCEEDED:
  514. status = SAM_STAT_CHECK_CONDITION;
  515. sense_key = MEDIUM_ERROR;
  516. asc = SCSI_ASC_NO_SENSE;
  517. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  518. break;
  519. case NVME_SC_NS_NOT_READY:
  520. status = SAM_STAT_CHECK_CONDITION;
  521. sense_key = NOT_READY;
  522. asc = SCSI_ASC_LUN_NOT_READY;
  523. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  524. break;
  525. /* Command Specific Status */
  526. case NVME_SC_INVALID_FORMAT:
  527. status = SAM_STAT_CHECK_CONDITION;
  528. sense_key = ILLEGAL_REQUEST;
  529. asc = SCSI_ASC_FORMAT_COMMAND_FAILED;
  530. ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED;
  531. break;
  532. case NVME_SC_BAD_ATTRIBUTES:
  533. status = SAM_STAT_CHECK_CONDITION;
  534. sense_key = ILLEGAL_REQUEST;
  535. asc = SCSI_ASC_INVALID_CDB;
  536. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  537. break;
  538. /* Media Errors */
  539. case NVME_SC_WRITE_FAULT:
  540. status = SAM_STAT_CHECK_CONDITION;
  541. sense_key = MEDIUM_ERROR;
  542. asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT;
  543. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  544. break;
  545. case NVME_SC_READ_ERROR:
  546. status = SAM_STAT_CHECK_CONDITION;
  547. sense_key = MEDIUM_ERROR;
  548. asc = SCSI_ASC_UNRECOVERED_READ_ERROR;
  549. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  550. break;
  551. case NVME_SC_GUARD_CHECK:
  552. status = SAM_STAT_CHECK_CONDITION;
  553. sense_key = MEDIUM_ERROR;
  554. asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED;
  555. ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED;
  556. break;
  557. case NVME_SC_APPTAG_CHECK:
  558. status = SAM_STAT_CHECK_CONDITION;
  559. sense_key = MEDIUM_ERROR;
  560. asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED;
  561. ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED;
  562. break;
  563. case NVME_SC_REFTAG_CHECK:
  564. status = SAM_STAT_CHECK_CONDITION;
  565. sense_key = MEDIUM_ERROR;
  566. asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED;
  567. ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED;
  568. break;
  569. case NVME_SC_COMPARE_FAILED:
  570. status = SAM_STAT_CHECK_CONDITION;
  571. sense_key = MISCOMPARE;
  572. asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY;
  573. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  574. break;
  575. case NVME_SC_ACCESS_DENIED:
  576. status = SAM_STAT_CHECK_CONDITION;
  577. sense_key = ILLEGAL_REQUEST;
  578. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  579. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  580. break;
  581. /* Unspecified/Default */
  582. case NVME_SC_CMDID_CONFLICT:
  583. case NVME_SC_CMD_SEQ_ERROR:
  584. case NVME_SC_CQ_INVALID:
  585. case NVME_SC_QID_INVALID:
  586. case NVME_SC_QUEUE_SIZE:
  587. case NVME_SC_ABORT_LIMIT:
  588. case NVME_SC_ABORT_MISSING:
  589. case NVME_SC_ASYNC_LIMIT:
  590. case NVME_SC_FIRMWARE_SLOT:
  591. case NVME_SC_FIRMWARE_IMAGE:
  592. case NVME_SC_INVALID_VECTOR:
  593. case NVME_SC_INVALID_LOG_PAGE:
  594. default:
  595. status = SAM_STAT_CHECK_CONDITION;
  596. sense_key = ILLEGAL_REQUEST;
  597. asc = SCSI_ASC_NO_SENSE;
  598. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  599. break;
  600. }
  601. res = nvme_trans_completion(hdr, status, sense_key, asc, ascq);
  602. return res;
  603. }
  604. /* INQUIRY Helper Functions */
  605. static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns,
  606. struct sg_io_hdr *hdr, u8 *inq_response,
  607. int alloc_len)
  608. {
  609. struct nvme_dev *dev = ns->dev;
  610. dma_addr_t dma_addr;
  611. void *mem;
  612. struct nvme_id_ns *id_ns;
  613. int res = SNTI_TRANSLATION_SUCCESS;
  614. int nvme_sc;
  615. int xfer_len;
  616. u8 resp_data_format = 0x02;
  617. u8 protect;
  618. u8 cmdque = 0x01 << 1;
  619. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  620. &dma_addr, GFP_KERNEL);
  621. if (mem == NULL) {
  622. res = -ENOMEM;
  623. goto out_dma;
  624. }
  625. /* nvme ns identify - use DPS value for PROTECT field */
  626. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  627. res = nvme_trans_status_code(hdr, nvme_sc);
  628. /*
  629. * If nvme_sc was -ve, res will be -ve here.
  630. * If nvme_sc was +ve, the status would bace been translated, and res
  631. * can only be 0 or -ve.
  632. * - If 0 && nvme_sc > 0, then go into next if where res gets nvme_sc
  633. * - If -ve, return because its a Linux error.
  634. */
  635. if (res)
  636. goto out_free;
  637. if (nvme_sc) {
  638. res = nvme_sc;
  639. goto out_free;
  640. }
  641. id_ns = mem;
  642. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  643. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  644. inq_response[2] = VERSION_SPC_4;
  645. inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */
  646. inq_response[4] = ADDITIONAL_STD_INQ_LENGTH;
  647. inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */
  648. inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */
  649. strncpy(&inq_response[8], "NVMe ", 8);
  650. strncpy(&inq_response[16], dev->model, 16);
  651. strncpy(&inq_response[32], dev->firmware_rev, 4);
  652. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  653. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  654. out_free:
  655. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  656. dma_addr);
  657. out_dma:
  658. return res;
  659. }
  660. static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns,
  661. struct sg_io_hdr *hdr, u8 *inq_response,
  662. int alloc_len)
  663. {
  664. int res = SNTI_TRANSLATION_SUCCESS;
  665. int xfer_len;
  666. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  667. inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */
  668. inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */
  669. inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE;
  670. inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE;
  671. inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE;
  672. inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE;
  673. inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE;
  674. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  675. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  676. return res;
  677. }
  678. static int nvme_trans_unit_serial_page(struct nvme_ns *ns,
  679. struct sg_io_hdr *hdr, u8 *inq_response,
  680. int alloc_len)
  681. {
  682. struct nvme_dev *dev = ns->dev;
  683. int res = SNTI_TRANSLATION_SUCCESS;
  684. int xfer_len;
  685. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  686. inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */
  687. inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */
  688. strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH);
  689. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  690. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  691. return res;
  692. }
  693. static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  694. u8 *inq_response, int alloc_len)
  695. {
  696. struct nvme_dev *dev = ns->dev;
  697. dma_addr_t dma_addr;
  698. void *mem;
  699. struct nvme_id_ctrl *id_ctrl;
  700. int res = SNTI_TRANSLATION_SUCCESS;
  701. int nvme_sc;
  702. u8 ieee[4];
  703. int xfer_len;
  704. __be32 tmp_id = cpu_to_be32(ns->ns_id);
  705. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  706. &dma_addr, GFP_KERNEL);
  707. if (mem == NULL) {
  708. res = -ENOMEM;
  709. goto out_dma;
  710. }
  711. /* nvme controller identify */
  712. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  713. res = nvme_trans_status_code(hdr, nvme_sc);
  714. if (res)
  715. goto out_free;
  716. if (nvme_sc) {
  717. res = nvme_sc;
  718. goto out_free;
  719. }
  720. id_ctrl = mem;
  721. /* Since SCSI tried to save 4 bits... [SPC-4(r34) Table 591] */
  722. ieee[0] = id_ctrl->ieee[0] << 4;
  723. ieee[1] = id_ctrl->ieee[0] >> 4 | id_ctrl->ieee[1] << 4;
  724. ieee[2] = id_ctrl->ieee[1] >> 4 | id_ctrl->ieee[2] << 4;
  725. ieee[3] = id_ctrl->ieee[2] >> 4;
  726. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  727. inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */
  728. inq_response[3] = 20; /* Page Length */
  729. /* Designation Descriptor start */
  730. inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */
  731. inq_response[5] = 0x03; /* PIV=0b | Asso=00b | Designator Type=3h */
  732. inq_response[6] = 0x00; /* Rsvd */
  733. inq_response[7] = 16; /* Designator Length */
  734. /* Designator start */
  735. inq_response[8] = 0x60 | ieee[3]; /* NAA=6h | IEEE ID MSB, High nibble*/
  736. inq_response[9] = ieee[2]; /* IEEE ID */
  737. inq_response[10] = ieee[1]; /* IEEE ID */
  738. inq_response[11] = ieee[0]; /* IEEE ID| Vendor Specific ID... */
  739. inq_response[12] = (dev->pci_dev->vendor & 0xFF00) >> 8;
  740. inq_response[13] = (dev->pci_dev->vendor & 0x00FF);
  741. inq_response[14] = dev->serial[0];
  742. inq_response[15] = dev->serial[1];
  743. inq_response[16] = dev->model[0];
  744. inq_response[17] = dev->model[1];
  745. memcpy(&inq_response[18], &tmp_id, sizeof(u32));
  746. /* Last 2 bytes are zero */
  747. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  748. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  749. out_free:
  750. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  751. dma_addr);
  752. out_dma:
  753. return res;
  754. }
  755. static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  756. int alloc_len)
  757. {
  758. u8 *inq_response;
  759. int res = SNTI_TRANSLATION_SUCCESS;
  760. int nvme_sc;
  761. struct nvme_dev *dev = ns->dev;
  762. dma_addr_t dma_addr;
  763. void *mem;
  764. struct nvme_id_ctrl *id_ctrl;
  765. struct nvme_id_ns *id_ns;
  766. int xfer_len;
  767. u8 microcode = 0x80;
  768. u8 spt;
  769. u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7};
  770. u8 grd_chk, app_chk, ref_chk, protect;
  771. u8 uask_sup = 0x20;
  772. u8 v_sup;
  773. u8 luiclr = 0x01;
  774. inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  775. if (inq_response == NULL) {
  776. res = -ENOMEM;
  777. goto out_mem;
  778. }
  779. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  780. &dma_addr, GFP_KERNEL);
  781. if (mem == NULL) {
  782. res = -ENOMEM;
  783. goto out_dma;
  784. }
  785. /* nvme ns identify */
  786. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  787. res = nvme_trans_status_code(hdr, nvme_sc);
  788. if (res)
  789. goto out_free;
  790. if (nvme_sc) {
  791. res = nvme_sc;
  792. goto out_free;
  793. }
  794. id_ns = mem;
  795. spt = spt_lut[(id_ns->dpc) & 0x07] << 3;
  796. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  797. grd_chk = protect << 2;
  798. app_chk = protect << 1;
  799. ref_chk = protect;
  800. /* nvme controller identify */
  801. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  802. res = nvme_trans_status_code(hdr, nvme_sc);
  803. if (res)
  804. goto out_free;
  805. if (nvme_sc) {
  806. res = nvme_sc;
  807. goto out_free;
  808. }
  809. id_ctrl = mem;
  810. v_sup = id_ctrl->vwc;
  811. memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  812. inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */
  813. inq_response[2] = 0x00; /* Page Length MSB */
  814. inq_response[3] = 0x3C; /* Page Length LSB */
  815. inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk;
  816. inq_response[5] = uask_sup;
  817. inq_response[6] = v_sup;
  818. inq_response[7] = luiclr;
  819. inq_response[8] = 0;
  820. inq_response[9] = 0;
  821. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  822. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  823. out_free:
  824. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  825. dma_addr);
  826. out_dma:
  827. kfree(inq_response);
  828. out_mem:
  829. return res;
  830. }
  831. static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  832. int alloc_len)
  833. {
  834. u8 *inq_response;
  835. int res = SNTI_TRANSLATION_SUCCESS;
  836. int xfer_len;
  837. inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  838. if (inq_response == NULL) {
  839. res = -ENOMEM;
  840. goto out_mem;
  841. }
  842. memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  843. inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */
  844. inq_response[2] = 0x00; /* Page Length MSB */
  845. inq_response[3] = 0x3C; /* Page Length LSB */
  846. inq_response[4] = 0x00; /* Medium Rotation Rate MSB */
  847. inq_response[5] = 0x01; /* Medium Rotation Rate LSB */
  848. inq_response[6] = 0x00; /* Form Factor */
  849. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  850. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  851. kfree(inq_response);
  852. out_mem:
  853. return res;
  854. }
  855. /* LOG SENSE Helper Functions */
  856. static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  857. int alloc_len)
  858. {
  859. int res = SNTI_TRANSLATION_SUCCESS;
  860. int xfer_len;
  861. u8 *log_response;
  862. log_response = kmalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL);
  863. if (log_response == NULL) {
  864. res = -ENOMEM;
  865. goto out_mem;
  866. }
  867. memset(log_response, 0, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
  868. log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  869. /* Subpage=0x00, Page Length MSB=0 */
  870. log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH;
  871. log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  872. log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  873. log_response[6] = LOG_PAGE_TEMPERATURE_PAGE;
  874. xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
  875. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  876. kfree(log_response);
  877. out_mem:
  878. return res;
  879. }
  880. static int nvme_trans_log_info_exceptions(struct nvme_ns *ns,
  881. struct sg_io_hdr *hdr, int alloc_len)
  882. {
  883. int res = SNTI_TRANSLATION_SUCCESS;
  884. int xfer_len;
  885. u8 *log_response;
  886. struct nvme_command c;
  887. struct nvme_dev *dev = ns->dev;
  888. struct nvme_smart_log *smart_log;
  889. dma_addr_t dma_addr;
  890. void *mem;
  891. u8 temp_c;
  892. u16 temp_k;
  893. log_response = kmalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL);
  894. if (log_response == NULL) {
  895. res = -ENOMEM;
  896. goto out_mem;
  897. }
  898. memset(log_response, 0, LOG_INFO_EXCP_PAGE_LENGTH);
  899. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  900. sizeof(struct nvme_smart_log),
  901. &dma_addr, GFP_KERNEL);
  902. if (mem == NULL) {
  903. res = -ENOMEM;
  904. goto out_dma;
  905. }
  906. /* Get SMART Log Page */
  907. memset(&c, 0, sizeof(c));
  908. c.common.opcode = nvme_admin_get_log_page;
  909. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  910. c.common.prp1 = cpu_to_le64(dma_addr);
  911. c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) /
  912. BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE);
  913. res = nvme_submit_admin_cmd(dev, &c, NULL);
  914. if (res != NVME_SC_SUCCESS) {
  915. temp_c = LOG_TEMP_UNKNOWN;
  916. } else {
  917. smart_log = mem;
  918. temp_k = (smart_log->temperature[1] << 8) +
  919. (smart_log->temperature[0]);
  920. temp_c = temp_k - KELVIN_TEMP_FACTOR;
  921. }
  922. log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  923. /* Subpage=0x00, Page Length MSB=0 */
  924. log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH;
  925. /* Informational Exceptions Log Parameter 1 Start */
  926. /* Parameter Code=0x0000 bytes 4,5 */
  927. log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */
  928. log_response[7] = 0x04; /* PARAMETER LENGTH */
  929. /* Add sense Code and qualifier = 0x00 each */
  930. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  931. log_response[10] = temp_c;
  932. xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH);
  933. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  934. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  935. mem, dma_addr);
  936. out_dma:
  937. kfree(log_response);
  938. out_mem:
  939. return res;
  940. }
  941. static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  942. int alloc_len)
  943. {
  944. int res = SNTI_TRANSLATION_SUCCESS;
  945. int xfer_len;
  946. u8 *log_response;
  947. struct nvme_command c;
  948. struct nvme_dev *dev = ns->dev;
  949. struct nvme_smart_log *smart_log;
  950. dma_addr_t dma_addr;
  951. void *mem;
  952. u32 feature_resp;
  953. u8 temp_c_cur, temp_c_thresh;
  954. u16 temp_k;
  955. log_response = kmalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL);
  956. if (log_response == NULL) {
  957. res = -ENOMEM;
  958. goto out_mem;
  959. }
  960. memset(log_response, 0, LOG_TEMP_PAGE_LENGTH);
  961. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  962. sizeof(struct nvme_smart_log),
  963. &dma_addr, GFP_KERNEL);
  964. if (mem == NULL) {
  965. res = -ENOMEM;
  966. goto out_dma;
  967. }
  968. /* Get SMART Log Page */
  969. memset(&c, 0, sizeof(c));
  970. c.common.opcode = nvme_admin_get_log_page;
  971. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  972. c.common.prp1 = cpu_to_le64(dma_addr);
  973. c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) /
  974. BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE);
  975. res = nvme_submit_admin_cmd(dev, &c, NULL);
  976. if (res != NVME_SC_SUCCESS) {
  977. temp_c_cur = LOG_TEMP_UNKNOWN;
  978. } else {
  979. smart_log = mem;
  980. temp_k = (smart_log->temperature[1] << 8) +
  981. (smart_log->temperature[0]);
  982. temp_c_cur = temp_k - KELVIN_TEMP_FACTOR;
  983. }
  984. /* Get Features for Temp Threshold */
  985. res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0,
  986. &feature_resp);
  987. if (res != NVME_SC_SUCCESS)
  988. temp_c_thresh = LOG_TEMP_UNKNOWN;
  989. else
  990. temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR;
  991. log_response[0] = LOG_PAGE_TEMPERATURE_PAGE;
  992. /* Subpage=0x00, Page Length MSB=0 */
  993. log_response[3] = REMAINING_TEMP_PAGE_LENGTH;
  994. /* Temperature Log Parameter 1 (Temperature) Start */
  995. /* Parameter Code = 0x0000 */
  996. log_response[6] = 0x01; /* Format and Linking = 01b */
  997. log_response[7] = 0x02; /* Parameter Length */
  998. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  999. log_response[9] = temp_c_cur;
  1000. /* Temperature Log Parameter 2 (Reference Temperature) Start */
  1001. log_response[11] = 0x01; /* Parameter Code = 0x0001 */
  1002. log_response[12] = 0x01; /* Format and Linking = 01b */
  1003. log_response[13] = 0x02; /* Parameter Length */
  1004. /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */
  1005. log_response[15] = temp_c_thresh;
  1006. xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH);
  1007. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  1008. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  1009. mem, dma_addr);
  1010. out_dma:
  1011. kfree(log_response);
  1012. out_mem:
  1013. return res;
  1014. }
  1015. /* MODE SENSE Helper Functions */
  1016. static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa,
  1017. u16 mode_data_length, u16 blk_desc_len)
  1018. {
  1019. /* Quick check to make sure I don't stomp on my own memory... */
  1020. if ((cdb10 && len < 8) || (!cdb10 && len < 4))
  1021. return SNTI_INTERNAL_ERROR;
  1022. if (cdb10) {
  1023. resp[0] = (mode_data_length & 0xFF00) >> 8;
  1024. resp[1] = (mode_data_length & 0x00FF);
  1025. /* resp[2] and [3] are zero */
  1026. resp[4] = llbaa;
  1027. resp[5] = RESERVED_FIELD;
  1028. resp[6] = (blk_desc_len & 0xFF00) >> 8;
  1029. resp[7] = (blk_desc_len & 0x00FF);
  1030. } else {
  1031. resp[0] = (mode_data_length & 0x00FF);
  1032. /* resp[1] and [2] are zero */
  1033. resp[3] = (blk_desc_len & 0x00FF);
  1034. }
  1035. return SNTI_TRANSLATION_SUCCESS;
  1036. }
  1037. static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1038. u8 *resp, int len, u8 llbaa)
  1039. {
  1040. int res = SNTI_TRANSLATION_SUCCESS;
  1041. int nvme_sc;
  1042. struct nvme_dev *dev = ns->dev;
  1043. dma_addr_t dma_addr;
  1044. void *mem;
  1045. struct nvme_id_ns *id_ns;
  1046. u8 flbas;
  1047. u32 lba_length;
  1048. if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN)
  1049. return SNTI_INTERNAL_ERROR;
  1050. else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN)
  1051. return SNTI_INTERNAL_ERROR;
  1052. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1053. &dma_addr, GFP_KERNEL);
  1054. if (mem == NULL) {
  1055. res = -ENOMEM;
  1056. goto out;
  1057. }
  1058. /* nvme ns identify */
  1059. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1060. res = nvme_trans_status_code(hdr, nvme_sc);
  1061. if (res)
  1062. goto out_dma;
  1063. if (nvme_sc) {
  1064. res = nvme_sc;
  1065. goto out_dma;
  1066. }
  1067. id_ns = mem;
  1068. flbas = (id_ns->flbas) & 0x0F;
  1069. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1070. if (llbaa == 0) {
  1071. __be32 tmp_cap = cpu_to_be32(le64_to_cpu(id_ns->ncap));
  1072. /* Byte 4 is reserved */
  1073. __be32 tmp_len = cpu_to_be32(lba_length & 0x00FFFFFF);
  1074. memcpy(resp, &tmp_cap, sizeof(u32));
  1075. memcpy(&resp[4], &tmp_len, sizeof(u32));
  1076. } else {
  1077. __be64 tmp_cap = cpu_to_be64(le64_to_cpu(id_ns->ncap));
  1078. __be32 tmp_len = cpu_to_be32(lba_length);
  1079. memcpy(resp, &tmp_cap, sizeof(u64));
  1080. /* Bytes 8, 9, 10, 11 are reserved */
  1081. memcpy(&resp[12], &tmp_len, sizeof(u32));
  1082. }
  1083. out_dma:
  1084. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1085. dma_addr);
  1086. out:
  1087. return res;
  1088. }
  1089. static int nvme_trans_fill_control_page(struct nvme_ns *ns,
  1090. struct sg_io_hdr *hdr, u8 *resp,
  1091. int len)
  1092. {
  1093. if (len < MODE_PAGE_CONTROL_LEN)
  1094. return SNTI_INTERNAL_ERROR;
  1095. resp[0] = MODE_PAGE_CONTROL;
  1096. resp[1] = MODE_PAGE_CONTROL_LEN_FIELD;
  1097. resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1,
  1098. * D_SENSE=1, GLTSD=1, RLEC=0 */
  1099. resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */
  1100. /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */
  1101. resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */
  1102. /* resp[6] and [7] are obsolete, thus zero */
  1103. resp[8] = 0xFF; /* Busy timeout period = 0xffff */
  1104. resp[9] = 0xFF;
  1105. /* Bytes 10,11: Extended selftest completion time = 0x0000 */
  1106. return SNTI_TRANSLATION_SUCCESS;
  1107. }
  1108. static int nvme_trans_fill_caching_page(struct nvme_ns *ns,
  1109. struct sg_io_hdr *hdr,
  1110. u8 *resp, int len)
  1111. {
  1112. int res = SNTI_TRANSLATION_SUCCESS;
  1113. int nvme_sc;
  1114. struct nvme_dev *dev = ns->dev;
  1115. u32 feature_resp;
  1116. u8 vwc;
  1117. if (len < MODE_PAGE_CACHING_LEN)
  1118. return SNTI_INTERNAL_ERROR;
  1119. nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0,
  1120. &feature_resp);
  1121. res = nvme_trans_status_code(hdr, nvme_sc);
  1122. if (res)
  1123. goto out;
  1124. if (nvme_sc) {
  1125. res = nvme_sc;
  1126. goto out;
  1127. }
  1128. vwc = feature_resp & 0x00000001;
  1129. resp[0] = MODE_PAGE_CACHING;
  1130. resp[1] = MODE_PAGE_CACHING_LEN_FIELD;
  1131. resp[2] = vwc << 2;
  1132. out:
  1133. return res;
  1134. }
  1135. static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns,
  1136. struct sg_io_hdr *hdr, u8 *resp,
  1137. int len)
  1138. {
  1139. int res = SNTI_TRANSLATION_SUCCESS;
  1140. if (len < MODE_PAGE_POW_CND_LEN)
  1141. return SNTI_INTERNAL_ERROR;
  1142. resp[0] = MODE_PAGE_POWER_CONDITION;
  1143. resp[1] = MODE_PAGE_POW_CND_LEN_FIELD;
  1144. /* All other bytes are zero */
  1145. return res;
  1146. }
  1147. static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns,
  1148. struct sg_io_hdr *hdr, u8 *resp,
  1149. int len)
  1150. {
  1151. int res = SNTI_TRANSLATION_SUCCESS;
  1152. if (len < MODE_PAGE_INF_EXC_LEN)
  1153. return SNTI_INTERNAL_ERROR;
  1154. resp[0] = MODE_PAGE_INFO_EXCEP;
  1155. resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD;
  1156. resp[2] = 0x88;
  1157. /* All other bytes are zero */
  1158. return res;
  1159. }
  1160. static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1161. u8 *resp, int len)
  1162. {
  1163. int res = SNTI_TRANSLATION_SUCCESS;
  1164. u16 mode_pages_offset_1 = 0;
  1165. u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4;
  1166. mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN;
  1167. mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN;
  1168. mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN;
  1169. res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1],
  1170. MODE_PAGE_CACHING_LEN);
  1171. if (res != SNTI_TRANSLATION_SUCCESS)
  1172. goto out;
  1173. res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2],
  1174. MODE_PAGE_CONTROL_LEN);
  1175. if (res != SNTI_TRANSLATION_SUCCESS)
  1176. goto out;
  1177. res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3],
  1178. MODE_PAGE_POW_CND_LEN);
  1179. if (res != SNTI_TRANSLATION_SUCCESS)
  1180. goto out;
  1181. res = nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4],
  1182. MODE_PAGE_INF_EXC_LEN);
  1183. if (res != SNTI_TRANSLATION_SUCCESS)
  1184. goto out;
  1185. out:
  1186. return res;
  1187. }
  1188. static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa)
  1189. {
  1190. if (dbd == MODE_SENSE_BLK_DESC_ENABLED) {
  1191. /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */
  1192. return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT;
  1193. } else {
  1194. return 0;
  1195. }
  1196. }
  1197. static int nvme_trans_mode_page_create(struct nvme_ns *ns,
  1198. struct sg_io_hdr *hdr, u8 *cmd,
  1199. u16 alloc_len, u8 cdb10,
  1200. int (*mode_page_fill_func)
  1201. (struct nvme_ns *,
  1202. struct sg_io_hdr *hdr, u8 *, int),
  1203. u16 mode_pages_tot_len)
  1204. {
  1205. int res = SNTI_TRANSLATION_SUCCESS;
  1206. int xfer_len;
  1207. u8 *response;
  1208. u8 dbd, llbaa;
  1209. u16 resp_size;
  1210. int mph_size;
  1211. u16 mode_pages_offset_1;
  1212. u16 blk_desc_len, blk_desc_offset, mode_data_length;
  1213. dbd = GET_MODE_SENSE_DBD(cmd);
  1214. llbaa = GET_MODE_SENSE_LLBAA(cmd);
  1215. mph_size = GET_MODE_SENSE_MPH_SIZE(cdb10);
  1216. blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa);
  1217. resp_size = mph_size + blk_desc_len + mode_pages_tot_len;
  1218. /* Refer spc4r34 Table 440 for calculation of Mode data Length field */
  1219. mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len;
  1220. blk_desc_offset = mph_size;
  1221. mode_pages_offset_1 = blk_desc_offset + blk_desc_len;
  1222. response = kmalloc(resp_size, GFP_KERNEL);
  1223. if (response == NULL) {
  1224. res = -ENOMEM;
  1225. goto out_mem;
  1226. }
  1227. memset(response, 0, resp_size);
  1228. res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10,
  1229. llbaa, mode_data_length, blk_desc_len);
  1230. if (res != SNTI_TRANSLATION_SUCCESS)
  1231. goto out_free;
  1232. if (blk_desc_len > 0) {
  1233. res = nvme_trans_fill_blk_desc(ns, hdr,
  1234. &response[blk_desc_offset],
  1235. blk_desc_len, llbaa);
  1236. if (res != SNTI_TRANSLATION_SUCCESS)
  1237. goto out_free;
  1238. }
  1239. res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1],
  1240. mode_pages_tot_len);
  1241. if (res != SNTI_TRANSLATION_SUCCESS)
  1242. goto out_free;
  1243. xfer_len = min(alloc_len, resp_size);
  1244. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  1245. out_free:
  1246. kfree(response);
  1247. out_mem:
  1248. return res;
  1249. }
  1250. /* Read Capacity Helper Functions */
  1251. static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns,
  1252. u8 cdb16)
  1253. {
  1254. u8 flbas;
  1255. u32 lba_length;
  1256. u64 rlba;
  1257. u8 prot_en;
  1258. u8 p_type_lut[4] = {0, 0, 1, 2};
  1259. __be64 tmp_rlba;
  1260. __be32 tmp_rlba_32;
  1261. __be32 tmp_len;
  1262. flbas = (id_ns->flbas) & 0x0F;
  1263. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1264. rlba = le64_to_cpup(&id_ns->nsze) - 1;
  1265. (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0);
  1266. if (!cdb16) {
  1267. if (rlba > 0xFFFFFFFF)
  1268. rlba = 0xFFFFFFFF;
  1269. tmp_rlba_32 = cpu_to_be32(rlba);
  1270. tmp_len = cpu_to_be32(lba_length);
  1271. memcpy(response, &tmp_rlba_32, sizeof(u32));
  1272. memcpy(&response[4], &tmp_len, sizeof(u32));
  1273. } else {
  1274. tmp_rlba = cpu_to_be64(rlba);
  1275. tmp_len = cpu_to_be32(lba_length);
  1276. memcpy(response, &tmp_rlba, sizeof(u64));
  1277. memcpy(&response[8], &tmp_len, sizeof(u32));
  1278. response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en;
  1279. /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */
  1280. /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */
  1281. /* Bytes 16-31 - Reserved */
  1282. }
  1283. }
  1284. /* Start Stop Unit Helper Functions */
  1285. static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1286. u8 pc, u8 pcmod, u8 start)
  1287. {
  1288. int res = SNTI_TRANSLATION_SUCCESS;
  1289. int nvme_sc;
  1290. struct nvme_dev *dev = ns->dev;
  1291. dma_addr_t dma_addr;
  1292. void *mem;
  1293. struct nvme_id_ctrl *id_ctrl;
  1294. int lowest_pow_st; /* max npss = lowest power consumption */
  1295. unsigned ps_desired = 0;
  1296. /* NVMe Controller Identify */
  1297. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1298. sizeof(struct nvme_id_ctrl),
  1299. &dma_addr, GFP_KERNEL);
  1300. if (mem == NULL) {
  1301. res = -ENOMEM;
  1302. goto out;
  1303. }
  1304. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  1305. res = nvme_trans_status_code(hdr, nvme_sc);
  1306. if (res)
  1307. goto out_dma;
  1308. if (nvme_sc) {
  1309. res = nvme_sc;
  1310. goto out_dma;
  1311. }
  1312. id_ctrl = mem;
  1313. lowest_pow_st = id_ctrl->npss - 1;
  1314. switch (pc) {
  1315. case NVME_POWER_STATE_START_VALID:
  1316. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1317. if (pcmod == 0 && start == 0x1)
  1318. ps_desired = POWER_STATE_0;
  1319. if (pcmod == 0 && start == 0x0)
  1320. ps_desired = lowest_pow_st;
  1321. break;
  1322. case NVME_POWER_STATE_ACTIVE:
  1323. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1324. if (pcmod == 0)
  1325. ps_desired = POWER_STATE_0;
  1326. break;
  1327. case NVME_POWER_STATE_IDLE:
  1328. /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */
  1329. /* min of desired state and (lps-1) because lps is STOP */
  1330. if (pcmod == 0x0)
  1331. ps_desired = min(POWER_STATE_1, (lowest_pow_st - 1));
  1332. else if (pcmod == 0x1)
  1333. ps_desired = min(POWER_STATE_2, (lowest_pow_st - 1));
  1334. else if (pcmod == 0x2)
  1335. ps_desired = min(POWER_STATE_3, (lowest_pow_st - 1));
  1336. break;
  1337. case NVME_POWER_STATE_STANDBY:
  1338. /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */
  1339. if (pcmod == 0x0)
  1340. ps_desired = max(0, (lowest_pow_st - 2));
  1341. else if (pcmod == 0x1)
  1342. ps_desired = max(0, (lowest_pow_st - 1));
  1343. break;
  1344. case NVME_POWER_STATE_LU_CONTROL:
  1345. default:
  1346. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1347. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1348. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1349. break;
  1350. }
  1351. nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0,
  1352. NULL);
  1353. res = nvme_trans_status_code(hdr, nvme_sc);
  1354. if (res)
  1355. goto out_dma;
  1356. if (nvme_sc)
  1357. res = nvme_sc;
  1358. out_dma:
  1359. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  1360. dma_addr);
  1361. out:
  1362. return res;
  1363. }
  1364. /* Write Buffer Helper Functions */
  1365. /* Also using this for Format Unit with hdr passed as NULL, and buffer_id, 0 */
  1366. static int nvme_trans_send_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1367. u8 opcode, u32 tot_len, u32 offset,
  1368. u8 buffer_id)
  1369. {
  1370. int res = SNTI_TRANSLATION_SUCCESS;
  1371. int nvme_sc;
  1372. struct nvme_dev *dev = ns->dev;
  1373. struct nvme_command c;
  1374. struct nvme_iod *iod = NULL;
  1375. unsigned length;
  1376. memset(&c, 0, sizeof(c));
  1377. c.common.opcode = opcode;
  1378. if (opcode == nvme_admin_download_fw) {
  1379. if (hdr->iovec_count > 0) {
  1380. /* Assuming SGL is not allowed for this command */
  1381. res = nvme_trans_completion(hdr,
  1382. SAM_STAT_CHECK_CONDITION,
  1383. ILLEGAL_REQUEST,
  1384. SCSI_ASC_INVALID_CDB,
  1385. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1386. goto out;
  1387. }
  1388. iod = nvme_map_user_pages(dev, DMA_TO_DEVICE,
  1389. (unsigned long)hdr->dxferp, tot_len);
  1390. if (IS_ERR(iod)) {
  1391. res = PTR_ERR(iod);
  1392. goto out;
  1393. }
  1394. length = nvme_setup_prps(dev, &c.common, iod, tot_len,
  1395. GFP_KERNEL);
  1396. if (length != tot_len) {
  1397. res = -ENOMEM;
  1398. goto out_unmap;
  1399. }
  1400. c.dlfw.numd = cpu_to_le32((tot_len/BYTES_TO_DWORDS) - 1);
  1401. c.dlfw.offset = cpu_to_le32(offset/BYTES_TO_DWORDS);
  1402. } else if (opcode == nvme_admin_activate_fw) {
  1403. u32 cdw10 = buffer_id | NVME_FWACT_REPL_ACTV;
  1404. c.common.cdw10[0] = cpu_to_le32(cdw10);
  1405. }
  1406. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1407. res = nvme_trans_status_code(hdr, nvme_sc);
  1408. if (res)
  1409. goto out_unmap;
  1410. if (nvme_sc)
  1411. res = nvme_sc;
  1412. out_unmap:
  1413. if (opcode == nvme_admin_download_fw) {
  1414. nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod);
  1415. nvme_free_iod(dev, iod);
  1416. }
  1417. out:
  1418. return res;
  1419. }
  1420. /* Mode Select Helper Functions */
  1421. static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10,
  1422. u16 *bd_len, u8 *llbaa)
  1423. {
  1424. if (cdb10) {
  1425. /* 10 Byte CDB */
  1426. *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) +
  1427. parm_list[MODE_SELECT_10_BD_OFFSET + 1];
  1428. *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] &&
  1429. MODE_SELECT_10_LLBAA_MASK;
  1430. } else {
  1431. /* 6 Byte CDB */
  1432. *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET];
  1433. }
  1434. }
  1435. static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
  1436. u16 idx, u16 bd_len, u8 llbaa)
  1437. {
  1438. u16 bd_num;
  1439. bd_num = bd_len / ((llbaa == 0) ?
  1440. SHORT_DESC_BLOCK : LONG_DESC_BLOCK);
  1441. /* Store block descriptor info if a FORMAT UNIT comes later */
  1442. /* TODO Saving 1st BD info; what to do if multiple BD received? */
  1443. if (llbaa == 0) {
  1444. /* Standard Block Descriptor - spc4r34 7.5.5.1 */
  1445. ns->mode_select_num_blocks =
  1446. (parm_list[idx + 1] << 16) +
  1447. (parm_list[idx + 2] << 8) +
  1448. (parm_list[idx + 3]);
  1449. ns->mode_select_block_len =
  1450. (parm_list[idx + 5] << 16) +
  1451. (parm_list[idx + 6] << 8) +
  1452. (parm_list[idx + 7]);
  1453. } else {
  1454. /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */
  1455. ns->mode_select_num_blocks =
  1456. (((u64)parm_list[idx + 0]) << 56) +
  1457. (((u64)parm_list[idx + 1]) << 48) +
  1458. (((u64)parm_list[idx + 2]) << 40) +
  1459. (((u64)parm_list[idx + 3]) << 32) +
  1460. (((u64)parm_list[idx + 4]) << 24) +
  1461. (((u64)parm_list[idx + 5]) << 16) +
  1462. (((u64)parm_list[idx + 6]) << 8) +
  1463. ((u64)parm_list[idx + 7]);
  1464. ns->mode_select_block_len =
  1465. (parm_list[idx + 12] << 24) +
  1466. (parm_list[idx + 13] << 16) +
  1467. (parm_list[idx + 14] << 8) +
  1468. (parm_list[idx + 15]);
  1469. }
  1470. }
  1471. static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1472. u8 *mode_page, u8 page_code)
  1473. {
  1474. int res = SNTI_TRANSLATION_SUCCESS;
  1475. int nvme_sc;
  1476. struct nvme_dev *dev = ns->dev;
  1477. unsigned dword11;
  1478. switch (page_code) {
  1479. case MODE_PAGE_CACHING:
  1480. dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0);
  1481. nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11,
  1482. 0, NULL);
  1483. res = nvme_trans_status_code(hdr, nvme_sc);
  1484. if (res)
  1485. break;
  1486. if (nvme_sc) {
  1487. res = nvme_sc;
  1488. break;
  1489. }
  1490. break;
  1491. case MODE_PAGE_CONTROL:
  1492. break;
  1493. case MODE_PAGE_POWER_CONDITION:
  1494. /* Verify the OS is not trying to set timers */
  1495. if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) {
  1496. res = nvme_trans_completion(hdr,
  1497. SAM_STAT_CHECK_CONDITION,
  1498. ILLEGAL_REQUEST,
  1499. SCSI_ASC_INVALID_PARAMETER,
  1500. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1501. if (!res)
  1502. res = SNTI_INTERNAL_ERROR;
  1503. break;
  1504. }
  1505. break;
  1506. default:
  1507. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1508. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1509. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1510. if (!res)
  1511. res = SNTI_INTERNAL_ERROR;
  1512. break;
  1513. }
  1514. return res;
  1515. }
  1516. static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1517. u8 *cmd, u16 parm_list_len, u8 pf,
  1518. u8 sp, u8 cdb10)
  1519. {
  1520. int res = SNTI_TRANSLATION_SUCCESS;
  1521. u8 *parm_list;
  1522. u16 bd_len;
  1523. u8 llbaa = 0;
  1524. u16 index, saved_index;
  1525. u8 page_code;
  1526. u16 mp_size;
  1527. /* Get parm list from data-in/out buffer */
  1528. parm_list = kmalloc(parm_list_len, GFP_KERNEL);
  1529. if (parm_list == NULL) {
  1530. res = -ENOMEM;
  1531. goto out;
  1532. }
  1533. res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len);
  1534. if (res != SNTI_TRANSLATION_SUCCESS)
  1535. goto out_mem;
  1536. nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa);
  1537. index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE);
  1538. if (bd_len != 0) {
  1539. /* Block Descriptors present, parse */
  1540. nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa);
  1541. index += bd_len;
  1542. }
  1543. saved_index = index;
  1544. /* Multiple mode pages may be present; iterate through all */
  1545. /* In 1st Iteration, don't do NVME Command, only check for CDB errors */
  1546. do {
  1547. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1548. mp_size = parm_list[index + 1] + 2;
  1549. if ((page_code != MODE_PAGE_CACHING) &&
  1550. (page_code != MODE_PAGE_CONTROL) &&
  1551. (page_code != MODE_PAGE_POWER_CONDITION)) {
  1552. res = nvme_trans_completion(hdr,
  1553. SAM_STAT_CHECK_CONDITION,
  1554. ILLEGAL_REQUEST,
  1555. SCSI_ASC_INVALID_CDB,
  1556. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1557. goto out_mem;
  1558. }
  1559. index += mp_size;
  1560. } while (index < parm_list_len);
  1561. /* In 2nd Iteration, do the NVME Commands */
  1562. index = saved_index;
  1563. do {
  1564. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1565. mp_size = parm_list[index + 1] + 2;
  1566. res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index],
  1567. page_code);
  1568. if (res != SNTI_TRANSLATION_SUCCESS)
  1569. break;
  1570. index += mp_size;
  1571. } while (index < parm_list_len);
  1572. out_mem:
  1573. kfree(parm_list);
  1574. out:
  1575. return res;
  1576. }
  1577. /* Format Unit Helper Functions */
  1578. static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns,
  1579. struct sg_io_hdr *hdr)
  1580. {
  1581. int res = SNTI_TRANSLATION_SUCCESS;
  1582. int nvme_sc;
  1583. struct nvme_dev *dev = ns->dev;
  1584. dma_addr_t dma_addr;
  1585. void *mem;
  1586. struct nvme_id_ns *id_ns;
  1587. u8 flbas;
  1588. /*
  1589. * SCSI Expects a MODE SELECT would have been issued prior to
  1590. * a FORMAT UNIT, and the block size and number would be used
  1591. * from the block descriptor in it. If a MODE SELECT had not
  1592. * been issued, FORMAT shall use the current values for both.
  1593. */
  1594. if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) {
  1595. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1596. sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL);
  1597. if (mem == NULL) {
  1598. res = -ENOMEM;
  1599. goto out;
  1600. }
  1601. /* nvme ns identify */
  1602. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1603. res = nvme_trans_status_code(hdr, nvme_sc);
  1604. if (res)
  1605. goto out_dma;
  1606. if (nvme_sc) {
  1607. res = nvme_sc;
  1608. goto out_dma;
  1609. }
  1610. id_ns = mem;
  1611. if (ns->mode_select_num_blocks == 0)
  1612. ns->mode_select_num_blocks = le64_to_cpu(id_ns->ncap);
  1613. if (ns->mode_select_block_len == 0) {
  1614. flbas = (id_ns->flbas) & 0x0F;
  1615. ns->mode_select_block_len =
  1616. (1 << (id_ns->lbaf[flbas].ds));
  1617. }
  1618. out_dma:
  1619. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1620. mem, dma_addr);
  1621. }
  1622. out:
  1623. return res;
  1624. }
  1625. static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len,
  1626. u8 format_prot_info, u8 *nvme_pf_code)
  1627. {
  1628. int res = SNTI_TRANSLATION_SUCCESS;
  1629. u8 *parm_list;
  1630. u8 pf_usage, pf_code;
  1631. parm_list = kmalloc(len, GFP_KERNEL);
  1632. if (parm_list == NULL) {
  1633. res = -ENOMEM;
  1634. goto out;
  1635. }
  1636. res = nvme_trans_copy_from_user(hdr, parm_list, len);
  1637. if (res != SNTI_TRANSLATION_SUCCESS)
  1638. goto out_mem;
  1639. if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] &
  1640. FORMAT_UNIT_IMMED_MASK) != 0) {
  1641. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1642. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1643. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1644. goto out_mem;
  1645. }
  1646. if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN &&
  1647. (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) {
  1648. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1649. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1650. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1651. goto out_mem;
  1652. }
  1653. pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] &
  1654. FORMAT_UNIT_PROT_FIELD_USAGE_MASK;
  1655. pf_code = (pf_usage << 2) | format_prot_info;
  1656. switch (pf_code) {
  1657. case 0:
  1658. *nvme_pf_code = 0;
  1659. break;
  1660. case 2:
  1661. *nvme_pf_code = 1;
  1662. break;
  1663. case 3:
  1664. *nvme_pf_code = 2;
  1665. break;
  1666. case 7:
  1667. *nvme_pf_code = 3;
  1668. break;
  1669. default:
  1670. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1671. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1672. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1673. break;
  1674. }
  1675. out_mem:
  1676. kfree(parm_list);
  1677. out:
  1678. return res;
  1679. }
  1680. static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1681. u8 prot_info)
  1682. {
  1683. int res = SNTI_TRANSLATION_SUCCESS;
  1684. int nvme_sc;
  1685. struct nvme_dev *dev = ns->dev;
  1686. dma_addr_t dma_addr;
  1687. void *mem;
  1688. struct nvme_id_ns *id_ns;
  1689. u8 i;
  1690. u8 flbas, nlbaf;
  1691. u8 selected_lbaf = 0xFF;
  1692. u32 cdw10 = 0;
  1693. struct nvme_command c;
  1694. /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */
  1695. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1696. &dma_addr, GFP_KERNEL);
  1697. if (mem == NULL) {
  1698. res = -ENOMEM;
  1699. goto out;
  1700. }
  1701. /* nvme ns identify */
  1702. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1703. res = nvme_trans_status_code(hdr, nvme_sc);
  1704. if (res)
  1705. goto out_dma;
  1706. if (nvme_sc) {
  1707. res = nvme_sc;
  1708. goto out_dma;
  1709. }
  1710. id_ns = mem;
  1711. flbas = (id_ns->flbas) & 0x0F;
  1712. nlbaf = id_ns->nlbaf;
  1713. for (i = 0; i < nlbaf; i++) {
  1714. if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) {
  1715. selected_lbaf = i;
  1716. break;
  1717. }
  1718. }
  1719. if (selected_lbaf > 0x0F) {
  1720. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1721. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1722. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1723. }
  1724. if (ns->mode_select_num_blocks != le64_to_cpu(id_ns->ncap)) {
  1725. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1726. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1727. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1728. }
  1729. cdw10 |= prot_info << 5;
  1730. cdw10 |= selected_lbaf & 0x0F;
  1731. memset(&c, 0, sizeof(c));
  1732. c.format.opcode = nvme_admin_format_nvm;
  1733. c.format.nsid = cpu_to_le32(ns->ns_id);
  1734. c.format.cdw10 = cpu_to_le32(cdw10);
  1735. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1736. res = nvme_trans_status_code(hdr, nvme_sc);
  1737. if (res)
  1738. goto out_dma;
  1739. if (nvme_sc)
  1740. res = nvme_sc;
  1741. out_dma:
  1742. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1743. dma_addr);
  1744. out:
  1745. return res;
  1746. }
  1747. /* Read/Write Helper Functions */
  1748. static inline void nvme_trans_get_io_cdb6(u8 *cmd,
  1749. struct nvme_trans_io_cdb *cdb_info)
  1750. {
  1751. cdb_info->fua = 0;
  1752. cdb_info->prot_info = 0;
  1753. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_6_CDB_LBA_OFFSET) &
  1754. IO_6_CDB_LBA_MASK;
  1755. cdb_info->xfer_len = GET_U8_FROM_CDB(cmd, IO_6_CDB_TX_LEN_OFFSET);
  1756. /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */
  1757. if (cdb_info->xfer_len == 0)
  1758. cdb_info->xfer_len = IO_6_DEFAULT_TX_LEN;
  1759. }
  1760. static inline void nvme_trans_get_io_cdb10(u8 *cmd,
  1761. struct nvme_trans_io_cdb *cdb_info)
  1762. {
  1763. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_10_CDB_FUA_OFFSET) &
  1764. IO_CDB_FUA_MASK;
  1765. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_10_CDB_WP_OFFSET) &
  1766. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1767. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_10_CDB_LBA_OFFSET);
  1768. cdb_info->xfer_len = GET_U16_FROM_CDB(cmd, IO_10_CDB_TX_LEN_OFFSET);
  1769. }
  1770. static inline void nvme_trans_get_io_cdb12(u8 *cmd,
  1771. struct nvme_trans_io_cdb *cdb_info)
  1772. {
  1773. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_12_CDB_FUA_OFFSET) &
  1774. IO_CDB_FUA_MASK;
  1775. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_12_CDB_WP_OFFSET) &
  1776. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1777. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_12_CDB_LBA_OFFSET);
  1778. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_12_CDB_TX_LEN_OFFSET);
  1779. }
  1780. static inline void nvme_trans_get_io_cdb16(u8 *cmd,
  1781. struct nvme_trans_io_cdb *cdb_info)
  1782. {
  1783. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_16_CDB_FUA_OFFSET) &
  1784. IO_CDB_FUA_MASK;
  1785. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_16_CDB_WP_OFFSET) &
  1786. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1787. cdb_info->lba = GET_U64_FROM_CDB(cmd, IO_16_CDB_LBA_OFFSET);
  1788. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_16_CDB_TX_LEN_OFFSET);
  1789. }
  1790. static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr,
  1791. struct nvme_trans_io_cdb *cdb_info,
  1792. u32 max_blocks)
  1793. {
  1794. /* If using iovecs, send one nvme command per vector */
  1795. if (hdr->iovec_count > 0)
  1796. return hdr->iovec_count;
  1797. else if (cdb_info->xfer_len > max_blocks)
  1798. return ((cdb_info->xfer_len - 1) / max_blocks) + 1;
  1799. else
  1800. return 1;
  1801. }
  1802. static u16 nvme_trans_io_get_control(struct nvme_ns *ns,
  1803. struct nvme_trans_io_cdb *cdb_info)
  1804. {
  1805. u16 control = 0;
  1806. /* When Protection information support is added, implement here */
  1807. if (cdb_info->fua > 0)
  1808. control |= NVME_RW_FUA;
  1809. return control;
  1810. }
  1811. static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1812. struct nvme_trans_io_cdb *cdb_info, u8 is_write)
  1813. {
  1814. int res = SNTI_TRANSLATION_SUCCESS;
  1815. int nvme_sc;
  1816. struct nvme_dev *dev = ns->dev;
  1817. struct nvme_queue *nvmeq;
  1818. u32 num_cmds;
  1819. struct nvme_iod *iod;
  1820. u64 unit_len;
  1821. u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */
  1822. u32 retcode;
  1823. u32 i = 0;
  1824. u64 nvme_offset = 0;
  1825. void __user *next_mapping_addr;
  1826. struct nvme_command c;
  1827. u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read);
  1828. u16 control;
  1829. u32 max_blocks = nvme_block_nr(ns, dev->max_hw_sectors);
  1830. num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks);
  1831. /*
  1832. * This loop handles two cases.
  1833. * First, when an SGL is used in the form of an iovec list:
  1834. * - Use iov_base as the next mapping address for the nvme command_id
  1835. * - Use iov_len as the data transfer length for the command.
  1836. * Second, when we have a single buffer
  1837. * - If larger than max_blocks, split into chunks, offset
  1838. * each nvme command accordingly.
  1839. */
  1840. for (i = 0; i < num_cmds; i++) {
  1841. memset(&c, 0, sizeof(c));
  1842. if (hdr->iovec_count > 0) {
  1843. struct sg_iovec sgl;
  1844. retcode = copy_from_user(&sgl, hdr->dxferp +
  1845. i * sizeof(struct sg_iovec),
  1846. sizeof(struct sg_iovec));
  1847. if (retcode)
  1848. return -EFAULT;
  1849. unit_len = sgl.iov_len;
  1850. unit_num_blocks = unit_len >> ns->lba_shift;
  1851. next_mapping_addr = sgl.iov_base;
  1852. } else {
  1853. unit_num_blocks = min((u64)max_blocks,
  1854. (cdb_info->xfer_len - nvme_offset));
  1855. unit_len = unit_num_blocks << ns->lba_shift;
  1856. next_mapping_addr = hdr->dxferp +
  1857. ((1 << ns->lba_shift) * nvme_offset);
  1858. }
  1859. c.rw.opcode = opcode;
  1860. c.rw.nsid = cpu_to_le32(ns->ns_id);
  1861. c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset);
  1862. c.rw.length = cpu_to_le16(unit_num_blocks - 1);
  1863. control = nvme_trans_io_get_control(ns, cdb_info);
  1864. c.rw.control = cpu_to_le16(control);
  1865. iod = nvme_map_user_pages(dev,
  1866. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1867. (unsigned long)next_mapping_addr, unit_len);
  1868. if (IS_ERR(iod)) {
  1869. res = PTR_ERR(iod);
  1870. goto out;
  1871. }
  1872. retcode = nvme_setup_prps(dev, &c.common, iod, unit_len,
  1873. GFP_KERNEL);
  1874. if (retcode != unit_len) {
  1875. nvme_unmap_user_pages(dev,
  1876. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1877. iod);
  1878. nvme_free_iod(dev, iod);
  1879. res = -ENOMEM;
  1880. goto out;
  1881. }
  1882. nvme_offset += unit_num_blocks;
  1883. nvmeq = get_nvmeq(dev);
  1884. /*
  1885. * Since nvme_submit_sync_cmd sleeps, we can't keep
  1886. * preemption disabled. We may be preempted at any
  1887. * point, and be rescheduled to a different CPU. That
  1888. * will cause cacheline bouncing, but no additional
  1889. * races since q_lock already protects against other
  1890. * CPUs.
  1891. */
  1892. put_nvmeq(nvmeq);
  1893. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL,
  1894. NVME_IO_TIMEOUT);
  1895. if (nvme_sc != NVME_SC_SUCCESS) {
  1896. nvme_unmap_user_pages(dev,
  1897. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1898. iod);
  1899. nvme_free_iod(dev, iod);
  1900. res = nvme_trans_status_code(hdr, nvme_sc);
  1901. goto out;
  1902. }
  1903. nvme_unmap_user_pages(dev,
  1904. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1905. iod);
  1906. nvme_free_iod(dev, iod);
  1907. }
  1908. res = nvme_trans_status_code(hdr, NVME_SC_SUCCESS);
  1909. out:
  1910. return res;
  1911. }
  1912. /* SCSI Command Translation Functions */
  1913. static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write,
  1914. u8 *cmd)
  1915. {
  1916. int res = SNTI_TRANSLATION_SUCCESS;
  1917. struct nvme_trans_io_cdb cdb_info;
  1918. u8 opcode = cmd[0];
  1919. u64 xfer_bytes;
  1920. u64 sum_iov_len = 0;
  1921. struct sg_iovec sgl;
  1922. int i;
  1923. size_t not_copied;
  1924. /* Extract Fields from CDB */
  1925. switch (opcode) {
  1926. case WRITE_6:
  1927. case READ_6:
  1928. nvme_trans_get_io_cdb6(cmd, &cdb_info);
  1929. break;
  1930. case WRITE_10:
  1931. case READ_10:
  1932. nvme_trans_get_io_cdb10(cmd, &cdb_info);
  1933. break;
  1934. case WRITE_12:
  1935. case READ_12:
  1936. nvme_trans_get_io_cdb12(cmd, &cdb_info);
  1937. break;
  1938. case WRITE_16:
  1939. case READ_16:
  1940. nvme_trans_get_io_cdb16(cmd, &cdb_info);
  1941. break;
  1942. default:
  1943. /* Will never really reach here */
  1944. res = SNTI_INTERNAL_ERROR;
  1945. goto out;
  1946. }
  1947. /* Calculate total length of transfer (in bytes) */
  1948. if (hdr->iovec_count > 0) {
  1949. for (i = 0; i < hdr->iovec_count; i++) {
  1950. not_copied = copy_from_user(&sgl, hdr->dxferp +
  1951. i * sizeof(struct sg_iovec),
  1952. sizeof(struct sg_iovec));
  1953. if (not_copied)
  1954. return -EFAULT;
  1955. sum_iov_len += sgl.iov_len;
  1956. /* IO vector sizes should be multiples of block size */
  1957. if (sgl.iov_len % (1 << ns->lba_shift) != 0) {
  1958. res = nvme_trans_completion(hdr,
  1959. SAM_STAT_CHECK_CONDITION,
  1960. ILLEGAL_REQUEST,
  1961. SCSI_ASC_INVALID_PARAMETER,
  1962. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1963. goto out;
  1964. }
  1965. }
  1966. } else {
  1967. sum_iov_len = hdr->dxfer_len;
  1968. }
  1969. /* As Per sg ioctl howto, if the lengths differ, use the lower one */
  1970. xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len);
  1971. /* If block count and actual data buffer size dont match, error out */
  1972. if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) {
  1973. res = -EINVAL;
  1974. goto out;
  1975. }
  1976. /* Check for 0 length transfer - it is not illegal */
  1977. if (cdb_info.xfer_len == 0)
  1978. goto out;
  1979. /* Send NVMe IO Command(s) */
  1980. res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write);
  1981. if (res != SNTI_TRANSLATION_SUCCESS)
  1982. goto out;
  1983. out:
  1984. return res;
  1985. }
  1986. static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1987. u8 *cmd)
  1988. {
  1989. int res = SNTI_TRANSLATION_SUCCESS;
  1990. u8 evpd;
  1991. u8 page_code;
  1992. int alloc_len;
  1993. u8 *inq_response;
  1994. evpd = GET_INQ_EVPD_BIT(cmd);
  1995. page_code = GET_INQ_PAGE_CODE(cmd);
  1996. alloc_len = GET_INQ_ALLOC_LENGTH(cmd);
  1997. inq_response = kmalloc(STANDARD_INQUIRY_LENGTH, GFP_KERNEL);
  1998. if (inq_response == NULL) {
  1999. res = -ENOMEM;
  2000. goto out_mem;
  2001. }
  2002. if (evpd == 0) {
  2003. if (page_code == INQ_STANDARD_INQUIRY_PAGE) {
  2004. res = nvme_trans_standard_inquiry_page(ns, hdr,
  2005. inq_response, alloc_len);
  2006. } else {
  2007. res = nvme_trans_completion(hdr,
  2008. SAM_STAT_CHECK_CONDITION,
  2009. ILLEGAL_REQUEST,
  2010. SCSI_ASC_INVALID_CDB,
  2011. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2012. }
  2013. } else {
  2014. switch (page_code) {
  2015. case VPD_SUPPORTED_PAGES:
  2016. res = nvme_trans_supported_vpd_pages(ns, hdr,
  2017. inq_response, alloc_len);
  2018. break;
  2019. case VPD_SERIAL_NUMBER:
  2020. res = nvme_trans_unit_serial_page(ns, hdr, inq_response,
  2021. alloc_len);
  2022. break;
  2023. case VPD_DEVICE_IDENTIFIERS:
  2024. res = nvme_trans_device_id_page(ns, hdr, inq_response,
  2025. alloc_len);
  2026. break;
  2027. case VPD_EXTENDED_INQUIRY:
  2028. res = nvme_trans_ext_inq_page(ns, hdr, alloc_len);
  2029. break;
  2030. case VPD_BLOCK_DEV_CHARACTERISTICS:
  2031. res = nvme_trans_bdev_char_page(ns, hdr, alloc_len);
  2032. break;
  2033. default:
  2034. res = nvme_trans_completion(hdr,
  2035. SAM_STAT_CHECK_CONDITION,
  2036. ILLEGAL_REQUEST,
  2037. SCSI_ASC_INVALID_CDB,
  2038. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2039. break;
  2040. }
  2041. }
  2042. kfree(inq_response);
  2043. out_mem:
  2044. return res;
  2045. }
  2046. static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2047. u8 *cmd)
  2048. {
  2049. int res = SNTI_TRANSLATION_SUCCESS;
  2050. u16 alloc_len;
  2051. u8 sp;
  2052. u8 pc;
  2053. u8 page_code;
  2054. sp = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_SP_OFFSET);
  2055. if (sp != LOG_SENSE_CDB_SP_NOT_ENABLED) {
  2056. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2057. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2058. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2059. goto out;
  2060. }
  2061. pc = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_PC_OFFSET);
  2062. page_code = pc & LOG_SENSE_CDB_PAGE_CODE_MASK;
  2063. pc = (pc & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT;
  2064. if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) {
  2065. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2066. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2067. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2068. goto out;
  2069. }
  2070. alloc_len = GET_U16_FROM_CDB(cmd, LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET);
  2071. switch (page_code) {
  2072. case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE:
  2073. res = nvme_trans_log_supp_pages(ns, hdr, alloc_len);
  2074. break;
  2075. case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE:
  2076. res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len);
  2077. break;
  2078. case LOG_PAGE_TEMPERATURE_PAGE:
  2079. res = nvme_trans_log_temperature(ns, hdr, alloc_len);
  2080. break;
  2081. default:
  2082. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2083. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2084. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2085. break;
  2086. }
  2087. out:
  2088. return res;
  2089. }
  2090. static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2091. u8 *cmd)
  2092. {
  2093. int res = SNTI_TRANSLATION_SUCCESS;
  2094. u8 cdb10 = 0;
  2095. u16 parm_list_len;
  2096. u8 page_format;
  2097. u8 save_pages;
  2098. page_format = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_PAGE_FORMAT_OFFSET);
  2099. page_format &= MODE_SELECT_CDB_PAGE_FORMAT_MASK;
  2100. save_pages = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_SAVE_PAGES_OFFSET);
  2101. save_pages &= MODE_SELECT_CDB_SAVE_PAGES_MASK;
  2102. if (GET_OPCODE(cmd) == MODE_SELECT) {
  2103. parm_list_len = GET_U8_FROM_CDB(cmd,
  2104. MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET);
  2105. } else {
  2106. parm_list_len = GET_U16_FROM_CDB(cmd,
  2107. MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET);
  2108. cdb10 = 1;
  2109. }
  2110. if (parm_list_len != 0) {
  2111. /*
  2112. * According to SPC-4 r24, a paramter list length field of 0
  2113. * shall not be considered an error
  2114. */
  2115. res = nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len,
  2116. page_format, save_pages, cdb10);
  2117. }
  2118. return res;
  2119. }
  2120. static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2121. u8 *cmd)
  2122. {
  2123. int res = SNTI_TRANSLATION_SUCCESS;
  2124. u16 alloc_len;
  2125. u8 cdb10 = 0;
  2126. u8 page_code;
  2127. u8 pc;
  2128. if (GET_OPCODE(cmd) == MODE_SENSE) {
  2129. alloc_len = GET_U8_FROM_CDB(cmd, MODE_SENSE6_ALLOC_LEN_OFFSET);
  2130. } else {
  2131. alloc_len = GET_U16_FROM_CDB(cmd,
  2132. MODE_SENSE10_ALLOC_LEN_OFFSET);
  2133. cdb10 = 1;
  2134. }
  2135. pc = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CONTROL_OFFSET) &
  2136. MODE_SENSE_PAGE_CONTROL_MASK;
  2137. if (pc != MODE_SENSE_PC_CURRENT_VALUES) {
  2138. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2139. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2140. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2141. goto out;
  2142. }
  2143. page_code = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CODE_OFFSET) &
  2144. MODE_SENSE_PAGE_CODE_MASK;
  2145. switch (page_code) {
  2146. case MODE_PAGE_CACHING:
  2147. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2148. cdb10,
  2149. &nvme_trans_fill_caching_page,
  2150. MODE_PAGE_CACHING_LEN);
  2151. break;
  2152. case MODE_PAGE_CONTROL:
  2153. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2154. cdb10,
  2155. &nvme_trans_fill_control_page,
  2156. MODE_PAGE_CONTROL_LEN);
  2157. break;
  2158. case MODE_PAGE_POWER_CONDITION:
  2159. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2160. cdb10,
  2161. &nvme_trans_fill_pow_cnd_page,
  2162. MODE_PAGE_POW_CND_LEN);
  2163. break;
  2164. case MODE_PAGE_INFO_EXCEP:
  2165. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2166. cdb10,
  2167. &nvme_trans_fill_inf_exc_page,
  2168. MODE_PAGE_INF_EXC_LEN);
  2169. break;
  2170. case MODE_PAGE_RETURN_ALL:
  2171. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2172. cdb10,
  2173. &nvme_trans_fill_all_pages,
  2174. MODE_PAGE_ALL_LEN);
  2175. break;
  2176. default:
  2177. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2178. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2179. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2180. break;
  2181. }
  2182. out:
  2183. return res;
  2184. }
  2185. static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2186. u8 *cmd)
  2187. {
  2188. int res = SNTI_TRANSLATION_SUCCESS;
  2189. int nvme_sc;
  2190. u32 alloc_len = READ_CAP_10_RESP_SIZE;
  2191. u32 resp_size = READ_CAP_10_RESP_SIZE;
  2192. u32 xfer_len;
  2193. u8 cdb16;
  2194. struct nvme_dev *dev = ns->dev;
  2195. dma_addr_t dma_addr;
  2196. void *mem;
  2197. struct nvme_id_ns *id_ns;
  2198. u8 *response;
  2199. cdb16 = IS_READ_CAP_16(cmd);
  2200. if (cdb16) {
  2201. alloc_len = GET_READ_CAP_16_ALLOC_LENGTH(cmd);
  2202. resp_size = READ_CAP_16_RESP_SIZE;
  2203. }
  2204. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  2205. &dma_addr, GFP_KERNEL);
  2206. if (mem == NULL) {
  2207. res = -ENOMEM;
  2208. goto out;
  2209. }
  2210. /* nvme ns identify */
  2211. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  2212. res = nvme_trans_status_code(hdr, nvme_sc);
  2213. if (res)
  2214. goto out_dma;
  2215. if (nvme_sc) {
  2216. res = nvme_sc;
  2217. goto out_dma;
  2218. }
  2219. id_ns = mem;
  2220. response = kmalloc(resp_size, GFP_KERNEL);
  2221. if (response == NULL) {
  2222. res = -ENOMEM;
  2223. goto out_dma;
  2224. }
  2225. memset(response, 0, resp_size);
  2226. nvme_trans_fill_read_cap(response, id_ns, cdb16);
  2227. xfer_len = min(alloc_len, resp_size);
  2228. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2229. kfree(response);
  2230. out_dma:
  2231. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  2232. dma_addr);
  2233. out:
  2234. return res;
  2235. }
  2236. static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2237. u8 *cmd)
  2238. {
  2239. int res = SNTI_TRANSLATION_SUCCESS;
  2240. int nvme_sc;
  2241. u32 alloc_len, xfer_len, resp_size;
  2242. u8 select_report;
  2243. u8 *response;
  2244. struct nvme_dev *dev = ns->dev;
  2245. dma_addr_t dma_addr;
  2246. void *mem;
  2247. struct nvme_id_ctrl *id_ctrl;
  2248. u32 ll_length, lun_id;
  2249. u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET;
  2250. __be32 tmp_len;
  2251. alloc_len = GET_REPORT_LUNS_ALLOC_LENGTH(cmd);
  2252. select_report = GET_U8_FROM_CDB(cmd, REPORT_LUNS_SR_OFFSET);
  2253. if ((select_report != ALL_LUNS_RETURNED) &&
  2254. (select_report != ALL_WELL_KNOWN_LUNS_RETURNED) &&
  2255. (select_report != RESTRICTED_LUNS_RETURNED)) {
  2256. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2257. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2258. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2259. goto out;
  2260. } else {
  2261. /* NVMe Controller Identify */
  2262. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  2263. sizeof(struct nvme_id_ctrl),
  2264. &dma_addr, GFP_KERNEL);
  2265. if (mem == NULL) {
  2266. res = -ENOMEM;
  2267. goto out;
  2268. }
  2269. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  2270. res = nvme_trans_status_code(hdr, nvme_sc);
  2271. if (res)
  2272. goto out_dma;
  2273. if (nvme_sc) {
  2274. res = nvme_sc;
  2275. goto out_dma;
  2276. }
  2277. id_ctrl = mem;
  2278. ll_length = le32_to_cpu(id_ctrl->nn) * LUN_ENTRY_SIZE;
  2279. resp_size = ll_length + LUN_DATA_HEADER_SIZE;
  2280. if (alloc_len < resp_size) {
  2281. res = nvme_trans_completion(hdr,
  2282. SAM_STAT_CHECK_CONDITION,
  2283. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2284. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2285. goto out_dma;
  2286. }
  2287. response = kmalloc(resp_size, GFP_KERNEL);
  2288. if (response == NULL) {
  2289. res = -ENOMEM;
  2290. goto out_dma;
  2291. }
  2292. memset(response, 0, resp_size);
  2293. /* The first LUN ID will always be 0 per the SAM spec */
  2294. for (lun_id = 0; lun_id < le32_to_cpu(id_ctrl->nn); lun_id++) {
  2295. /*
  2296. * Set the LUN Id and then increment to the next LUN
  2297. * location in the parameter data.
  2298. */
  2299. __be64 tmp_id = cpu_to_be64(lun_id);
  2300. memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64));
  2301. lun_id_offset += LUN_ENTRY_SIZE;
  2302. }
  2303. tmp_len = cpu_to_be32(ll_length);
  2304. memcpy(response, &tmp_len, sizeof(u32));
  2305. }
  2306. xfer_len = min(alloc_len, resp_size);
  2307. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2308. kfree(response);
  2309. out_dma:
  2310. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  2311. dma_addr);
  2312. out:
  2313. return res;
  2314. }
  2315. static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2316. u8 *cmd)
  2317. {
  2318. int res = SNTI_TRANSLATION_SUCCESS;
  2319. u8 alloc_len, xfer_len, resp_size;
  2320. u8 desc_format;
  2321. u8 *response;
  2322. alloc_len = GET_REQUEST_SENSE_ALLOC_LENGTH(cmd);
  2323. desc_format = GET_U8_FROM_CDB(cmd, REQUEST_SENSE_DESC_OFFSET);
  2324. desc_format &= REQUEST_SENSE_DESC_MASK;
  2325. resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) :
  2326. (FIXED_FMT_SENSE_DATA_SIZE));
  2327. response = kmalloc(resp_size, GFP_KERNEL);
  2328. if (response == NULL) {
  2329. res = -ENOMEM;
  2330. goto out;
  2331. }
  2332. memset(response, 0, resp_size);
  2333. if (desc_format == DESCRIPTOR_FORMAT_SENSE_DATA_TYPE) {
  2334. /* Descriptor Format Sense Data */
  2335. response[0] = DESC_FORMAT_SENSE_DATA;
  2336. response[1] = NO_SENSE;
  2337. /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */
  2338. response[2] = SCSI_ASC_NO_SENSE;
  2339. response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2340. /* SDAT_OVFL = 0 | Additional Sense Length = 0 */
  2341. } else {
  2342. /* Fixed Format Sense Data */
  2343. response[0] = FIXED_SENSE_DATA;
  2344. /* Byte 1 = Obsolete */
  2345. response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */
  2346. /* Bytes 3-6 - Information - set to zero */
  2347. response[7] = FIXED_SENSE_DATA_ADD_LENGTH;
  2348. /* Bytes 8-11 - Cmd Specific Information - set to zero */
  2349. response[12] = SCSI_ASC_NO_SENSE;
  2350. response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2351. /* Byte 14 = Field Replaceable Unit Code = 0 */
  2352. /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */
  2353. }
  2354. xfer_len = min(alloc_len, resp_size);
  2355. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2356. kfree(response);
  2357. out:
  2358. return res;
  2359. }
  2360. static int nvme_trans_security_protocol(struct nvme_ns *ns,
  2361. struct sg_io_hdr *hdr,
  2362. u8 *cmd)
  2363. {
  2364. return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2365. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2366. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2367. }
  2368. static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2369. u8 *cmd)
  2370. {
  2371. int res = SNTI_TRANSLATION_SUCCESS;
  2372. int nvme_sc;
  2373. struct nvme_queue *nvmeq;
  2374. struct nvme_command c;
  2375. u8 immed, pcmod, pc, no_flush, start;
  2376. immed = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_IMMED_OFFSET);
  2377. pcmod = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET);
  2378. pc = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_OFFSET);
  2379. no_flush = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_NO_FLUSH_OFFSET);
  2380. start = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_START_OFFSET);
  2381. immed &= START_STOP_UNIT_CDB_IMMED_MASK;
  2382. pcmod &= START_STOP_UNIT_CDB_POWER_COND_MOD_MASK;
  2383. pc = (pc & START_STOP_UNIT_CDB_POWER_COND_MASK) >> NIBBLE_SHIFT;
  2384. no_flush &= START_STOP_UNIT_CDB_NO_FLUSH_MASK;
  2385. start &= START_STOP_UNIT_CDB_START_MASK;
  2386. if (immed != 0) {
  2387. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2388. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2389. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2390. } else {
  2391. if (no_flush == 0) {
  2392. /* Issue NVME FLUSH command prior to START STOP UNIT */
  2393. memset(&c, 0, sizeof(c));
  2394. c.common.opcode = nvme_cmd_flush;
  2395. c.common.nsid = cpu_to_le32(ns->ns_id);
  2396. nvmeq = get_nvmeq(ns->dev);
  2397. put_nvmeq(nvmeq);
  2398. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2399. res = nvme_trans_status_code(hdr, nvme_sc);
  2400. if (res)
  2401. goto out;
  2402. if (nvme_sc) {
  2403. res = nvme_sc;
  2404. goto out;
  2405. }
  2406. }
  2407. /* Setup the expected power state transition */
  2408. res = nvme_trans_power_state(ns, hdr, pc, pcmod, start);
  2409. }
  2410. out:
  2411. return res;
  2412. }
  2413. static int nvme_trans_synchronize_cache(struct nvme_ns *ns,
  2414. struct sg_io_hdr *hdr, u8 *cmd)
  2415. {
  2416. int res = SNTI_TRANSLATION_SUCCESS;
  2417. int nvme_sc;
  2418. struct nvme_command c;
  2419. struct nvme_queue *nvmeq;
  2420. memset(&c, 0, sizeof(c));
  2421. c.common.opcode = nvme_cmd_flush;
  2422. c.common.nsid = cpu_to_le32(ns->ns_id);
  2423. nvmeq = get_nvmeq(ns->dev);
  2424. put_nvmeq(nvmeq);
  2425. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2426. res = nvme_trans_status_code(hdr, nvme_sc);
  2427. if (res)
  2428. goto out;
  2429. if (nvme_sc)
  2430. res = nvme_sc;
  2431. out:
  2432. return res;
  2433. }
  2434. static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2435. u8 *cmd)
  2436. {
  2437. int res = SNTI_TRANSLATION_SUCCESS;
  2438. u8 parm_hdr_len = 0;
  2439. u8 nvme_pf_code = 0;
  2440. u8 format_prot_info, long_list, format_data;
  2441. format_prot_info = GET_U8_FROM_CDB(cmd,
  2442. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET);
  2443. long_list = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_LONG_LIST_OFFSET);
  2444. format_data = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET);
  2445. format_prot_info = (format_prot_info &
  2446. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK) >>
  2447. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT;
  2448. long_list &= FORMAT_UNIT_CDB_LONG_LIST_MASK;
  2449. format_data &= FORMAT_UNIT_CDB_FORMAT_DATA_MASK;
  2450. if (format_data != 0) {
  2451. if (format_prot_info != 0) {
  2452. if (long_list == 0)
  2453. parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN;
  2454. else
  2455. parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN;
  2456. }
  2457. } else if (format_data == 0 && format_prot_info != 0) {
  2458. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2459. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2460. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2461. goto out;
  2462. }
  2463. /* Get parm header from data-in/out buffer */
  2464. /*
  2465. * According to the translation spec, the only fields in the parameter
  2466. * list we are concerned with are in the header. So allocate only that.
  2467. */
  2468. if (parm_hdr_len > 0) {
  2469. res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len,
  2470. format_prot_info, &nvme_pf_code);
  2471. if (res != SNTI_TRANSLATION_SUCCESS)
  2472. goto out;
  2473. }
  2474. /* Attempt to activate any previously downloaded firmware image */
  2475. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 0, 0, 0);
  2476. /* Determine Block size and count and send format command */
  2477. res = nvme_trans_fmt_set_blk_size_count(ns, hdr);
  2478. if (res != SNTI_TRANSLATION_SUCCESS)
  2479. goto out;
  2480. res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code);
  2481. out:
  2482. return res;
  2483. }
  2484. static int nvme_trans_test_unit_ready(struct nvme_ns *ns,
  2485. struct sg_io_hdr *hdr,
  2486. u8 *cmd)
  2487. {
  2488. int res = SNTI_TRANSLATION_SUCCESS;
  2489. struct nvme_dev *dev = ns->dev;
  2490. if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY))
  2491. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2492. NOT_READY, SCSI_ASC_LUN_NOT_READY,
  2493. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2494. else
  2495. res = nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0);
  2496. return res;
  2497. }
  2498. static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2499. u8 *cmd)
  2500. {
  2501. int res = SNTI_TRANSLATION_SUCCESS;
  2502. u32 buffer_offset, parm_list_length;
  2503. u8 buffer_id, mode;
  2504. parm_list_length =
  2505. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET);
  2506. if (parm_list_length % BYTES_TO_DWORDS != 0) {
  2507. /* NVMe expects Firmware file to be a whole number of DWORDS */
  2508. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2509. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2510. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2511. goto out;
  2512. }
  2513. buffer_id = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_ID_OFFSET);
  2514. if (buffer_id > NVME_MAX_FIRMWARE_SLOT) {
  2515. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2516. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2517. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2518. goto out;
  2519. }
  2520. mode = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_MODE_OFFSET) &
  2521. WRITE_BUFFER_CDB_MODE_MASK;
  2522. buffer_offset =
  2523. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET);
  2524. switch (mode) {
  2525. case DOWNLOAD_SAVE_ACTIVATE:
  2526. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2527. parm_list_length, buffer_offset,
  2528. buffer_id);
  2529. if (res != SNTI_TRANSLATION_SUCCESS)
  2530. goto out;
  2531. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2532. parm_list_length, buffer_offset,
  2533. buffer_id);
  2534. break;
  2535. case DOWNLOAD_SAVE_DEFER_ACTIVATE:
  2536. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2537. parm_list_length, buffer_offset,
  2538. buffer_id);
  2539. break;
  2540. case ACTIVATE_DEFERRED_MICROCODE:
  2541. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2542. parm_list_length, buffer_offset,
  2543. buffer_id);
  2544. break;
  2545. default:
  2546. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2547. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2548. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2549. break;
  2550. }
  2551. out:
  2552. return res;
  2553. }
  2554. struct scsi_unmap_blk_desc {
  2555. __be64 slba;
  2556. __be32 nlb;
  2557. u32 resv;
  2558. };
  2559. struct scsi_unmap_parm_list {
  2560. __be16 unmap_data_len;
  2561. __be16 unmap_blk_desc_data_len;
  2562. u32 resv;
  2563. struct scsi_unmap_blk_desc desc[0];
  2564. };
  2565. static int nvme_trans_unmap(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2566. u8 *cmd)
  2567. {
  2568. struct nvme_dev *dev = ns->dev;
  2569. struct scsi_unmap_parm_list *plist;
  2570. struct nvme_dsm_range *range;
  2571. struct nvme_queue *nvmeq;
  2572. struct nvme_command c;
  2573. int i, nvme_sc, res = -ENOMEM;
  2574. u16 ndesc, list_len;
  2575. dma_addr_t dma_addr;
  2576. list_len = GET_U16_FROM_CDB(cmd, UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET);
  2577. if (!list_len)
  2578. return -EINVAL;
  2579. plist = kmalloc(list_len, GFP_KERNEL);
  2580. if (!plist)
  2581. return -ENOMEM;
  2582. res = nvme_trans_copy_from_user(hdr, plist, list_len);
  2583. if (res != SNTI_TRANSLATION_SUCCESS)
  2584. goto out;
  2585. ndesc = be16_to_cpu(plist->unmap_blk_desc_data_len) >> 4;
  2586. if (!ndesc || ndesc > 256) {
  2587. res = -EINVAL;
  2588. goto out;
  2589. }
  2590. range = dma_alloc_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2591. &dma_addr, GFP_KERNEL);
  2592. if (!range)
  2593. goto out;
  2594. for (i = 0; i < ndesc; i++) {
  2595. range[i].nlb = cpu_to_le32(be32_to_cpu(plist->desc[i].nlb));
  2596. range[i].slba = cpu_to_le64(be64_to_cpu(plist->desc[i].slba));
  2597. range[i].cattr = 0;
  2598. }
  2599. memset(&c, 0, sizeof(c));
  2600. c.dsm.opcode = nvme_cmd_dsm;
  2601. c.dsm.nsid = cpu_to_le32(ns->ns_id);
  2602. c.dsm.prp1 = cpu_to_le64(dma_addr);
  2603. c.dsm.nr = cpu_to_le32(ndesc - 1);
  2604. c.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
  2605. nvmeq = get_nvmeq(dev);
  2606. put_nvmeq(nvmeq);
  2607. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2608. res = nvme_trans_status_code(hdr, nvme_sc);
  2609. dma_free_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2610. range, dma_addr);
  2611. out:
  2612. kfree(plist);
  2613. return res;
  2614. }
  2615. static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr)
  2616. {
  2617. u8 cmd[BLK_MAX_CDB];
  2618. int retcode;
  2619. unsigned int opcode;
  2620. if (hdr->cmdp == NULL)
  2621. return -EMSGSIZE;
  2622. if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len))
  2623. return -EFAULT;
  2624. opcode = cmd[0];
  2625. switch (opcode) {
  2626. case READ_6:
  2627. case READ_10:
  2628. case READ_12:
  2629. case READ_16:
  2630. retcode = nvme_trans_io(ns, hdr, 0, cmd);
  2631. break;
  2632. case WRITE_6:
  2633. case WRITE_10:
  2634. case WRITE_12:
  2635. case WRITE_16:
  2636. retcode = nvme_trans_io(ns, hdr, 1, cmd);
  2637. break;
  2638. case INQUIRY:
  2639. retcode = nvme_trans_inquiry(ns, hdr, cmd);
  2640. break;
  2641. case LOG_SENSE:
  2642. retcode = nvme_trans_log_sense(ns, hdr, cmd);
  2643. break;
  2644. case MODE_SELECT:
  2645. case MODE_SELECT_10:
  2646. retcode = nvme_trans_mode_select(ns, hdr, cmd);
  2647. break;
  2648. case MODE_SENSE:
  2649. case MODE_SENSE_10:
  2650. retcode = nvme_trans_mode_sense(ns, hdr, cmd);
  2651. break;
  2652. case READ_CAPACITY:
  2653. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2654. break;
  2655. case SERVICE_ACTION_IN:
  2656. if (IS_READ_CAP_16(cmd))
  2657. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2658. else
  2659. goto out;
  2660. break;
  2661. case REPORT_LUNS:
  2662. retcode = nvme_trans_report_luns(ns, hdr, cmd);
  2663. break;
  2664. case REQUEST_SENSE:
  2665. retcode = nvme_trans_request_sense(ns, hdr, cmd);
  2666. break;
  2667. case SECURITY_PROTOCOL_IN:
  2668. case SECURITY_PROTOCOL_OUT:
  2669. retcode = nvme_trans_security_protocol(ns, hdr, cmd);
  2670. break;
  2671. case START_STOP:
  2672. retcode = nvme_trans_start_stop(ns, hdr, cmd);
  2673. break;
  2674. case SYNCHRONIZE_CACHE:
  2675. retcode = nvme_trans_synchronize_cache(ns, hdr, cmd);
  2676. break;
  2677. case FORMAT_UNIT:
  2678. retcode = nvme_trans_format_unit(ns, hdr, cmd);
  2679. break;
  2680. case TEST_UNIT_READY:
  2681. retcode = nvme_trans_test_unit_ready(ns, hdr, cmd);
  2682. break;
  2683. case WRITE_BUFFER:
  2684. retcode = nvme_trans_write_buffer(ns, hdr, cmd);
  2685. break;
  2686. case UNMAP:
  2687. retcode = nvme_trans_unmap(ns, hdr, cmd);
  2688. break;
  2689. default:
  2690. out:
  2691. retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2692. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2693. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2694. break;
  2695. }
  2696. return retcode;
  2697. }
  2698. int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr)
  2699. {
  2700. struct sg_io_hdr hdr;
  2701. int retcode;
  2702. if (!capable(CAP_SYS_ADMIN))
  2703. return -EACCES;
  2704. if (copy_from_user(&hdr, u_hdr, sizeof(hdr)))
  2705. return -EFAULT;
  2706. if (hdr.interface_id != 'S')
  2707. return -EINVAL;
  2708. if (hdr.cmd_len > BLK_MAX_CDB)
  2709. return -EINVAL;
  2710. retcode = nvme_scsi_translate(ns, &hdr);
  2711. if (retcode < 0)
  2712. return retcode;
  2713. if (retcode > 0)
  2714. retcode = SNTI_TRANSLATION_SUCCESS;
  2715. if (copy_to_user(u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0)
  2716. return -EFAULT;
  2717. return retcode;
  2718. }
  2719. int nvme_sg_get_version_num(int __user *ip)
  2720. {
  2721. return put_user(sg_version_num, ip);
  2722. }