i915_drv.c 17 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. unsigned int i915_lvds_downclock = 0;
  43. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  44. static struct drm_driver driver;
  45. extern int intel_agp_enabled;
  46. #define INTEL_VGA_DEVICE(id, info) { \
  47. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  48. .class_mask = 0xffff00, \
  49. .vendor = 0x8086, \
  50. .device = id, \
  51. .subvendor = PCI_ANY_ID, \
  52. .subdevice = PCI_ANY_ID, \
  53. .driver_data = (unsigned long) info }
  54. static const struct intel_device_info intel_i830_info = {
  55. .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  56. };
  57. static const struct intel_device_info intel_845g_info = {
  58. .gen = 2, .is_i8xx = 1,
  59. };
  60. static const struct intel_device_info intel_i85x_info = {
  61. .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
  62. .cursor_needs_physical = 1,
  63. };
  64. static const struct intel_device_info intel_i865g_info = {
  65. .gen = 2, .is_i8xx = 1,
  66. };
  67. static const struct intel_device_info intel_i915g_info = {
  68. .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  69. };
  70. static const struct intel_device_info intel_i915gm_info = {
  71. .gen = 3, .is_i9xx = 1, .is_mobile = 1,
  72. .cursor_needs_physical = 1,
  73. };
  74. static const struct intel_device_info intel_i945g_info = {
  75. .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  76. };
  77. static const struct intel_device_info intel_i945gm_info = {
  78. .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
  79. .has_hotplug = 1, .cursor_needs_physical = 1,
  80. };
  81. static const struct intel_device_info intel_i965g_info = {
  82. .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
  83. .has_hotplug = 1,
  84. };
  85. static const struct intel_device_info intel_i965gm_info = {
  86. .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
  87. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
  88. };
  89. static const struct intel_device_info intel_g33_info = {
  90. .gen = 3, .is_g33 = 1, .is_i9xx = 1,
  91. .need_gfx_hws = 1, .has_hotplug = 1,
  92. };
  93. static const struct intel_device_info intel_g45_info = {
  94. .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  95. .has_pipe_cxsr = 1, .has_hotplug = 1,
  96. };
  97. static const struct intel_device_info intel_gm45_info = {
  98. .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
  99. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  100. .has_pipe_cxsr = 1, .has_hotplug = 1,
  101. };
  102. static const struct intel_device_info intel_pineview_info = {
  103. .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  104. .need_gfx_hws = 1, .has_hotplug = 1,
  105. };
  106. static const struct intel_device_info intel_ironlake_d_info = {
  107. .gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,
  108. .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
  109. };
  110. static const struct intel_device_info intel_ironlake_m_info = {
  111. .gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  112. .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
  113. };
  114. static const struct intel_device_info intel_sandybridge_d_info = {
  115. .gen = 6, .is_i965g = 1, .is_i9xx = 1,
  116. .need_gfx_hws = 1, .has_hotplug = 1,
  117. };
  118. static const struct intel_device_info intel_sandybridge_m_info = {
  119. .gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,
  120. .need_gfx_hws = 1, .has_hotplug = 1,
  121. };
  122. static const struct pci_device_id pciidlist[] = { /* aka */
  123. INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
  124. INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
  125. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
  126. INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
  127. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
  128. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
  129. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
  130. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
  131. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
  132. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
  133. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
  134. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
  135. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
  136. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
  137. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
  138. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
  139. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
  140. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
  141. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
  142. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
  143. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
  144. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
  145. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
  146. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
  147. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
  148. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
  149. INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
  150. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  151. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  152. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  153. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  154. INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  155. INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  156. INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  157. INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  158. INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  159. INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  160. INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  161. {0, 0, 0}
  162. };
  163. #if defined(CONFIG_DRM_I915_KMS)
  164. MODULE_DEVICE_TABLE(pci, pciidlist);
  165. #endif
  166. #define INTEL_PCH_DEVICE_ID_MASK 0xff00
  167. #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
  168. void intel_detect_pch (struct drm_device *dev)
  169. {
  170. struct drm_i915_private *dev_priv = dev->dev_private;
  171. struct pci_dev *pch;
  172. /*
  173. * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  174. * make graphics device passthrough work easy for VMM, that only
  175. * need to expose ISA bridge to let driver know the real hardware
  176. * underneath. This is a requirement from virtualization team.
  177. */
  178. pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  179. if (pch) {
  180. if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  181. int id;
  182. id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  183. if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  184. dev_priv->pch_type = PCH_CPT;
  185. DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  186. }
  187. }
  188. pci_dev_put(pch);
  189. }
  190. }
  191. static int i915_drm_freeze(struct drm_device *dev)
  192. {
  193. struct drm_i915_private *dev_priv = dev->dev_private;
  194. pci_save_state(dev->pdev);
  195. /* If KMS is active, we do the leavevt stuff here */
  196. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  197. int error = i915_gem_idle(dev);
  198. if (error) {
  199. dev_err(&dev->pdev->dev,
  200. "GEM idle failed, resume might fail\n");
  201. return error;
  202. }
  203. drm_irq_uninstall(dev);
  204. }
  205. i915_save_state(dev);
  206. intel_opregion_free(dev, 1);
  207. /* Modeset on resume, not lid events */
  208. dev_priv->modeset_on_lid = 0;
  209. return 0;
  210. }
  211. int i915_suspend(struct drm_device *dev, pm_message_t state)
  212. {
  213. int error;
  214. if (!dev || !dev->dev_private) {
  215. DRM_ERROR("dev: %p\n", dev);
  216. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  217. return -ENODEV;
  218. }
  219. if (state.event == PM_EVENT_PRETHAW)
  220. return 0;
  221. error = i915_drm_freeze(dev);
  222. if (error)
  223. return error;
  224. if (state.event == PM_EVENT_SUSPEND) {
  225. /* Shut down the device */
  226. pci_disable_device(dev->pdev);
  227. pci_set_power_state(dev->pdev, PCI_D3hot);
  228. }
  229. return 0;
  230. }
  231. static int i915_drm_thaw(struct drm_device *dev)
  232. {
  233. struct drm_i915_private *dev_priv = dev->dev_private;
  234. int error = 0;
  235. i915_restore_state(dev);
  236. intel_opregion_init(dev, 1);
  237. /* KMS EnterVT equivalent */
  238. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  239. mutex_lock(&dev->struct_mutex);
  240. dev_priv->mm.suspended = 0;
  241. error = i915_gem_init_ringbuffer(dev);
  242. mutex_unlock(&dev->struct_mutex);
  243. drm_irq_install(dev);
  244. /* Resume the modeset for every activated CRTC */
  245. drm_helper_resume_force_mode(dev);
  246. }
  247. dev_priv->modeset_on_lid = 0;
  248. return error;
  249. }
  250. int i915_resume(struct drm_device *dev)
  251. {
  252. if (pci_enable_device(dev->pdev))
  253. return -EIO;
  254. pci_set_master(dev->pdev);
  255. return i915_drm_thaw(dev);
  256. }
  257. /**
  258. * i965_reset - reset chip after a hang
  259. * @dev: drm device to reset
  260. * @flags: reset domains
  261. *
  262. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  263. * reset or otherwise an error code.
  264. *
  265. * Procedure is fairly simple:
  266. * - reset the chip using the reset reg
  267. * - re-init context state
  268. * - re-init hardware status page
  269. * - re-init ring buffer
  270. * - re-init interrupt state
  271. * - re-init display
  272. */
  273. int i965_reset(struct drm_device *dev, u8 flags)
  274. {
  275. drm_i915_private_t *dev_priv = dev->dev_private;
  276. unsigned long timeout;
  277. u8 gdrst;
  278. /*
  279. * We really should only reset the display subsystem if we actually
  280. * need to
  281. */
  282. bool need_display = true;
  283. mutex_lock(&dev->struct_mutex);
  284. /*
  285. * Clear request list
  286. */
  287. i915_gem_retire_requests(dev);
  288. if (need_display)
  289. i915_save_display(dev);
  290. if (IS_I965G(dev) || IS_G4X(dev)) {
  291. /*
  292. * Set the domains we want to reset, then the reset bit (bit 0).
  293. * Clear the reset bit after a while and wait for hardware status
  294. * bit (bit 1) to be set
  295. */
  296. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  297. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  298. udelay(50);
  299. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  300. /* ...we don't want to loop forever though, 500ms should be plenty */
  301. timeout = jiffies + msecs_to_jiffies(500);
  302. do {
  303. udelay(100);
  304. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  305. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  306. if (gdrst & 0x1) {
  307. WARN(true, "i915: Failed to reset chip\n");
  308. mutex_unlock(&dev->struct_mutex);
  309. return -EIO;
  310. }
  311. } else {
  312. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  313. mutex_unlock(&dev->struct_mutex);
  314. return -ENODEV;
  315. }
  316. /* Ok, now get things going again... */
  317. /*
  318. * Everything depends on having the GTT running, so we need to start
  319. * there. Fortunately we don't need to do this unless we reset the
  320. * chip at a PCI level.
  321. *
  322. * Next we need to restore the context, but we don't use those
  323. * yet either...
  324. *
  325. * Ring buffer needs to be re-initialized in the KMS case, or if X
  326. * was running at the time of the reset (i.e. we weren't VT
  327. * switched away).
  328. */
  329. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  330. !dev_priv->mm.suspended) {
  331. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  332. dev_priv->mm.suspended = 0;
  333. ring->init(dev, ring);
  334. mutex_unlock(&dev->struct_mutex);
  335. drm_irq_uninstall(dev);
  336. drm_irq_install(dev);
  337. mutex_lock(&dev->struct_mutex);
  338. }
  339. /*
  340. * Display needs restore too...
  341. */
  342. if (need_display)
  343. i915_restore_display(dev);
  344. mutex_unlock(&dev->struct_mutex);
  345. return 0;
  346. }
  347. static int __devinit
  348. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  349. {
  350. return drm_get_pci_dev(pdev, ent, &driver);
  351. }
  352. static void
  353. i915_pci_remove(struct pci_dev *pdev)
  354. {
  355. struct drm_device *dev = pci_get_drvdata(pdev);
  356. drm_put_dev(dev);
  357. }
  358. static int i915_pm_suspend(struct device *dev)
  359. {
  360. struct pci_dev *pdev = to_pci_dev(dev);
  361. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  362. int error;
  363. if (!drm_dev || !drm_dev->dev_private) {
  364. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  365. return -ENODEV;
  366. }
  367. error = i915_drm_freeze(drm_dev);
  368. if (error)
  369. return error;
  370. pci_disable_device(pdev);
  371. pci_set_power_state(pdev, PCI_D3hot);
  372. return 0;
  373. }
  374. static int i915_pm_resume(struct device *dev)
  375. {
  376. struct pci_dev *pdev = to_pci_dev(dev);
  377. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  378. return i915_resume(drm_dev);
  379. }
  380. static int i915_pm_freeze(struct device *dev)
  381. {
  382. struct pci_dev *pdev = to_pci_dev(dev);
  383. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  384. if (!drm_dev || !drm_dev->dev_private) {
  385. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  386. return -ENODEV;
  387. }
  388. return i915_drm_freeze(drm_dev);
  389. }
  390. static int i915_pm_thaw(struct device *dev)
  391. {
  392. struct pci_dev *pdev = to_pci_dev(dev);
  393. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  394. return i915_drm_thaw(drm_dev);
  395. }
  396. static int i915_pm_poweroff(struct device *dev)
  397. {
  398. struct pci_dev *pdev = to_pci_dev(dev);
  399. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  400. return i915_drm_freeze(drm_dev);
  401. }
  402. static const struct dev_pm_ops i915_pm_ops = {
  403. .suspend = i915_pm_suspend,
  404. .resume = i915_pm_resume,
  405. .freeze = i915_pm_freeze,
  406. .thaw = i915_pm_thaw,
  407. .poweroff = i915_pm_poweroff,
  408. .restore = i915_pm_resume,
  409. };
  410. static struct vm_operations_struct i915_gem_vm_ops = {
  411. .fault = i915_gem_fault,
  412. .open = drm_gem_vm_open,
  413. .close = drm_gem_vm_close,
  414. };
  415. static struct drm_driver driver = {
  416. /* don't use mtrr's here, the Xserver or user space app should
  417. * deal with them for intel hardware.
  418. */
  419. .driver_features =
  420. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  421. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  422. .load = i915_driver_load,
  423. .unload = i915_driver_unload,
  424. .open = i915_driver_open,
  425. .lastclose = i915_driver_lastclose,
  426. .preclose = i915_driver_preclose,
  427. .postclose = i915_driver_postclose,
  428. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  429. .suspend = i915_suspend,
  430. .resume = i915_resume,
  431. .device_is_agp = i915_driver_device_is_agp,
  432. .enable_vblank = i915_enable_vblank,
  433. .disable_vblank = i915_disable_vblank,
  434. .irq_preinstall = i915_driver_irq_preinstall,
  435. .irq_postinstall = i915_driver_irq_postinstall,
  436. .irq_uninstall = i915_driver_irq_uninstall,
  437. .irq_handler = i915_driver_irq_handler,
  438. .reclaim_buffers = drm_core_reclaim_buffers,
  439. .get_map_ofs = drm_core_get_map_ofs,
  440. .get_reg_ofs = drm_core_get_reg_ofs,
  441. .master_create = i915_master_create,
  442. .master_destroy = i915_master_destroy,
  443. #if defined(CONFIG_DEBUG_FS)
  444. .debugfs_init = i915_debugfs_init,
  445. .debugfs_cleanup = i915_debugfs_cleanup,
  446. #endif
  447. .gem_init_object = i915_gem_init_object,
  448. .gem_free_object = i915_gem_free_object,
  449. .gem_vm_ops = &i915_gem_vm_ops,
  450. .ioctls = i915_ioctls,
  451. .fops = {
  452. .owner = THIS_MODULE,
  453. .open = drm_open,
  454. .release = drm_release,
  455. .unlocked_ioctl = drm_ioctl,
  456. .mmap = drm_gem_mmap,
  457. .poll = drm_poll,
  458. .fasync = drm_fasync,
  459. .read = drm_read,
  460. #ifdef CONFIG_COMPAT
  461. .compat_ioctl = i915_compat_ioctl,
  462. #endif
  463. .llseek = noop_llseek,
  464. },
  465. .pci_driver = {
  466. .name = DRIVER_NAME,
  467. .id_table = pciidlist,
  468. .probe = i915_pci_probe,
  469. .remove = i915_pci_remove,
  470. .driver.pm = &i915_pm_ops,
  471. },
  472. .name = DRIVER_NAME,
  473. .desc = DRIVER_DESC,
  474. .date = DRIVER_DATE,
  475. .major = DRIVER_MAJOR,
  476. .minor = DRIVER_MINOR,
  477. .patchlevel = DRIVER_PATCHLEVEL,
  478. };
  479. static int __init i915_init(void)
  480. {
  481. if (!intel_agp_enabled) {
  482. DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  483. return -ENODEV;
  484. }
  485. driver.num_ioctls = i915_max_ioctl;
  486. i915_gem_shrinker_init();
  487. /*
  488. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  489. * explicitly disabled with the module pararmeter.
  490. *
  491. * Otherwise, just follow the parameter (defaulting to off).
  492. *
  493. * Allow optional vga_text_mode_force boot option to override
  494. * the default behavior.
  495. */
  496. #if defined(CONFIG_DRM_I915_KMS)
  497. if (i915_modeset != 0)
  498. driver.driver_features |= DRIVER_MODESET;
  499. #endif
  500. if (i915_modeset == 1)
  501. driver.driver_features |= DRIVER_MODESET;
  502. #ifdef CONFIG_VGA_CONSOLE
  503. if (vgacon_text_force() && i915_modeset == -1)
  504. driver.driver_features &= ~DRIVER_MODESET;
  505. #endif
  506. if (!(driver.driver_features & DRIVER_MODESET)) {
  507. driver.suspend = i915_suspend;
  508. driver.resume = i915_resume;
  509. }
  510. return drm_init(&driver);
  511. }
  512. static void __exit i915_exit(void)
  513. {
  514. i915_gem_shrinker_exit();
  515. drm_exit(&driver);
  516. }
  517. module_init(i915_init);
  518. module_exit(i915_exit);
  519. MODULE_AUTHOR(DRIVER_AUTHOR);
  520. MODULE_DESCRIPTION(DRIVER_DESC);
  521. MODULE_LICENSE("GPL and additional rights");