tsi108_eth.c 47 KB

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  1. /*******************************************************************************
  2. Copyright(c) 2006 Tundra Semiconductor Corporation.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. *******************************************************************************/
  15. /* This driver is based on the driver code originally developed
  16. * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by
  17. * scott.wood@timesys.com * Copyright (C) 2003 TimeSys Corporation
  18. *
  19. * Currently changes from original version are:
  20. * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com)
  21. * - modifications to handle two ports independently and support for
  22. * additional PHY devices (alexandre.bounine@tundra.com)
  23. * - Get hardware information from platform device. (tie-fei.zang@freescale.com)
  24. *
  25. */
  26. #include <linux/module.h>
  27. #include <linux/types.h>
  28. #include <linux/init.h>
  29. #include <linux/net.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/slab.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/delay.h>
  37. #include <linux/crc32.h>
  38. #include <linux/mii.h>
  39. #include <linux/device.h>
  40. #include <linux/pci.h>
  41. #include <linux/rtnetlink.h>
  42. #include <linux/timer.h>
  43. #include <linux/platform_device.h>
  44. #include <asm/system.h>
  45. #include <asm/io.h>
  46. #include <asm/tsi108.h>
  47. #include "tsi108_eth.h"
  48. #define MII_READ_DELAY 10000 /* max link wait time in msec */
  49. #define TSI108_RXRING_LEN 256
  50. /* NOTE: The driver currently does not support receiving packets
  51. * larger than the buffer size, so don't decrease this (unless you
  52. * want to add such support).
  53. */
  54. #define TSI108_RXBUF_SIZE 1536
  55. #define TSI108_TXRING_LEN 256
  56. #define TSI108_TX_INT_FREQ 64
  57. /* Check the phy status every half a second. */
  58. #define CHECK_PHY_INTERVAL (HZ/2)
  59. static int tsi108_init_one(struct platform_device *pdev);
  60. static int tsi108_ether_remove(struct platform_device *pdev);
  61. struct tsi108_prv_data {
  62. void __iomem *regs; /* Base of normal regs */
  63. void __iomem *phyregs; /* Base of register bank used for PHY access */
  64. struct net_device *dev;
  65. struct napi_struct napi;
  66. unsigned int phy; /* Index of PHY for this interface */
  67. unsigned int irq_num;
  68. unsigned int id;
  69. unsigned int phy_type;
  70. struct timer_list timer;/* Timer that triggers the check phy function */
  71. unsigned int rxtail; /* Next entry in rxring to read */
  72. unsigned int rxhead; /* Next entry in rxring to give a new buffer */
  73. unsigned int rxfree; /* Number of free, allocated RX buffers */
  74. unsigned int rxpending; /* Non-zero if there are still descriptors
  75. * to be processed from a previous descriptor
  76. * interrupt condition that has been cleared */
  77. unsigned int txtail; /* Next TX descriptor to check status on */
  78. unsigned int txhead; /* Next TX descriptor to use */
  79. /* Number of free TX descriptors. This could be calculated from
  80. * rxhead and rxtail if one descriptor were left unused to disambiguate
  81. * full and empty conditions, but it's simpler to just keep track
  82. * explicitly. */
  83. unsigned int txfree;
  84. unsigned int phy_ok; /* The PHY is currently powered on. */
  85. /* PHY status (duplex is 1 for half, 2 for full,
  86. * so that the default 0 indicates that neither has
  87. * yet been configured). */
  88. unsigned int link_up;
  89. unsigned int speed;
  90. unsigned int duplex;
  91. tx_desc *txring;
  92. rx_desc *rxring;
  93. struct sk_buff *txskbs[TSI108_TXRING_LEN];
  94. struct sk_buff *rxskbs[TSI108_RXRING_LEN];
  95. dma_addr_t txdma, rxdma;
  96. /* txlock nests in misclock and phy_lock */
  97. spinlock_t txlock, misclock;
  98. /* stats is used to hold the upper bits of each hardware counter,
  99. * and tmpstats is used to hold the full values for returning
  100. * to the caller of get_stats(). They must be separate in case
  101. * an overflow interrupt occurs before the stats are consumed.
  102. */
  103. struct net_device_stats stats;
  104. struct net_device_stats tmpstats;
  105. /* These stats are kept separate in hardware, thus require individual
  106. * fields for handling carry. They are combined in get_stats.
  107. */
  108. unsigned long rx_fcs; /* Add to rx_frame_errors */
  109. unsigned long rx_short_fcs; /* Add to rx_frame_errors */
  110. unsigned long rx_long_fcs; /* Add to rx_frame_errors */
  111. unsigned long rx_underruns; /* Add to rx_length_errors */
  112. unsigned long rx_overruns; /* Add to rx_length_errors */
  113. unsigned long tx_coll_abort; /* Add to tx_aborted_errors/collisions */
  114. unsigned long tx_pause_drop; /* Add to tx_aborted_errors */
  115. unsigned long mc_hash[16];
  116. u32 msg_enable; /* debug message level */
  117. struct mii_if_info mii_if;
  118. unsigned int init_media;
  119. };
  120. /* Structure for a device driver */
  121. static struct platform_driver tsi_eth_driver = {
  122. .probe = tsi108_init_one,
  123. .remove = tsi108_ether_remove,
  124. .driver = {
  125. .name = "tsi-ethernet",
  126. },
  127. };
  128. static void tsi108_timed_checker(unsigned long dev_ptr);
  129. static void dump_eth_one(struct net_device *dev)
  130. {
  131. struct tsi108_prv_data *data = netdev_priv(dev);
  132. printk("Dumping %s...\n", dev->name);
  133. printk("intstat %x intmask %x phy_ok %d"
  134. " link %d speed %d duplex %d\n",
  135. TSI_READ(TSI108_EC_INTSTAT),
  136. TSI_READ(TSI108_EC_INTMASK), data->phy_ok,
  137. data->link_up, data->speed, data->duplex);
  138. printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n",
  139. data->txhead, data->txtail, data->txfree,
  140. TSI_READ(TSI108_EC_TXSTAT),
  141. TSI_READ(TSI108_EC_TXESTAT),
  142. TSI_READ(TSI108_EC_TXERR));
  143. printk("RX: head %d, tail %d, free %d, stat %x,"
  144. " estat %x, err %x, pending %d\n\n",
  145. data->rxhead, data->rxtail, data->rxfree,
  146. TSI_READ(TSI108_EC_RXSTAT),
  147. TSI_READ(TSI108_EC_RXESTAT),
  148. TSI_READ(TSI108_EC_RXERR), data->rxpending);
  149. }
  150. /* Synchronization is needed between the thread and up/down events.
  151. * Note that the PHY is accessed through the same registers for both
  152. * interfaces, so this can't be made interface-specific.
  153. */
  154. static DEFINE_SPINLOCK(phy_lock);
  155. static int tsi108_read_mii(struct tsi108_prv_data *data, int reg)
  156. {
  157. unsigned i;
  158. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  159. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  160. (reg << TSI108_MAC_MII_ADDR_REG));
  161. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0);
  162. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ);
  163. for (i = 0; i < 100; i++) {
  164. if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  165. (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY)))
  166. break;
  167. udelay(10);
  168. }
  169. if (i == 100)
  170. return 0xffff;
  171. else
  172. return (TSI_READ_PHY(TSI108_MAC_MII_DATAIN));
  173. }
  174. static void tsi108_write_mii(struct tsi108_prv_data *data,
  175. int reg, u16 val)
  176. {
  177. unsigned i = 100;
  178. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  179. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  180. (reg << TSI108_MAC_MII_ADDR_REG));
  181. TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val);
  182. while (i--) {
  183. if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  184. TSI108_MAC_MII_IND_BUSY))
  185. break;
  186. udelay(10);
  187. }
  188. }
  189. static int tsi108_mdio_read(struct net_device *dev, int addr, int reg)
  190. {
  191. struct tsi108_prv_data *data = netdev_priv(dev);
  192. return tsi108_read_mii(data, reg);
  193. }
  194. static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val)
  195. {
  196. struct tsi108_prv_data *data = netdev_priv(dev);
  197. tsi108_write_mii(data, reg, val);
  198. }
  199. static inline void tsi108_write_tbi(struct tsi108_prv_data *data,
  200. int reg, u16 val)
  201. {
  202. unsigned i = 1000;
  203. TSI_WRITE(TSI108_MAC_MII_ADDR,
  204. (0x1e << TSI108_MAC_MII_ADDR_PHY)
  205. | (reg << TSI108_MAC_MII_ADDR_REG));
  206. TSI_WRITE(TSI108_MAC_MII_DATAOUT, val);
  207. while(i--) {
  208. if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY))
  209. return;
  210. udelay(10);
  211. }
  212. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  213. }
  214. static int mii_speed(struct mii_if_info *mii)
  215. {
  216. int advert, lpa, val, media;
  217. int lpa2 = 0;
  218. int speed;
  219. if (!mii_link_ok(mii))
  220. return 0;
  221. val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
  222. if ((val & BMSR_ANEGCOMPLETE) == 0)
  223. return 0;
  224. advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
  225. lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
  226. media = mii_nway_result(advert & lpa);
  227. if (mii->supports_gmii)
  228. lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
  229. speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 :
  230. (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10);
  231. return speed;
  232. }
  233. static void tsi108_check_phy(struct net_device *dev)
  234. {
  235. struct tsi108_prv_data *data = netdev_priv(dev);
  236. u32 mac_cfg2_reg, portctrl_reg;
  237. u32 duplex;
  238. u32 speed;
  239. unsigned long flags;
  240. spin_lock_irqsave(&phy_lock, flags);
  241. if (!data->phy_ok)
  242. goto out;
  243. duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media);
  244. data->init_media = 0;
  245. if (netif_carrier_ok(dev)) {
  246. speed = mii_speed(&data->mii_if);
  247. if ((speed != data->speed) || duplex) {
  248. mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2);
  249. portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL);
  250. mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK;
  251. if (speed == 1000) {
  252. mac_cfg2_reg |= TSI108_MAC_CFG2_GIG;
  253. portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG;
  254. } else {
  255. mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG;
  256. portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG;
  257. }
  258. data->speed = speed;
  259. if (data->mii_if.full_duplex) {
  260. mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX;
  261. portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX;
  262. data->duplex = 2;
  263. } else {
  264. mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX;
  265. portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX;
  266. data->duplex = 1;
  267. }
  268. TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
  269. TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
  270. }
  271. if (data->link_up == 0) {
  272. /* The manual says it can take 3-4 usecs for the speed change
  273. * to take effect.
  274. */
  275. udelay(5);
  276. spin_lock(&data->txlock);
  277. if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
  278. netif_wake_queue(dev);
  279. data->link_up = 1;
  280. spin_unlock(&data->txlock);
  281. }
  282. } else {
  283. if (data->link_up == 1) {
  284. netif_stop_queue(dev);
  285. data->link_up = 0;
  286. printk(KERN_NOTICE "%s : link is down\n", dev->name);
  287. }
  288. goto out;
  289. }
  290. out:
  291. spin_unlock_irqrestore(&phy_lock, flags);
  292. }
  293. static inline void
  294. tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift,
  295. unsigned long *upper)
  296. {
  297. if (carry & carry_bit)
  298. *upper += carry_shift;
  299. }
  300. static void tsi108_stat_carry(struct net_device *dev)
  301. {
  302. struct tsi108_prv_data *data = netdev_priv(dev);
  303. u32 carry1, carry2;
  304. spin_lock_irq(&data->misclock);
  305. carry1 = TSI_READ(TSI108_STAT_CARRY1);
  306. carry2 = TSI_READ(TSI108_STAT_CARRY2);
  307. TSI_WRITE(TSI108_STAT_CARRY1, carry1);
  308. TSI_WRITE(TSI108_STAT_CARRY2, carry2);
  309. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES,
  310. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  311. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS,
  312. TSI108_STAT_RXPKTS_CARRY,
  313. &data->stats.rx_packets);
  314. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS,
  315. TSI108_STAT_RXFCS_CARRY, &data->rx_fcs);
  316. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST,
  317. TSI108_STAT_RXMCAST_CARRY,
  318. &data->stats.multicast);
  319. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN,
  320. TSI108_STAT_RXALIGN_CARRY,
  321. &data->stats.rx_frame_errors);
  322. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH,
  323. TSI108_STAT_RXLENGTH_CARRY,
  324. &data->stats.rx_length_errors);
  325. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT,
  326. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  327. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO,
  328. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  329. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG,
  330. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  331. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER,
  332. TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs);
  333. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP,
  334. TSI108_STAT_RXDROP_CARRY,
  335. &data->stats.rx_missed_errors);
  336. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES,
  337. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  338. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS,
  339. TSI108_STAT_TXPKTS_CARRY,
  340. &data->stats.tx_packets);
  341. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF,
  342. TSI108_STAT_TXEXDEF_CARRY,
  343. &data->stats.tx_aborted_errors);
  344. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL,
  345. TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort);
  346. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL,
  347. TSI108_STAT_TXTCOL_CARRY,
  348. &data->stats.collisions);
  349. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE,
  350. TSI108_STAT_TXPAUSEDROP_CARRY,
  351. &data->tx_pause_drop);
  352. spin_unlock_irq(&data->misclock);
  353. }
  354. /* Read a stat counter atomically with respect to carries.
  355. * data->misclock must be held.
  356. */
  357. static inline unsigned long
  358. tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit,
  359. int carry_shift, unsigned long *upper)
  360. {
  361. int carryreg;
  362. unsigned long val;
  363. if (reg < 0xb0)
  364. carryreg = TSI108_STAT_CARRY1;
  365. else
  366. carryreg = TSI108_STAT_CARRY2;
  367. again:
  368. val = TSI_READ(reg) | *upper;
  369. /* Check to see if it overflowed, but the interrupt hasn't
  370. * been serviced yet. If so, handle the carry here, and
  371. * try again.
  372. */
  373. if (unlikely(TSI_READ(carryreg) & carry_bit)) {
  374. *upper += carry_shift;
  375. TSI_WRITE(carryreg, carry_bit);
  376. goto again;
  377. }
  378. return val;
  379. }
  380. static struct net_device_stats *tsi108_get_stats(struct net_device *dev)
  381. {
  382. unsigned long excol;
  383. struct tsi108_prv_data *data = netdev_priv(dev);
  384. spin_lock_irq(&data->misclock);
  385. data->tmpstats.rx_packets =
  386. tsi108_read_stat(data, TSI108_STAT_RXPKTS,
  387. TSI108_STAT_CARRY1_RXPKTS,
  388. TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets);
  389. data->tmpstats.tx_packets =
  390. tsi108_read_stat(data, TSI108_STAT_TXPKTS,
  391. TSI108_STAT_CARRY2_TXPKTS,
  392. TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets);
  393. data->tmpstats.rx_bytes =
  394. tsi108_read_stat(data, TSI108_STAT_RXBYTES,
  395. TSI108_STAT_CARRY1_RXBYTES,
  396. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  397. data->tmpstats.tx_bytes =
  398. tsi108_read_stat(data, TSI108_STAT_TXBYTES,
  399. TSI108_STAT_CARRY2_TXBYTES,
  400. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  401. data->tmpstats.multicast =
  402. tsi108_read_stat(data, TSI108_STAT_RXMCAST,
  403. TSI108_STAT_CARRY1_RXMCAST,
  404. TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast);
  405. excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL,
  406. TSI108_STAT_CARRY2_TXEXCOL,
  407. TSI108_STAT_TXEXCOL_CARRY,
  408. &data->tx_coll_abort);
  409. data->tmpstats.collisions =
  410. tsi108_read_stat(data, TSI108_STAT_TXTCOL,
  411. TSI108_STAT_CARRY2_TXTCOL,
  412. TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions);
  413. data->tmpstats.collisions += excol;
  414. data->tmpstats.rx_length_errors =
  415. tsi108_read_stat(data, TSI108_STAT_RXLENGTH,
  416. TSI108_STAT_CARRY1_RXLENGTH,
  417. TSI108_STAT_RXLENGTH_CARRY,
  418. &data->stats.rx_length_errors);
  419. data->tmpstats.rx_length_errors +=
  420. tsi108_read_stat(data, TSI108_STAT_RXRUNT,
  421. TSI108_STAT_CARRY1_RXRUNT,
  422. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  423. data->tmpstats.rx_length_errors +=
  424. tsi108_read_stat(data, TSI108_STAT_RXJUMBO,
  425. TSI108_STAT_CARRY1_RXJUMBO,
  426. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  427. data->tmpstats.rx_frame_errors =
  428. tsi108_read_stat(data, TSI108_STAT_RXALIGN,
  429. TSI108_STAT_CARRY1_RXALIGN,
  430. TSI108_STAT_RXALIGN_CARRY,
  431. &data->stats.rx_frame_errors);
  432. data->tmpstats.rx_frame_errors +=
  433. tsi108_read_stat(data, TSI108_STAT_RXFCS,
  434. TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY,
  435. &data->rx_fcs);
  436. data->tmpstats.rx_frame_errors +=
  437. tsi108_read_stat(data, TSI108_STAT_RXFRAG,
  438. TSI108_STAT_CARRY1_RXFRAG,
  439. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  440. data->tmpstats.rx_missed_errors =
  441. tsi108_read_stat(data, TSI108_STAT_RXDROP,
  442. TSI108_STAT_CARRY1_RXDROP,
  443. TSI108_STAT_RXDROP_CARRY,
  444. &data->stats.rx_missed_errors);
  445. /* These three are maintained by software. */
  446. data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors;
  447. data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors;
  448. data->tmpstats.tx_aborted_errors =
  449. tsi108_read_stat(data, TSI108_STAT_TXEXDEF,
  450. TSI108_STAT_CARRY2_TXEXDEF,
  451. TSI108_STAT_TXEXDEF_CARRY,
  452. &data->stats.tx_aborted_errors);
  453. data->tmpstats.tx_aborted_errors +=
  454. tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP,
  455. TSI108_STAT_CARRY2_TXPAUSE,
  456. TSI108_STAT_TXPAUSEDROP_CARRY,
  457. &data->tx_pause_drop);
  458. data->tmpstats.tx_aborted_errors += excol;
  459. data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors;
  460. data->tmpstats.rx_errors = data->tmpstats.rx_length_errors +
  461. data->tmpstats.rx_crc_errors +
  462. data->tmpstats.rx_frame_errors +
  463. data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors;
  464. spin_unlock_irq(&data->misclock);
  465. return &data->tmpstats;
  466. }
  467. static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev)
  468. {
  469. TSI_WRITE(TSI108_EC_RXQ_PTRHIGH,
  470. TSI108_EC_RXQ_PTRHIGH_VALID);
  471. TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO
  472. | TSI108_EC_RXCTRL_QUEUE0);
  473. }
  474. static void tsi108_restart_tx(struct tsi108_prv_data * data)
  475. {
  476. TSI_WRITE(TSI108_EC_TXQ_PTRHIGH,
  477. TSI108_EC_TXQ_PTRHIGH_VALID);
  478. TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT |
  479. TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0);
  480. }
  481. /* txlock must be held by caller, with IRQs disabled, and
  482. * with permission to re-enable them when the lock is dropped.
  483. */
  484. static void tsi108_complete_tx(struct net_device *dev)
  485. {
  486. struct tsi108_prv_data *data = netdev_priv(dev);
  487. int tx;
  488. struct sk_buff *skb;
  489. int release = 0;
  490. while (!data->txfree || data->txhead != data->txtail) {
  491. tx = data->txtail;
  492. if (data->txring[tx].misc & TSI108_TX_OWN)
  493. break;
  494. skb = data->txskbs[tx];
  495. if (!(data->txring[tx].misc & TSI108_TX_OK))
  496. printk("%s: bad tx packet, misc %x\n",
  497. dev->name, data->txring[tx].misc);
  498. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  499. data->txfree++;
  500. if (data->txring[tx].misc & TSI108_TX_EOF) {
  501. dev_kfree_skb_any(skb);
  502. release++;
  503. }
  504. }
  505. if (release) {
  506. if (is_valid_ether_addr(dev->dev_addr) && data->link_up)
  507. netif_wake_queue(dev);
  508. }
  509. }
  510. static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
  511. {
  512. struct tsi108_prv_data *data = netdev_priv(dev);
  513. int frags = skb_shinfo(skb)->nr_frags + 1;
  514. int i;
  515. if (!data->phy_ok && net_ratelimit())
  516. printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name);
  517. if (!data->link_up) {
  518. printk(KERN_ERR "%s: Transmit while link is down!\n",
  519. dev->name);
  520. netif_stop_queue(dev);
  521. return NETDEV_TX_BUSY;
  522. }
  523. if (data->txfree < MAX_SKB_FRAGS + 1) {
  524. netif_stop_queue(dev);
  525. if (net_ratelimit())
  526. printk(KERN_ERR "%s: Transmit with full tx ring!\n",
  527. dev->name);
  528. return NETDEV_TX_BUSY;
  529. }
  530. if (data->txfree - frags < MAX_SKB_FRAGS + 1) {
  531. netif_stop_queue(dev);
  532. }
  533. spin_lock_irq(&data->txlock);
  534. for (i = 0; i < frags; i++) {
  535. int misc = 0;
  536. int tx = data->txhead;
  537. /* This is done to mark every TSI108_TX_INT_FREQ tx buffers with
  538. * the interrupt bit. TX descriptor-complete interrupts are
  539. * enabled when the queue fills up, and masked when there is
  540. * still free space. This way, when saturating the outbound
  541. * link, the tx interrupts are kept to a reasonable level.
  542. * When the queue is not full, reclamation of skbs still occurs
  543. * as new packets are transmitted, or on a queue-empty
  544. * interrupt.
  545. */
  546. if ((tx % TSI108_TX_INT_FREQ == 0) &&
  547. ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ))
  548. misc = TSI108_TX_INT;
  549. data->txskbs[tx] = skb;
  550. if (i == 0) {
  551. data->txring[tx].buf0 = dma_map_single(NULL, skb->data,
  552. skb->len - skb->data_len, DMA_TO_DEVICE);
  553. data->txring[tx].len = skb->len - skb->data_len;
  554. misc |= TSI108_TX_SOF;
  555. } else {
  556. skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  557. data->txring[tx].buf0 =
  558. dma_map_page(NULL, frag->page, frag->page_offset,
  559. frag->size, DMA_TO_DEVICE);
  560. data->txring[tx].len = frag->size;
  561. }
  562. if (i == frags - 1)
  563. misc |= TSI108_TX_EOF;
  564. if (netif_msg_pktdata(data)) {
  565. int i;
  566. printk("%s: Tx Frame contents (%d)\n", dev->name,
  567. skb->len);
  568. for (i = 0; i < skb->len; i++)
  569. printk(" %2.2x", skb->data[i]);
  570. printk(".\n");
  571. }
  572. data->txring[tx].misc = misc | TSI108_TX_OWN;
  573. data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN;
  574. data->txfree--;
  575. }
  576. tsi108_complete_tx(dev);
  577. /* This must be done after the check for completed tx descriptors,
  578. * so that the tail pointer is correct.
  579. */
  580. if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0))
  581. tsi108_restart_tx(data);
  582. spin_unlock_irq(&data->txlock);
  583. return NETDEV_TX_OK;
  584. }
  585. static int tsi108_complete_rx(struct net_device *dev, int budget)
  586. {
  587. struct tsi108_prv_data *data = netdev_priv(dev);
  588. int done = 0;
  589. while (data->rxfree && done != budget) {
  590. int rx = data->rxtail;
  591. struct sk_buff *skb;
  592. if (data->rxring[rx].misc & TSI108_RX_OWN)
  593. break;
  594. skb = data->rxskbs[rx];
  595. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  596. data->rxfree--;
  597. done++;
  598. if (data->rxring[rx].misc & TSI108_RX_BAD) {
  599. spin_lock_irq(&data->misclock);
  600. if (data->rxring[rx].misc & TSI108_RX_CRC)
  601. data->stats.rx_crc_errors++;
  602. if (data->rxring[rx].misc & TSI108_RX_OVER)
  603. data->stats.rx_fifo_errors++;
  604. spin_unlock_irq(&data->misclock);
  605. dev_kfree_skb_any(skb);
  606. continue;
  607. }
  608. if (netif_msg_pktdata(data)) {
  609. int i;
  610. printk("%s: Rx Frame contents (%d)\n",
  611. dev->name, data->rxring[rx].len);
  612. for (i = 0; i < data->rxring[rx].len; i++)
  613. printk(" %2.2x", skb->data[i]);
  614. printk(".\n");
  615. }
  616. skb_put(skb, data->rxring[rx].len);
  617. skb->protocol = eth_type_trans(skb, dev);
  618. netif_receive_skb(skb);
  619. dev->last_rx = jiffies;
  620. }
  621. return done;
  622. }
  623. static int tsi108_refill_rx(struct net_device *dev, int budget)
  624. {
  625. struct tsi108_prv_data *data = netdev_priv(dev);
  626. int done = 0;
  627. while (data->rxfree != TSI108_RXRING_LEN && done != budget) {
  628. int rx = data->rxhead;
  629. struct sk_buff *skb;
  630. data->rxskbs[rx] = skb = dev_alloc_skb(TSI108_RXBUF_SIZE + 2);
  631. if (!skb)
  632. break;
  633. skb_reserve(skb, 2); /* Align the data on a 4-byte boundary. */
  634. data->rxring[rx].buf0 = dma_map_single(NULL, skb->data,
  635. TSI108_RX_SKB_SIZE,
  636. DMA_FROM_DEVICE);
  637. /* Sometimes the hardware sets blen to zero after packet
  638. * reception, even though the manual says that it's only ever
  639. * modified by the driver.
  640. */
  641. data->rxring[rx].blen = TSI108_RX_SKB_SIZE;
  642. data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT;
  643. data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN;
  644. data->rxfree++;
  645. done++;
  646. }
  647. if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) &
  648. TSI108_EC_RXSTAT_QUEUE0))
  649. tsi108_restart_rx(data, dev);
  650. return done;
  651. }
  652. static int tsi108_poll(struct napi_struct *napi, int budget)
  653. {
  654. struct tsi108_prv_data *data = container_of(napi, struct tsi108_prv_data, napi);
  655. struct net_device *dev = data->dev;
  656. u32 estat = TSI_READ(TSI108_EC_RXESTAT);
  657. u32 intstat = TSI_READ(TSI108_EC_INTSTAT);
  658. int num_received = 0, num_filled = 0;
  659. intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  660. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT;
  661. TSI_WRITE(TSI108_EC_RXESTAT, estat);
  662. TSI_WRITE(TSI108_EC_INTSTAT, intstat);
  663. if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT))
  664. num_received = tsi108_complete_rx(dev, budget);
  665. /* This should normally fill no more slots than the number of
  666. * packets received in tsi108_complete_rx(). The exception
  667. * is when we previously ran out of memory for RX SKBs. In that
  668. * case, it's helpful to obey the budget, not only so that the
  669. * CPU isn't hogged, but so that memory (which may still be low)
  670. * is not hogged by one device.
  671. *
  672. * A work unit is considered to be two SKBs to allow us to catch
  673. * up when the ring has shrunk due to out-of-memory but we're
  674. * still removing the full budget's worth of packets each time.
  675. */
  676. if (data->rxfree < TSI108_RXRING_LEN)
  677. num_filled = tsi108_refill_rx(dev, budget * 2);
  678. if (intstat & TSI108_INT_RXERROR) {
  679. u32 err = TSI_READ(TSI108_EC_RXERR);
  680. TSI_WRITE(TSI108_EC_RXERR, err);
  681. if (err) {
  682. if (net_ratelimit())
  683. printk(KERN_DEBUG "%s: RX error %x\n",
  684. dev->name, err);
  685. if (!(TSI_READ(TSI108_EC_RXSTAT) &
  686. TSI108_EC_RXSTAT_QUEUE0))
  687. tsi108_restart_rx(data, dev);
  688. }
  689. }
  690. if (intstat & TSI108_INT_RXOVERRUN) {
  691. spin_lock_irq(&data->misclock);
  692. data->stats.rx_fifo_errors++;
  693. spin_unlock_irq(&data->misclock);
  694. }
  695. if (num_received < budget) {
  696. data->rxpending = 0;
  697. netif_rx_complete(dev, napi);
  698. TSI_WRITE(TSI108_EC_INTMASK,
  699. TSI_READ(TSI108_EC_INTMASK)
  700. & ~(TSI108_INT_RXQUEUE0
  701. | TSI108_INT_RXTHRESH |
  702. TSI108_INT_RXOVERRUN |
  703. TSI108_INT_RXERROR |
  704. TSI108_INT_RXWAIT));
  705. } else {
  706. data->rxpending = 1;
  707. }
  708. return num_received;
  709. }
  710. static void tsi108_rx_int(struct net_device *dev)
  711. {
  712. struct tsi108_prv_data *data = netdev_priv(dev);
  713. /* A race could cause dev to already be scheduled, so it's not an
  714. * error if that happens (and interrupts shouldn't be re-masked,
  715. * because that can cause harmful races, if poll has already
  716. * unmasked them but not cleared LINK_STATE_SCHED).
  717. *
  718. * This can happen if this code races with tsi108_poll(), which masks
  719. * the interrupts after tsi108_irq_one() read the mask, but before
  720. * netif_rx_schedule is called. It could also happen due to calls
  721. * from tsi108_check_rxring().
  722. */
  723. if (netif_rx_schedule_prep(dev, &data->napi)) {
  724. /* Mask, rather than ack, the receive interrupts. The ack
  725. * will happen in tsi108_poll().
  726. */
  727. TSI_WRITE(TSI108_EC_INTMASK,
  728. TSI_READ(TSI108_EC_INTMASK) |
  729. TSI108_INT_RXQUEUE0
  730. | TSI108_INT_RXTHRESH |
  731. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR |
  732. TSI108_INT_RXWAIT);
  733. __netif_rx_schedule(dev, &data->napi);
  734. } else {
  735. if (!netif_running(dev)) {
  736. /* This can happen if an interrupt occurs while the
  737. * interface is being brought down, as the START
  738. * bit is cleared before the stop function is called.
  739. *
  740. * In this case, the interrupts must be masked, or
  741. * they will continue indefinitely.
  742. *
  743. * There's a race here if the interface is brought down
  744. * and then up in rapid succession, as the device could
  745. * be made running after the above check and before
  746. * the masking below. This will only happen if the IRQ
  747. * thread has a lower priority than the task brining
  748. * up the interface. Fixing this race would likely
  749. * require changes in generic code.
  750. */
  751. TSI_WRITE(TSI108_EC_INTMASK,
  752. TSI_READ
  753. (TSI108_EC_INTMASK) |
  754. TSI108_INT_RXQUEUE0 |
  755. TSI108_INT_RXTHRESH |
  756. TSI108_INT_RXOVERRUN |
  757. TSI108_INT_RXERROR |
  758. TSI108_INT_RXWAIT);
  759. }
  760. }
  761. }
  762. /* If the RX ring has run out of memory, try periodically
  763. * to allocate some more, as otherwise poll would never
  764. * get called (apart from the initial end-of-queue condition).
  765. *
  766. * This is called once per second (by default) from the thread.
  767. */
  768. static void tsi108_check_rxring(struct net_device *dev)
  769. {
  770. struct tsi108_prv_data *data = netdev_priv(dev);
  771. /* A poll is scheduled, as opposed to caling tsi108_refill_rx
  772. * directly, so as to keep the receive path single-threaded
  773. * (and thus not needing a lock).
  774. */
  775. if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4)
  776. tsi108_rx_int(dev);
  777. }
  778. static void tsi108_tx_int(struct net_device *dev)
  779. {
  780. struct tsi108_prv_data *data = netdev_priv(dev);
  781. u32 estat = TSI_READ(TSI108_EC_TXESTAT);
  782. TSI_WRITE(TSI108_EC_TXESTAT, estat);
  783. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 |
  784. TSI108_INT_TXIDLE | TSI108_INT_TXERROR);
  785. if (estat & TSI108_EC_TXESTAT_Q0_ERR) {
  786. u32 err = TSI_READ(TSI108_EC_TXERR);
  787. TSI_WRITE(TSI108_EC_TXERR, err);
  788. if (err && net_ratelimit())
  789. printk(KERN_ERR "%s: TX error %x\n", dev->name, err);
  790. }
  791. if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) {
  792. spin_lock(&data->txlock);
  793. tsi108_complete_tx(dev);
  794. spin_unlock(&data->txlock);
  795. }
  796. }
  797. static irqreturn_t tsi108_irq(int irq, void *dev_id)
  798. {
  799. struct net_device *dev = dev_id;
  800. struct tsi108_prv_data *data = netdev_priv(dev);
  801. u32 stat = TSI_READ(TSI108_EC_INTSTAT);
  802. if (!(stat & TSI108_INT_ANY))
  803. return IRQ_NONE; /* Not our interrupt */
  804. stat &= ~TSI_READ(TSI108_EC_INTMASK);
  805. if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE |
  806. TSI108_INT_TXERROR))
  807. tsi108_tx_int(dev);
  808. if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  809. TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN |
  810. TSI108_INT_RXERROR))
  811. tsi108_rx_int(dev);
  812. if (stat & TSI108_INT_SFN) {
  813. if (net_ratelimit())
  814. printk(KERN_DEBUG "%s: SFN error\n", dev->name);
  815. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN);
  816. }
  817. if (stat & TSI108_INT_STATCARRY) {
  818. tsi108_stat_carry(dev);
  819. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY);
  820. }
  821. return IRQ_HANDLED;
  822. }
  823. static void tsi108_stop_ethernet(struct net_device *dev)
  824. {
  825. struct tsi108_prv_data *data = netdev_priv(dev);
  826. int i = 1000;
  827. /* Disable all TX and RX queues ... */
  828. TSI_WRITE(TSI108_EC_TXCTRL, 0);
  829. TSI_WRITE(TSI108_EC_RXCTRL, 0);
  830. /* ...and wait for them to become idle */
  831. while(i--) {
  832. if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE))
  833. break;
  834. udelay(10);
  835. }
  836. i = 1000;
  837. while(i--){
  838. if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE))
  839. return;
  840. udelay(10);
  841. }
  842. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  843. }
  844. static void tsi108_reset_ether(struct tsi108_prv_data * data)
  845. {
  846. TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST);
  847. udelay(100);
  848. TSI_WRITE(TSI108_MAC_CFG1, 0);
  849. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST);
  850. udelay(100);
  851. TSI_WRITE(TSI108_EC_PORTCTRL,
  852. TSI_READ(TSI108_EC_PORTCTRL) &
  853. ~TSI108_EC_PORTCTRL_STATRST);
  854. TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST);
  855. udelay(100);
  856. TSI_WRITE(TSI108_EC_TXCFG,
  857. TSI_READ(TSI108_EC_TXCFG) &
  858. ~TSI108_EC_TXCFG_RST);
  859. TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST);
  860. udelay(100);
  861. TSI_WRITE(TSI108_EC_RXCFG,
  862. TSI_READ(TSI108_EC_RXCFG) &
  863. ~TSI108_EC_RXCFG_RST);
  864. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  865. TSI_READ(TSI108_MAC_MII_MGMT_CFG) |
  866. TSI108_MAC_MII_MGMT_RST);
  867. udelay(100);
  868. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  869. (TSI_READ(TSI108_MAC_MII_MGMT_CFG) &
  870. ~(TSI108_MAC_MII_MGMT_RST |
  871. TSI108_MAC_MII_MGMT_CLK)) | 0x07);
  872. }
  873. static int tsi108_get_mac(struct net_device *dev)
  874. {
  875. struct tsi108_prv_data *data = netdev_priv(dev);
  876. u32 word1 = TSI_READ(TSI108_MAC_ADDR1);
  877. u32 word2 = TSI_READ(TSI108_MAC_ADDR2);
  878. /* Note that the octets are reversed from what the manual says,
  879. * producing an even weirder ordering...
  880. */
  881. if (word2 == 0 && word1 == 0) {
  882. dev->dev_addr[0] = 0x00;
  883. dev->dev_addr[1] = 0x06;
  884. dev->dev_addr[2] = 0xd2;
  885. dev->dev_addr[3] = 0x00;
  886. dev->dev_addr[4] = 0x00;
  887. if (0x8 == data->phy)
  888. dev->dev_addr[5] = 0x01;
  889. else
  890. dev->dev_addr[5] = 0x02;
  891. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  892. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  893. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  894. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  895. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  896. } else {
  897. dev->dev_addr[0] = (word2 >> 16) & 0xff;
  898. dev->dev_addr[1] = (word2 >> 24) & 0xff;
  899. dev->dev_addr[2] = (word1 >> 0) & 0xff;
  900. dev->dev_addr[3] = (word1 >> 8) & 0xff;
  901. dev->dev_addr[4] = (word1 >> 16) & 0xff;
  902. dev->dev_addr[5] = (word1 >> 24) & 0xff;
  903. }
  904. if (!is_valid_ether_addr(dev->dev_addr)) {
  905. printk("KERN_ERR: word1: %08x, word2: %08x\n", word1, word2);
  906. return -EINVAL;
  907. }
  908. return 0;
  909. }
  910. static int tsi108_set_mac(struct net_device *dev, void *addr)
  911. {
  912. struct tsi108_prv_data *data = netdev_priv(dev);
  913. u32 word1, word2;
  914. int i;
  915. if (!is_valid_ether_addr(addr))
  916. return -EINVAL;
  917. for (i = 0; i < 6; i++)
  918. /* +2 is for the offset of the HW addr type */
  919. dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
  920. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  921. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  922. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  923. spin_lock_irq(&data->misclock);
  924. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  925. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  926. spin_lock(&data->txlock);
  927. if (data->txfree && data->link_up)
  928. netif_wake_queue(dev);
  929. spin_unlock(&data->txlock);
  930. spin_unlock_irq(&data->misclock);
  931. return 0;
  932. }
  933. /* Protected by dev->xmit_lock. */
  934. static void tsi108_set_rx_mode(struct net_device *dev)
  935. {
  936. struct tsi108_prv_data *data = netdev_priv(dev);
  937. u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
  938. if (dev->flags & IFF_PROMISC) {
  939. rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
  940. rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
  941. goto out;
  942. }
  943. rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
  944. if (dev->flags & IFF_ALLMULTI || dev->mc_count) {
  945. int i;
  946. struct dev_mc_list *mc = dev->mc_list;
  947. rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
  948. memset(data->mc_hash, 0, sizeof(data->mc_hash));
  949. while (mc) {
  950. u32 hash, crc;
  951. if (mc->dmi_addrlen == 6) {
  952. crc = ether_crc(6, mc->dmi_addr);
  953. hash = crc >> 23;
  954. __set_bit(hash, &data->mc_hash[0]);
  955. } else {
  956. printk(KERN_ERR
  957. "%s: got multicast address of length %d "
  958. "instead of 6.\n", dev->name,
  959. mc->dmi_addrlen);
  960. }
  961. mc = mc->next;
  962. }
  963. TSI_WRITE(TSI108_EC_HASHADDR,
  964. TSI108_EC_HASHADDR_AUTOINC |
  965. TSI108_EC_HASHADDR_MCAST);
  966. for (i = 0; i < 16; i++) {
  967. /* The manual says that the hardware may drop
  968. * back-to-back writes to the data register.
  969. */
  970. udelay(1);
  971. TSI_WRITE(TSI108_EC_HASHDATA,
  972. data->mc_hash[i]);
  973. }
  974. }
  975. out:
  976. TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
  977. }
  978. static void tsi108_init_phy(struct net_device *dev)
  979. {
  980. struct tsi108_prv_data *data = netdev_priv(dev);
  981. u32 i = 0;
  982. u16 phyval = 0;
  983. unsigned long flags;
  984. spin_lock_irqsave(&phy_lock, flags);
  985. tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
  986. while (i--){
  987. if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
  988. break;
  989. udelay(10);
  990. }
  991. if (i == 0)
  992. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  993. if (data->phy_type == TSI108_PHY_BCM54XX) {
  994. tsi108_write_mii(data, 0x09, 0x0300);
  995. tsi108_write_mii(data, 0x10, 0x1020);
  996. tsi108_write_mii(data, 0x1c, 0x8c00);
  997. }
  998. tsi108_write_mii(data,
  999. MII_BMCR,
  1000. BMCR_ANENABLE | BMCR_ANRESTART);
  1001. while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
  1002. cpu_relax();
  1003. /* Set G/MII mode and receive clock select in TBI control #2. The
  1004. * second port won't work if this isn't done, even though we don't
  1005. * use TBI mode.
  1006. */
  1007. tsi108_write_tbi(data, 0x11, 0x30);
  1008. /* FIXME: It seems to take more than 2 back-to-back reads to the
  1009. * PHY_STAT register before the link up status bit is set.
  1010. */
  1011. data->link_up = 0;
  1012. while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
  1013. BMSR_LSTATUS)) {
  1014. if (i++ > (MII_READ_DELAY / 10)) {
  1015. break;
  1016. }
  1017. spin_unlock_irqrestore(&phy_lock, flags);
  1018. msleep(10);
  1019. spin_lock_irqsave(&phy_lock, flags);
  1020. }
  1021. data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if);
  1022. printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval);
  1023. data->phy_ok = 1;
  1024. data->init_media = 1;
  1025. spin_unlock_irqrestore(&phy_lock, flags);
  1026. }
  1027. static void tsi108_kill_phy(struct net_device *dev)
  1028. {
  1029. struct tsi108_prv_data *data = netdev_priv(dev);
  1030. unsigned long flags;
  1031. spin_lock_irqsave(&phy_lock, flags);
  1032. tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
  1033. data->phy_ok = 0;
  1034. spin_unlock_irqrestore(&phy_lock, flags);
  1035. }
  1036. static int tsi108_open(struct net_device *dev)
  1037. {
  1038. int i;
  1039. struct tsi108_prv_data *data = netdev_priv(dev);
  1040. unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc);
  1041. unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc);
  1042. i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev);
  1043. if (i != 0) {
  1044. printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n",
  1045. data->id, data->irq_num);
  1046. return i;
  1047. } else {
  1048. dev->irq = data->irq_num;
  1049. printk(KERN_NOTICE
  1050. "tsi108_open : Port %d Assigned IRQ %d to %s\n",
  1051. data->id, dev->irq, dev->name);
  1052. }
  1053. data->rxring = dma_alloc_coherent(NULL, rxring_size,
  1054. &data->rxdma, GFP_KERNEL);
  1055. if (!data->rxring) {
  1056. printk(KERN_DEBUG
  1057. "TSI108_ETH: failed to allocate memory for rxring!\n");
  1058. return -ENOMEM;
  1059. } else {
  1060. memset(data->rxring, 0, rxring_size);
  1061. }
  1062. data->txring = dma_alloc_coherent(NULL, txring_size,
  1063. &data->txdma, GFP_KERNEL);
  1064. if (!data->txring) {
  1065. printk(KERN_DEBUG
  1066. "TSI108_ETH: failed to allocate memory for txring!\n");
  1067. pci_free_consistent(0, rxring_size, data->rxring, data->rxdma);
  1068. return -ENOMEM;
  1069. } else {
  1070. memset(data->txring, 0, txring_size);
  1071. }
  1072. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1073. data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc);
  1074. data->rxring[i].blen = TSI108_RXBUF_SIZE;
  1075. data->rxring[i].vlan = 0;
  1076. }
  1077. data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma;
  1078. data->rxtail = 0;
  1079. data->rxhead = 0;
  1080. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1081. struct sk_buff *skb = dev_alloc_skb(TSI108_RXBUF_SIZE + NET_IP_ALIGN);
  1082. if (!skb) {
  1083. /* Bah. No memory for now, but maybe we'll get
  1084. * some more later.
  1085. * For now, we'll live with the smaller ring.
  1086. */
  1087. printk(KERN_WARNING
  1088. "%s: Could only allocate %d receive skb(s).\n",
  1089. dev->name, i);
  1090. data->rxhead = i;
  1091. break;
  1092. }
  1093. data->rxskbs[i] = skb;
  1094. /* Align the payload on a 4-byte boundary */
  1095. skb_reserve(skb, 2);
  1096. data->rxskbs[i] = skb;
  1097. data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data);
  1098. data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT;
  1099. }
  1100. data->rxfree = i;
  1101. TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma);
  1102. for (i = 0; i < TSI108_TXRING_LEN; i++) {
  1103. data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc);
  1104. data->txring[i].misc = 0;
  1105. }
  1106. data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma;
  1107. data->txtail = 0;
  1108. data->txhead = 0;
  1109. data->txfree = TSI108_TXRING_LEN;
  1110. TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma);
  1111. tsi108_init_phy(dev);
  1112. napi_enable(&data->napi);
  1113. setup_timer(&data->timer, tsi108_timed_checker, (unsigned long)dev);
  1114. mod_timer(&data->timer, jiffies + 1);
  1115. tsi108_restart_rx(data, dev);
  1116. TSI_WRITE(TSI108_EC_INTSTAT, ~0);
  1117. TSI_WRITE(TSI108_EC_INTMASK,
  1118. ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR |
  1119. TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 |
  1120. TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT |
  1121. TSI108_INT_SFN | TSI108_INT_STATCARRY));
  1122. TSI_WRITE(TSI108_MAC_CFG1,
  1123. TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN);
  1124. netif_start_queue(dev);
  1125. return 0;
  1126. }
  1127. static int tsi108_close(struct net_device *dev)
  1128. {
  1129. struct tsi108_prv_data *data = netdev_priv(dev);
  1130. netif_stop_queue(dev);
  1131. napi_disable(&data->napi);
  1132. del_timer_sync(&data->timer);
  1133. tsi108_stop_ethernet(dev);
  1134. tsi108_kill_phy(dev);
  1135. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1136. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1137. /* Check for any pending TX packets, and drop them. */
  1138. while (!data->txfree || data->txhead != data->txtail) {
  1139. int tx = data->txtail;
  1140. struct sk_buff *skb;
  1141. skb = data->txskbs[tx];
  1142. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  1143. data->txfree++;
  1144. dev_kfree_skb(skb);
  1145. }
  1146. synchronize_irq(data->irq_num);
  1147. free_irq(data->irq_num, dev);
  1148. /* Discard the RX ring. */
  1149. while (data->rxfree) {
  1150. int rx = data->rxtail;
  1151. struct sk_buff *skb;
  1152. skb = data->rxskbs[rx];
  1153. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  1154. data->rxfree--;
  1155. dev_kfree_skb(skb);
  1156. }
  1157. dma_free_coherent(0,
  1158. TSI108_RXRING_LEN * sizeof(rx_desc),
  1159. data->rxring, data->rxdma);
  1160. dma_free_coherent(0,
  1161. TSI108_TXRING_LEN * sizeof(tx_desc),
  1162. data->txring, data->txdma);
  1163. return 0;
  1164. }
  1165. static void tsi108_init_mac(struct net_device *dev)
  1166. {
  1167. struct tsi108_prv_data *data = netdev_priv(dev);
  1168. TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE |
  1169. TSI108_MAC_CFG2_PADCRC);
  1170. TSI_WRITE(TSI108_EC_TXTHRESH,
  1171. (192 << TSI108_EC_TXTHRESH_STARTFILL) |
  1172. (192 << TSI108_EC_TXTHRESH_STOPFILL));
  1173. TSI_WRITE(TSI108_STAT_CARRYMASK1,
  1174. ~(TSI108_STAT_CARRY1_RXBYTES |
  1175. TSI108_STAT_CARRY1_RXPKTS |
  1176. TSI108_STAT_CARRY1_RXFCS |
  1177. TSI108_STAT_CARRY1_RXMCAST |
  1178. TSI108_STAT_CARRY1_RXALIGN |
  1179. TSI108_STAT_CARRY1_RXLENGTH |
  1180. TSI108_STAT_CARRY1_RXRUNT |
  1181. TSI108_STAT_CARRY1_RXJUMBO |
  1182. TSI108_STAT_CARRY1_RXFRAG |
  1183. TSI108_STAT_CARRY1_RXJABBER |
  1184. TSI108_STAT_CARRY1_RXDROP));
  1185. TSI_WRITE(TSI108_STAT_CARRYMASK2,
  1186. ~(TSI108_STAT_CARRY2_TXBYTES |
  1187. TSI108_STAT_CARRY2_TXPKTS |
  1188. TSI108_STAT_CARRY2_TXEXDEF |
  1189. TSI108_STAT_CARRY2_TXEXCOL |
  1190. TSI108_STAT_CARRY2_TXTCOL |
  1191. TSI108_STAT_CARRY2_TXPAUSE));
  1192. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN);
  1193. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1194. TSI_WRITE(TSI108_EC_RXCFG,
  1195. TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE);
  1196. TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT |
  1197. TSI108_EC_TXQ_CFG_EOQ_OWN_INT |
  1198. TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1199. TSI108_EC_TXQ_CFG_SFNPORT));
  1200. TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT |
  1201. TSI108_EC_RXQ_CFG_EOQ_OWN_INT |
  1202. TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1203. TSI108_EC_RXQ_CFG_SFNPORT));
  1204. TSI_WRITE(TSI108_EC_TXQ_BUFCFG,
  1205. TSI108_EC_TXQ_BUFCFG_BURST256 |
  1206. TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1207. TSI108_EC_TXQ_BUFCFG_SFNPORT));
  1208. TSI_WRITE(TSI108_EC_RXQ_BUFCFG,
  1209. TSI108_EC_RXQ_BUFCFG_BURST256 |
  1210. TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1211. TSI108_EC_RXQ_BUFCFG_SFNPORT));
  1212. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1213. }
  1214. static int tsi108_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1215. {
  1216. struct tsi108_prv_data *data = netdev_priv(dev);
  1217. unsigned long flags;
  1218. int rc;
  1219. spin_lock_irqsave(&data->txlock, flags);
  1220. rc = mii_ethtool_gset(&data->mii_if, cmd);
  1221. spin_unlock_irqrestore(&data->txlock, flags);
  1222. return rc;
  1223. }
  1224. static int tsi108_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1225. {
  1226. struct tsi108_prv_data *data = netdev_priv(dev);
  1227. unsigned long flags;
  1228. int rc;
  1229. spin_lock_irqsave(&data->txlock, flags);
  1230. rc = mii_ethtool_sset(&data->mii_if, cmd);
  1231. spin_unlock_irqrestore(&data->txlock, flags);
  1232. return rc;
  1233. }
  1234. static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1235. {
  1236. struct tsi108_prv_data *data = netdev_priv(dev);
  1237. if (!netif_running(dev))
  1238. return -EINVAL;
  1239. return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL);
  1240. }
  1241. static const struct ethtool_ops tsi108_ethtool_ops = {
  1242. .get_link = ethtool_op_get_link,
  1243. .get_settings = tsi108_get_settings,
  1244. .set_settings = tsi108_set_settings,
  1245. };
  1246. static int
  1247. tsi108_init_one(struct platform_device *pdev)
  1248. {
  1249. struct net_device *dev = NULL;
  1250. struct tsi108_prv_data *data = NULL;
  1251. hw_info *einfo;
  1252. int err = 0;
  1253. DECLARE_MAC_BUF(mac);
  1254. einfo = pdev->dev.platform_data;
  1255. if (NULL == einfo) {
  1256. printk(KERN_ERR "tsi-eth %d: Missing additional data!\n",
  1257. pdev->id);
  1258. return -ENODEV;
  1259. }
  1260. /* Create an ethernet device instance */
  1261. dev = alloc_etherdev(sizeof(struct tsi108_prv_data));
  1262. if (!dev) {
  1263. printk("tsi108_eth: Could not allocate a device structure\n");
  1264. return -ENOMEM;
  1265. }
  1266. printk("tsi108_eth%d: probe...\n", pdev->id);
  1267. data = netdev_priv(dev);
  1268. data->dev = dev;
  1269. pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
  1270. pdev->id, einfo->regs, einfo->phyregs,
  1271. einfo->phy, einfo->irq_num);
  1272. data->regs = ioremap(einfo->regs, 0x400);
  1273. if (NULL == data->regs) {
  1274. err = -ENOMEM;
  1275. goto regs_fail;
  1276. }
  1277. data->phyregs = ioremap(einfo->phyregs, 0x400);
  1278. if (NULL == data->phyregs) {
  1279. err = -ENOMEM;
  1280. goto regs_fail;
  1281. }
  1282. /* MII setup */
  1283. data->mii_if.dev = dev;
  1284. data->mii_if.mdio_read = tsi108_mdio_read;
  1285. data->mii_if.mdio_write = tsi108_mdio_write;
  1286. data->mii_if.phy_id = einfo->phy;
  1287. data->mii_if.phy_id_mask = 0x1f;
  1288. data->mii_if.reg_num_mask = 0x1f;
  1289. data->phy = einfo->phy;
  1290. data->phy_type = einfo->phy_type;
  1291. data->irq_num = einfo->irq_num;
  1292. data->id = pdev->id;
  1293. dev->open = tsi108_open;
  1294. dev->stop = tsi108_close;
  1295. dev->hard_start_xmit = tsi108_send_packet;
  1296. dev->set_mac_address = tsi108_set_mac;
  1297. dev->set_multicast_list = tsi108_set_rx_mode;
  1298. dev->get_stats = tsi108_get_stats;
  1299. netif_napi_add(dev, &data->napi, tsi108_poll, 64);
  1300. dev->do_ioctl = tsi108_do_ioctl;
  1301. dev->ethtool_ops = &tsi108_ethtool_ops;
  1302. /* Apparently, the Linux networking code won't use scatter-gather
  1303. * if the hardware doesn't do checksums. However, it's faster
  1304. * to checksum in place and use SG, as (among other reasons)
  1305. * the cache won't be dirtied (which then has to be flushed
  1306. * before DMA). The checksumming is done by the driver (via
  1307. * a new function skb_csum_dev() in net/core/skbuff.c).
  1308. */
  1309. dev->features = NETIF_F_HIGHDMA;
  1310. spin_lock_init(&data->txlock);
  1311. spin_lock_init(&data->misclock);
  1312. tsi108_reset_ether(data);
  1313. tsi108_kill_phy(dev);
  1314. if ((err = tsi108_get_mac(dev)) != 0) {
  1315. printk(KERN_ERR "%s: Invalid MAC address. Please correct.\n",
  1316. dev->name);
  1317. goto register_fail;
  1318. }
  1319. tsi108_init_mac(dev);
  1320. err = register_netdev(dev);
  1321. if (err) {
  1322. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  1323. dev->name);
  1324. goto register_fail;
  1325. }
  1326. platform_set_drvdata(pdev, dev);
  1327. printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: %s\n",
  1328. dev->name, print_mac(mac, dev->dev_addr));
  1329. #ifdef DEBUG
  1330. data->msg_enable = DEBUG;
  1331. dump_eth_one(dev);
  1332. #endif
  1333. return 0;
  1334. register_fail:
  1335. iounmap(data->regs);
  1336. iounmap(data->phyregs);
  1337. regs_fail:
  1338. free_netdev(dev);
  1339. return err;
  1340. }
  1341. /* There's no way to either get interrupts from the PHY when
  1342. * something changes, or to have the Tsi108 automatically communicate
  1343. * with the PHY to reconfigure itself.
  1344. *
  1345. * Thus, we have to do it using a timer.
  1346. */
  1347. static void tsi108_timed_checker(unsigned long dev_ptr)
  1348. {
  1349. struct net_device *dev = (struct net_device *)dev_ptr;
  1350. struct tsi108_prv_data *data = netdev_priv(dev);
  1351. tsi108_check_phy(dev);
  1352. tsi108_check_rxring(dev);
  1353. mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL);
  1354. }
  1355. static int tsi108_ether_init(void)
  1356. {
  1357. int ret;
  1358. ret = platform_driver_register (&tsi_eth_driver);
  1359. if (ret < 0){
  1360. printk("tsi108_ether_init: error initializing ethernet "
  1361. "device\n");
  1362. return ret;
  1363. }
  1364. return 0;
  1365. }
  1366. static int tsi108_ether_remove(struct platform_device *pdev)
  1367. {
  1368. struct net_device *dev = platform_get_drvdata(pdev);
  1369. struct tsi108_prv_data *priv = netdev_priv(dev);
  1370. unregister_netdev(dev);
  1371. tsi108_stop_ethernet(dev);
  1372. platform_set_drvdata(pdev, NULL);
  1373. iounmap(priv->regs);
  1374. iounmap(priv->phyregs);
  1375. free_netdev(dev);
  1376. return 0;
  1377. }
  1378. static void tsi108_ether_exit(void)
  1379. {
  1380. platform_driver_unregister(&tsi_eth_driver);
  1381. }
  1382. module_init(tsi108_ether_init);
  1383. module_exit(tsi108_ether_exit);
  1384. MODULE_AUTHOR("Tundra Semiconductor Corporation");
  1385. MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver");
  1386. MODULE_LICENSE("GPL");