state.c 2.0 KB

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  1. #include <linux/mm.h>
  2. #include <linux/init.h>
  3. #include <asm/io.h>
  4. #include <asm/mtrr.h>
  5. #include <asm/msr.h>
  6. #include <asm/processor-cyrix.h>
  7. #include <asm/processor-flags.h>
  8. #include "mtrr.h"
  9. /* Put the processor into a state where MTRRs can be safely set */
  10. void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
  11. {
  12. unsigned int cr0;
  13. /* Disable interrupts locally */
  14. local_irq_save(ctxt->flags);
  15. if (use_intel() || is_cpu(CYRIX)) {
  16. /* Save value of CR4 and clear Page Global Enable (bit 7) */
  17. if ( cpu_has_pge ) {
  18. ctxt->cr4val = read_cr4();
  19. write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
  20. }
  21. /* Disable and flush caches. Note that wbinvd flushes the TLBs as
  22. a side-effect */
  23. cr0 = read_cr0() | X86_CR0_CD;
  24. wbinvd();
  25. write_cr0(cr0);
  26. wbinvd();
  27. if (use_intel())
  28. /* Save MTRR state */
  29. rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  30. else
  31. /* Cyrix ARRs - everything else were excluded at the top */
  32. ctxt->ccr3 = getCx86(CX86_CCR3);
  33. }
  34. }
  35. void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
  36. {
  37. if (use_intel())
  38. /* Disable MTRRs, and set the default type to uncached */
  39. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
  40. ctxt->deftype_hi);
  41. else if (is_cpu(CYRIX))
  42. /* Cyrix ARRs - everything else were excluded at the top */
  43. setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
  44. }
  45. /* Restore the processor after a set_mtrr_prepare */
  46. void set_mtrr_done(struct set_mtrr_context *ctxt)
  47. {
  48. if (use_intel() || is_cpu(CYRIX)) {
  49. /* Flush caches and TLBs */
  50. wbinvd();
  51. /* Restore MTRRdefType */
  52. if (use_intel())
  53. /* Intel (P6) standard MTRRs */
  54. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  55. else
  56. /* Cyrix ARRs - everything else was excluded at the top */
  57. setCx86(CX86_CCR3, ctxt->ccr3);
  58. /* Enable caches */
  59. write_cr0(read_cr0() & 0xbfffffff);
  60. /* Restore value of CR4 */
  61. if ( cpu_has_pge )
  62. write_cr4(ctxt->cr4val);
  63. }
  64. /* Re-enable interrupts locally (if enabled previously) */
  65. local_irq_restore(ctxt->flags);
  66. }