taishan.dts 8.8 KB

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  1. /*
  2. * Device Tree Source for IBM/AMCC Taishan
  3. *
  4. * Copyright 2007 IBM Corp.
  5. * Hugh Blemings <hugh@au.ibm.com> based off code by
  6. * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without
  10. * any warranty of any kind, whether express or implied.
  11. */
  12. / {
  13. #address-cells = <2>;
  14. #size-cells = <1>;
  15. model = "amcc,taishan";
  16. compatible = "amcc,taishan";
  17. dcr-parent = <&/cpus/cpu@0>;
  18. aliases {
  19. ethernet0 = &EMAC2;
  20. ethernet1 = &EMAC3;
  21. serial0 = &UART0;
  22. serial1 = &UART1;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. device_type = "cpu";
  29. model = "PowerPC,440GX";
  30. reg = <0>;
  31. clock-frequency = <2FAF0800>; // 800MHz
  32. timebase-frequency = <0>; // Filled in by zImage
  33. i-cache-line-size = <32>;
  34. d-cache-line-size = <32>;
  35. i-cache-size = <8000>; /* 32 kB */
  36. d-cache-size = <8000>; /* 32 kB */
  37. dcr-controller;
  38. dcr-access-method = "native";
  39. };
  40. };
  41. memory {
  42. device_type = "memory";
  43. reg = <0 0 0>; // Filled in by zImage
  44. };
  45. UICB0: interrupt-controller-base {
  46. compatible = "ibm,uic-440gx", "ibm,uic";
  47. interrupt-controller;
  48. cell-index = <3>;
  49. dcr-reg = <200 009>;
  50. #address-cells = <0>;
  51. #size-cells = <0>;
  52. #interrupt-cells = <2>;
  53. };
  54. UIC0: interrupt-controller0 {
  55. compatible = "ibm,uic-440gx", "ibm,uic";
  56. interrupt-controller;
  57. cell-index = <0>;
  58. dcr-reg = <0c0 009>;
  59. #address-cells = <0>;
  60. #size-cells = <0>;
  61. #interrupt-cells = <2>;
  62. interrupts = <01 4 00 4>; /* cascade - first non-critical */
  63. interrupt-parent = <&UICB0>;
  64. };
  65. UIC1: interrupt-controller1 {
  66. compatible = "ibm,uic-440gx", "ibm,uic";
  67. interrupt-controller;
  68. cell-index = <1>;
  69. dcr-reg = <0d0 009>;
  70. #address-cells = <0>;
  71. #size-cells = <0>;
  72. #interrupt-cells = <2>;
  73. interrupts = <03 4 02 4>; /* cascade */
  74. interrupt-parent = <&UICB0>;
  75. };
  76. UIC2: interrupt-controller2 {
  77. compatible = "ibm,uic-440gx", "ibm,uic";
  78. interrupt-controller;
  79. cell-index = <2>; /* was 1 */
  80. dcr-reg = <210 009>;
  81. #address-cells = <0>;
  82. #size-cells = <0>;
  83. #interrupt-cells = <2>;
  84. interrupts = <05 4 04 4>; /* cascade */
  85. interrupt-parent = <&UICB0>;
  86. };
  87. CPC0: cpc {
  88. compatible = "ibm,cpc-440gp";
  89. dcr-reg = <0b0 003 0e0 010>;
  90. // FIXME: anything else?
  91. };
  92. plb {
  93. compatible = "ibm,plb-440gx", "ibm,plb4";
  94. #address-cells = <2>;
  95. #size-cells = <1>;
  96. ranges;
  97. clock-frequency = <9896800>; // 160MHz
  98. SDRAM0: memory-controller {
  99. compatible = "ibm,sdram-440gp";
  100. dcr-reg = <010 2>;
  101. // FIXME: anything else?
  102. };
  103. SRAM0: sram {
  104. compatible = "ibm,sram-440gp";
  105. dcr-reg = <020 8 00a 1>;
  106. };
  107. DMA0: dma {
  108. // FIXME: ???
  109. compatible = "ibm,dma-440gp";
  110. dcr-reg = <100 027>;
  111. };
  112. MAL0: mcmal {
  113. compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
  114. dcr-reg = <180 62>;
  115. num-tx-chans = <4>;
  116. num-rx-chans = <4>;
  117. interrupt-parent = <&MAL0>;
  118. interrupts = <0 1 2 3 4>;
  119. #interrupt-cells = <1>;
  120. #address-cells = <0>;
  121. #size-cells = <0>;
  122. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  123. /*RXEOB*/ 1 &UIC0 b 4
  124. /*SERR*/ 2 &UIC1 0 4
  125. /*TXDE*/ 3 &UIC1 1 4
  126. /*RXDE*/ 4 &UIC1 2 4>;
  127. interrupt-map-mask = <ffffffff>;
  128. };
  129. POB0: opb {
  130. compatible = "ibm,opb-440gx", "ibm,opb";
  131. #address-cells = <1>;
  132. #size-cells = <1>;
  133. /* Wish there was a nicer way of specifying a full 32-bit
  134. range */
  135. ranges = <00000000 1 00000000 80000000
  136. 80000000 1 80000000 80000000>;
  137. dcr-reg = <090 00b>;
  138. interrupt-parent = <&UIC1>;
  139. interrupts = <7 4>;
  140. clock-frequency = <4C4B400>; // 80MHz
  141. EBC0: ebc {
  142. compatible = "ibm,ebc-440gx", "ibm,ebc";
  143. dcr-reg = <012 2>;
  144. #address-cells = <2>;
  145. #size-cells = <1>;
  146. clock-frequency = <4C4B400>; // 80MHz
  147. /* ranges property is supplied by zImage
  148. * based on firmware's configuration of the
  149. * EBC bridge */
  150. interrupts = <5 4>;
  151. interrupt-parent = <&UIC1>;
  152. /* TODO: Add other EBC devices */
  153. };
  154. UART0: serial@40000200 {
  155. device_type = "serial";
  156. compatible = "ns16550";
  157. reg = <40000200 8>;
  158. virtual-reg = <e0000200>;
  159. clock-frequency = <A8C000>;
  160. current-speed = <1C200>; /* 115200 */
  161. interrupt-parent = <&UIC0>;
  162. interrupts = <0 4>;
  163. };
  164. UART1: serial@40000300 {
  165. device_type = "serial";
  166. compatible = "ns16550";
  167. reg = <40000300 8>;
  168. virtual-reg = <e0000300>;
  169. clock-frequency = <A8C000>;
  170. current-speed = <1C200>; /* 115200 */
  171. interrupt-parent = <&UIC0>;
  172. interrupts = <1 4>;
  173. };
  174. IIC0: i2c@40000400 {
  175. /* FIXME */
  176. compatible = "ibm,iic-440gp", "ibm,iic";
  177. reg = <40000400 14>;
  178. interrupt-parent = <&UIC0>;
  179. interrupts = <2 4>;
  180. };
  181. IIC1: i2c@40000500 {
  182. /* FIXME */
  183. compatible = "ibm,iic-440gp", "ibm,iic";
  184. reg = <40000500 14>;
  185. interrupt-parent = <&UIC0>;
  186. interrupts = <3 4>;
  187. };
  188. GPIO0: gpio@40000700 {
  189. /* FIXME */
  190. compatible = "ibm,gpio-440gp";
  191. reg = <40000700 20>;
  192. };
  193. ZMII0: emac-zmii@40000780 {
  194. compatible = "ibm,zmii-440gx", "ibm,zmii";
  195. reg = <40000780 c>;
  196. };
  197. RGMII0: emac-rgmii@40000790 {
  198. compatible = "ibm,rgmii";
  199. reg = <40000790 8>;
  200. };
  201. EMAC0: ethernet@40000800 {
  202. unused = <1>;
  203. linux,network-index = <2>;
  204. device_type = "network";
  205. compatible = "ibm,emac-440gx", "ibm,emac4";
  206. interrupt-parent = <&UIC1>;
  207. interrupts = <1c 4 1d 4>;
  208. reg = <40000800 70>;
  209. local-mac-address = [000000000000]; // Filled in by zImage
  210. mal-device = <&MAL0>;
  211. mal-tx-channel = <0>;
  212. mal-rx-channel = <0>;
  213. cell-index = <0>;
  214. max-frame-size = <5dc>;
  215. rx-fifo-size = <1000>;
  216. tx-fifo-size = <800>;
  217. phy-mode = "rmii";
  218. phy-map = <00000001>;
  219. zmii-device = <&ZMII0>;
  220. zmii-channel = <0>;
  221. };
  222. EMAC1: ethernet@40000900 {
  223. unused = <1>;
  224. linux,network-index = <3>;
  225. device_type = "network";
  226. compatible = "ibm,emac-440gx", "ibm,emac4";
  227. interrupt-parent = <&UIC1>;
  228. interrupts = <1e 4 1f 4>;
  229. reg = <40000900 70>;
  230. local-mac-address = [000000000000]; // Filled in by zImage
  231. mal-device = <&MAL0>;
  232. mal-tx-channel = <1>;
  233. mal-rx-channel = <1>;
  234. cell-index = <1>;
  235. max-frame-size = <5dc>;
  236. rx-fifo-size = <1000>;
  237. tx-fifo-size = <800>;
  238. phy-mode = "rmii";
  239. phy-map = <00000001>;
  240. zmii-device = <&ZMII0>;
  241. zmii-channel = <1>;
  242. };
  243. EMAC2: ethernet@40000c00 {
  244. linux,network-index = <0>;
  245. device_type = "network";
  246. compatible = "ibm,emac-440gx", "ibm,emac4";
  247. interrupt-parent = <&UIC2>;
  248. interrupts = <0 4 1 4>;
  249. reg = <40000c00 70>;
  250. local-mac-address = [000000000000]; // Filled in by zImage
  251. mal-device = <&MAL0>;
  252. mal-tx-channel = <2>;
  253. mal-rx-channel = <2>;
  254. cell-index = <2>;
  255. max-frame-size = <5dc>;
  256. rx-fifo-size = <1000>;
  257. tx-fifo-size = <800>;
  258. phy-mode = "rgmii";
  259. phy-map = <00000001>;
  260. rgmii-device = <&RGMII0>;
  261. rgmii-channel = <0>;
  262. zmii-device = <&ZMII0>;
  263. zmii-channel = <2>;
  264. };
  265. EMAC3: ethernet@40000e00 {
  266. linux,network-index = <1>;
  267. device_type = "network";
  268. compatible = "ibm,emac-440gx", "ibm,emac4";
  269. interrupt-parent = <&UIC2>;
  270. interrupts = <2 4 3 4>;
  271. reg = <40000e00 70>;
  272. local-mac-address = [000000000000]; // Filled in by zImage
  273. mal-device = <&MAL0>;
  274. mal-tx-channel = <3>;
  275. mal-rx-channel = <3>;
  276. cell-index = <3>;
  277. max-frame-size = <5dc>;
  278. rx-fifo-size = <1000>;
  279. tx-fifo-size = <800>;
  280. phy-mode = "rgmii";
  281. phy-map = <00000003>;
  282. rgmii-device = <&RGMII0>;
  283. rgmii-channel = <1>;
  284. zmii-device = <&ZMII0>;
  285. zmii-channel = <3>;
  286. };
  287. GPT0: gpt@40000a00 {
  288. /* FIXME */
  289. reg = <40000a00 d4>;
  290. interrupt-parent = <&UIC0>;
  291. interrupts = <12 4 13 4 14 4 15 4 16 4>;
  292. };
  293. };
  294. PCIX0: pci@20ec00000 {
  295. device_type = "pci";
  296. #interrupt-cells = <1>;
  297. #size-cells = <2>;
  298. #address-cells = <3>;
  299. compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
  300. primary;
  301. large-inbound-windows;
  302. enable-msi-hole;
  303. reg = <2 0ec00000 8 /* Config space access */
  304. 0 0 0 /* no IACK cycles */
  305. 2 0ed00000 4 /* Special cycles */
  306. 2 0ec80000 100 /* Internal registers */
  307. 2 0ec80100 fc>; /* Internal messaging registers */
  308. /* Outbound ranges, one memory and one IO,
  309. * later cannot be changed
  310. */
  311. ranges = <02000000 0 80000000 00000003 80000000 0 80000000
  312. 01000000 0 00000000 00000002 08000000 0 00010000>;
  313. /* Inbound 2GB range starting at 0 */
  314. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  315. interrupt-map-mask = <f800 0 0 7>;
  316. interrupt-map = <
  317. /* IDSEL 1 */
  318. 0800 0 0 1 &UIC0 17 8
  319. 0800 0 0 2 &UIC0 18 8
  320. 0800 0 0 3 &UIC0 19 8
  321. 0800 0 0 4 &UIC0 1a 8
  322. /* IDSEL 2 */
  323. 1000 0 0 1 &UIC0 18 8
  324. 1000 0 0 2 &UIC0 19 8
  325. 1000 0 0 3 &UIC0 1a 8
  326. 1000 0 0 4 &UIC0 17 8
  327. >;
  328. };
  329. };
  330. chosen {
  331. linux,stdout-path = "/plb/opb/serial@40000300";
  332. };
  333. };