mpc8378_mds.dts 6.0 KB

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  1. /*
  2. * MPC8378E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8378emds";
  14. compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8378@0 {
  28. device_type = "cpu";
  29. reg = <0x0>;
  30. d-cache-line-size = <32>;
  31. i-cache-line-size = <32>;
  32. d-cache-size = <32768>;
  33. i-cache-size = <32768>;
  34. timebase-frequency = <0>;
  35. bus-frequency = <0>;
  36. clock-frequency = <0>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x20000000>; // 512MB at 0
  42. };
  43. soc@e0000000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. device_type = "soc";
  47. ranges = <0x0 0xe0000000 0x00100000>;
  48. reg = <0xe0000000 0x00000200>;
  49. bus-frequency = <0>;
  50. wdt@200 {
  51. compatible = "mpc83xx_wdt";
  52. reg = <0x200 0x100>;
  53. };
  54. i2c@3000 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. cell-index = <0>;
  58. compatible = "fsl-i2c";
  59. reg = <0x3000 0x100>;
  60. interrupts = <14 0x8>;
  61. interrupt-parent = <&ipic>;
  62. dfsrr;
  63. };
  64. i2c@3100 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. cell-index = <1>;
  68. compatible = "fsl-i2c";
  69. reg = <0x3100 0x100>;
  70. interrupts = <15 0x8>;
  71. interrupt-parent = <&ipic>;
  72. dfsrr;
  73. };
  74. spi@7000 {
  75. cell-index = <0>;
  76. compatible = "fsl,spi";
  77. reg = <0x7000 0x1000>;
  78. interrupts = <16 0x8>;
  79. interrupt-parent = <&ipic>;
  80. mode = "cpu";
  81. };
  82. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  83. usb@23000 {
  84. compatible = "fsl-usb2-dr";
  85. reg = <0x23000 0x1000>;
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. interrupt-parent = <&ipic>;
  89. interrupts = <38 0x8>;
  90. phy_type = "utmi_wide";
  91. };
  92. mdio@24520 {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. compatible = "fsl,gianfar-mdio";
  96. reg = <0x24520 0x20>;
  97. phy2: ethernet-phy@2 {
  98. interrupt-parent = <&ipic>;
  99. interrupts = <17 0x8>;
  100. reg = <0x2>;
  101. device_type = "ethernet-phy";
  102. };
  103. phy3: ethernet-phy@3 {
  104. interrupt-parent = <&ipic>;
  105. interrupts = <18 0x8>;
  106. reg = <0x3>;
  107. device_type = "ethernet-phy";
  108. };
  109. };
  110. enet0: ethernet@24000 {
  111. cell-index = <0>;
  112. device_type = "network";
  113. model = "eTSEC";
  114. compatible = "gianfar";
  115. reg = <0x24000 0x1000>;
  116. local-mac-address = [ 00 00 00 00 00 00 ];
  117. interrupts = <32 0x8 33 0x8 34 0x8>;
  118. phy-connection-type = "mii";
  119. interrupt-parent = <&ipic>;
  120. phy-handle = <&phy2>;
  121. };
  122. enet1: ethernet@25000 {
  123. cell-index = <1>;
  124. device_type = "network";
  125. model = "eTSEC";
  126. compatible = "gianfar";
  127. reg = <0x25000 0x1000>;
  128. local-mac-address = [ 00 00 00 00 00 00 ];
  129. interrupts = <35 0x8 36 0x8 37 0x8>;
  130. phy-connection-type = "mii";
  131. interrupt-parent = <&ipic>;
  132. phy-handle = <&phy3>;
  133. };
  134. serial0: serial@4500 {
  135. cell-index = <0>;
  136. device_type = "serial";
  137. compatible = "ns16550";
  138. reg = <0x4500 0x100>;
  139. clock-frequency = <0>;
  140. interrupts = <9 0x8>;
  141. interrupt-parent = <&ipic>;
  142. };
  143. serial1: serial@4600 {
  144. cell-index = <1>;
  145. device_type = "serial";
  146. compatible = "ns16550";
  147. reg = <0x4600 0x100>;
  148. clock-frequency = <0>;
  149. interrupts = <10 0x8>;
  150. interrupt-parent = <&ipic>;
  151. };
  152. crypto@30000 {
  153. model = "SEC3";
  154. compatible = "talitos";
  155. reg = <0x30000 0x10000>;
  156. interrupts = <11 0x8>;
  157. interrupt-parent = <&ipic>;
  158. /* Rev. 3.0 geometry */
  159. num-channels = <4>;
  160. channel-fifo-len = <24>;
  161. exec-units-mask = <0x000001fe>;
  162. descriptor-types-mask = <0x03ab0ebf>;
  163. };
  164. sdhc@2e000 {
  165. model = "eSDHC";
  166. compatible = "fsl,esdhc";
  167. reg = <0x2e000 0x1000>;
  168. interrupts = <42 0x8>;
  169. interrupt-parent = <&ipic>;
  170. };
  171. /* IPIC
  172. * interrupts cell = <intr #, sense>
  173. * sense values match linux IORESOURCE_IRQ_* defines:
  174. * sense == 8: Level, low assertion
  175. * sense == 2: Edge, high-to-low change
  176. */
  177. ipic: pic@700 {
  178. compatible = "fsl,ipic";
  179. interrupt-controller;
  180. #address-cells = <0>;
  181. #interrupt-cells = <2>;
  182. reg = <0x700 0x100>;
  183. };
  184. };
  185. pci0: pci@e0008500 {
  186. cell-index = <0>;
  187. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  188. interrupt-map = <
  189. /* IDSEL 0x11 */
  190. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  191. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  192. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  193. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  194. /* IDSEL 0x12 */
  195. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  196. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  197. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  198. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  199. /* IDSEL 0x13 */
  200. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  201. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  202. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  203. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  204. /* IDSEL 0x15 */
  205. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  206. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  207. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  208. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  209. /* IDSEL 0x16 */
  210. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  211. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  212. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  213. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  214. /* IDSEL 0x17 */
  215. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  216. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  217. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  218. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  219. /* IDSEL 0x18 */
  220. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  221. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  222. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  223. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  224. interrupt-parent = <&ipic>;
  225. interrupts = <66 0x8>;
  226. bus-range = <0x0 0x0>;
  227. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  228. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  229. 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
  230. clock-frequency = <0>;
  231. #interrupt-cells = <1>;
  232. #size-cells = <2>;
  233. #address-cells = <3>;
  234. reg = <0xe0008500 0x100>;
  235. compatible = "fsl,mpc8349-pci";
  236. device_type = "pci";
  237. };
  238. };