devices.c 13 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <asm/arch/gpio.h>
  7. #include <asm/arch/udc.h>
  8. #include <asm/arch/pxafb.h>
  9. #include <asm/arch/mmc.h>
  10. #include <asm/arch/irda.h>
  11. #include <asm/arch/i2c.h>
  12. #include <asm/arch/ohci.h>
  13. #include "devices.h"
  14. void __init pxa_register_device(struct platform_device *dev, void *data)
  15. {
  16. int ret;
  17. dev->dev.platform_data = data;
  18. ret = platform_device_register(dev);
  19. if (ret)
  20. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  21. }
  22. static struct resource pxamci_resources[] = {
  23. [0] = {
  24. .start = 0x41100000,
  25. .end = 0x41100fff,
  26. .flags = IORESOURCE_MEM,
  27. },
  28. [1] = {
  29. .start = IRQ_MMC,
  30. .end = IRQ_MMC,
  31. .flags = IORESOURCE_IRQ,
  32. },
  33. [2] = {
  34. .start = 21,
  35. .end = 21,
  36. .flags = IORESOURCE_DMA,
  37. },
  38. [3] = {
  39. .start = 22,
  40. .end = 22,
  41. .flags = IORESOURCE_DMA,
  42. },
  43. };
  44. static u64 pxamci_dmamask = 0xffffffffUL;
  45. struct platform_device pxa_device_mci = {
  46. .name = "pxa2xx-mci",
  47. .id = 0,
  48. .dev = {
  49. .dma_mask = &pxamci_dmamask,
  50. .coherent_dma_mask = 0xffffffff,
  51. },
  52. .num_resources = ARRAY_SIZE(pxamci_resources),
  53. .resource = pxamci_resources,
  54. };
  55. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  56. {
  57. pxa_register_device(&pxa_device_mci, info);
  58. }
  59. static struct pxa2xx_udc_mach_info pxa_udc_info;
  60. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  61. {
  62. memcpy(&pxa_udc_info, info, sizeof *info);
  63. }
  64. static struct resource pxa2xx_udc_resources[] = {
  65. [0] = {
  66. .start = 0x40600000,
  67. .end = 0x4060ffff,
  68. .flags = IORESOURCE_MEM,
  69. },
  70. [1] = {
  71. .start = IRQ_USB,
  72. .end = IRQ_USB,
  73. .flags = IORESOURCE_IRQ,
  74. },
  75. };
  76. static u64 udc_dma_mask = ~(u32)0;
  77. struct platform_device pxa_device_udc = {
  78. .name = "pxa2xx-udc",
  79. .id = -1,
  80. .resource = pxa2xx_udc_resources,
  81. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  82. .dev = {
  83. .platform_data = &pxa_udc_info,
  84. .dma_mask = &udc_dma_mask,
  85. }
  86. };
  87. static struct resource pxafb_resources[] = {
  88. [0] = {
  89. .start = 0x44000000,
  90. .end = 0x4400ffff,
  91. .flags = IORESOURCE_MEM,
  92. },
  93. [1] = {
  94. .start = IRQ_LCD,
  95. .end = IRQ_LCD,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. static u64 fb_dma_mask = ~(u64)0;
  100. struct platform_device pxa_device_fb = {
  101. .name = "pxa2xx-fb",
  102. .id = -1,
  103. .dev = {
  104. .dma_mask = &fb_dma_mask,
  105. .coherent_dma_mask = 0xffffffff,
  106. },
  107. .num_resources = ARRAY_SIZE(pxafb_resources),
  108. .resource = pxafb_resources,
  109. };
  110. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  111. {
  112. pxa_register_device(&pxa_device_fb, info);
  113. }
  114. void __init set_pxa_fb_parent(struct device *parent_dev)
  115. {
  116. pxa_device_fb.dev.parent = parent_dev;
  117. }
  118. static struct resource pxa_resource_ffuart[] = {
  119. {
  120. .start = __PREG(FFUART),
  121. .end = __PREG(FFUART) + 35,
  122. .flags = IORESOURCE_MEM,
  123. }, {
  124. .start = IRQ_FFUART,
  125. .end = IRQ_FFUART,
  126. .flags = IORESOURCE_IRQ,
  127. }
  128. };
  129. struct platform_device pxa_device_ffuart= {
  130. .name = "pxa2xx-uart",
  131. .id = 0,
  132. .resource = pxa_resource_ffuart,
  133. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  134. };
  135. static struct resource pxa_resource_btuart[] = {
  136. {
  137. .start = __PREG(BTUART),
  138. .end = __PREG(BTUART) + 35,
  139. .flags = IORESOURCE_MEM,
  140. }, {
  141. .start = IRQ_BTUART,
  142. .end = IRQ_BTUART,
  143. .flags = IORESOURCE_IRQ,
  144. }
  145. };
  146. struct platform_device pxa_device_btuart = {
  147. .name = "pxa2xx-uart",
  148. .id = 1,
  149. .resource = pxa_resource_btuart,
  150. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  151. };
  152. static struct resource pxa_resource_stuart[] = {
  153. {
  154. .start = __PREG(STUART),
  155. .end = __PREG(STUART) + 35,
  156. .flags = IORESOURCE_MEM,
  157. }, {
  158. .start = IRQ_STUART,
  159. .end = IRQ_STUART,
  160. .flags = IORESOURCE_IRQ,
  161. }
  162. };
  163. struct platform_device pxa_device_stuart = {
  164. .name = "pxa2xx-uart",
  165. .id = 2,
  166. .resource = pxa_resource_stuart,
  167. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  168. };
  169. static struct resource pxa_resource_hwuart[] = {
  170. {
  171. .start = __PREG(HWUART),
  172. .end = __PREG(HWUART) + 47,
  173. .flags = IORESOURCE_MEM,
  174. }, {
  175. .start = IRQ_HWUART,
  176. .end = IRQ_HWUART,
  177. .flags = IORESOURCE_IRQ,
  178. }
  179. };
  180. struct platform_device pxa_device_hwuart = {
  181. .name = "pxa2xx-uart",
  182. .id = 3,
  183. .resource = pxa_resource_hwuart,
  184. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  185. };
  186. static struct resource pxai2c_resources[] = {
  187. {
  188. .start = 0x40301680,
  189. .end = 0x403016a3,
  190. .flags = IORESOURCE_MEM,
  191. }, {
  192. .start = IRQ_I2C,
  193. .end = IRQ_I2C,
  194. .flags = IORESOURCE_IRQ,
  195. },
  196. };
  197. struct platform_device pxa_device_i2c = {
  198. .name = "pxa2xx-i2c",
  199. .id = 0,
  200. .resource = pxai2c_resources,
  201. .num_resources = ARRAY_SIZE(pxai2c_resources),
  202. };
  203. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  204. {
  205. pxa_register_device(&pxa_device_i2c, info);
  206. }
  207. static struct resource pxai2s_resources[] = {
  208. {
  209. .start = 0x40400000,
  210. .end = 0x40400083,
  211. .flags = IORESOURCE_MEM,
  212. }, {
  213. .start = IRQ_I2S,
  214. .end = IRQ_I2S,
  215. .flags = IORESOURCE_IRQ,
  216. },
  217. };
  218. struct platform_device pxa_device_i2s = {
  219. .name = "pxa2xx-i2s",
  220. .id = -1,
  221. .resource = pxai2s_resources,
  222. .num_resources = ARRAY_SIZE(pxai2s_resources),
  223. };
  224. static u64 pxaficp_dmamask = ~(u32)0;
  225. struct platform_device pxa_device_ficp = {
  226. .name = "pxa2xx-ir",
  227. .id = -1,
  228. .dev = {
  229. .dma_mask = &pxaficp_dmamask,
  230. .coherent_dma_mask = 0xffffffff,
  231. },
  232. };
  233. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  234. {
  235. pxa_register_device(&pxa_device_ficp, info);
  236. }
  237. struct platform_device pxa_device_rtc = {
  238. .name = "sa1100-rtc",
  239. .id = -1,
  240. };
  241. #ifdef CONFIG_PXA25x
  242. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  243. static struct resource pxa25x_resource_ssp[] = {
  244. [0] = {
  245. .start = 0x41000000,
  246. .end = 0x4100001f,
  247. .flags = IORESOURCE_MEM,
  248. },
  249. [1] = {
  250. .start = IRQ_SSP,
  251. .end = IRQ_SSP,
  252. .flags = IORESOURCE_IRQ,
  253. },
  254. [2] = {
  255. /* DRCMR for RX */
  256. .start = 13,
  257. .end = 13,
  258. .flags = IORESOURCE_DMA,
  259. },
  260. [3] = {
  261. /* DRCMR for TX */
  262. .start = 14,
  263. .end = 14,
  264. .flags = IORESOURCE_DMA,
  265. },
  266. };
  267. struct platform_device pxa25x_device_ssp = {
  268. .name = "pxa25x-ssp",
  269. .id = 0,
  270. .dev = {
  271. .dma_mask = &pxa25x_ssp_dma_mask,
  272. .coherent_dma_mask = DMA_BIT_MASK(32),
  273. },
  274. .resource = pxa25x_resource_ssp,
  275. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  276. };
  277. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  278. static struct resource pxa25x_resource_nssp[] = {
  279. [0] = {
  280. .start = 0x41400000,
  281. .end = 0x4140002f,
  282. .flags = IORESOURCE_MEM,
  283. },
  284. [1] = {
  285. .start = IRQ_NSSP,
  286. .end = IRQ_NSSP,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. [2] = {
  290. /* DRCMR for RX */
  291. .start = 15,
  292. .end = 15,
  293. .flags = IORESOURCE_DMA,
  294. },
  295. [3] = {
  296. /* DRCMR for TX */
  297. .start = 16,
  298. .end = 16,
  299. .flags = IORESOURCE_DMA,
  300. },
  301. };
  302. struct platform_device pxa25x_device_nssp = {
  303. .name = "pxa25x-nssp",
  304. .id = 1,
  305. .dev = {
  306. .dma_mask = &pxa25x_nssp_dma_mask,
  307. .coherent_dma_mask = DMA_BIT_MASK(32),
  308. },
  309. .resource = pxa25x_resource_nssp,
  310. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  311. };
  312. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  313. static struct resource pxa25x_resource_assp[] = {
  314. [0] = {
  315. .start = 0x41500000,
  316. .end = 0x4150002f,
  317. .flags = IORESOURCE_MEM,
  318. },
  319. [1] = {
  320. .start = IRQ_ASSP,
  321. .end = IRQ_ASSP,
  322. .flags = IORESOURCE_IRQ,
  323. },
  324. [2] = {
  325. /* DRCMR for RX */
  326. .start = 23,
  327. .end = 23,
  328. .flags = IORESOURCE_DMA,
  329. },
  330. [3] = {
  331. /* DRCMR for TX */
  332. .start = 24,
  333. .end = 24,
  334. .flags = IORESOURCE_DMA,
  335. },
  336. };
  337. struct platform_device pxa25x_device_assp = {
  338. /* ASSP is basically equivalent to NSSP */
  339. .name = "pxa25x-nssp",
  340. .id = 2,
  341. .dev = {
  342. .dma_mask = &pxa25x_assp_dma_mask,
  343. .coherent_dma_mask = DMA_BIT_MASK(32),
  344. },
  345. .resource = pxa25x_resource_assp,
  346. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  347. };
  348. #endif /* CONFIG_PXA25x */
  349. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  350. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  351. static struct resource pxa27x_resource_ohci[] = {
  352. [0] = {
  353. .start = 0x4C000000,
  354. .end = 0x4C00ff6f,
  355. .flags = IORESOURCE_MEM,
  356. },
  357. [1] = {
  358. .start = IRQ_USBH1,
  359. .end = IRQ_USBH1,
  360. .flags = IORESOURCE_IRQ,
  361. },
  362. };
  363. struct platform_device pxa27x_device_ohci = {
  364. .name = "pxa27x-ohci",
  365. .id = -1,
  366. .dev = {
  367. .dma_mask = &pxa27x_ohci_dma_mask,
  368. .coherent_dma_mask = DMA_BIT_MASK(32),
  369. },
  370. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  371. .resource = pxa27x_resource_ohci,
  372. };
  373. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  374. {
  375. pxa_register_device(&pxa27x_device_ohci, info);
  376. }
  377. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  378. static struct resource pxa27x_resource_ssp1[] = {
  379. [0] = {
  380. .start = 0x41000000,
  381. .end = 0x4100003f,
  382. .flags = IORESOURCE_MEM,
  383. },
  384. [1] = {
  385. .start = IRQ_SSP,
  386. .end = IRQ_SSP,
  387. .flags = IORESOURCE_IRQ,
  388. },
  389. [2] = {
  390. /* DRCMR for RX */
  391. .start = 13,
  392. .end = 13,
  393. .flags = IORESOURCE_DMA,
  394. },
  395. [3] = {
  396. /* DRCMR for TX */
  397. .start = 14,
  398. .end = 14,
  399. .flags = IORESOURCE_DMA,
  400. },
  401. };
  402. struct platform_device pxa27x_device_ssp1 = {
  403. .name = "pxa27x-ssp",
  404. .id = 0,
  405. .dev = {
  406. .dma_mask = &pxa27x_ssp1_dma_mask,
  407. .coherent_dma_mask = DMA_BIT_MASK(32),
  408. },
  409. .resource = pxa27x_resource_ssp1,
  410. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  411. };
  412. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  413. static struct resource pxa27x_resource_ssp2[] = {
  414. [0] = {
  415. .start = 0x41700000,
  416. .end = 0x4170003f,
  417. .flags = IORESOURCE_MEM,
  418. },
  419. [1] = {
  420. .start = IRQ_SSP2,
  421. .end = IRQ_SSP2,
  422. .flags = IORESOURCE_IRQ,
  423. },
  424. [2] = {
  425. /* DRCMR for RX */
  426. .start = 15,
  427. .end = 15,
  428. .flags = IORESOURCE_DMA,
  429. },
  430. [3] = {
  431. /* DRCMR for TX */
  432. .start = 16,
  433. .end = 16,
  434. .flags = IORESOURCE_DMA,
  435. },
  436. };
  437. struct platform_device pxa27x_device_ssp2 = {
  438. .name = "pxa27x-ssp",
  439. .id = 1,
  440. .dev = {
  441. .dma_mask = &pxa27x_ssp2_dma_mask,
  442. .coherent_dma_mask = DMA_BIT_MASK(32),
  443. },
  444. .resource = pxa27x_resource_ssp2,
  445. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  446. };
  447. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  448. static struct resource pxa27x_resource_ssp3[] = {
  449. [0] = {
  450. .start = 0x41900000,
  451. .end = 0x4190003f,
  452. .flags = IORESOURCE_MEM,
  453. },
  454. [1] = {
  455. .start = IRQ_SSP3,
  456. .end = IRQ_SSP3,
  457. .flags = IORESOURCE_IRQ,
  458. },
  459. [2] = {
  460. /* DRCMR for RX */
  461. .start = 66,
  462. .end = 66,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. [3] = {
  466. /* DRCMR for TX */
  467. .start = 67,
  468. .end = 67,
  469. .flags = IORESOURCE_DMA,
  470. },
  471. };
  472. struct platform_device pxa27x_device_ssp3 = {
  473. .name = "pxa27x-ssp",
  474. .id = 2,
  475. .dev = {
  476. .dma_mask = &pxa27x_ssp3_dma_mask,
  477. .coherent_dma_mask = DMA_BIT_MASK(32),
  478. },
  479. .resource = pxa27x_resource_ssp3,
  480. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  481. };
  482. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  483. #ifdef CONFIG_PXA3xx
  484. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  485. static struct resource pxa3xx_resource_ssp4[] = {
  486. [0] = {
  487. .start = 0x41a00000,
  488. .end = 0x41a0003f,
  489. .flags = IORESOURCE_MEM,
  490. },
  491. [1] = {
  492. .start = IRQ_SSP4,
  493. .end = IRQ_SSP4,
  494. .flags = IORESOURCE_IRQ,
  495. },
  496. [2] = {
  497. /* DRCMR for RX */
  498. .start = 2,
  499. .end = 2,
  500. .flags = IORESOURCE_DMA,
  501. },
  502. [3] = {
  503. /* DRCMR for TX */
  504. .start = 3,
  505. .end = 3,
  506. .flags = IORESOURCE_DMA,
  507. },
  508. };
  509. struct platform_device pxa3xx_device_ssp4 = {
  510. /* PXA3xx SSP is basically equivalent to PXA27x */
  511. .name = "pxa27x-ssp",
  512. .id = 3,
  513. .dev = {
  514. .dma_mask = &pxa3xx_ssp4_dma_mask,
  515. .coherent_dma_mask = DMA_BIT_MASK(32),
  516. },
  517. .resource = pxa3xx_resource_ssp4,
  518. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  519. };
  520. static struct resource pxa3xx_resources_mci2[] = {
  521. [0] = {
  522. .start = 0x42000000,
  523. .end = 0x42000fff,
  524. .flags = IORESOURCE_MEM,
  525. },
  526. [1] = {
  527. .start = IRQ_MMC2,
  528. .end = IRQ_MMC2,
  529. .flags = IORESOURCE_IRQ,
  530. },
  531. [2] = {
  532. .start = 93,
  533. .end = 93,
  534. .flags = IORESOURCE_DMA,
  535. },
  536. [3] = {
  537. .start = 94,
  538. .end = 94,
  539. .flags = IORESOURCE_DMA,
  540. },
  541. };
  542. struct platform_device pxa3xx_device_mci2 = {
  543. .name = "pxa2xx-mci",
  544. .id = 1,
  545. .dev = {
  546. .dma_mask = &pxamci_dmamask,
  547. .coherent_dma_mask = 0xffffffff,
  548. },
  549. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  550. .resource = pxa3xx_resources_mci2,
  551. };
  552. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  553. {
  554. pxa_register_device(&pxa3xx_device_mci2, info);
  555. }
  556. static struct resource pxa3xx_resources_mci3[] = {
  557. [0] = {
  558. .start = 0x42500000,
  559. .end = 0x42500fff,
  560. .flags = IORESOURCE_MEM,
  561. },
  562. [1] = {
  563. .start = IRQ_MMC3,
  564. .end = IRQ_MMC3,
  565. .flags = IORESOURCE_IRQ,
  566. },
  567. [2] = {
  568. .start = 100,
  569. .end = 100,
  570. .flags = IORESOURCE_DMA,
  571. },
  572. [3] = {
  573. .start = 101,
  574. .end = 101,
  575. .flags = IORESOURCE_DMA,
  576. },
  577. };
  578. struct platform_device pxa3xx_device_mci3 = {
  579. .name = "pxa2xx-mci",
  580. .id = 2,
  581. .dev = {
  582. .dma_mask = &pxamci_dmamask,
  583. .coherent_dma_mask = 0xffffffff,
  584. },
  585. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  586. .resource = pxa3xx_resources_mci3,
  587. };
  588. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  589. {
  590. pxa_register_device(&pxa3xx_device_mci3, info);
  591. }
  592. #endif /* CONFIG_PXA3xx */