netxen_nic.h 47 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #ifndef _NETXEN_NIC_H_
  31. #define _NETXEN_NIC_H_
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/types.h>
  35. #include <linux/compiler.h>
  36. #include <linux/slab.h>
  37. #include <linux/delay.h>
  38. #include <linux/init.h>
  39. #include <linux/ioport.h>
  40. #include <linux/pci.h>
  41. #include <linux/netdevice.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/ip.h>
  44. #include <linux/in.h>
  45. #include <linux/tcp.h>
  46. #include <linux/skbuff.h>
  47. #include <linux/ethtool.h>
  48. #include <linux/mii.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/timer.h>
  51. #include <linux/mm.h>
  52. #include <linux/mman.h>
  53. #include <linux/vmalloc.h>
  54. #include <asm/system.h>
  55. #include <asm/io.h>
  56. #include <asm/byteorder.h>
  57. #include <asm/uaccess.h>
  58. #include <asm/pgtable.h>
  59. #include "netxen_nic_hw.h"
  60. #define _NETXEN_NIC_LINUX_MAJOR 4
  61. #define _NETXEN_NIC_LINUX_MINOR 0
  62. #define _NETXEN_NIC_LINUX_SUBVERSION 11
  63. #define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
  64. #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
  65. #define NETXEN_NUM_FLASH_SECTORS (64)
  66. #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  67. #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
  68. * NETXEN_FLASH_SECTOR_SIZE)
  69. #define PHAN_VENDOR_ID 0x4040
  70. #define RCV_DESC_RINGSIZE \
  71. (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
  72. #define STATUS_DESC_RINGSIZE \
  73. (sizeof(struct status_desc)* adapter->max_rx_desc_count)
  74. #define LRO_DESC_RINGSIZE \
  75. (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
  76. #define TX_RINGSIZE \
  77. (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
  78. #define RCV_BUFFSIZE \
  79. (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
  80. #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  81. #define NETXEN_NETDEV_STATUS 0x1
  82. #define NETXEN_RCV_PRODUCER_OFFSET 0
  83. #define NETXEN_RCV_PEG_DB_ID 2
  84. #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  85. #define FLASH_SUCCESS 0
  86. #define ADDR_IN_WINDOW1(off) \
  87. ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  88. /*
  89. * normalize a 64MB crb address to 32MB PCI window
  90. * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  91. */
  92. #define NETXEN_CRB_NORMAL(reg) \
  93. ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  94. #define NETXEN_CRB_NORMALIZE(adapter, reg) \
  95. pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
  96. #define DB_NORMALIZE(adapter, off) \
  97. (adapter->ahw.db_base + (off))
  98. #define NX_P2_C0 0x24
  99. #define NX_P2_C1 0x25
  100. #define NX_P3_A0 0x30
  101. #define NX_P3_A2 0x30
  102. #define NX_P3_B0 0x40
  103. #define NX_P3_B1 0x41
  104. #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
  105. #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
  106. #define FIRST_PAGE_GROUP_START 0
  107. #define FIRST_PAGE_GROUP_END 0x100000
  108. #define SECOND_PAGE_GROUP_START 0x6000000
  109. #define SECOND_PAGE_GROUP_END 0x68BC000
  110. #define THIRD_PAGE_GROUP_START 0x70E4000
  111. #define THIRD_PAGE_GROUP_END 0x8000000
  112. #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
  113. #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
  114. #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
  115. #define P2_MAX_MTU (8000)
  116. #define P3_MAX_MTU (9600)
  117. #define NX_ETHERMTU 1500
  118. #define NX_MAX_ETHERHDR 32 /* This contains some padding */
  119. #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
  120. #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
  121. #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
  122. #define NX_CT_DEFAULT_RX_BUF_LEN 2048
  123. #define MAX_RX_BUFFER_LENGTH 1760
  124. #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
  125. #define MAX_RX_LRO_BUFFER_LENGTH (8062)
  126. #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
  127. #define RX_JUMBO_DMA_MAP_LEN \
  128. (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
  129. #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
  130. /*
  131. * Maximum number of ring contexts
  132. */
  133. #define MAX_RING_CTX 1
  134. /* Opcodes to be used with the commands */
  135. #define TX_ETHER_PKT 0x01
  136. #define TX_TCP_PKT 0x02
  137. #define TX_UDP_PKT 0x03
  138. #define TX_IP_PKT 0x04
  139. #define TX_TCP_LSO 0x05
  140. #define TX_TCP_LSO6 0x06
  141. #define TX_IPSEC 0x07
  142. #define TX_IPSEC_CMD 0x0a
  143. #define TX_TCPV6_PKT 0x0b
  144. #define TX_UDPV6_PKT 0x0c
  145. /* The following opcodes are for internal consumption. */
  146. #define NETXEN_CONTROL_OP 0x10
  147. #define PEGNET_REQUEST 0x11
  148. #define MAX_NUM_CARDS 4
  149. #define MAX_BUFFERS_PER_CMD 32
  150. /*
  151. * Following are the states of the Phantom. Phantom will set them and
  152. * Host will read to check if the fields are correct.
  153. */
  154. #define PHAN_INITIALIZE_START 0xff00
  155. #define PHAN_INITIALIZE_FAILED 0xffff
  156. #define PHAN_INITIALIZE_COMPLETE 0xff01
  157. /* Host writes the following to notify that it has done the init-handshake */
  158. #define PHAN_INITIALIZE_ACK 0xf00f
  159. #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
  160. /* descriptor types */
  161. #define RCV_DESC_NORMAL 0x01
  162. #define RCV_DESC_JUMBO 0x02
  163. #define RCV_DESC_LRO 0x04
  164. #define RCV_DESC_NORMAL_CTXID 0
  165. #define RCV_DESC_JUMBO_CTXID 1
  166. #define RCV_DESC_LRO_CTXID 2
  167. #define RCV_DESC_TYPE(ID) \
  168. ((ID == RCV_DESC_JUMBO_CTXID) \
  169. ? RCV_DESC_JUMBO \
  170. : ((ID == RCV_DESC_LRO_CTXID) \
  171. ? RCV_DESC_LRO : \
  172. (RCV_DESC_NORMAL)))
  173. #define MAX_CMD_DESCRIPTORS 4096
  174. #define MAX_RCV_DESCRIPTORS 16384
  175. #define MAX_CMD_DESCRIPTORS_HOST 1024
  176. #define MAX_RCV_DESCRIPTORS_1G 2048
  177. #define MAX_RCV_DESCRIPTORS_10G 4096
  178. #define MAX_JUMBO_RCV_DESCRIPTORS 1024
  179. #define MAX_LRO_RCV_DESCRIPTORS 8
  180. #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
  181. #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
  182. #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
  183. #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
  184. #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
  185. #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
  186. MAX_LRO_RCV_DESCRIPTORS)
  187. #define MIN_TX_COUNT 4096
  188. #define MIN_RX_COUNT 4096
  189. #define NETXEN_CTX_SIGNATURE 0xdee0
  190. #define NETXEN_RCV_PRODUCER(ringid) (ringid)
  191. #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
  192. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  193. #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
  194. #define get_next_index(index, length) \
  195. (((index) + 1) & ((length) - 1))
  196. #define get_index_range(index,length,count) \
  197. (((index) + (count)) & ((length) - 1))
  198. #define MPORT_SINGLE_FUNCTION_MODE 0x1111
  199. #define MPORT_MULTI_FUNCTION_MODE 0x2222
  200. #include "netxen_nic_phan_reg.h"
  201. /*
  202. * NetXen host-peg signal message structure
  203. *
  204. * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
  205. * Bit 2 : priv_id => must be 1
  206. * Bit 3-17 : count => for doorbell
  207. * Bit 18-27 : ctx_id => Context id
  208. * Bit 28-31 : opcode
  209. */
  210. typedef u32 netxen_ctx_msg;
  211. #define netxen_set_msg_peg_id(config_word, val) \
  212. ((config_word) &= ~3, (config_word) |= val & 3)
  213. #define netxen_set_msg_privid(config_word) \
  214. ((config_word) |= 1 << 2)
  215. #define netxen_set_msg_count(config_word, val) \
  216. ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
  217. #define netxen_set_msg_ctxid(config_word, val) \
  218. ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
  219. #define netxen_set_msg_opcode(config_word, val) \
  220. ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
  221. struct netxen_rcv_context {
  222. __le64 rcv_ring_addr;
  223. __le32 rcv_ring_size;
  224. __le32 rsrvd;
  225. };
  226. struct netxen_ring_ctx {
  227. /* one command ring */
  228. __le64 cmd_consumer_offset;
  229. __le64 cmd_ring_addr;
  230. __le32 cmd_ring_size;
  231. __le32 rsrvd;
  232. /* three receive rings */
  233. struct netxen_rcv_context rcv_ctx[3];
  234. /* one status ring */
  235. __le64 sts_ring_addr;
  236. __le32 sts_ring_size;
  237. __le32 ctx_id;
  238. } __attribute__ ((aligned(64)));
  239. /*
  240. * Following data structures describe the descriptors that will be used.
  241. * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
  242. * we are doing LSO (above the 1500 size packet) only.
  243. */
  244. /*
  245. * The size of reference handle been changed to 16 bits to pass the MSS fields
  246. * for the LSO packet
  247. */
  248. #define FLAGS_CHECKSUM_ENABLED 0x01
  249. #define FLAGS_LSO_ENABLED 0x02
  250. #define FLAGS_IPSEC_SA_ADD 0x04
  251. #define FLAGS_IPSEC_SA_DELETE 0x08
  252. #define FLAGS_VLAN_TAGGED 0x10
  253. #define netxen_set_cmd_desc_port(cmd_desc, var) \
  254. ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
  255. #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
  256. ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
  257. #define netxen_set_tx_port(_desc, _port) \
  258. (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
  259. #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
  260. (_desc)->flags_opcode = \
  261. cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
  262. #define netxen_set_tx_frags_len(_desc, _frags, _len) \
  263. (_desc)->num_of_buffers_total_length = \
  264. cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
  265. struct cmd_desc_type0 {
  266. u8 tcp_hdr_offset; /* For LSO only */
  267. u8 ip_hdr_offset; /* For LSO only */
  268. /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
  269. __le16 flags_opcode;
  270. /* Bit pattern: 0-7 total number of segments,
  271. 8-31 Total size of the packet */
  272. __le32 num_of_buffers_total_length;
  273. union {
  274. struct {
  275. __le32 addr_low_part2;
  276. __le32 addr_high_part2;
  277. };
  278. __le64 addr_buffer2;
  279. };
  280. __le16 reference_handle; /* changed to u16 to add mss */
  281. __le16 mss; /* passed by NDIS_PACKET for LSO */
  282. /* Bit pattern 0-3 port, 0-3 ctx id */
  283. u8 port_ctxid;
  284. u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
  285. __le16 conn_id; /* IPSec offoad only */
  286. union {
  287. struct {
  288. __le32 addr_low_part3;
  289. __le32 addr_high_part3;
  290. };
  291. __le64 addr_buffer3;
  292. };
  293. union {
  294. struct {
  295. __le32 addr_low_part1;
  296. __le32 addr_high_part1;
  297. };
  298. __le64 addr_buffer1;
  299. };
  300. __le16 buffer1_length;
  301. __le16 buffer2_length;
  302. __le16 buffer3_length;
  303. __le16 buffer4_length;
  304. union {
  305. struct {
  306. __le32 addr_low_part4;
  307. __le32 addr_high_part4;
  308. };
  309. __le64 addr_buffer4;
  310. };
  311. __le64 unused;
  312. } __attribute__ ((aligned(64)));
  313. /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
  314. struct rcv_desc {
  315. __le16 reference_handle;
  316. __le16 reserved;
  317. __le32 buffer_length; /* allocated buffer length (usually 2K) */
  318. __le64 addr_buffer;
  319. };
  320. /* opcode field in status_desc */
  321. #define NETXEN_NIC_RXPKT_DESC 0x04
  322. #define NETXEN_OLD_RXPKT_DESC 0x3f
  323. /* for status field in status_desc */
  324. #define STATUS_NEED_CKSUM (1)
  325. #define STATUS_CKSUM_OK (2)
  326. /* owner bits of status_desc */
  327. #define STATUS_OWNER_HOST (0x1ULL << 56)
  328. #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
  329. /* Note: sizeof(status_desc) should always be a mutliple of 2 */
  330. #define netxen_get_sts_desc_lro_cnt(status_desc) \
  331. ((status_desc)->lro & 0x7F)
  332. #define netxen_get_sts_desc_lro_last_frag(status_desc) \
  333. (((status_desc)->lro & 0x80) >> 7)
  334. #define netxen_get_sts_port(sts_data) \
  335. ((sts_data) & 0x0F)
  336. #define netxen_get_sts_status(sts_data) \
  337. (((sts_data) >> 4) & 0x0F)
  338. #define netxen_get_sts_type(sts_data) \
  339. (((sts_data) >> 8) & 0x0F)
  340. #define netxen_get_sts_totallength(sts_data) \
  341. (((sts_data) >> 12) & 0xFFFF)
  342. #define netxen_get_sts_refhandle(sts_data) \
  343. (((sts_data) >> 28) & 0xFFFF)
  344. #define netxen_get_sts_prot(sts_data) \
  345. (((sts_data) >> 44) & 0x0F)
  346. #define netxen_get_sts_pkt_offset(sts_data) \
  347. (((sts_data) >> 48) & 0x1F)
  348. #define netxen_get_sts_opcode(sts_data) \
  349. (((sts_data) >> 58) & 0x03F)
  350. struct status_desc {
  351. /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
  352. 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
  353. 53-55 desc_cnt, 56-57 owner, 58-63 opcode
  354. */
  355. __le64 status_desc_data;
  356. union {
  357. struct {
  358. __le32 hash_value;
  359. u8 hash_type;
  360. u8 msg_type;
  361. u8 unused;
  362. union {
  363. /* Bit pattern: 0-6 lro_count indicates frag
  364. * sequence, 7 last_frag indicates last frag
  365. */
  366. u8 lro;
  367. /* chained buffers */
  368. u8 nr_frags;
  369. };
  370. };
  371. struct {
  372. __le16 frag_handles[4];
  373. };
  374. };
  375. } __attribute__ ((aligned(16)));
  376. enum {
  377. NETXEN_RCV_PEG_0 = 0,
  378. NETXEN_RCV_PEG_1
  379. };
  380. /* The version of the main data structure */
  381. #define NETXEN_BDINFO_VERSION 1
  382. /* Magic number to let user know flash is programmed */
  383. #define NETXEN_BDINFO_MAGIC 0x12345678
  384. /* Max number of Gig ports on a Phantom board */
  385. #define NETXEN_MAX_PORTS 4
  386. typedef enum {
  387. NETXEN_BRDTYPE_P1_BD = 0x0000,
  388. NETXEN_BRDTYPE_P1_SB = 0x0001,
  389. NETXEN_BRDTYPE_P1_SMAX = 0x0002,
  390. NETXEN_BRDTYPE_P1_SOCK = 0x0003,
  391. NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
  392. NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
  393. NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
  394. NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
  395. NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
  396. NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
  397. NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
  398. NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
  399. NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
  400. NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
  401. NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
  402. NETXEN_BRDTYPE_P3_4_GB = 0x0024,
  403. NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
  404. NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
  405. NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
  406. NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
  407. NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
  408. NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
  409. NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
  410. NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
  411. NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
  412. NETXEN_BRDTYPE_P3_10G_TP = 0x0080
  413. } netxen_brdtype_t;
  414. typedef enum {
  415. NETXEN_BRDMFG_INVENTEC = 1
  416. } netxen_brdmfg;
  417. typedef enum {
  418. MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
  419. MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
  420. MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
  421. MEM_ORG_256Mbx4 = 0x3,
  422. MEM_ORG_256Mbx8 = 0x4,
  423. MEM_ORG_256Mbx16 = 0x5,
  424. MEM_ORG_512Mbx4 = 0x6,
  425. MEM_ORG_512Mbx8 = 0x7,
  426. MEM_ORG_512Mbx16 = 0x8,
  427. MEM_ORG_1Gbx4 = 0x9,
  428. MEM_ORG_1Gbx8 = 0xa,
  429. MEM_ORG_1Gbx16 = 0xb,
  430. MEM_ORG_2Gbx4 = 0xc,
  431. MEM_ORG_2Gbx8 = 0xd,
  432. MEM_ORG_2Gbx16 = 0xe,
  433. MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
  434. MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
  435. } netxen_mn_mem_org_t;
  436. typedef enum {
  437. MEM_ORG_512Kx36 = 0x0,
  438. MEM_ORG_1Mx36 = 0x1,
  439. MEM_ORG_2Mx36 = 0x2
  440. } netxen_sn_mem_org_t;
  441. typedef enum {
  442. MEM_DEPTH_4MB = 0x1,
  443. MEM_DEPTH_8MB = 0x2,
  444. MEM_DEPTH_16MB = 0x3,
  445. MEM_DEPTH_32MB = 0x4,
  446. MEM_DEPTH_64MB = 0x5,
  447. MEM_DEPTH_128MB = 0x6,
  448. MEM_DEPTH_256MB = 0x7,
  449. MEM_DEPTH_512MB = 0x8,
  450. MEM_DEPTH_1GB = 0x9,
  451. MEM_DEPTH_2GB = 0xa,
  452. MEM_DEPTH_4GB = 0xb,
  453. MEM_DEPTH_8GB = 0xc,
  454. MEM_DEPTH_16GB = 0xd,
  455. MEM_DEPTH_32GB = 0xe
  456. } netxen_mem_depth_t;
  457. struct netxen_board_info {
  458. u32 header_version;
  459. u32 board_mfg;
  460. u32 board_type;
  461. u32 board_num;
  462. u32 chip_id;
  463. u32 chip_minor;
  464. u32 chip_major;
  465. u32 chip_pkg;
  466. u32 chip_lot;
  467. u32 port_mask; /* available niu ports */
  468. u32 peg_mask; /* available pegs */
  469. u32 icache_ok; /* can we run with icache? */
  470. u32 dcache_ok; /* can we run with dcache? */
  471. u32 casper_ok;
  472. u32 mac_addr_lo_0;
  473. u32 mac_addr_lo_1;
  474. u32 mac_addr_lo_2;
  475. u32 mac_addr_lo_3;
  476. /* MN-related config */
  477. u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
  478. u32 mn_sync_shift_cclk;
  479. u32 mn_sync_shift_mclk;
  480. u32 mn_wb_en;
  481. u32 mn_crystal_freq; /* in MHz */
  482. u32 mn_speed; /* in MHz */
  483. u32 mn_org;
  484. u32 mn_depth;
  485. u32 mn_ranks_0; /* ranks per slot */
  486. u32 mn_ranks_1; /* ranks per slot */
  487. u32 mn_rd_latency_0;
  488. u32 mn_rd_latency_1;
  489. u32 mn_rd_latency_2;
  490. u32 mn_rd_latency_3;
  491. u32 mn_rd_latency_4;
  492. u32 mn_rd_latency_5;
  493. u32 mn_rd_latency_6;
  494. u32 mn_rd_latency_7;
  495. u32 mn_rd_latency_8;
  496. u32 mn_dll_val[18];
  497. u32 mn_mode_reg; /* MIU DDR Mode Register */
  498. u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
  499. u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
  500. u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
  501. u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
  502. /* SN-related config */
  503. u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
  504. u32 sn_pt_mode; /* pass through mode */
  505. u32 sn_ecc_en;
  506. u32 sn_wb_en;
  507. u32 sn_crystal_freq;
  508. u32 sn_speed;
  509. u32 sn_org;
  510. u32 sn_depth;
  511. u32 sn_dll_tap;
  512. u32 sn_rd_latency;
  513. u32 mac_addr_hi_0;
  514. u32 mac_addr_hi_1;
  515. u32 mac_addr_hi_2;
  516. u32 mac_addr_hi_3;
  517. u32 magic; /* indicates flash has been initialized */
  518. u32 mn_rdimm;
  519. u32 mn_dll_override;
  520. };
  521. #define FLASH_NUM_PORTS (4)
  522. struct netxen_flash_mac_addr {
  523. u32 flash_addr[32];
  524. };
  525. struct netxen_user_old_info {
  526. u8 flash_md5[16];
  527. u8 crbinit_md5[16];
  528. u8 brdcfg_md5[16];
  529. /* bootloader */
  530. u32 bootld_version;
  531. u32 bootld_size;
  532. u8 bootld_md5[16];
  533. /* image */
  534. u32 image_version;
  535. u32 image_size;
  536. u8 image_md5[16];
  537. /* primary image status */
  538. u32 primary_status;
  539. u32 secondary_present;
  540. /* MAC address , 4 ports */
  541. struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
  542. };
  543. #define FLASH_NUM_MAC_PER_PORT 32
  544. struct netxen_user_info {
  545. u8 flash_md5[16 * 64];
  546. /* bootloader */
  547. u32 bootld_version;
  548. u32 bootld_size;
  549. /* image */
  550. u32 image_version;
  551. u32 image_size;
  552. /* primary image status */
  553. u32 primary_status;
  554. u32 secondary_present;
  555. /* MAC address , 4 ports, 32 address per port */
  556. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  557. u32 sub_sys_id;
  558. u8 serial_num[32];
  559. /* Any user defined data */
  560. };
  561. /*
  562. * Flash Layout - new format.
  563. */
  564. struct netxen_new_user_info {
  565. u8 flash_md5[16 * 64];
  566. /* bootloader */
  567. u32 bootld_version;
  568. u32 bootld_size;
  569. /* image */
  570. u32 image_version;
  571. u32 image_size;
  572. /* primary image status */
  573. u32 primary_status;
  574. u32 secondary_present;
  575. /* MAC address , 4 ports, 32 address per port */
  576. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  577. u32 sub_sys_id;
  578. u8 serial_num[32];
  579. /* Any user defined data */
  580. };
  581. #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
  582. #define SECONDARY_IMAGE_ABSENT 0xffffffff
  583. #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
  584. #define PRIMARY_IMAGE_BAD 0xffffffff
  585. /* Flash memory map */
  586. typedef enum {
  587. NETXEN_CRBINIT_START = 0, /* Crbinit section */
  588. NETXEN_BRDCFG_START = 0x4000, /* board config */
  589. NETXEN_INITCODE_START = 0x6000, /* pegtune code */
  590. NETXEN_BOOTLD_START = 0x10000, /* bootld */
  591. NETXEN_IMAGE_START = 0x43000, /* compressed image */
  592. NETXEN_SECONDARY_START = 0x200000, /* backup images */
  593. NETXEN_PXE_START = 0x3E0000, /* user defined region */
  594. NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
  595. NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
  596. } netxen_flash_map_t;
  597. #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
  598. #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
  599. #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
  600. #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
  601. #define NX_FW_MIN_SIZE (0x3fffff)
  602. #define NX_P2_MN_ROMIMAGE "nxromimg.bin"
  603. #define NX_P3_CT_ROMIMAGE "nx3fwct.bin"
  604. #define NX_P3_MN_ROMIMAGE "nx3fwmn.bin"
  605. #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
  606. #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
  607. #define NETXEN_INIT_SECTOR (0)
  608. #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
  609. #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
  610. #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
  611. #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
  612. #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
  613. #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
  614. #define NETXEN_NUM_CONFIG_SECTORS (1)
  615. #define PFX "NetXen: "
  616. extern char netxen_nic_driver_name[];
  617. /* Note: Make sure to not call this before adapter->port is valid */
  618. #if !defined(NETXEN_DEBUG)
  619. #define DPRINTK(klevel, fmt, args...) do { \
  620. } while (0)
  621. #else
  622. #define DPRINTK(klevel, fmt, args...) do { \
  623. printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
  624. (adapter != NULL && adapter->netdev != NULL) ? \
  625. adapter->netdev->name : NULL, \
  626. ## args); } while(0)
  627. #endif
  628. /* Number of status descriptors to handle per interrupt */
  629. #define MAX_STATUS_HANDLE (128)
  630. /*
  631. * netxen_skb_frag{} is to contain mapping info for each SG list. This
  632. * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
  633. */
  634. struct netxen_skb_frag {
  635. u64 dma;
  636. ulong length;
  637. };
  638. #define _netxen_set_bits(config_word, start, bits, val) {\
  639. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
  640. unsigned long long __tvalue = (val); \
  641. (config_word) &= ~__tmask; \
  642. (config_word) |= (((__tvalue) << (start)) & __tmask); \
  643. }
  644. #define _netxen_clear_bits(config_word, start, bits) {\
  645. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
  646. (config_word) &= ~__tmask; \
  647. }
  648. /* Following defines are for the state of the buffers */
  649. #define NETXEN_BUFFER_FREE 0
  650. #define NETXEN_BUFFER_BUSY 1
  651. /*
  652. * There will be one netxen_buffer per skb packet. These will be
  653. * used to save the dma info for pci_unmap_page()
  654. */
  655. struct netxen_cmd_buffer {
  656. struct sk_buff *skb;
  657. struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
  658. u32 frag_count;
  659. };
  660. /* In rx_buffer, we do not need multiple fragments as is a single buffer */
  661. struct netxen_rx_buffer {
  662. struct list_head list;
  663. struct sk_buff *skb;
  664. u64 dma;
  665. u16 ref_handle;
  666. u16 state;
  667. u32 lro_expected_frags;
  668. u32 lro_current_frags;
  669. u32 lro_length;
  670. };
  671. /* Board types */
  672. #define NETXEN_NIC_GBE 0x01
  673. #define NETXEN_NIC_XGBE 0x02
  674. /*
  675. * One hardware_context{} per adapter
  676. * contains interrupt info as well shared hardware info.
  677. */
  678. struct netxen_hardware_context {
  679. void __iomem *pci_base0;
  680. void __iomem *pci_base1;
  681. void __iomem *pci_base2;
  682. unsigned long first_page_group_end;
  683. unsigned long first_page_group_start;
  684. void __iomem *db_base;
  685. unsigned long db_len;
  686. unsigned long pci_len0;
  687. u8 cut_through;
  688. int qdr_sn_window;
  689. int ddr_mn_window;
  690. unsigned long mn_win_crb;
  691. unsigned long ms_win_crb;
  692. u8 revision_id;
  693. u16 board_type;
  694. struct netxen_board_info boardcfg;
  695. u32 linkup;
  696. /* Address of cmd ring in Phantom */
  697. struct cmd_desc_type0 *cmd_desc_head;
  698. dma_addr_t cmd_desc_phys_addr;
  699. struct netxen_adapter *adapter;
  700. int pci_func;
  701. };
  702. #define RCV_RING_LRO RCV_DESC_LRO
  703. #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
  704. #define ETHERNET_FCS_SIZE 4
  705. struct netxen_adapter_stats {
  706. u64 rcvdbadskb;
  707. u64 xmitcalled;
  708. u64 xmitedframes;
  709. u64 xmitfinished;
  710. u64 badskblen;
  711. u64 nocmddescriptor;
  712. u64 polled;
  713. u64 rxdropped;
  714. u64 txdropped;
  715. u64 csummed;
  716. u64 no_rcv;
  717. u64 rxbytes;
  718. u64 txbytes;
  719. u64 ints;
  720. };
  721. /*
  722. * Rcv Descriptor Context. One such per Rcv Descriptor. There may
  723. * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
  724. */
  725. struct nx_host_rds_ring {
  726. u32 flags;
  727. u32 producer;
  728. dma_addr_t phys_addr;
  729. u32 crb_rcv_producer; /* reg offset */
  730. struct rcv_desc *desc_head; /* address of rx ring in Phantom */
  731. u32 max_rx_desc_count;
  732. u32 dma_size;
  733. u32 skb_size;
  734. struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
  735. struct list_head free_list;
  736. };
  737. /*
  738. * Receive context. There is one such structure per instance of the
  739. * receive processing. Any state information that is relevant to
  740. * the receive, and is must be in this structure. The global data may be
  741. * present elsewhere.
  742. */
  743. struct netxen_recv_context {
  744. u32 state;
  745. u16 context_id;
  746. u16 virt_port;
  747. struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
  748. u32 status_rx_consumer;
  749. u32 crb_sts_consumer; /* reg offset */
  750. dma_addr_t rcv_status_desc_phys_addr;
  751. struct status_desc *rcv_status_desc_head;
  752. };
  753. /* New HW context creation */
  754. #define NX_OS_CRB_RETRY_COUNT 4000
  755. #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
  756. (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
  757. #define NX_CDRP_CLEAR 0x00000000
  758. #define NX_CDRP_CMD_BIT 0x80000000
  759. /*
  760. * All responses must have the NX_CDRP_CMD_BIT cleared
  761. * in the crb NX_CDRP_CRB_OFFSET.
  762. */
  763. #define NX_CDRP_FORM_RSP(rsp) (rsp)
  764. #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
  765. #define NX_CDRP_RSP_OK 0x00000001
  766. #define NX_CDRP_RSP_FAIL 0x00000002
  767. #define NX_CDRP_RSP_TIMEOUT 0x00000003
  768. /*
  769. * All commands must have the NX_CDRP_CMD_BIT set in
  770. * the crb NX_CDRP_CRB_OFFSET.
  771. */
  772. #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
  773. #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
  774. #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
  775. #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
  776. #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
  777. #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
  778. #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
  779. #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
  780. #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
  781. #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
  782. #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
  783. #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
  784. #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
  785. #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
  786. #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
  787. #define NX_CDRP_CMD_SET_MTU 0x00000012
  788. #define NX_CDRP_CMD_MAX 0x00000013
  789. #define NX_RCODE_SUCCESS 0
  790. #define NX_RCODE_NO_HOST_MEM 1
  791. #define NX_RCODE_NO_HOST_RESOURCE 2
  792. #define NX_RCODE_NO_CARD_CRB 3
  793. #define NX_RCODE_NO_CARD_MEM 4
  794. #define NX_RCODE_NO_CARD_RESOURCE 5
  795. #define NX_RCODE_INVALID_ARGS 6
  796. #define NX_RCODE_INVALID_ACTION 7
  797. #define NX_RCODE_INVALID_STATE 8
  798. #define NX_RCODE_NOT_SUPPORTED 9
  799. #define NX_RCODE_NOT_PERMITTED 10
  800. #define NX_RCODE_NOT_READY 11
  801. #define NX_RCODE_DOES_NOT_EXIST 12
  802. #define NX_RCODE_ALREADY_EXISTS 13
  803. #define NX_RCODE_BAD_SIGNATURE 14
  804. #define NX_RCODE_CMD_NOT_IMPL 15
  805. #define NX_RCODE_CMD_INVALID 16
  806. #define NX_RCODE_TIMEOUT 17
  807. #define NX_RCODE_CMD_FAILED 18
  808. #define NX_RCODE_MAX_EXCEEDED 19
  809. #define NX_RCODE_MAX 20
  810. #define NX_DESTROY_CTX_RESET 0
  811. #define NX_DESTROY_CTX_D3_RESET 1
  812. #define NX_DESTROY_CTX_MAX 2
  813. /*
  814. * Capabilities
  815. */
  816. #define NX_CAP_BIT(class, bit) (1 << bit)
  817. #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
  818. #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
  819. #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
  820. #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
  821. #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
  822. #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
  823. #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
  824. #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
  825. #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
  826. /*
  827. * Context state
  828. */
  829. #define NX_HOST_CTX_STATE_FREED 0
  830. #define NX_HOST_CTX_STATE_ALLOCATED 1
  831. #define NX_HOST_CTX_STATE_ACTIVE 2
  832. #define NX_HOST_CTX_STATE_DISABLED 3
  833. #define NX_HOST_CTX_STATE_QUIESCED 4
  834. #define NX_HOST_CTX_STATE_MAX 5
  835. /*
  836. * Rx context
  837. */
  838. typedef struct {
  839. __le64 host_phys_addr; /* Ring base addr */
  840. __le32 ring_size; /* Ring entries */
  841. __le16 msi_index;
  842. __le16 rsvd; /* Padding */
  843. } nx_hostrq_sds_ring_t;
  844. typedef struct {
  845. __le64 host_phys_addr; /* Ring base addr */
  846. __le64 buff_size; /* Packet buffer size */
  847. __le32 ring_size; /* Ring entries */
  848. __le32 ring_kind; /* Class of ring */
  849. } nx_hostrq_rds_ring_t;
  850. typedef struct {
  851. __le64 host_rsp_dma_addr; /* Response dma'd here */
  852. __le32 capabilities[4]; /* Flag bit vector */
  853. __le32 host_int_crb_mode; /* Interrupt crb usage */
  854. __le32 host_rds_crb_mode; /* RDS crb usage */
  855. /* These ring offsets are relative to data[0] below */
  856. __le32 rds_ring_offset; /* Offset to RDS config */
  857. __le32 sds_ring_offset; /* Offset to SDS config */
  858. __le16 num_rds_rings; /* Count of RDS rings */
  859. __le16 num_sds_rings; /* Count of SDS rings */
  860. __le16 rsvd1; /* Padding */
  861. __le16 rsvd2; /* Padding */
  862. u8 reserved[128]; /* reserve space for future expansion*/
  863. /* MUST BE 64-bit aligned.
  864. The following is packed:
  865. - N hostrq_rds_rings
  866. - N hostrq_sds_rings */
  867. char data[0];
  868. } nx_hostrq_rx_ctx_t;
  869. typedef struct {
  870. __le32 host_producer_crb; /* Crb to use */
  871. __le32 rsvd1; /* Padding */
  872. } nx_cardrsp_rds_ring_t;
  873. typedef struct {
  874. __le32 host_consumer_crb; /* Crb to use */
  875. __le32 interrupt_crb; /* Crb to use */
  876. } nx_cardrsp_sds_ring_t;
  877. typedef struct {
  878. /* These ring offsets are relative to data[0] below */
  879. __le32 rds_ring_offset; /* Offset to RDS config */
  880. __le32 sds_ring_offset; /* Offset to SDS config */
  881. __le32 host_ctx_state; /* Starting State */
  882. __le32 num_fn_per_port; /* How many PCI fn share the port */
  883. __le16 num_rds_rings; /* Count of RDS rings */
  884. __le16 num_sds_rings; /* Count of SDS rings */
  885. __le16 context_id; /* Handle for context */
  886. u8 phys_port; /* Physical id of port */
  887. u8 virt_port; /* Virtual/Logical id of port */
  888. u8 reserved[128]; /* save space for future expansion */
  889. /* MUST BE 64-bit aligned.
  890. The following is packed:
  891. - N cardrsp_rds_rings
  892. - N cardrs_sds_rings */
  893. char data[0];
  894. } nx_cardrsp_rx_ctx_t;
  895. #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
  896. (sizeof(HOSTRQ_RX) + \
  897. (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
  898. (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
  899. #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
  900. (sizeof(CARDRSP_RX) + \
  901. (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
  902. (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
  903. /*
  904. * Tx context
  905. */
  906. typedef struct {
  907. __le64 host_phys_addr; /* Ring base addr */
  908. __le32 ring_size; /* Ring entries */
  909. __le32 rsvd; /* Padding */
  910. } nx_hostrq_cds_ring_t;
  911. typedef struct {
  912. __le64 host_rsp_dma_addr; /* Response dma'd here */
  913. __le64 cmd_cons_dma_addr; /* */
  914. __le64 dummy_dma_addr; /* */
  915. __le32 capabilities[4]; /* Flag bit vector */
  916. __le32 host_int_crb_mode; /* Interrupt crb usage */
  917. __le32 rsvd1; /* Padding */
  918. __le16 rsvd2; /* Padding */
  919. __le16 interrupt_ctl;
  920. __le16 msi_index;
  921. __le16 rsvd3; /* Padding */
  922. nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
  923. u8 reserved[128]; /* future expansion */
  924. } nx_hostrq_tx_ctx_t;
  925. typedef struct {
  926. __le32 host_producer_crb; /* Crb to use */
  927. __le32 interrupt_crb; /* Crb to use */
  928. } nx_cardrsp_cds_ring_t;
  929. typedef struct {
  930. __le32 host_ctx_state; /* Starting state */
  931. __le16 context_id; /* Handle for context */
  932. u8 phys_port; /* Physical id of port */
  933. u8 virt_port; /* Virtual/Logical id of port */
  934. nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
  935. u8 reserved[128]; /* future expansion */
  936. } nx_cardrsp_tx_ctx_t;
  937. #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
  938. #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
  939. /* CRB */
  940. #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
  941. #define NX_HOST_RDS_CRB_MODE_SHARED 1
  942. #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
  943. #define NX_HOST_RDS_CRB_MODE_MAX 3
  944. #define NX_HOST_INT_CRB_MODE_UNIQUE 0
  945. #define NX_HOST_INT_CRB_MODE_SHARED 1
  946. #define NX_HOST_INT_CRB_MODE_NORX 2
  947. #define NX_HOST_INT_CRB_MODE_NOTX 3
  948. #define NX_HOST_INT_CRB_MODE_NORXTX 4
  949. /* MAC */
  950. #define MC_COUNT_P2 16
  951. #define MC_COUNT_P3 38
  952. #define NETXEN_MAC_NOOP 0
  953. #define NETXEN_MAC_ADD 1
  954. #define NETXEN_MAC_DEL 2
  955. typedef struct nx_mac_list_s {
  956. struct nx_mac_list_s *next;
  957. uint8_t mac_addr[MAX_ADDR_LEN];
  958. } nx_mac_list_t;
  959. /*
  960. * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
  961. * adjusted based on configured MTU.
  962. */
  963. #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
  964. #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
  965. #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
  966. #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
  967. #define NETXEN_NIC_INTR_DEFAULT 0x04
  968. typedef union {
  969. struct {
  970. uint16_t rx_packets;
  971. uint16_t rx_time_us;
  972. uint16_t tx_packets;
  973. uint16_t tx_time_us;
  974. } data;
  975. uint64_t word;
  976. } nx_nic_intr_coalesce_data_t;
  977. typedef struct {
  978. uint16_t stats_time_us;
  979. uint16_t rate_sample_time;
  980. uint16_t flags;
  981. uint16_t rsvd_1;
  982. uint32_t low_threshold;
  983. uint32_t high_threshold;
  984. nx_nic_intr_coalesce_data_t normal;
  985. nx_nic_intr_coalesce_data_t low;
  986. nx_nic_intr_coalesce_data_t high;
  987. nx_nic_intr_coalesce_data_t irq;
  988. } nx_nic_intr_coalesce_t;
  989. #define NX_HOST_REQUEST 0x13
  990. #define NX_NIC_REQUEST 0x14
  991. #define NX_MAC_EVENT 0x1
  992. enum {
  993. NX_NIC_H2C_OPCODE_START = 0,
  994. NX_NIC_H2C_OPCODE_CONFIG_RSS,
  995. NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
  996. NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
  997. NX_NIC_H2C_OPCODE_CONFIG_LED,
  998. NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
  999. NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
  1000. NX_NIC_H2C_OPCODE_LRO_REQUEST,
  1001. NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
  1002. NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
  1003. NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
  1004. NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
  1005. NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
  1006. NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
  1007. NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
  1008. NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
  1009. NX_NIC_H2C_OPCODE_GET_NET_STATS,
  1010. NX_NIC_H2C_OPCODE_LAST
  1011. };
  1012. #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
  1013. #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
  1014. #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
  1015. typedef struct {
  1016. __le64 qhdr;
  1017. __le64 req_hdr;
  1018. __le64 words[6];
  1019. } nx_nic_req_t;
  1020. typedef struct {
  1021. u8 op;
  1022. u8 tag;
  1023. u8 mac_addr[6];
  1024. } nx_mac_req_t;
  1025. #define MAX_PENDING_DESC_BLOCK_SIZE 64
  1026. #define NETXEN_NIC_MSI_ENABLED 0x02
  1027. #define NETXEN_NIC_MSIX_ENABLED 0x04
  1028. #define NETXEN_IS_MSI_FAMILY(adapter) \
  1029. ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
  1030. #define MSIX_ENTRIES_PER_ADAPTER 1
  1031. #define NETXEN_MSIX_TBL_SPACE 8192
  1032. #define NETXEN_PCI_REG_MSIX_TBL 0x44
  1033. #define NETXEN_DB_MAPSIZE_BYTES 0x1000
  1034. #define NETXEN_NETDEV_WEIGHT 120
  1035. #define NETXEN_ADAPTER_UP_MAGIC 777
  1036. #define NETXEN_NIC_PEG_TUNE 0
  1037. struct netxen_dummy_dma {
  1038. void *addr;
  1039. dma_addr_t phys_addr;
  1040. };
  1041. struct netxen_adapter {
  1042. struct netxen_hardware_context ahw;
  1043. struct net_device *netdev;
  1044. struct pci_dev *pdev;
  1045. int pci_using_dac;
  1046. struct napi_struct napi;
  1047. struct net_device_stats net_stats;
  1048. int mtu;
  1049. int portnum;
  1050. u8 physical_port;
  1051. u16 tx_context_id;
  1052. uint8_t mc_enabled;
  1053. uint8_t max_mc_count;
  1054. nx_mac_list_t *mac_list;
  1055. struct netxen_legacy_intr_set legacy_intr;
  1056. u32 crb_intr_mask;
  1057. struct work_struct watchdog_task;
  1058. struct timer_list watchdog_timer;
  1059. struct work_struct tx_timeout_task;
  1060. u32 curr_window;
  1061. u32 crb_win;
  1062. rwlock_t adapter_lock;
  1063. u32 cmd_producer;
  1064. __le32 *cmd_consumer;
  1065. u32 last_cmd_consumer;
  1066. u32 crb_addr_cmd_producer;
  1067. u32 crb_addr_cmd_consumer;
  1068. u32 max_tx_desc_count;
  1069. u32 max_rx_desc_count;
  1070. u32 max_jumbo_rx_desc_count;
  1071. u32 max_lro_rx_desc_count;
  1072. int max_rds_rings;
  1073. u32 flags;
  1074. u32 irq;
  1075. int driver_mismatch;
  1076. u32 temp;
  1077. u32 fw_major;
  1078. u8 msix_supported;
  1079. u8 max_possible_rss_rings;
  1080. struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
  1081. struct netxen_adapter_stats stats;
  1082. u16 link_speed;
  1083. u16 link_duplex;
  1084. u16 state;
  1085. u16 link_autoneg;
  1086. int rx_csum;
  1087. int status;
  1088. struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
  1089. /*
  1090. * Receive instances. These can be either one per port,
  1091. * or one per peg, etc.
  1092. */
  1093. struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
  1094. int is_up;
  1095. struct netxen_dummy_dma dummy_dma;
  1096. nx_nic_intr_coalesce_t coal;
  1097. /* Context interface shared between card and host */
  1098. struct netxen_ring_ctx *ctx_desc;
  1099. dma_addr_t ctx_desc_phys_addr;
  1100. int intr_scheme;
  1101. int msi_mode;
  1102. int (*enable_phy_interrupts) (struct netxen_adapter *);
  1103. int (*disable_phy_interrupts) (struct netxen_adapter *);
  1104. int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
  1105. int (*set_mtu) (struct netxen_adapter *, int);
  1106. int (*set_promisc) (struct netxen_adapter *, u32);
  1107. int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
  1108. int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
  1109. int (*init_port) (struct netxen_adapter *, int);
  1110. int (*stop_port) (struct netxen_adapter *);
  1111. int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
  1112. int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
  1113. int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
  1114. int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
  1115. int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
  1116. u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
  1117. void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
  1118. u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
  1119. unsigned long (*pci_set_window)(struct netxen_adapter *,
  1120. unsigned long long);
  1121. }; /* netxen_adapter structure */
  1122. /*
  1123. * NetXen dma watchdog control structure
  1124. *
  1125. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1126. * Bit 1 : disable_request => 1 req disable dma watchdog
  1127. * Bit 2 : enable_request => 1 req enable dma watchdog
  1128. * Bit 3-31 : unused
  1129. */
  1130. #define netxen_set_dma_watchdog_disable_req(config_word) \
  1131. _netxen_set_bits(config_word, 1, 1, 1)
  1132. #define netxen_set_dma_watchdog_enable_req(config_word) \
  1133. _netxen_set_bits(config_word, 2, 1, 1)
  1134. #define netxen_get_dma_watchdog_enabled(config_word) \
  1135. ((config_word) & 0x1)
  1136. #define netxen_get_dma_watchdog_disabled(config_word) \
  1137. (((config_word) >> 1) & 0x1)
  1138. /* Max number of xmit producer threads that can run simultaneously */
  1139. #define MAX_XMIT_PRODUCERS 16
  1140. #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
  1141. ((adapter)->ahw.pci_base0 + (off))
  1142. #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
  1143. ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
  1144. #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
  1145. ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
  1146. static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
  1147. unsigned long off)
  1148. {
  1149. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  1150. return (adapter->ahw.pci_base0 + off);
  1151. } else if ((off < SECOND_PAGE_GROUP_END) &&
  1152. (off >= SECOND_PAGE_GROUP_START)) {
  1153. return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
  1154. } else if ((off < THIRD_PAGE_GROUP_END) &&
  1155. (off >= THIRD_PAGE_GROUP_START)) {
  1156. return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
  1157. }
  1158. return NULL;
  1159. }
  1160. static inline void __iomem *pci_base(struct netxen_adapter *adapter,
  1161. unsigned long off)
  1162. {
  1163. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  1164. return adapter->ahw.pci_base0;
  1165. } else if ((off < SECOND_PAGE_GROUP_END) &&
  1166. (off >= SECOND_PAGE_GROUP_START)) {
  1167. return adapter->ahw.pci_base1;
  1168. } else if ((off < THIRD_PAGE_GROUP_END) &&
  1169. (off >= THIRD_PAGE_GROUP_START)) {
  1170. return adapter->ahw.pci_base2;
  1171. }
  1172. return NULL;
  1173. }
  1174. int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1175. int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1176. int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1177. int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1178. int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
  1179. __u32 * readval);
  1180. int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
  1181. long reg, __u32 val);
  1182. /* Functions available from netxen_nic_hw.c */
  1183. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
  1184. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
  1185. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
  1186. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
  1187. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
  1188. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
  1189. void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
  1190. void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
  1191. int netxen_nic_get_board_info(struct netxen_adapter *adapter);
  1192. int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
  1193. ulong off, void *data, int len);
  1194. int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
  1195. ulong off, void *data, int len);
  1196. int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
  1197. u64 off, void *data, int size);
  1198. int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
  1199. u64 off, void *data, int size);
  1200. int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
  1201. u64 off, u32 data);
  1202. u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
  1203. void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
  1204. u64 off, u32 data);
  1205. u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
  1206. unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
  1207. unsigned long long addr);
  1208. void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
  1209. u32 wndw);
  1210. int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
  1211. ulong off, void *data, int len);
  1212. int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
  1213. ulong off, void *data, int len);
  1214. int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
  1215. u64 off, void *data, int size);
  1216. int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
  1217. u64 off, void *data, int size);
  1218. void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
  1219. unsigned long off, int data);
  1220. int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
  1221. u64 off, u32 data);
  1222. u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
  1223. void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
  1224. u64 off, u32 data);
  1225. u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
  1226. unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
  1227. unsigned long long addr);
  1228. /* Functions from netxen_nic_init.c */
  1229. void netxen_free_adapter_offload(struct netxen_adapter *adapter);
  1230. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
  1231. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
  1232. int netxen_receive_peg_ready(struct netxen_adapter *adapter);
  1233. int netxen_load_firmware(struct netxen_adapter *adapter);
  1234. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
  1235. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
  1236. int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  1237. u8 *bytes, size_t size);
  1238. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  1239. u8 *bytes, size_t size);
  1240. int netxen_flash_unlock(struct netxen_adapter *adapter);
  1241. int netxen_backup_crbinit(struct netxen_adapter *adapter);
  1242. int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
  1243. int netxen_flash_erase_primary(struct netxen_adapter *adapter);
  1244. void netxen_halt_pegs(struct netxen_adapter *adapter);
  1245. int netxen_rom_se(struct netxen_adapter *adapter, int addr);
  1246. int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
  1247. void netxen_free_sw_resources(struct netxen_adapter *adapter);
  1248. int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
  1249. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  1250. void netxen_release_rx_buffers(struct netxen_adapter *adapter);
  1251. void netxen_release_tx_buffers(struct netxen_adapter *adapter);
  1252. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
  1253. int netxen_init_firmware(struct netxen_adapter *adapter);
  1254. void netxen_nic_clear_stats(struct netxen_adapter *adapter);
  1255. void netxen_watchdog_task(struct work_struct *work);
  1256. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
  1257. u32 ringid);
  1258. int netxen_process_cmd_ring(struct netxen_adapter *adapter);
  1259. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
  1260. void netxen_p2_nic_set_multi(struct net_device *netdev);
  1261. void netxen_p3_nic_set_multi(struct net_device *netdev);
  1262. void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
  1263. int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
  1264. int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
  1265. int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
  1266. int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
  1267. int netxen_nic_set_mac(struct net_device *netdev, void *p);
  1268. struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
  1269. void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
  1270. uint32_t crb_producer);
  1271. /*
  1272. * NetXen Board information
  1273. */
  1274. #define NETXEN_MAX_SHORT_NAME 32
  1275. struct netxen_brdinfo {
  1276. netxen_brdtype_t brdtype; /* type of board */
  1277. long ports; /* max no of physical ports */
  1278. char short_name[NETXEN_MAX_SHORT_NAME];
  1279. };
  1280. static const struct netxen_brdinfo netxen_boards[] = {
  1281. {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
  1282. {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
  1283. {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
  1284. {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
  1285. {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
  1286. {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
  1287. {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
  1288. {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
  1289. {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
  1290. {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
  1291. {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
  1292. {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
  1293. {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
  1294. {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
  1295. {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
  1296. {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
  1297. {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
  1298. {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
  1299. {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
  1300. };
  1301. #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
  1302. static inline void get_brd_name_by_type(u32 type, char *name)
  1303. {
  1304. int i, found = 0;
  1305. for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
  1306. if (netxen_boards[i].brdtype == type) {
  1307. strcpy(name, netxen_boards[i].short_name);
  1308. found = 1;
  1309. break;
  1310. }
  1311. }
  1312. if (!found)
  1313. name = "Unknown";
  1314. }
  1315. static inline int
  1316. dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
  1317. {
  1318. u32 ctrl;
  1319. /* check if already inactive */
  1320. if (adapter->hw_read_wx(adapter,
  1321. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1322. printk(KERN_ERR "failed to read dma watchdog status\n");
  1323. if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
  1324. return 1;
  1325. /* Send the disable request */
  1326. netxen_set_dma_watchdog_disable_req(ctrl);
  1327. netxen_crb_writelit_adapter(adapter,
  1328. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1329. return 0;
  1330. }
  1331. static inline int
  1332. dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
  1333. {
  1334. u32 ctrl;
  1335. if (adapter->hw_read_wx(adapter,
  1336. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1337. printk(KERN_ERR "failed to read dma watchdog status\n");
  1338. return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
  1339. }
  1340. static inline int
  1341. dma_watchdog_wakeup(struct netxen_adapter *adapter)
  1342. {
  1343. u32 ctrl;
  1344. if (adapter->hw_read_wx(adapter,
  1345. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1346. printk(KERN_ERR "failed to read dma watchdog status\n");
  1347. if (netxen_get_dma_watchdog_enabled(ctrl))
  1348. return 1;
  1349. /* send the wakeup request */
  1350. netxen_set_dma_watchdog_enable_req(ctrl);
  1351. netxen_crb_writelit_adapter(adapter,
  1352. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1353. return 0;
  1354. }
  1355. int netxen_is_flash_supported(struct netxen_adapter *adapter);
  1356. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1357. int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1358. extern void netxen_change_ringparam(struct netxen_adapter *adapter);
  1359. extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
  1360. int *valp);
  1361. extern struct ethtool_ops netxen_nic_ethtool_ops;
  1362. #endif /* __NETXEN_NIC_H_ */