intel_hdmi.c 26 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Jesse Barnes <jesse.barnes@intel.com>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  39. {
  40. return container_of(encoder, struct intel_hdmi, base.base);
  41. }
  42. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  43. {
  44. return container_of(intel_attached_encoder(connector),
  45. struct intel_hdmi, base);
  46. }
  47. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  48. {
  49. uint8_t *data = (uint8_t *)frame;
  50. uint8_t sum = 0;
  51. unsigned i;
  52. frame->checksum = 0;
  53. frame->ecc = 0;
  54. for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  55. sum += data[i];
  56. frame->checksum = 0x100 - sum;
  57. }
  58. static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  59. {
  60. switch (frame->type) {
  61. case DIP_TYPE_AVI:
  62. return VIDEO_DIP_SELECT_AVI;
  63. case DIP_TYPE_SPD:
  64. return VIDEO_DIP_SELECT_SPD;
  65. default:
  66. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  67. return 0;
  68. }
  69. }
  70. static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  71. {
  72. switch (frame->type) {
  73. case DIP_TYPE_AVI:
  74. return VIDEO_DIP_ENABLE_AVI;
  75. case DIP_TYPE_SPD:
  76. return VIDEO_DIP_ENABLE_SPD;
  77. default:
  78. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  79. return 0;
  80. }
  81. }
  82. static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
  83. {
  84. switch (frame->type) {
  85. case DIP_TYPE_AVI:
  86. return VIDEO_DIP_ENABLE_AVI_HSW;
  87. case DIP_TYPE_SPD:
  88. return VIDEO_DIP_ENABLE_SPD_HSW;
  89. default:
  90. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  91. return 0;
  92. }
  93. }
  94. static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
  95. {
  96. switch (frame->type) {
  97. case DIP_TYPE_AVI:
  98. return HSW_TVIDEO_DIP_AVI_DATA(pipe);
  99. case DIP_TYPE_SPD:
  100. return HSW_TVIDEO_DIP_SPD_DATA(pipe);
  101. default:
  102. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  103. return 0;
  104. }
  105. }
  106. static void g4x_write_infoframe(struct drm_encoder *encoder,
  107. struct dip_infoframe *frame)
  108. {
  109. uint32_t *data = (uint32_t *)frame;
  110. struct drm_device *dev = encoder->dev;
  111. struct drm_i915_private *dev_priv = dev->dev_private;
  112. u32 val = I915_READ(VIDEO_DIP_CTL);
  113. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  114. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  115. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  116. val |= g4x_infoframe_index(frame);
  117. val &= ~g4x_infoframe_enable(frame);
  118. I915_WRITE(VIDEO_DIP_CTL, val);
  119. for (i = 0; i < len; i += 4) {
  120. I915_WRITE(VIDEO_DIP_DATA, *data);
  121. data++;
  122. }
  123. val |= g4x_infoframe_enable(frame);
  124. val &= ~VIDEO_DIP_FREQ_MASK;
  125. val |= VIDEO_DIP_FREQ_VSYNC;
  126. I915_WRITE(VIDEO_DIP_CTL, val);
  127. }
  128. static void ibx_write_infoframe(struct drm_encoder *encoder,
  129. struct dip_infoframe *frame)
  130. {
  131. uint32_t *data = (uint32_t *)frame;
  132. struct drm_device *dev = encoder->dev;
  133. struct drm_i915_private *dev_priv = dev->dev_private;
  134. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  135. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  136. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  137. u32 val = I915_READ(reg);
  138. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  139. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  140. val |= g4x_infoframe_index(frame);
  141. val &= ~g4x_infoframe_enable(frame);
  142. I915_WRITE(reg, val);
  143. for (i = 0; i < len; i += 4) {
  144. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  145. data++;
  146. }
  147. val |= g4x_infoframe_enable(frame);
  148. val &= ~VIDEO_DIP_FREQ_MASK;
  149. val |= VIDEO_DIP_FREQ_VSYNC;
  150. I915_WRITE(reg, val);
  151. }
  152. static void cpt_write_infoframe(struct drm_encoder *encoder,
  153. struct dip_infoframe *frame)
  154. {
  155. uint32_t *data = (uint32_t *)frame;
  156. struct drm_device *dev = encoder->dev;
  157. struct drm_i915_private *dev_priv = dev->dev_private;
  158. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  159. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  160. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  161. u32 val = I915_READ(reg);
  162. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  163. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  164. val |= g4x_infoframe_index(frame);
  165. /* The DIP control register spec says that we need to update the AVI
  166. * infoframe without clearing its enable bit */
  167. if (frame->type != DIP_TYPE_AVI)
  168. val &= ~g4x_infoframe_enable(frame);
  169. I915_WRITE(reg, val);
  170. for (i = 0; i < len; i += 4) {
  171. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  172. data++;
  173. }
  174. val |= g4x_infoframe_enable(frame);
  175. val &= ~VIDEO_DIP_FREQ_MASK;
  176. val |= VIDEO_DIP_FREQ_VSYNC;
  177. I915_WRITE(reg, val);
  178. }
  179. static void vlv_write_infoframe(struct drm_encoder *encoder,
  180. struct dip_infoframe *frame)
  181. {
  182. uint32_t *data = (uint32_t *)frame;
  183. struct drm_device *dev = encoder->dev;
  184. struct drm_i915_private *dev_priv = dev->dev_private;
  185. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  186. int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  187. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  188. u32 val = I915_READ(reg);
  189. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  190. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  191. val |= g4x_infoframe_index(frame);
  192. val &= ~g4x_infoframe_enable(frame);
  193. I915_WRITE(reg, val);
  194. for (i = 0; i < len; i += 4) {
  195. I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  196. data++;
  197. }
  198. val |= g4x_infoframe_enable(frame);
  199. val &= ~VIDEO_DIP_FREQ_MASK;
  200. val |= VIDEO_DIP_FREQ_VSYNC;
  201. I915_WRITE(reg, val);
  202. }
  203. static void hsw_write_infoframe(struct drm_encoder *encoder,
  204. struct dip_infoframe *frame)
  205. {
  206. uint32_t *data = (uint32_t *)frame;
  207. struct drm_device *dev = encoder->dev;
  208. struct drm_i915_private *dev_priv = dev->dev_private;
  209. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  210. u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  211. u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
  212. unsigned int i, len = DIP_HEADER_SIZE + frame->len;
  213. u32 val = I915_READ(ctl_reg);
  214. if (data_reg == 0)
  215. return;
  216. val &= ~hsw_infoframe_enable(frame);
  217. I915_WRITE(ctl_reg, val);
  218. for (i = 0; i < len; i += 4) {
  219. I915_WRITE(data_reg + i, *data);
  220. data++;
  221. }
  222. val |= hsw_infoframe_enable(frame);
  223. I915_WRITE(ctl_reg, val);
  224. }
  225. static void intel_set_infoframe(struct drm_encoder *encoder,
  226. struct dip_infoframe *frame)
  227. {
  228. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  229. intel_dip_infoframe_csum(frame);
  230. intel_hdmi->write_infoframe(encoder, frame);
  231. }
  232. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  233. struct drm_display_mode *adjusted_mode)
  234. {
  235. struct dip_infoframe avi_if = {
  236. .type = DIP_TYPE_AVI,
  237. .ver = DIP_VERSION_AVI,
  238. .len = DIP_LEN_AVI,
  239. };
  240. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  241. avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
  242. intel_set_infoframe(encoder, &avi_if);
  243. }
  244. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  245. {
  246. struct dip_infoframe spd_if;
  247. memset(&spd_if, 0, sizeof(spd_if));
  248. spd_if.type = DIP_TYPE_SPD;
  249. spd_if.ver = DIP_VERSION_SPD;
  250. spd_if.len = DIP_LEN_SPD;
  251. strcpy(spd_if.body.spd.vn, "Intel");
  252. strcpy(spd_if.body.spd.pd, "Integrated gfx");
  253. spd_if.body.spd.sdi = DIP_SPD_PC;
  254. intel_set_infoframe(encoder, &spd_if);
  255. }
  256. static void g4x_set_infoframes(struct drm_encoder *encoder,
  257. struct drm_display_mode *adjusted_mode)
  258. {
  259. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  260. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  261. u32 reg = VIDEO_DIP_CTL;
  262. u32 val = I915_READ(reg);
  263. /* If the registers were not initialized yet, they might be zeroes,
  264. * which means we're selecting the AVI DIP and we're setting its
  265. * frequency to once. This seems to really confuse the HW and make
  266. * things stop working (the register spec says the AVI always needs to
  267. * be sent every VSync). So here we avoid writing to the register more
  268. * than we need and also explicitly select the AVI DIP and explicitly
  269. * set its frequency to every VSync. Avoiding to write it twice seems to
  270. * be enough to solve the problem, but being defensive shouldn't hurt us
  271. * either. */
  272. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  273. if (!intel_hdmi->has_hdmi_sink) {
  274. if (!(val & VIDEO_DIP_ENABLE))
  275. return;
  276. val &= ~VIDEO_DIP_ENABLE;
  277. I915_WRITE(reg, val);
  278. return;
  279. }
  280. val &= ~VIDEO_DIP_PORT_MASK;
  281. switch (intel_hdmi->sdvox_reg) {
  282. case SDVOB:
  283. val |= VIDEO_DIP_PORT_B;
  284. break;
  285. case SDVOC:
  286. val |= VIDEO_DIP_PORT_C;
  287. break;
  288. default:
  289. return;
  290. }
  291. val |= VIDEO_DIP_ENABLE;
  292. val &= ~VIDEO_DIP_ENABLE_VENDOR;
  293. I915_WRITE(reg, val);
  294. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  295. intel_hdmi_set_spd_infoframe(encoder);
  296. }
  297. static void ibx_set_infoframes(struct drm_encoder *encoder,
  298. struct drm_display_mode *adjusted_mode)
  299. {
  300. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  301. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  302. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  303. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  304. u32 val = I915_READ(reg);
  305. /* See the big comment in g4x_set_infoframes() */
  306. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  307. if (!intel_hdmi->has_hdmi_sink) {
  308. if (!(val & VIDEO_DIP_ENABLE))
  309. return;
  310. val &= ~VIDEO_DIP_ENABLE;
  311. I915_WRITE(reg, val);
  312. return;
  313. }
  314. val &= ~VIDEO_DIP_PORT_MASK;
  315. switch (intel_hdmi->sdvox_reg) {
  316. case HDMIB:
  317. val |= VIDEO_DIP_PORT_B;
  318. break;
  319. case HDMIC:
  320. val |= VIDEO_DIP_PORT_C;
  321. break;
  322. case HDMID:
  323. val |= VIDEO_DIP_PORT_D;
  324. break;
  325. default:
  326. return;
  327. }
  328. val |= VIDEO_DIP_ENABLE;
  329. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  330. VIDEO_DIP_ENABLE_GCP);
  331. I915_WRITE(reg, val);
  332. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  333. intel_hdmi_set_spd_infoframe(encoder);
  334. }
  335. static void cpt_set_infoframes(struct drm_encoder *encoder,
  336. struct drm_display_mode *adjusted_mode)
  337. {
  338. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  339. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  340. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  341. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  342. u32 val = I915_READ(reg);
  343. /* See the big comment in g4x_set_infoframes() */
  344. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  345. if (!intel_hdmi->has_hdmi_sink) {
  346. if (!(val & VIDEO_DIP_ENABLE))
  347. return;
  348. val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
  349. I915_WRITE(reg, val);
  350. return;
  351. }
  352. /* Set both together, unset both together: see the spec. */
  353. val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  354. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  355. VIDEO_DIP_ENABLE_GCP);
  356. I915_WRITE(reg, val);
  357. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  358. intel_hdmi_set_spd_infoframe(encoder);
  359. }
  360. static void vlv_set_infoframes(struct drm_encoder *encoder,
  361. struct drm_display_mode *adjusted_mode)
  362. {
  363. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  364. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  365. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  366. u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  367. u32 val = I915_READ(reg);
  368. /* See the big comment in g4x_set_infoframes() */
  369. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  370. if (!intel_hdmi->has_hdmi_sink) {
  371. if (!(val & VIDEO_DIP_ENABLE))
  372. return;
  373. val &= ~VIDEO_DIP_ENABLE;
  374. I915_WRITE(reg, val);
  375. return;
  376. }
  377. val |= VIDEO_DIP_ENABLE;
  378. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  379. VIDEO_DIP_ENABLE_GCP);
  380. I915_WRITE(reg, val);
  381. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  382. intel_hdmi_set_spd_infoframe(encoder);
  383. }
  384. static void hsw_set_infoframes(struct drm_encoder *encoder,
  385. struct drm_display_mode *adjusted_mode)
  386. {
  387. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  388. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  389. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  390. u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  391. u32 val = I915_READ(reg);
  392. if (!intel_hdmi->has_hdmi_sink) {
  393. I915_WRITE(reg, 0);
  394. return;
  395. }
  396. val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  397. VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
  398. I915_WRITE(reg, val);
  399. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  400. intel_hdmi_set_spd_infoframe(encoder);
  401. }
  402. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  403. struct drm_display_mode *mode,
  404. struct drm_display_mode *adjusted_mode)
  405. {
  406. struct drm_device *dev = encoder->dev;
  407. struct drm_i915_private *dev_priv = dev->dev_private;
  408. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  409. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  410. u32 sdvox;
  411. sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
  412. if (!HAS_PCH_SPLIT(dev))
  413. sdvox |= intel_hdmi->color_range;
  414. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  415. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  416. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  417. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  418. if (intel_crtc->bpp > 24)
  419. sdvox |= COLOR_FORMAT_12bpc;
  420. else
  421. sdvox |= COLOR_FORMAT_8bpc;
  422. /* Required on CPT */
  423. if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  424. sdvox |= HDMI_MODE_SELECT;
  425. if (intel_hdmi->has_audio) {
  426. DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  427. pipe_name(intel_crtc->pipe));
  428. sdvox |= SDVO_AUDIO_ENABLE;
  429. sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
  430. intel_write_eld(encoder, adjusted_mode);
  431. }
  432. if (HAS_PCH_CPT(dev))
  433. sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  434. else if (intel_crtc->pipe == 1)
  435. sdvox |= SDVO_PIPE_B_SELECT;
  436. I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
  437. POSTING_READ(intel_hdmi->sdvox_reg);
  438. intel_hdmi->set_infoframes(encoder, adjusted_mode);
  439. }
  440. static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
  441. {
  442. struct drm_device *dev = encoder->dev;
  443. struct drm_i915_private *dev_priv = dev->dev_private;
  444. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  445. u32 temp;
  446. u32 enable_bits = SDVO_ENABLE;
  447. if (intel_hdmi->has_audio)
  448. enable_bits |= SDVO_AUDIO_ENABLE;
  449. temp = I915_READ(intel_hdmi->sdvox_reg);
  450. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  451. * we do this anyway which shows more stable in testing.
  452. */
  453. if (HAS_PCH_SPLIT(dev)) {
  454. I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  455. POSTING_READ(intel_hdmi->sdvox_reg);
  456. }
  457. if (mode != DRM_MODE_DPMS_ON) {
  458. temp &= ~enable_bits;
  459. } else {
  460. temp |= enable_bits;
  461. }
  462. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  463. POSTING_READ(intel_hdmi->sdvox_reg);
  464. /* HW workaround, need to write this twice for issue that may result
  465. * in first write getting masked.
  466. */
  467. if (HAS_PCH_SPLIT(dev)) {
  468. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  469. POSTING_READ(intel_hdmi->sdvox_reg);
  470. }
  471. }
  472. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  473. struct drm_display_mode *mode)
  474. {
  475. if (mode->clock > 165000)
  476. return MODE_CLOCK_HIGH;
  477. if (mode->clock < 20000)
  478. return MODE_CLOCK_LOW;
  479. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  480. return MODE_NO_DBLESCAN;
  481. return MODE_OK;
  482. }
  483. static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  484. struct drm_display_mode *mode,
  485. struct drm_display_mode *adjusted_mode)
  486. {
  487. return true;
  488. }
  489. static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
  490. {
  491. struct drm_device *dev = intel_hdmi->base.base.dev;
  492. struct drm_i915_private *dev_priv = dev->dev_private;
  493. uint32_t bit;
  494. switch (intel_hdmi->sdvox_reg) {
  495. case SDVOB:
  496. bit = HDMIB_HOTPLUG_LIVE_STATUS;
  497. break;
  498. case SDVOC:
  499. bit = HDMIC_HOTPLUG_LIVE_STATUS;
  500. break;
  501. default:
  502. bit = 0;
  503. break;
  504. }
  505. return I915_READ(PORT_HOTPLUG_STAT) & bit;
  506. }
  507. static enum drm_connector_status
  508. intel_hdmi_detect(struct drm_connector *connector, bool force)
  509. {
  510. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  511. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  512. struct edid *edid;
  513. enum drm_connector_status status = connector_status_disconnected;
  514. if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
  515. return status;
  516. intel_hdmi->has_hdmi_sink = false;
  517. intel_hdmi->has_audio = false;
  518. edid = drm_get_edid(connector,
  519. intel_gmbus_get_adapter(dev_priv,
  520. intel_hdmi->ddc_bus));
  521. if (edid) {
  522. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  523. status = connector_status_connected;
  524. if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  525. intel_hdmi->has_hdmi_sink =
  526. drm_detect_hdmi_monitor(edid);
  527. intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  528. }
  529. connector->display_info.raw_edid = NULL;
  530. kfree(edid);
  531. }
  532. if (status == connector_status_connected) {
  533. if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  534. intel_hdmi->has_audio =
  535. (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  536. }
  537. return status;
  538. }
  539. static int intel_hdmi_get_modes(struct drm_connector *connector)
  540. {
  541. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  542. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  543. /* We should parse the EDID data and find out if it's an HDMI sink so
  544. * we can send audio to it.
  545. */
  546. return intel_ddc_get_modes(connector,
  547. intel_gmbus_get_adapter(dev_priv,
  548. intel_hdmi->ddc_bus));
  549. }
  550. static bool
  551. intel_hdmi_detect_audio(struct drm_connector *connector)
  552. {
  553. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  554. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  555. struct edid *edid;
  556. bool has_audio = false;
  557. edid = drm_get_edid(connector,
  558. intel_gmbus_get_adapter(dev_priv,
  559. intel_hdmi->ddc_bus));
  560. if (edid) {
  561. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  562. has_audio = drm_detect_monitor_audio(edid);
  563. connector->display_info.raw_edid = NULL;
  564. kfree(edid);
  565. }
  566. return has_audio;
  567. }
  568. static int
  569. intel_hdmi_set_property(struct drm_connector *connector,
  570. struct drm_property *property,
  571. uint64_t val)
  572. {
  573. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  574. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  575. int ret;
  576. ret = drm_connector_property_set_value(connector, property, val);
  577. if (ret)
  578. return ret;
  579. if (property == dev_priv->force_audio_property) {
  580. enum hdmi_force_audio i = val;
  581. bool has_audio;
  582. if (i == intel_hdmi->force_audio)
  583. return 0;
  584. intel_hdmi->force_audio = i;
  585. if (i == HDMI_AUDIO_AUTO)
  586. has_audio = intel_hdmi_detect_audio(connector);
  587. else
  588. has_audio = (i == HDMI_AUDIO_ON);
  589. if (i == HDMI_AUDIO_OFF_DVI)
  590. intel_hdmi->has_hdmi_sink = 0;
  591. intel_hdmi->has_audio = has_audio;
  592. goto done;
  593. }
  594. if (property == dev_priv->broadcast_rgb_property) {
  595. if (val == !!intel_hdmi->color_range)
  596. return 0;
  597. intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  598. goto done;
  599. }
  600. return -EINVAL;
  601. done:
  602. if (intel_hdmi->base.base.crtc) {
  603. struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
  604. drm_crtc_helper_set_mode(crtc, &crtc->mode,
  605. crtc->x, crtc->y,
  606. crtc->fb);
  607. }
  608. return 0;
  609. }
  610. static void intel_hdmi_destroy(struct drm_connector *connector)
  611. {
  612. drm_sysfs_connector_remove(connector);
  613. drm_connector_cleanup(connector);
  614. kfree(connector);
  615. }
  616. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
  617. .dpms = intel_ddi_dpms,
  618. .mode_fixup = intel_hdmi_mode_fixup,
  619. .prepare = intel_encoder_prepare,
  620. .mode_set = intel_ddi_mode_set,
  621. .commit = intel_encoder_commit,
  622. };
  623. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  624. .dpms = intel_hdmi_dpms,
  625. .mode_fixup = intel_hdmi_mode_fixup,
  626. .prepare = intel_encoder_prepare,
  627. .mode_set = intel_hdmi_mode_set,
  628. .commit = intel_encoder_commit,
  629. };
  630. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  631. .dpms = drm_helper_connector_dpms,
  632. .detect = intel_hdmi_detect,
  633. .fill_modes = drm_helper_probe_single_connector_modes,
  634. .set_property = intel_hdmi_set_property,
  635. .destroy = intel_hdmi_destroy,
  636. };
  637. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  638. .get_modes = intel_hdmi_get_modes,
  639. .mode_valid = intel_hdmi_mode_valid,
  640. .best_encoder = intel_best_encoder,
  641. };
  642. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  643. .destroy = intel_encoder_destroy,
  644. };
  645. static void
  646. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  647. {
  648. intel_attach_force_audio_property(connector);
  649. intel_attach_broadcast_rgb_property(connector);
  650. }
  651. void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
  652. {
  653. struct drm_i915_private *dev_priv = dev->dev_private;
  654. struct drm_connector *connector;
  655. struct intel_encoder *intel_encoder;
  656. struct intel_connector *intel_connector;
  657. struct intel_hdmi *intel_hdmi;
  658. int i;
  659. intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
  660. if (!intel_hdmi)
  661. return;
  662. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  663. if (!intel_connector) {
  664. kfree(intel_hdmi);
  665. return;
  666. }
  667. intel_encoder = &intel_hdmi->base;
  668. drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  669. DRM_MODE_ENCODER_TMDS);
  670. connector = &intel_connector->base;
  671. drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  672. DRM_MODE_CONNECTOR_HDMIA);
  673. drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  674. intel_encoder->type = INTEL_OUTPUT_HDMI;
  675. connector->polled = DRM_CONNECTOR_POLL_HPD;
  676. connector->interlace_allowed = 1;
  677. connector->doublescan_allowed = 0;
  678. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  679. /* Set up the DDC bus. */
  680. if (sdvox_reg == SDVOB) {
  681. intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
  682. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  683. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  684. } else if (sdvox_reg == SDVOC) {
  685. intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
  686. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  687. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  688. } else if (sdvox_reg == HDMIB) {
  689. intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
  690. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  691. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  692. } else if (sdvox_reg == HDMIC) {
  693. intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
  694. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  695. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  696. } else if (sdvox_reg == HDMID) {
  697. intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
  698. intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  699. dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  700. } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
  701. DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
  702. intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
  703. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  704. intel_hdmi->ddi_port = PORT_B;
  705. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  706. } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
  707. DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
  708. intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
  709. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  710. intel_hdmi->ddi_port = PORT_C;
  711. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  712. } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
  713. DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
  714. intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
  715. intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  716. intel_hdmi->ddi_port = PORT_D;
  717. dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  718. } else {
  719. /* If we got an unknown sdvox_reg, things are pretty much broken
  720. * in a way that we should let the kernel know about it */
  721. BUG();
  722. }
  723. intel_hdmi->sdvox_reg = sdvox_reg;
  724. if (!HAS_PCH_SPLIT(dev)) {
  725. intel_hdmi->write_infoframe = g4x_write_infoframe;
  726. intel_hdmi->set_infoframes = g4x_set_infoframes;
  727. I915_WRITE(VIDEO_DIP_CTL, 0);
  728. } else if (IS_VALLEYVIEW(dev)) {
  729. intel_hdmi->write_infoframe = vlv_write_infoframe;
  730. intel_hdmi->set_infoframes = vlv_set_infoframes;
  731. for_each_pipe(i)
  732. I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
  733. } else if (IS_HASWELL(dev)) {
  734. /* FIXME: Haswell has a new set of DIP frame registers, but we are
  735. * just doing the minimal required for HDMI to work at this stage.
  736. */
  737. intel_hdmi->write_infoframe = hsw_write_infoframe;
  738. intel_hdmi->set_infoframes = hsw_set_infoframes;
  739. for_each_pipe(i)
  740. I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
  741. } else if (HAS_PCH_IBX(dev)) {
  742. intel_hdmi->write_infoframe = ibx_write_infoframe;
  743. intel_hdmi->set_infoframes = ibx_set_infoframes;
  744. for_each_pipe(i)
  745. I915_WRITE(TVIDEO_DIP_CTL(i), 0);
  746. } else {
  747. intel_hdmi->write_infoframe = cpt_write_infoframe;
  748. intel_hdmi->set_infoframes = cpt_set_infoframes;
  749. for_each_pipe(i)
  750. I915_WRITE(TVIDEO_DIP_CTL(i), 0);
  751. }
  752. if (IS_HASWELL(dev))
  753. drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
  754. else
  755. drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
  756. intel_hdmi_add_properties(intel_hdmi, connector);
  757. intel_connector_attach_encoder(intel_connector, intel_encoder);
  758. drm_sysfs_connector_add(connector);
  759. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  760. * 0xd. Failure to do so will result in spurious interrupts being
  761. * generated on the port when a cable is not attached.
  762. */
  763. if (IS_G4X(dev) && !IS_GM45(dev)) {
  764. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  765. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  766. }
  767. }