ql4_mbx.c 35 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182
  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. /* Make sure that pointers are valid */
  33. if (!mbx_cmd || !mbx_sts) {
  34. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  35. "pointer\n", ha->host_no, __func__));
  36. return status;
  37. }
  38. if (is_qla8022(ha) &&
  39. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  40. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: prematurely "
  41. "completing mbx cmd as firmware recovery detected\n",
  42. ha->host_no, __func__));
  43. return status;
  44. }
  45. if ((is_aer_supported(ha)) &&
  46. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  47. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  48. "timeout MBX Exiting.\n", ha->host_no, __func__));
  49. return status;
  50. }
  51. /* Mailbox code active */
  52. wait_count = MBOX_TOV * 100;
  53. while (wait_count--) {
  54. mutex_lock(&ha->mbox_sem);
  55. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  56. set_bit(AF_MBOX_COMMAND, &ha->flags);
  57. mutex_unlock(&ha->mbox_sem);
  58. break;
  59. }
  60. mutex_unlock(&ha->mbox_sem);
  61. if (!wait_count) {
  62. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  63. ha->host_no, __func__));
  64. return status;
  65. }
  66. msleep(10);
  67. }
  68. /* To prevent overwriting mailbox registers for a command that has
  69. * not yet been serviced, check to see if an active command
  70. * (AEN, IOCB, etc.) is interrupting, then service it.
  71. * -----------------------------------------------------------------
  72. */
  73. spin_lock_irqsave(&ha->hardware_lock, flags);
  74. if (!is_qla8022(ha)) {
  75. intr_status = readl(&ha->reg->ctrl_status);
  76. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  77. /* Service existing interrupt */
  78. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  79. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  80. }
  81. }
  82. ha->mbox_status_count = outCount;
  83. for (i = 0; i < outCount; i++)
  84. ha->mbox_status[i] = 0;
  85. if (is_qla8022(ha)) {
  86. /* Load all mailbox registers, except mailbox 0. */
  87. DEBUG5(
  88. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  89. for (i = 0; i < inCount; i++)
  90. printk("mb%d=%04x ", i, mbx_cmd[i]);
  91. printk("\n"));
  92. for (i = 1; i < inCount; i++)
  93. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  94. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  95. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  96. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  97. } else {
  98. /* Load all mailbox registers, except mailbox 0. */
  99. for (i = 1; i < inCount; i++)
  100. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  101. /* Wakeup firmware */
  102. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  103. readl(&ha->reg->mailbox[0]);
  104. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  105. readl(&ha->reg->ctrl_status);
  106. }
  107. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  108. /* Wait for completion */
  109. /*
  110. * If we don't want status, don't wait for the mailbox command to
  111. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  112. * you must poll the inbound Interrupt Mask for completion.
  113. */
  114. if (outCount == 0) {
  115. status = QLA_SUCCESS;
  116. goto mbox_exit;
  117. }
  118. /*
  119. * Wait for completion: Poll or completion queue
  120. */
  121. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  122. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  123. test_bit(AF_ONLINE, &ha->flags) &&
  124. !test_bit(AF_HBA_GOING_AWAY, &ha->flags)) {
  125. /* Do not poll for completion. Use completion queue */
  126. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  127. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  128. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  129. } else {
  130. /* Poll for command to complete */
  131. wait_count = jiffies + MBOX_TOV * HZ;
  132. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  133. if (time_after_eq(jiffies, wait_count))
  134. break;
  135. /*
  136. * Service the interrupt.
  137. * The ISR will save the mailbox status registers
  138. * to a temporary storage location in the adapter
  139. * structure.
  140. */
  141. spin_lock_irqsave(&ha->hardware_lock, flags);
  142. if (is_qla8022(ha)) {
  143. intr_status =
  144. readl(&ha->qla4_8xxx_reg->host_int);
  145. if (intr_status & ISRX_82XX_RISC_INT) {
  146. ha->mbox_status_count = outCount;
  147. intr_status =
  148. readl(&ha->qla4_8xxx_reg->host_status);
  149. ha->isp_ops->interrupt_service_routine(
  150. ha, intr_status);
  151. if (test_bit(AF_INTERRUPTS_ON,
  152. &ha->flags) &&
  153. test_bit(AF_INTx_ENABLED,
  154. &ha->flags))
  155. qla4_8xxx_wr_32(ha,
  156. ha->nx_legacy_intr.tgt_mask_reg,
  157. 0xfbff);
  158. }
  159. } else {
  160. intr_status = readl(&ha->reg->ctrl_status);
  161. if (intr_status & INTR_PENDING) {
  162. /*
  163. * Service the interrupt.
  164. * The ISR will save the mailbox status
  165. * registers to a temporary storage
  166. * location in the adapter structure.
  167. */
  168. ha->mbox_status_count = outCount;
  169. ha->isp_ops->interrupt_service_routine(
  170. ha, intr_status);
  171. }
  172. }
  173. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  174. msleep(10);
  175. }
  176. }
  177. /* Check for mailbox timeout. */
  178. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  179. if (is_qla8022(ha) &&
  180. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  181. DEBUG2(ql4_printk(KERN_INFO, ha,
  182. "scsi%ld: %s: prematurely completing mbx cmd as "
  183. "firmware recovery detected\n",
  184. ha->host_no, __func__));
  185. goto mbox_exit;
  186. }
  187. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  188. " Scheduling Adapter Reset\n", ha->host_no,
  189. mbx_cmd[0]));
  190. ha->mailbox_timeout_count++;
  191. mbx_sts[0] = (-1);
  192. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  193. goto mbox_exit;
  194. }
  195. /*
  196. * Copy the mailbox out registers to the caller's mailbox in/out
  197. * structure.
  198. */
  199. spin_lock_irqsave(&ha->hardware_lock, flags);
  200. for (i = 0; i < outCount; i++)
  201. mbx_sts[i] = ha->mbox_status[i];
  202. /* Set return status and error flags (if applicable). */
  203. switch (ha->mbox_status[0]) {
  204. case MBOX_STS_COMMAND_COMPLETE:
  205. status = QLA_SUCCESS;
  206. break;
  207. case MBOX_STS_INTERMEDIATE_COMPLETION:
  208. status = QLA_SUCCESS;
  209. break;
  210. case MBOX_STS_BUSY:
  211. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  212. ha->host_no, __func__, mbx_cmd[0]));
  213. ha->mailbox_timeout_count++;
  214. break;
  215. default:
  216. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  217. "sts = %08X ****\n", ha->host_no, __func__,
  218. mbx_cmd[0], mbx_sts[0]));
  219. break;
  220. }
  221. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  222. mbox_exit:
  223. mutex_lock(&ha->mbox_sem);
  224. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  225. mutex_unlock(&ha->mbox_sem);
  226. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  227. return status;
  228. }
  229. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  230. {
  231. set_bit(AF_FW_RECOVERY, &ha->flags);
  232. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  233. ha->host_no, __func__);
  234. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  235. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  236. complete(&ha->mbx_intr_comp);
  237. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  238. "recovery, doing premature completion of "
  239. "mbx cmd\n", ha->host_no, __func__);
  240. } else {
  241. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  242. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  243. "recovery, doing premature completion of "
  244. "polling mbx cmd\n", ha->host_no, __func__);
  245. }
  246. }
  247. }
  248. static uint8_t
  249. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  250. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  251. {
  252. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  253. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  254. if (is_qla8022(ha))
  255. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  256. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  257. mbox_cmd[1] = 0;
  258. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  259. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  260. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  261. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  262. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  263. QLA_SUCCESS) {
  264. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  265. "MBOX_CMD_INITIALIZE_FIRMWARE"
  266. " failed w/ status %04X\n",
  267. ha->host_no, __func__, mbox_sts[0]));
  268. return QLA_ERROR;
  269. }
  270. return QLA_SUCCESS;
  271. }
  272. static uint8_t
  273. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  274. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  275. {
  276. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  277. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  278. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  279. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  280. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  281. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  282. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  283. QLA_SUCCESS) {
  284. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  285. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  286. " failed w/ status %04X\n",
  287. ha->host_no, __func__, mbox_sts[0]));
  288. return QLA_ERROR;
  289. }
  290. return QLA_SUCCESS;
  291. }
  292. static void
  293. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  294. struct addr_ctrl_blk *init_fw_cb)
  295. {
  296. /* Save IPv4 Address Info */
  297. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  298. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  299. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  300. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  301. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  302. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  303. if (is_ipv6_enabled(ha)) {
  304. /* Save IPv6 Address */
  305. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  306. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  307. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  308. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  309. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  310. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  311. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  312. init_fw_cb->ipv6_if_id,
  313. min(sizeof(ha->ipv6_link_local_addr)/2,
  314. sizeof(init_fw_cb->ipv6_if_id)));
  315. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  316. min(sizeof(ha->ipv6_addr0),
  317. sizeof(init_fw_cb->ipv6_addr0)));
  318. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  319. min(sizeof(ha->ipv6_addr1),
  320. sizeof(init_fw_cb->ipv6_addr1)));
  321. memcpy(&ha->ipv6_default_router_addr,
  322. init_fw_cb->ipv6_dflt_rtr_addr,
  323. min(sizeof(ha->ipv6_default_router_addr),
  324. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  325. }
  326. }
  327. static uint8_t
  328. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  329. uint32_t *mbox_cmd,
  330. uint32_t *mbox_sts,
  331. struct addr_ctrl_blk *init_fw_cb,
  332. dma_addr_t init_fw_cb_dma)
  333. {
  334. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  335. != QLA_SUCCESS) {
  336. DEBUG2(printk(KERN_WARNING
  337. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  338. ha->host_no, __func__));
  339. return QLA_ERROR;
  340. }
  341. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  342. /* Save some info in adapter structure. */
  343. ha->acb_version = init_fw_cb->acb_version;
  344. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  345. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  346. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  347. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  348. ha->heartbeat_interval = init_fw_cb->hb_interval;
  349. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  350. min(sizeof(ha->name_string),
  351. sizeof(init_fw_cb->iscsi_name)));
  352. /*memcpy(ha->alias, init_fw_cb->Alias,
  353. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  354. /* Save Command Line Paramater info */
  355. ha->discovery_wait = ql4xdiscoverywait;
  356. if (ha->acb_version == ACB_SUPPORTED) {
  357. ha->ipv6_options = init_fw_cb->ipv6_opts;
  358. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  359. }
  360. qla4xxx_update_local_ip(ha, init_fw_cb);
  361. return QLA_SUCCESS;
  362. }
  363. /**
  364. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  365. * @ha: Pointer to host adapter structure.
  366. **/
  367. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  368. {
  369. struct addr_ctrl_blk *init_fw_cb;
  370. dma_addr_t init_fw_cb_dma;
  371. uint32_t mbox_cmd[MBOX_REG_COUNT];
  372. uint32_t mbox_sts[MBOX_REG_COUNT];
  373. int status = QLA_ERROR;
  374. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  375. sizeof(struct addr_ctrl_blk),
  376. &init_fw_cb_dma, GFP_KERNEL);
  377. if (init_fw_cb == NULL) {
  378. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  379. ha->host_no, __func__));
  380. goto exit_init_fw_cb_no_free;
  381. }
  382. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  383. /* Get Initialize Firmware Control Block. */
  384. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  385. memset(&mbox_sts, 0, sizeof(mbox_sts));
  386. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  387. QLA_SUCCESS) {
  388. dma_free_coherent(&ha->pdev->dev,
  389. sizeof(struct addr_ctrl_blk),
  390. init_fw_cb, init_fw_cb_dma);
  391. goto exit_init_fw_cb;
  392. }
  393. /* Initialize request and response queues. */
  394. qla4xxx_init_rings(ha);
  395. /* Fill in the request and response queue information. */
  396. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  397. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  398. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  399. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  400. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  401. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  402. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  403. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  404. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  405. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  406. /* Set up required options. */
  407. init_fw_cb->fw_options |=
  408. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  409. FWOPT_INITIATOR_MODE);
  410. if (is_qla8022(ha))
  411. init_fw_cb->fw_options |=
  412. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  413. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  414. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  415. != QLA_SUCCESS) {
  416. DEBUG2(printk(KERN_WARNING
  417. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  418. ha->host_no, __func__));
  419. goto exit_init_fw_cb;
  420. }
  421. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  422. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  423. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  424. ha->host_no, __func__));
  425. goto exit_init_fw_cb;
  426. }
  427. status = QLA_SUCCESS;
  428. exit_init_fw_cb:
  429. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  430. init_fw_cb, init_fw_cb_dma);
  431. exit_init_fw_cb_no_free:
  432. return status;
  433. }
  434. /**
  435. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  436. * @ha: Pointer to host adapter structure.
  437. **/
  438. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  439. {
  440. struct addr_ctrl_blk *init_fw_cb;
  441. dma_addr_t init_fw_cb_dma;
  442. uint32_t mbox_cmd[MBOX_REG_COUNT];
  443. uint32_t mbox_sts[MBOX_REG_COUNT];
  444. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  445. sizeof(struct addr_ctrl_blk),
  446. &init_fw_cb_dma, GFP_KERNEL);
  447. if (init_fw_cb == NULL) {
  448. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  449. __func__);
  450. return QLA_ERROR;
  451. }
  452. /* Get Initialize Firmware Control Block. */
  453. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  454. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  455. QLA_SUCCESS) {
  456. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  457. ha->host_no, __func__));
  458. dma_free_coherent(&ha->pdev->dev,
  459. sizeof(struct addr_ctrl_blk),
  460. init_fw_cb, init_fw_cb_dma);
  461. return QLA_ERROR;
  462. }
  463. /* Save IP Address. */
  464. qla4xxx_update_local_ip(ha, init_fw_cb);
  465. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  466. init_fw_cb, init_fw_cb_dma);
  467. return QLA_SUCCESS;
  468. }
  469. /**
  470. * qla4xxx_get_firmware_state - gets firmware state of HBA
  471. * @ha: Pointer to host adapter structure.
  472. **/
  473. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  474. {
  475. uint32_t mbox_cmd[MBOX_REG_COUNT];
  476. uint32_t mbox_sts[MBOX_REG_COUNT];
  477. /* Get firmware version */
  478. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  479. memset(&mbox_sts, 0, sizeof(mbox_sts));
  480. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  481. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  482. QLA_SUCCESS) {
  483. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  484. "status %04X\n", ha->host_no, __func__,
  485. mbox_sts[0]));
  486. return QLA_ERROR;
  487. }
  488. ha->firmware_state = mbox_sts[1];
  489. ha->board_id = mbox_sts[2];
  490. ha->addl_fw_state = mbox_sts[3];
  491. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  492. ha->host_no, __func__, ha->firmware_state);)
  493. return QLA_SUCCESS;
  494. }
  495. /**
  496. * qla4xxx_get_firmware_status - retrieves firmware status
  497. * @ha: Pointer to host adapter structure.
  498. **/
  499. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  500. {
  501. uint32_t mbox_cmd[MBOX_REG_COUNT];
  502. uint32_t mbox_sts[MBOX_REG_COUNT];
  503. /* Get firmware version */
  504. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  505. memset(&mbox_sts, 0, sizeof(mbox_sts));
  506. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  507. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  508. QLA_SUCCESS) {
  509. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  510. "status %04X\n", ha->host_no, __func__,
  511. mbox_sts[0]));
  512. return QLA_ERROR;
  513. }
  514. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  515. ha->host_no, mbox_sts[2]);
  516. return QLA_SUCCESS;
  517. }
  518. /**
  519. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  520. * @ha: Pointer to host adapter structure.
  521. * @fw_ddb_index: Firmware's device database index
  522. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  523. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  524. * @next_ddb_index: Pointer to next valid device database index
  525. * @fw_ddb_device_state: Pointer to device state
  526. **/
  527. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  528. uint16_t fw_ddb_index,
  529. struct dev_db_entry *fw_ddb_entry,
  530. dma_addr_t fw_ddb_entry_dma,
  531. uint32_t *num_valid_ddb_entries,
  532. uint32_t *next_ddb_index,
  533. uint32_t *fw_ddb_device_state,
  534. uint32_t *conn_err_detail,
  535. uint16_t *tcp_source_port_num,
  536. uint16_t *connection_id)
  537. {
  538. int status = QLA_ERROR;
  539. uint16_t options;
  540. uint32_t mbox_cmd[MBOX_REG_COUNT];
  541. uint32_t mbox_sts[MBOX_REG_COUNT];
  542. /* Make sure the device index is valid */
  543. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  544. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  545. ha->host_no, __func__, fw_ddb_index));
  546. goto exit_get_fwddb;
  547. }
  548. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  549. memset(&mbox_sts, 0, sizeof(mbox_sts));
  550. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  551. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  552. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  553. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  554. mbox_cmd[4] = sizeof(struct dev_db_entry);
  555. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  556. QLA_ERROR) {
  557. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  558. " with status 0x%04X\n", ha->host_no, __func__,
  559. mbox_sts[0]));
  560. goto exit_get_fwddb;
  561. }
  562. if (fw_ddb_index != mbox_sts[1]) {
  563. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  564. ha->host_no, __func__, fw_ddb_index,
  565. mbox_sts[1]));
  566. goto exit_get_fwddb;
  567. }
  568. if (fw_ddb_entry) {
  569. options = le16_to_cpu(fw_ddb_entry->options);
  570. if (options & DDB_OPT_IPV6_DEVICE) {
  571. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  572. "Next %d State %04x ConnErr %08x %pI6 "
  573. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  574. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  575. mbox_sts[4], mbox_sts[5],
  576. fw_ddb_entry->ip_addr,
  577. le16_to_cpu(fw_ddb_entry->port),
  578. fw_ddb_entry->iscsi_name);
  579. } else {
  580. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  581. "Next %d State %04x ConnErr %08x %pI4 "
  582. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  583. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  584. mbox_sts[4], mbox_sts[5],
  585. fw_ddb_entry->ip_addr,
  586. le16_to_cpu(fw_ddb_entry->port),
  587. fw_ddb_entry->iscsi_name);
  588. }
  589. }
  590. if (num_valid_ddb_entries)
  591. *num_valid_ddb_entries = mbox_sts[2];
  592. if (next_ddb_index)
  593. *next_ddb_index = mbox_sts[3];
  594. if (fw_ddb_device_state)
  595. *fw_ddb_device_state = mbox_sts[4];
  596. /*
  597. * RA: This mailbox has been changed to pass connection error and
  598. * details. Its true for ISP4010 as per Version E - Not sure when it
  599. * was changed. Get the time2wait from the fw_dd_entry field :
  600. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  601. * struct.
  602. */
  603. if (conn_err_detail)
  604. *conn_err_detail = mbox_sts[5];
  605. if (tcp_source_port_num)
  606. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  607. if (connection_id)
  608. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  609. status = QLA_SUCCESS;
  610. exit_get_fwddb:
  611. return status;
  612. }
  613. /**
  614. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  615. * @ha: Pointer to host adapter structure.
  616. * @fw_ddb_index: Firmware's device database index
  617. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  618. *
  619. * This routine initializes or updates the adapter's device database
  620. * entry for the specified device. It also triggers a login for the
  621. * specified device. Therefore, it may also be used as a secondary
  622. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  623. **/
  624. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  625. dma_addr_t fw_ddb_entry_dma)
  626. {
  627. uint32_t mbox_cmd[MBOX_REG_COUNT];
  628. uint32_t mbox_sts[MBOX_REG_COUNT];
  629. int status;
  630. /* Do not wait for completion. The firmware will send us an
  631. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  632. */
  633. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  634. memset(&mbox_sts, 0, sizeof(mbox_sts));
  635. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  636. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  637. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  638. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  639. mbox_cmd[4] = sizeof(struct dev_db_entry);
  640. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  641. &mbox_sts[0]);
  642. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  643. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  644. return status;
  645. }
  646. /**
  647. * qla4xxx_get_crash_record - retrieves crash record.
  648. * @ha: Pointer to host adapter structure.
  649. *
  650. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  651. **/
  652. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  653. {
  654. uint32_t mbox_cmd[MBOX_REG_COUNT];
  655. uint32_t mbox_sts[MBOX_REG_COUNT];
  656. struct crash_record *crash_record = NULL;
  657. dma_addr_t crash_record_dma = 0;
  658. uint32_t crash_record_size = 0;
  659. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  660. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  661. /* Get size of crash record. */
  662. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  663. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  664. QLA_SUCCESS) {
  665. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  666. ha->host_no, __func__));
  667. goto exit_get_crash_record;
  668. }
  669. crash_record_size = mbox_sts[4];
  670. if (crash_record_size == 0) {
  671. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  672. ha->host_no, __func__));
  673. goto exit_get_crash_record;
  674. }
  675. /* Alloc Memory for Crash Record. */
  676. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  677. &crash_record_dma, GFP_KERNEL);
  678. if (crash_record == NULL)
  679. goto exit_get_crash_record;
  680. /* Get Crash Record. */
  681. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  682. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  683. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  684. mbox_cmd[2] = LSDW(crash_record_dma);
  685. mbox_cmd[3] = MSDW(crash_record_dma);
  686. mbox_cmd[4] = crash_record_size;
  687. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  688. QLA_SUCCESS)
  689. goto exit_get_crash_record;
  690. /* Dump Crash Record. */
  691. exit_get_crash_record:
  692. if (crash_record)
  693. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  694. crash_record, crash_record_dma);
  695. }
  696. /**
  697. * qla4xxx_get_conn_event_log - retrieves connection event log
  698. * @ha: Pointer to host adapter structure.
  699. **/
  700. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  701. {
  702. uint32_t mbox_cmd[MBOX_REG_COUNT];
  703. uint32_t mbox_sts[MBOX_REG_COUNT];
  704. struct conn_event_log_entry *event_log = NULL;
  705. dma_addr_t event_log_dma = 0;
  706. uint32_t event_log_size = 0;
  707. uint32_t num_valid_entries;
  708. uint32_t oldest_entry = 0;
  709. uint32_t max_event_log_entries;
  710. uint8_t i;
  711. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  712. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  713. /* Get size of crash record. */
  714. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  715. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  716. QLA_SUCCESS)
  717. goto exit_get_event_log;
  718. event_log_size = mbox_sts[4];
  719. if (event_log_size == 0)
  720. goto exit_get_event_log;
  721. /* Alloc Memory for Crash Record. */
  722. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  723. &event_log_dma, GFP_KERNEL);
  724. if (event_log == NULL)
  725. goto exit_get_event_log;
  726. /* Get Crash Record. */
  727. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  728. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  729. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  730. mbox_cmd[2] = LSDW(event_log_dma);
  731. mbox_cmd[3] = MSDW(event_log_dma);
  732. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  733. QLA_SUCCESS) {
  734. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  735. "log!\n", ha->host_no, __func__));
  736. goto exit_get_event_log;
  737. }
  738. /* Dump Event Log. */
  739. num_valid_entries = mbox_sts[1];
  740. max_event_log_entries = event_log_size /
  741. sizeof(struct conn_event_log_entry);
  742. if (num_valid_entries > max_event_log_entries)
  743. oldest_entry = num_valid_entries % max_event_log_entries;
  744. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  745. ha->host_no, num_valid_entries));
  746. if (ql4xextended_error_logging == 3) {
  747. if (oldest_entry == 0) {
  748. /* Circular Buffer has not wrapped around */
  749. for (i=0; i < num_valid_entries; i++) {
  750. qla4xxx_dump_buffer((uint8_t *)event_log+
  751. (i*sizeof(*event_log)),
  752. sizeof(*event_log));
  753. }
  754. }
  755. else {
  756. /* Circular Buffer has wrapped around -
  757. * display accordingly*/
  758. for (i=oldest_entry; i < max_event_log_entries; i++) {
  759. qla4xxx_dump_buffer((uint8_t *)event_log+
  760. (i*sizeof(*event_log)),
  761. sizeof(*event_log));
  762. }
  763. for (i=0; i < oldest_entry; i++) {
  764. qla4xxx_dump_buffer((uint8_t *)event_log+
  765. (i*sizeof(*event_log)),
  766. sizeof(*event_log));
  767. }
  768. }
  769. }
  770. exit_get_event_log:
  771. if (event_log)
  772. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  773. event_log_dma);
  774. }
  775. /**
  776. * qla4xxx_abort_task - issues Abort Task
  777. * @ha: Pointer to host adapter structure.
  778. * @srb: Pointer to srb entry
  779. *
  780. * This routine performs a LUN RESET on the specified target/lun.
  781. * The caller must ensure that the ddb_entry and lun_entry pointers
  782. * are valid before calling this routine.
  783. **/
  784. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  785. {
  786. uint32_t mbox_cmd[MBOX_REG_COUNT];
  787. uint32_t mbox_sts[MBOX_REG_COUNT];
  788. struct scsi_cmnd *cmd = srb->cmd;
  789. int status = QLA_SUCCESS;
  790. unsigned long flags = 0;
  791. uint32_t index;
  792. /*
  793. * Send abort task command to ISP, so that the ISP will return
  794. * request with ABORT status
  795. */
  796. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  797. memset(&mbox_sts, 0, sizeof(mbox_sts));
  798. spin_lock_irqsave(&ha->hardware_lock, flags);
  799. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  800. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  801. /* Firmware already posted completion on response queue */
  802. if (index == MAX_SRBS)
  803. return status;
  804. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  805. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  806. mbox_cmd[2] = index;
  807. /* Immediate Command Enable */
  808. mbox_cmd[5] = 0x01;
  809. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  810. &mbox_sts[0]);
  811. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  812. status = QLA_ERROR;
  813. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  814. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  815. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  816. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  817. }
  818. return status;
  819. }
  820. /**
  821. * qla4xxx_reset_lun - issues LUN Reset
  822. * @ha: Pointer to host adapter structure.
  823. * @ddb_entry: Pointer to device database entry
  824. * @lun: lun number
  825. *
  826. * This routine performs a LUN RESET on the specified target/lun.
  827. * The caller must ensure that the ddb_entry and lun_entry pointers
  828. * are valid before calling this routine.
  829. **/
  830. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  831. int lun)
  832. {
  833. uint32_t mbox_cmd[MBOX_REG_COUNT];
  834. uint32_t mbox_sts[MBOX_REG_COUNT];
  835. int status = QLA_SUCCESS;
  836. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  837. ddb_entry->fw_ddb_index, lun));
  838. /*
  839. * Send lun reset command to ISP, so that the ISP will return all
  840. * outstanding requests with RESET status
  841. */
  842. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  843. memset(&mbox_sts, 0, sizeof(mbox_sts));
  844. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  845. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  846. mbox_cmd[2] = lun << 8;
  847. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  848. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  849. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  850. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  851. status = QLA_ERROR;
  852. return status;
  853. }
  854. /**
  855. * qla4xxx_reset_target - issues target Reset
  856. * @ha: Pointer to host adapter structure.
  857. * @db_entry: Pointer to device database entry
  858. * @un_entry: Pointer to lun entry structure
  859. *
  860. * This routine performs a TARGET RESET on the specified target.
  861. * The caller must ensure that the ddb_entry pointers
  862. * are valid before calling this routine.
  863. **/
  864. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  865. struct ddb_entry *ddb_entry)
  866. {
  867. uint32_t mbox_cmd[MBOX_REG_COUNT];
  868. uint32_t mbox_sts[MBOX_REG_COUNT];
  869. int status = QLA_SUCCESS;
  870. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  871. ddb_entry->fw_ddb_index));
  872. /*
  873. * Send target reset command to ISP, so that the ISP will return all
  874. * outstanding requests with RESET status
  875. */
  876. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  877. memset(&mbox_sts, 0, sizeof(mbox_sts));
  878. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  879. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  880. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  881. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  882. &mbox_sts[0]);
  883. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  884. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  885. status = QLA_ERROR;
  886. return status;
  887. }
  888. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  889. uint32_t offset, uint32_t len)
  890. {
  891. uint32_t mbox_cmd[MBOX_REG_COUNT];
  892. uint32_t mbox_sts[MBOX_REG_COUNT];
  893. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  894. memset(&mbox_sts, 0, sizeof(mbox_sts));
  895. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  896. mbox_cmd[1] = LSDW(dma_addr);
  897. mbox_cmd[2] = MSDW(dma_addr);
  898. mbox_cmd[3] = offset;
  899. mbox_cmd[4] = len;
  900. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  901. QLA_SUCCESS) {
  902. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  903. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  904. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  905. return QLA_ERROR;
  906. }
  907. return QLA_SUCCESS;
  908. }
  909. /**
  910. * qla4xxx_get_fw_version - gets firmware version
  911. * @ha: Pointer to host adapter structure.
  912. *
  913. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  914. * hold an address for data. Make sure that we write 0 to those mailboxes,
  915. * if unused.
  916. **/
  917. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  918. {
  919. uint32_t mbox_cmd[MBOX_REG_COUNT];
  920. uint32_t mbox_sts[MBOX_REG_COUNT];
  921. /* Get firmware version. */
  922. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  923. memset(&mbox_sts, 0, sizeof(mbox_sts));
  924. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  925. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  926. QLA_SUCCESS) {
  927. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  928. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  929. return QLA_ERROR;
  930. }
  931. /* Save firmware version information. */
  932. ha->firmware_version[0] = mbox_sts[1];
  933. ha->firmware_version[1] = mbox_sts[2];
  934. ha->patch_number = mbox_sts[3];
  935. ha->build_number = mbox_sts[4];
  936. return QLA_SUCCESS;
  937. }
  938. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  939. dma_addr_t dma_addr)
  940. {
  941. uint32_t mbox_cmd[MBOX_REG_COUNT];
  942. uint32_t mbox_sts[MBOX_REG_COUNT];
  943. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  944. memset(&mbox_sts, 0, sizeof(mbox_sts));
  945. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  946. mbox_cmd[2] = LSDW(dma_addr);
  947. mbox_cmd[3] = MSDW(dma_addr);
  948. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  949. QLA_SUCCESS) {
  950. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  951. ha->host_no, __func__, mbox_sts[0]));
  952. return QLA_ERROR;
  953. }
  954. return QLA_SUCCESS;
  955. }
  956. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  957. {
  958. uint32_t mbox_cmd[MBOX_REG_COUNT];
  959. uint32_t mbox_sts[MBOX_REG_COUNT];
  960. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  961. memset(&mbox_sts, 0, sizeof(mbox_sts));
  962. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  963. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  964. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  965. QLA_SUCCESS) {
  966. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  967. *ddb_index = mbox_sts[2];
  968. } else {
  969. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  970. ha->host_no, __func__, mbox_sts[0]));
  971. return QLA_ERROR;
  972. }
  973. } else {
  974. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  975. }
  976. return QLA_SUCCESS;
  977. }
  978. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  979. {
  980. struct dev_db_entry *fw_ddb_entry;
  981. dma_addr_t fw_ddb_entry_dma;
  982. uint32_t ddb_index;
  983. int ret_val = QLA_SUCCESS;
  984. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  985. sizeof(*fw_ddb_entry),
  986. &fw_ddb_entry_dma, GFP_KERNEL);
  987. if (!fw_ddb_entry) {
  988. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  989. ha->host_no, __func__));
  990. ret_val = QLA_ERROR;
  991. goto exit_send_tgts_no_free;
  992. }
  993. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  994. if (ret_val != QLA_SUCCESS)
  995. goto exit_send_tgts;
  996. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  997. if (ret_val != QLA_SUCCESS)
  998. goto exit_send_tgts;
  999. memset(fw_ddb_entry->iscsi_alias, 0,
  1000. sizeof(fw_ddb_entry->iscsi_alias));
  1001. memset(fw_ddb_entry->iscsi_name, 0,
  1002. sizeof(fw_ddb_entry->iscsi_name));
  1003. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1004. memset(fw_ddb_entry->tgt_addr, 0,
  1005. sizeof(fw_ddb_entry->tgt_addr));
  1006. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1007. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1008. fw_ddb_entry->ip_addr[0] = *ip;
  1009. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1010. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1011. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1012. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1013. exit_send_tgts:
  1014. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1015. fw_ddb_entry, fw_ddb_entry_dma);
  1016. exit_send_tgts_no_free:
  1017. return ret_val;
  1018. }