mpt2sas_base.c 116 KB

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  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt2sas/mpt2_base.c
  6. * Copyright (C) 2007-2010 LSI Corporation
  7. * (mailto:DL-MPTFusionLinux@lsi.com)
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * NO WARRANTY
  20. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  21. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  22. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  23. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  24. * solely responsible for determining the appropriateness of using and
  25. * distributing the Program and assumes all risks associated with its
  26. * exercise of rights under this Agreement, including but not limited to
  27. * the risks and costs of program errors, damage to or loss of data,
  28. * programs or equipment, and unavailability or interruption of operations.
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. * You should have received a copy of the GNU General Public License
  38. * along with this program; if not, write to the Free Software
  39. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  40. * USA.
  41. */
  42. #include <linux/version.h>
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/sort.h>
  56. #include <linux/io.h>
  57. #include <linux/time.h>
  58. #include <linux/aer.h>
  59. #include "mpt2sas_base.h"
  60. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  61. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  62. static int max_queue_depth = -1;
  63. module_param(max_queue_depth, int, 0);
  64. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  65. static int max_sgl_entries = -1;
  66. module_param(max_sgl_entries, int, 0);
  67. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  68. static int msix_disable = -1;
  69. module_param(msix_disable, int, 0);
  70. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  71. static int missing_delay[2] = {-1, -1};
  72. module_param_array(missing_delay, int, NULL, 0);
  73. MODULE_PARM_DESC(missing_delay, " device missing delay , io missing delay");
  74. /* diag_buffer_enable is bitwise
  75. * bit 0 set = TRACE
  76. * bit 1 set = SNAPSHOT
  77. * bit 2 set = EXTENDED
  78. *
  79. * Either bit can be set, or both
  80. */
  81. static int diag_buffer_enable;
  82. module_param(diag_buffer_enable, int, 0);
  83. MODULE_PARM_DESC(diag_buffer_enable, " post diag buffers "
  84. "(TRACE=1/SNAPSHOT=2/EXTENDED=4/default=0)");
  85. int mpt2sas_fwfault_debug;
  86. MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
  87. "and halt firmware - (default=0)");
  88. static int disable_discovery = -1;
  89. module_param(disable_discovery, int, 0);
  90. MODULE_PARM_DESC(disable_discovery, " disable discovery ");
  91. /**
  92. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  93. *
  94. */
  95. static int
  96. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  97. {
  98. int ret = param_set_int(val, kp);
  99. struct MPT2SAS_ADAPTER *ioc;
  100. if (ret)
  101. return ret;
  102. printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
  103. list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
  104. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  105. return 0;
  106. }
  107. module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
  108. param_get_int, &mpt2sas_fwfault_debug, 0644);
  109. /**
  110. * _base_fault_reset_work - workq handling ioc fault conditions
  111. * @work: input argument, used to derive ioc
  112. * Context: sleep.
  113. *
  114. * Return nothing.
  115. */
  116. static void
  117. _base_fault_reset_work(struct work_struct *work)
  118. {
  119. struct MPT2SAS_ADAPTER *ioc =
  120. container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
  121. unsigned long flags;
  122. u32 doorbell;
  123. int rc;
  124. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  125. if (ioc->shost_recovery)
  126. goto rearm_timer;
  127. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  128. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  129. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  130. rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  131. FORCE_BIG_HAMMER);
  132. printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
  133. __func__, (rc == 0) ? "success" : "failed");
  134. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  135. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  136. mpt2sas_base_fault_info(ioc, doorbell &
  137. MPI2_DOORBELL_DATA_MASK);
  138. }
  139. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  140. rearm_timer:
  141. if (ioc->fault_reset_work_q)
  142. queue_delayed_work(ioc->fault_reset_work_q,
  143. &ioc->fault_reset_work,
  144. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  145. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  146. }
  147. /**
  148. * mpt2sas_base_start_watchdog - start the fault_reset_work_q
  149. * @ioc: per adapter object
  150. * Context: sleep.
  151. *
  152. * Return nothing.
  153. */
  154. void
  155. mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
  156. {
  157. unsigned long flags;
  158. if (ioc->fault_reset_work_q)
  159. return;
  160. /* initialize fault polling */
  161. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  162. snprintf(ioc->fault_reset_work_q_name,
  163. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  164. ioc->fault_reset_work_q =
  165. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  166. if (!ioc->fault_reset_work_q) {
  167. printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
  168. ioc->name, __func__, __LINE__);
  169. return;
  170. }
  171. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  172. if (ioc->fault_reset_work_q)
  173. queue_delayed_work(ioc->fault_reset_work_q,
  174. &ioc->fault_reset_work,
  175. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  176. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  177. }
  178. /**
  179. * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q
  180. * @ioc: per adapter object
  181. * Context: sleep.
  182. *
  183. * Return nothing.
  184. */
  185. void
  186. mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
  187. {
  188. unsigned long flags;
  189. struct workqueue_struct *wq;
  190. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  191. wq = ioc->fault_reset_work_q;
  192. ioc->fault_reset_work_q = NULL;
  193. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  194. if (wq) {
  195. if (!cancel_delayed_work(&ioc->fault_reset_work))
  196. flush_workqueue(wq);
  197. destroy_workqueue(wq);
  198. }
  199. }
  200. /**
  201. * mpt2sas_base_fault_info - verbose translation of firmware FAULT code
  202. * @ioc: per adapter object
  203. * @fault_code: fault code
  204. *
  205. * Return nothing.
  206. */
  207. void
  208. mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
  209. {
  210. printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
  211. ioc->name, fault_code);
  212. }
  213. /**
  214. * mpt2sas_halt_firmware - halt's mpt controller firmware
  215. * @ioc: per adapter object
  216. *
  217. * For debugging timeout related issues. Writing 0xCOFFEE00
  218. * to the doorbell register will halt controller firmware. With
  219. * the purpose to stop both driver and firmware, the enduser can
  220. * obtain a ring buffer from controller UART.
  221. */
  222. void
  223. mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
  224. {
  225. u32 doorbell;
  226. if (!ioc->fwfault_debug)
  227. return;
  228. dump_stack();
  229. doorbell = readl(&ioc->chip->Doorbell);
  230. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  231. mpt2sas_base_fault_info(ioc , doorbell);
  232. else {
  233. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  234. printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
  235. "timeout\n", ioc->name);
  236. }
  237. panic("panic in %s\n", __func__);
  238. }
  239. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  240. /**
  241. * _base_sas_ioc_info - verbose translation of the ioc status
  242. * @ioc: per adapter object
  243. * @mpi_reply: reply mf payload returned from firmware
  244. * @request_hdr: request mf
  245. *
  246. * Return nothing.
  247. */
  248. static void
  249. _base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  250. MPI2RequestHeader_t *request_hdr)
  251. {
  252. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  253. MPI2_IOCSTATUS_MASK;
  254. char *desc = NULL;
  255. u16 frame_sz;
  256. char *func_str = NULL;
  257. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  258. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  259. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  260. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  261. return;
  262. if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
  263. return;
  264. switch (ioc_status) {
  265. /****************************************************************************
  266. * Common IOCStatus values for all replies
  267. ****************************************************************************/
  268. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  269. desc = "invalid function";
  270. break;
  271. case MPI2_IOCSTATUS_BUSY:
  272. desc = "busy";
  273. break;
  274. case MPI2_IOCSTATUS_INVALID_SGL:
  275. desc = "invalid sgl";
  276. break;
  277. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  278. desc = "internal error";
  279. break;
  280. case MPI2_IOCSTATUS_INVALID_VPID:
  281. desc = "invalid vpid";
  282. break;
  283. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  284. desc = "insufficient resources";
  285. break;
  286. case MPI2_IOCSTATUS_INVALID_FIELD:
  287. desc = "invalid field";
  288. break;
  289. case MPI2_IOCSTATUS_INVALID_STATE:
  290. desc = "invalid state";
  291. break;
  292. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  293. desc = "op state not supported";
  294. break;
  295. /****************************************************************************
  296. * Config IOCStatus values
  297. ****************************************************************************/
  298. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  299. desc = "config invalid action";
  300. break;
  301. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  302. desc = "config invalid type";
  303. break;
  304. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  305. desc = "config invalid page";
  306. break;
  307. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  308. desc = "config invalid data";
  309. break;
  310. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  311. desc = "config no defaults";
  312. break;
  313. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  314. desc = "config cant commit";
  315. break;
  316. /****************************************************************************
  317. * SCSI IO Reply
  318. ****************************************************************************/
  319. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  320. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  321. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  322. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  323. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  324. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  325. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  326. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  327. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  328. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  329. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  330. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  331. break;
  332. /****************************************************************************
  333. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  334. ****************************************************************************/
  335. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  336. desc = "eedp guard error";
  337. break;
  338. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  339. desc = "eedp ref tag error";
  340. break;
  341. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  342. desc = "eedp app tag error";
  343. break;
  344. /****************************************************************************
  345. * SCSI Target values
  346. ****************************************************************************/
  347. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  348. desc = "target invalid io index";
  349. break;
  350. case MPI2_IOCSTATUS_TARGET_ABORTED:
  351. desc = "target aborted";
  352. break;
  353. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  354. desc = "target no conn retryable";
  355. break;
  356. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  357. desc = "target no connection";
  358. break;
  359. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  360. desc = "target xfer count mismatch";
  361. break;
  362. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  363. desc = "target data offset error";
  364. break;
  365. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  366. desc = "target too much write data";
  367. break;
  368. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  369. desc = "target iu too short";
  370. break;
  371. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  372. desc = "target ack nak timeout";
  373. break;
  374. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  375. desc = "target nak received";
  376. break;
  377. /****************************************************************************
  378. * Serial Attached SCSI values
  379. ****************************************************************************/
  380. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  381. desc = "smp request failed";
  382. break;
  383. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  384. desc = "smp data overrun";
  385. break;
  386. /****************************************************************************
  387. * Diagnostic Buffer Post / Diagnostic Release values
  388. ****************************************************************************/
  389. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  390. desc = "diagnostic released";
  391. break;
  392. default:
  393. break;
  394. }
  395. if (!desc)
  396. return;
  397. switch (request_hdr->Function) {
  398. case MPI2_FUNCTION_CONFIG:
  399. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  400. func_str = "config_page";
  401. break;
  402. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  403. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  404. func_str = "task_mgmt";
  405. break;
  406. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  407. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  408. func_str = "sas_iounit_ctl";
  409. break;
  410. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  411. frame_sz = sizeof(Mpi2SepRequest_t);
  412. func_str = "enclosure";
  413. break;
  414. case MPI2_FUNCTION_IOC_INIT:
  415. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  416. func_str = "ioc_init";
  417. break;
  418. case MPI2_FUNCTION_PORT_ENABLE:
  419. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  420. func_str = "port_enable";
  421. break;
  422. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  423. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  424. func_str = "smp_passthru";
  425. break;
  426. default:
  427. frame_sz = 32;
  428. func_str = "unknown";
  429. break;
  430. }
  431. printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
  432. " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
  433. _debug_dump_mf(request_hdr, frame_sz/4);
  434. }
  435. /**
  436. * _base_display_event_data - verbose translation of firmware asyn events
  437. * @ioc: per adapter object
  438. * @mpi_reply: reply mf payload returned from firmware
  439. *
  440. * Return nothing.
  441. */
  442. static void
  443. _base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
  444. Mpi2EventNotificationReply_t *mpi_reply)
  445. {
  446. char *desc = NULL;
  447. u16 event;
  448. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  449. return;
  450. event = le16_to_cpu(mpi_reply->Event);
  451. switch (event) {
  452. case MPI2_EVENT_LOG_DATA:
  453. desc = "Log Data";
  454. break;
  455. case MPI2_EVENT_STATE_CHANGE:
  456. desc = "Status Change";
  457. break;
  458. case MPI2_EVENT_HARD_RESET_RECEIVED:
  459. desc = "Hard Reset Received";
  460. break;
  461. case MPI2_EVENT_EVENT_CHANGE:
  462. desc = "Event Change";
  463. break;
  464. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  465. desc = "Device Status Change";
  466. break;
  467. case MPI2_EVENT_IR_OPERATION_STATUS:
  468. desc = "IR Operation Status";
  469. break;
  470. case MPI2_EVENT_SAS_DISCOVERY:
  471. {
  472. Mpi2EventDataSasDiscovery_t *event_data =
  473. (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
  474. printk(MPT2SAS_INFO_FMT "Discovery: (%s)", ioc->name,
  475. (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
  476. "start" : "stop");
  477. if (event_data->DiscoveryStatus)
  478. printk("discovery_status(0x%08x)",
  479. le32_to_cpu(event_data->DiscoveryStatus));
  480. printk("\n");
  481. return;
  482. }
  483. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  484. desc = "SAS Broadcast Primitive";
  485. break;
  486. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  487. desc = "SAS Init Device Status Change";
  488. break;
  489. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  490. desc = "SAS Init Table Overflow";
  491. break;
  492. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  493. desc = "SAS Topology Change List";
  494. break;
  495. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  496. desc = "SAS Enclosure Device Status Change";
  497. break;
  498. case MPI2_EVENT_IR_VOLUME:
  499. desc = "IR Volume";
  500. break;
  501. case MPI2_EVENT_IR_PHYSICAL_DISK:
  502. desc = "IR Physical Disk";
  503. break;
  504. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  505. desc = "IR Configuration Change List";
  506. break;
  507. case MPI2_EVENT_LOG_ENTRY_ADDED:
  508. desc = "Log Entry Added";
  509. break;
  510. }
  511. if (!desc)
  512. return;
  513. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
  514. }
  515. #endif
  516. /**
  517. * _base_sas_log_info - verbose translation of firmware log info
  518. * @ioc: per adapter object
  519. * @log_info: log info
  520. *
  521. * Return nothing.
  522. */
  523. static void
  524. _base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
  525. {
  526. union loginfo_type {
  527. u32 loginfo;
  528. struct {
  529. u32 subcode:16;
  530. u32 code:8;
  531. u32 originator:4;
  532. u32 bus_type:4;
  533. } dw;
  534. };
  535. union loginfo_type sas_loginfo;
  536. char *originator_str = NULL;
  537. sas_loginfo.loginfo = log_info;
  538. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  539. return;
  540. /* each nexus loss loginfo */
  541. if (log_info == 0x31170000)
  542. return;
  543. /* eat the loginfos associated with task aborts */
  544. if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
  545. 0x31140000 || log_info == 0x31130000))
  546. return;
  547. switch (sas_loginfo.dw.originator) {
  548. case 0:
  549. originator_str = "IOP";
  550. break;
  551. case 1:
  552. originator_str = "PL";
  553. break;
  554. case 2:
  555. originator_str = "IR";
  556. break;
  557. }
  558. printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
  559. "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
  560. originator_str, sas_loginfo.dw.code,
  561. sas_loginfo.dw.subcode);
  562. }
  563. /**
  564. * _base_display_reply_info -
  565. * @ioc: per adapter object
  566. * @smid: system request message index
  567. * @msix_index: MSIX table index supplied by the OS
  568. * @reply: reply message frame(lower 32bit addr)
  569. *
  570. * Return nothing.
  571. */
  572. static void
  573. _base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  574. u32 reply)
  575. {
  576. MPI2DefaultReply_t *mpi_reply;
  577. u16 ioc_status;
  578. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  579. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  580. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  581. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  582. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  583. _base_sas_ioc_info(ioc , mpi_reply,
  584. mpt2sas_base_get_msg_frame(ioc, smid));
  585. }
  586. #endif
  587. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
  588. _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
  589. }
  590. /**
  591. * mpt2sas_base_done - base internal command completion routine
  592. * @ioc: per adapter object
  593. * @smid: system request message index
  594. * @msix_index: MSIX table index supplied by the OS
  595. * @reply: reply message frame(lower 32bit addr)
  596. *
  597. * Return 1 meaning mf should be freed from _base_interrupt
  598. * 0 means the mf is freed from this function.
  599. */
  600. u8
  601. mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  602. u32 reply)
  603. {
  604. MPI2DefaultReply_t *mpi_reply;
  605. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  606. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  607. return 1;
  608. if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
  609. return 1;
  610. ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
  611. if (mpi_reply) {
  612. ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
  613. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  614. }
  615. ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
  616. complete(&ioc->base_cmds.done);
  617. return 1;
  618. }
  619. /**
  620. * _base_async_event - main callback handler for firmware asyn events
  621. * @ioc: per adapter object
  622. * @msix_index: MSIX table index supplied by the OS
  623. * @reply: reply message frame(lower 32bit addr)
  624. *
  625. * Return 1 meaning mf should be freed from _base_interrupt
  626. * 0 means the mf is freed from this function.
  627. */
  628. static u8
  629. _base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  630. {
  631. Mpi2EventNotificationReply_t *mpi_reply;
  632. Mpi2EventAckRequest_t *ack_request;
  633. u16 smid;
  634. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  635. if (!mpi_reply)
  636. return 1;
  637. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  638. return 1;
  639. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  640. _base_display_event_data(ioc, mpi_reply);
  641. #endif
  642. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  643. goto out;
  644. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  645. if (!smid) {
  646. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  647. ioc->name, __func__);
  648. goto out;
  649. }
  650. ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
  651. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  652. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  653. ack_request->Event = mpi_reply->Event;
  654. ack_request->EventContext = mpi_reply->EventContext;
  655. ack_request->VF_ID = 0; /* TODO */
  656. ack_request->VP_ID = 0;
  657. mpt2sas_base_put_smid_default(ioc, smid);
  658. out:
  659. /* scsih callback handler */
  660. mpt2sas_scsih_event_callback(ioc, msix_index, reply);
  661. /* ctl callback handler */
  662. mpt2sas_ctl_event_callback(ioc, msix_index, reply);
  663. return 1;
  664. }
  665. /**
  666. * _base_get_cb_idx - obtain the callback index
  667. * @ioc: per adapter object
  668. * @smid: system request message index
  669. *
  670. * Return callback index.
  671. */
  672. static u8
  673. _base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  674. {
  675. int i;
  676. u8 cb_idx;
  677. if (smid < ioc->hi_priority_smid) {
  678. i = smid - 1;
  679. cb_idx = ioc->scsi_lookup[i].cb_idx;
  680. } else if (smid < ioc->internal_smid) {
  681. i = smid - ioc->hi_priority_smid;
  682. cb_idx = ioc->hpr_lookup[i].cb_idx;
  683. } else if (smid <= ioc->hba_queue_depth) {
  684. i = smid - ioc->internal_smid;
  685. cb_idx = ioc->internal_lookup[i].cb_idx;
  686. } else
  687. cb_idx = 0xFF;
  688. return cb_idx;
  689. }
  690. /**
  691. * _base_mask_interrupts - disable interrupts
  692. * @ioc: per adapter object
  693. *
  694. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  695. *
  696. * Return nothing.
  697. */
  698. static void
  699. _base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  700. {
  701. u32 him_register;
  702. ioc->mask_interrupts = 1;
  703. him_register = readl(&ioc->chip->HostInterruptMask);
  704. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  705. writel(him_register, &ioc->chip->HostInterruptMask);
  706. readl(&ioc->chip->HostInterruptMask);
  707. }
  708. /**
  709. * _base_unmask_interrupts - enable interrupts
  710. * @ioc: per adapter object
  711. *
  712. * Enabling only Reply Interrupts
  713. *
  714. * Return nothing.
  715. */
  716. static void
  717. _base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  718. {
  719. u32 him_register;
  720. him_register = readl(&ioc->chip->HostInterruptMask);
  721. him_register &= ~MPI2_HIM_RIM;
  722. writel(him_register, &ioc->chip->HostInterruptMask);
  723. ioc->mask_interrupts = 0;
  724. }
  725. union reply_descriptor {
  726. u64 word;
  727. struct {
  728. u32 low;
  729. u32 high;
  730. } u;
  731. };
  732. /**
  733. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  734. * @irq: irq number (not used)
  735. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  736. * @r: pt_regs pointer (not used)
  737. *
  738. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  739. */
  740. static irqreturn_t
  741. _base_interrupt(int irq, void *bus_id)
  742. {
  743. union reply_descriptor rd;
  744. u32 completed_cmds;
  745. u8 request_desript_type;
  746. u16 smid;
  747. u8 cb_idx;
  748. u32 reply;
  749. u8 msix_index;
  750. struct MPT2SAS_ADAPTER *ioc = bus_id;
  751. Mpi2ReplyDescriptorsUnion_t *rpf;
  752. u8 rc;
  753. if (ioc->mask_interrupts)
  754. return IRQ_NONE;
  755. rpf = &ioc->reply_post_free[ioc->reply_post_host_index];
  756. request_desript_type = rpf->Default.ReplyFlags
  757. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  758. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  759. return IRQ_NONE;
  760. completed_cmds = 0;
  761. cb_idx = 0xFF;
  762. do {
  763. rd.word = rpf->Words;
  764. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  765. goto out;
  766. reply = 0;
  767. cb_idx = 0xFF;
  768. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  769. msix_index = rpf->Default.MSIxIndex;
  770. if (request_desript_type ==
  771. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  772. reply = le32_to_cpu
  773. (rpf->AddressReply.ReplyFrameAddress);
  774. if (reply > ioc->reply_dma_max_address ||
  775. reply < ioc->reply_dma_min_address)
  776. reply = 0;
  777. } else if (request_desript_type ==
  778. MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
  779. goto next;
  780. else if (request_desript_type ==
  781. MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
  782. goto next;
  783. if (smid)
  784. cb_idx = _base_get_cb_idx(ioc, smid);
  785. if (smid && cb_idx != 0xFF) {
  786. rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
  787. reply);
  788. if (reply)
  789. _base_display_reply_info(ioc, smid, msix_index,
  790. reply);
  791. if (rc)
  792. mpt2sas_base_free_smid(ioc, smid);
  793. }
  794. if (!smid)
  795. _base_async_event(ioc, msix_index, reply);
  796. /* reply free queue handling */
  797. if (reply) {
  798. ioc->reply_free_host_index =
  799. (ioc->reply_free_host_index ==
  800. (ioc->reply_free_queue_depth - 1)) ?
  801. 0 : ioc->reply_free_host_index + 1;
  802. ioc->reply_free[ioc->reply_free_host_index] =
  803. cpu_to_le32(reply);
  804. wmb();
  805. writel(ioc->reply_free_host_index,
  806. &ioc->chip->ReplyFreeHostIndex);
  807. }
  808. next:
  809. rpf->Words = ULLONG_MAX;
  810. ioc->reply_post_host_index = (ioc->reply_post_host_index ==
  811. (ioc->reply_post_queue_depth - 1)) ? 0 :
  812. ioc->reply_post_host_index + 1;
  813. request_desript_type =
  814. ioc->reply_post_free[ioc->reply_post_host_index].Default.
  815. ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  816. completed_cmds++;
  817. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  818. goto out;
  819. if (!ioc->reply_post_host_index)
  820. rpf = ioc->reply_post_free;
  821. else
  822. rpf++;
  823. } while (1);
  824. out:
  825. if (!completed_cmds)
  826. return IRQ_NONE;
  827. wmb();
  828. writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex);
  829. return IRQ_HANDLED;
  830. }
  831. /**
  832. * mpt2sas_base_release_callback_handler - clear interupt callback handler
  833. * @cb_idx: callback index
  834. *
  835. * Return nothing.
  836. */
  837. void
  838. mpt2sas_base_release_callback_handler(u8 cb_idx)
  839. {
  840. mpt_callbacks[cb_idx] = NULL;
  841. }
  842. /**
  843. * mpt2sas_base_register_callback_handler - obtain index for the interrupt callback handler
  844. * @cb_func: callback function
  845. *
  846. * Returns cb_func.
  847. */
  848. u8
  849. mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  850. {
  851. u8 cb_idx;
  852. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  853. if (mpt_callbacks[cb_idx] == NULL)
  854. break;
  855. mpt_callbacks[cb_idx] = cb_func;
  856. return cb_idx;
  857. }
  858. /**
  859. * mpt2sas_base_initialize_callback_handler - initialize the interrupt callback handler
  860. *
  861. * Return nothing.
  862. */
  863. void
  864. mpt2sas_base_initialize_callback_handler(void)
  865. {
  866. u8 cb_idx;
  867. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  868. mpt2sas_base_release_callback_handler(cb_idx);
  869. }
  870. /**
  871. * mpt2sas_base_build_zero_len_sge - build zero length sg entry
  872. * @ioc: per adapter object
  873. * @paddr: virtual address for SGE
  874. *
  875. * Create a zero length scatter gather entry to insure the IOCs hardware has
  876. * something to use if the target device goes brain dead and tries
  877. * to send data even when none is asked for.
  878. *
  879. * Return nothing.
  880. */
  881. void
  882. mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
  883. {
  884. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  885. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  886. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  887. MPI2_SGE_FLAGS_SHIFT);
  888. ioc->base_add_sg_single(paddr, flags_length, -1);
  889. }
  890. /**
  891. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  892. * @paddr: virtual address for SGE
  893. * @flags_length: SGE flags and data transfer length
  894. * @dma_addr: Physical address
  895. *
  896. * Return nothing.
  897. */
  898. static void
  899. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  900. {
  901. Mpi2SGESimple32_t *sgel = paddr;
  902. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  903. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  904. sgel->FlagsLength = cpu_to_le32(flags_length);
  905. sgel->Address = cpu_to_le32(dma_addr);
  906. }
  907. /**
  908. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  909. * @paddr: virtual address for SGE
  910. * @flags_length: SGE flags and data transfer length
  911. * @dma_addr: Physical address
  912. *
  913. * Return nothing.
  914. */
  915. static void
  916. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  917. {
  918. Mpi2SGESimple64_t *sgel = paddr;
  919. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  920. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  921. sgel->FlagsLength = cpu_to_le32(flags_length);
  922. sgel->Address = cpu_to_le64(dma_addr);
  923. }
  924. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  925. /**
  926. * _base_config_dma_addressing - set dma addressing
  927. * @ioc: per adapter object
  928. * @pdev: PCI device struct
  929. *
  930. * Returns 0 for success, non-zero for failure.
  931. */
  932. static int
  933. _base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
  934. {
  935. struct sysinfo s;
  936. char *desc = NULL;
  937. if (sizeof(dma_addr_t) > 4) {
  938. const uint64_t required_mask =
  939. dma_get_required_mask(&pdev->dev);
  940. if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
  941. DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
  942. DMA_BIT_MASK(64))) {
  943. ioc->base_add_sg_single = &_base_add_sg_single_64;
  944. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  945. desc = "64";
  946. goto out;
  947. }
  948. }
  949. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  950. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  951. ioc->base_add_sg_single = &_base_add_sg_single_32;
  952. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  953. desc = "32";
  954. } else
  955. return -ENODEV;
  956. out:
  957. si_meminfo(&s);
  958. printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
  959. "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
  960. return 0;
  961. }
  962. /**
  963. * _base_save_msix_table - backup msix vector table
  964. * @ioc: per adapter object
  965. *
  966. * This address an errata where diag reset clears out the table
  967. */
  968. static void
  969. _base_save_msix_table(struct MPT2SAS_ADAPTER *ioc)
  970. {
  971. int i;
  972. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  973. return;
  974. for (i = 0; i < ioc->msix_vector_count; i++)
  975. ioc->msix_table_backup[i] = ioc->msix_table[i];
  976. }
  977. /**
  978. * _base_restore_msix_table - this restores the msix vector table
  979. * @ioc: per adapter object
  980. *
  981. */
  982. static void
  983. _base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc)
  984. {
  985. int i;
  986. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  987. return;
  988. for (i = 0; i < ioc->msix_vector_count; i++)
  989. ioc->msix_table[i] = ioc->msix_table_backup[i];
  990. }
  991. /**
  992. * _base_check_enable_msix - checks MSIX capabable.
  993. * @ioc: per adapter object
  994. *
  995. * Check to see if card is capable of MSIX, and set number
  996. * of avaliable msix vectors
  997. */
  998. static int
  999. _base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1000. {
  1001. int base;
  1002. u16 message_control;
  1003. u32 msix_table_offset;
  1004. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  1005. if (!base) {
  1006. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
  1007. "supported\n", ioc->name));
  1008. return -EINVAL;
  1009. }
  1010. /* get msix vector count */
  1011. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  1012. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  1013. /* get msix table */
  1014. pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset);
  1015. msix_table_offset &= 0xFFFFFFF8;
  1016. ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset);
  1017. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
  1018. "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name,
  1019. ioc->msix_vector_count, msix_table_offset, ioc->msix_table));
  1020. return 0;
  1021. }
  1022. /**
  1023. * _base_disable_msix - disables msix
  1024. * @ioc: per adapter object
  1025. *
  1026. */
  1027. static void
  1028. _base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
  1029. {
  1030. if (ioc->msix_enable) {
  1031. pci_disable_msix(ioc->pdev);
  1032. kfree(ioc->msix_table_backup);
  1033. ioc->msix_table_backup = NULL;
  1034. ioc->msix_enable = 0;
  1035. }
  1036. }
  1037. /**
  1038. * _base_enable_msix - enables msix, failback to io_apic
  1039. * @ioc: per adapter object
  1040. *
  1041. */
  1042. static int
  1043. _base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1044. {
  1045. struct msix_entry entries;
  1046. int r;
  1047. u8 try_msix = 0;
  1048. if (msix_disable == -1 || msix_disable == 0)
  1049. try_msix = 1;
  1050. if (!try_msix)
  1051. goto try_ioapic;
  1052. if (_base_check_enable_msix(ioc) != 0)
  1053. goto try_ioapic;
  1054. ioc->msix_table_backup = kcalloc(ioc->msix_vector_count,
  1055. sizeof(u32), GFP_KERNEL);
  1056. if (!ioc->msix_table_backup) {
  1057. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
  1058. "msix_table_backup failed!!!\n", ioc->name));
  1059. goto try_ioapic;
  1060. }
  1061. memset(&entries, 0, sizeof(struct msix_entry));
  1062. r = pci_enable_msix(ioc->pdev, &entries, 1);
  1063. if (r) {
  1064. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
  1065. "failed (r=%d) !!!\n", ioc->name, r));
  1066. goto try_ioapic;
  1067. }
  1068. r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED,
  1069. ioc->name, ioc);
  1070. if (r) {
  1071. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate "
  1072. "interrupt %d !!!\n", ioc->name, entries.vector));
  1073. pci_disable_msix(ioc->pdev);
  1074. goto try_ioapic;
  1075. }
  1076. ioc->pci_irq = entries.vector;
  1077. ioc->msix_enable = 1;
  1078. return 0;
  1079. /* failback to io_apic interrupt routing */
  1080. try_ioapic:
  1081. r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED,
  1082. ioc->name, ioc);
  1083. if (r) {
  1084. printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
  1085. ioc->name, ioc->pdev->irq);
  1086. r = -EBUSY;
  1087. goto out_fail;
  1088. }
  1089. ioc->pci_irq = ioc->pdev->irq;
  1090. return 0;
  1091. out_fail:
  1092. return r;
  1093. }
  1094. /**
  1095. * mpt2sas_base_map_resources - map in controller resources (io/irq/memap)
  1096. * @ioc: per adapter object
  1097. *
  1098. * Returns 0 for success, non-zero for failure.
  1099. */
  1100. int
  1101. mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
  1102. {
  1103. struct pci_dev *pdev = ioc->pdev;
  1104. u32 memap_sz;
  1105. u32 pio_sz;
  1106. int i, r = 0;
  1107. u64 pio_chip = 0;
  1108. u64 chip_phys = 0;
  1109. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n",
  1110. ioc->name, __func__));
  1111. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1112. if (pci_enable_device_mem(pdev)) {
  1113. printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
  1114. "failed\n", ioc->name);
  1115. return -ENODEV;
  1116. }
  1117. if (pci_request_selected_regions(pdev, ioc->bars,
  1118. MPT2SAS_DRIVER_NAME)) {
  1119. printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
  1120. "failed\n", ioc->name);
  1121. r = -ENODEV;
  1122. goto out_fail;
  1123. }
  1124. /* AER (Advanced Error Reporting) hooks */
  1125. pci_enable_pcie_error_reporting(pdev);
  1126. pci_set_master(pdev);
  1127. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1128. printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
  1129. ioc->name, pci_name(pdev));
  1130. r = -ENODEV;
  1131. goto out_fail;
  1132. }
  1133. for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
  1134. if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  1135. if (pio_sz)
  1136. continue;
  1137. pio_chip = (u64)pci_resource_start(pdev, i);
  1138. pio_sz = pci_resource_len(pdev, i);
  1139. } else {
  1140. if (memap_sz)
  1141. continue;
  1142. /* verify memory resource is valid before using */
  1143. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  1144. ioc->chip_phys = pci_resource_start(pdev, i);
  1145. chip_phys = (u64)ioc->chip_phys;
  1146. memap_sz = pci_resource_len(pdev, i);
  1147. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1148. if (ioc->chip == NULL) {
  1149. printk(MPT2SAS_ERR_FMT "unable to map "
  1150. "adapter memory!\n", ioc->name);
  1151. r = -EINVAL;
  1152. goto out_fail;
  1153. }
  1154. }
  1155. }
  1156. }
  1157. _base_mask_interrupts(ioc);
  1158. r = _base_enable_msix(ioc);
  1159. if (r)
  1160. goto out_fail;
  1161. printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
  1162. ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1163. "IO-APIC enabled"), ioc->pci_irq);
  1164. printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1165. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1166. printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
  1167. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1168. /* Save PCI configuration state for recovery from PCI AER/EEH errors */
  1169. pci_save_state(pdev);
  1170. return 0;
  1171. out_fail:
  1172. if (ioc->chip_phys)
  1173. iounmap(ioc->chip);
  1174. ioc->chip_phys = 0;
  1175. ioc->pci_irq = -1;
  1176. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1177. pci_disable_pcie_error_reporting(pdev);
  1178. pci_disable_device(pdev);
  1179. return r;
  1180. }
  1181. /**
  1182. * mpt2sas_base_get_msg_frame - obtain request mf pointer
  1183. * @ioc: per adapter object
  1184. * @smid: system request message index(smid zero is invalid)
  1185. *
  1186. * Returns virt pointer to message frame.
  1187. */
  1188. void *
  1189. mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1190. {
  1191. return (void *)(ioc->request + (smid * ioc->request_sz));
  1192. }
  1193. /**
  1194. * mpt2sas_base_get_sense_buffer - obtain a sense buffer assigned to a mf request
  1195. * @ioc: per adapter object
  1196. * @smid: system request message index
  1197. *
  1198. * Returns virt pointer to sense buffer.
  1199. */
  1200. void *
  1201. mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1202. {
  1203. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1204. }
  1205. /**
  1206. * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer assigned to a mf request
  1207. * @ioc: per adapter object
  1208. * @smid: system request message index
  1209. *
  1210. * Returns phys pointer to the low 32bit address of the sense buffer.
  1211. */
  1212. __le32
  1213. mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1214. {
  1215. return cpu_to_le32(ioc->sense_dma +
  1216. ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1217. }
  1218. /**
  1219. * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address
  1220. * @ioc: per adapter object
  1221. * @phys_addr: lower 32 physical addr of the reply
  1222. *
  1223. * Converts 32bit lower physical addr into a virt address.
  1224. */
  1225. void *
  1226. mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
  1227. {
  1228. if (!phys_addr)
  1229. return NULL;
  1230. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1231. }
  1232. /**
  1233. * mpt2sas_base_get_smid - obtain a free smid from internal queue
  1234. * @ioc: per adapter object
  1235. * @cb_idx: callback index
  1236. *
  1237. * Returns smid (zero is invalid)
  1238. */
  1239. u16
  1240. mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1241. {
  1242. unsigned long flags;
  1243. struct request_tracker *request;
  1244. u16 smid;
  1245. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1246. if (list_empty(&ioc->internal_free_list)) {
  1247. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1248. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1249. ioc->name, __func__);
  1250. return 0;
  1251. }
  1252. request = list_entry(ioc->internal_free_list.next,
  1253. struct request_tracker, tracker_list);
  1254. request->cb_idx = cb_idx;
  1255. smid = request->smid;
  1256. list_del(&request->tracker_list);
  1257. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1258. return smid;
  1259. }
  1260. /**
  1261. * mpt2sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1262. * @ioc: per adapter object
  1263. * @cb_idx: callback index
  1264. * @scmd: pointer to scsi command object
  1265. *
  1266. * Returns smid (zero is invalid)
  1267. */
  1268. u16
  1269. mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
  1270. struct scsi_cmnd *scmd)
  1271. {
  1272. unsigned long flags;
  1273. struct scsiio_tracker *request;
  1274. u16 smid;
  1275. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1276. if (list_empty(&ioc->free_list)) {
  1277. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1278. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1279. ioc->name, __func__);
  1280. return 0;
  1281. }
  1282. request = list_entry(ioc->free_list.next,
  1283. struct scsiio_tracker, tracker_list);
  1284. request->scmd = scmd;
  1285. request->cb_idx = cb_idx;
  1286. smid = request->smid;
  1287. list_del(&request->tracker_list);
  1288. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1289. return smid;
  1290. }
  1291. /**
  1292. * mpt2sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1293. * @ioc: per adapter object
  1294. * @cb_idx: callback index
  1295. *
  1296. * Returns smid (zero is invalid)
  1297. */
  1298. u16
  1299. mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1300. {
  1301. unsigned long flags;
  1302. struct request_tracker *request;
  1303. u16 smid;
  1304. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1305. if (list_empty(&ioc->hpr_free_list)) {
  1306. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1307. return 0;
  1308. }
  1309. request = list_entry(ioc->hpr_free_list.next,
  1310. struct request_tracker, tracker_list);
  1311. request->cb_idx = cb_idx;
  1312. smid = request->smid;
  1313. list_del(&request->tracker_list);
  1314. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1315. return smid;
  1316. }
  1317. /**
  1318. * mpt2sas_base_free_smid - put smid back on free_list
  1319. * @ioc: per adapter object
  1320. * @smid: system request message index
  1321. *
  1322. * Return nothing.
  1323. */
  1324. void
  1325. mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1326. {
  1327. unsigned long flags;
  1328. int i;
  1329. struct chain_tracker *chain_req, *next;
  1330. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1331. if (smid < ioc->hi_priority_smid) {
  1332. /* scsiio queue */
  1333. i = smid - 1;
  1334. if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
  1335. list_for_each_entry_safe(chain_req, next,
  1336. &ioc->scsi_lookup[i].chain_list, tracker_list) {
  1337. list_del_init(&chain_req->tracker_list);
  1338. list_add_tail(&chain_req->tracker_list,
  1339. &ioc->free_chain_list);
  1340. }
  1341. }
  1342. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1343. ioc->scsi_lookup[i].scmd = NULL;
  1344. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  1345. &ioc->free_list);
  1346. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1347. /*
  1348. * See _wait_for_commands_to_complete() call with regards
  1349. * to this code.
  1350. */
  1351. if (ioc->shost_recovery && ioc->pending_io_count) {
  1352. if (ioc->pending_io_count == 1)
  1353. wake_up(&ioc->reset_wq);
  1354. ioc->pending_io_count--;
  1355. }
  1356. return;
  1357. } else if (smid < ioc->internal_smid) {
  1358. /* hi-priority */
  1359. i = smid - ioc->hi_priority_smid;
  1360. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1361. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  1362. &ioc->hpr_free_list);
  1363. } else if (smid <= ioc->hba_queue_depth) {
  1364. /* internal queue */
  1365. i = smid - ioc->internal_smid;
  1366. ioc->internal_lookup[i].cb_idx = 0xFF;
  1367. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  1368. &ioc->internal_free_list);
  1369. }
  1370. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1371. }
  1372. /**
  1373. * _base_writeq - 64 bit write to MMIO
  1374. * @ioc: per adapter object
  1375. * @b: data payload
  1376. * @addr: address in MMIO space
  1377. * @writeq_lock: spin lock
  1378. *
  1379. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1380. * care of 32 bit environment where its not quarenteed to send the entire word
  1381. * in one transfer.
  1382. */
  1383. #ifndef writeq
  1384. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1385. spinlock_t *writeq_lock)
  1386. {
  1387. unsigned long flags;
  1388. __u64 data_out = cpu_to_le64(b);
  1389. spin_lock_irqsave(writeq_lock, flags);
  1390. writel((u32)(data_out), addr);
  1391. writel((u32)(data_out >> 32), (addr + 4));
  1392. spin_unlock_irqrestore(writeq_lock, flags);
  1393. }
  1394. #else
  1395. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1396. spinlock_t *writeq_lock)
  1397. {
  1398. writeq(cpu_to_le64(b), addr);
  1399. }
  1400. #endif
  1401. /**
  1402. * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1403. * @ioc: per adapter object
  1404. * @smid: system request message index
  1405. * @handle: device handle
  1406. *
  1407. * Return nothing.
  1408. */
  1409. void
  1410. mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1411. {
  1412. Mpi2RequestDescriptorUnion_t descriptor;
  1413. u64 *request = (u64 *)&descriptor;
  1414. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1415. descriptor.SCSIIO.MSIxIndex = 0; /* TODO */
  1416. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1417. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1418. descriptor.SCSIIO.LMID = 0;
  1419. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1420. &ioc->scsi_lookup_lock);
  1421. }
  1422. /**
  1423. * mpt2sas_base_put_smid_hi_priority - send Task Managment request to firmware
  1424. * @ioc: per adapter object
  1425. * @smid: system request message index
  1426. *
  1427. * Return nothing.
  1428. */
  1429. void
  1430. mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1431. {
  1432. Mpi2RequestDescriptorUnion_t descriptor;
  1433. u64 *request = (u64 *)&descriptor;
  1434. descriptor.HighPriority.RequestFlags =
  1435. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1436. descriptor.HighPriority.MSIxIndex = 0; /* TODO */
  1437. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1438. descriptor.HighPriority.LMID = 0;
  1439. descriptor.HighPriority.Reserved1 = 0;
  1440. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1441. &ioc->scsi_lookup_lock);
  1442. }
  1443. /**
  1444. * mpt2sas_base_put_smid_default - Default, primarily used for config pages
  1445. * @ioc: per adapter object
  1446. * @smid: system request message index
  1447. *
  1448. * Return nothing.
  1449. */
  1450. void
  1451. mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1452. {
  1453. Mpi2RequestDescriptorUnion_t descriptor;
  1454. u64 *request = (u64 *)&descriptor;
  1455. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1456. descriptor.Default.MSIxIndex = 0; /* TODO */
  1457. descriptor.Default.SMID = cpu_to_le16(smid);
  1458. descriptor.Default.LMID = 0;
  1459. descriptor.Default.DescriptorTypeDependent = 0;
  1460. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1461. &ioc->scsi_lookup_lock);
  1462. }
  1463. /**
  1464. * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware
  1465. * @ioc: per adapter object
  1466. * @smid: system request message index
  1467. * @io_index: value used to track the IO
  1468. *
  1469. * Return nothing.
  1470. */
  1471. void
  1472. mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
  1473. u16 io_index)
  1474. {
  1475. Mpi2RequestDescriptorUnion_t descriptor;
  1476. u64 *request = (u64 *)&descriptor;
  1477. descriptor.SCSITarget.RequestFlags =
  1478. MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
  1479. descriptor.SCSITarget.MSIxIndex = 0; /* TODO */
  1480. descriptor.SCSITarget.SMID = cpu_to_le16(smid);
  1481. descriptor.SCSITarget.LMID = 0;
  1482. descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
  1483. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1484. &ioc->scsi_lookup_lock);
  1485. }
  1486. /**
  1487. * _base_display_dell_branding - Disply branding string
  1488. * @ioc: per adapter object
  1489. *
  1490. * Return nothing.
  1491. */
  1492. static void
  1493. _base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
  1494. {
  1495. char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
  1496. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
  1497. return;
  1498. memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
  1499. switch (ioc->pdev->subsystem_device) {
  1500. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  1501. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
  1502. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1503. break;
  1504. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  1505. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
  1506. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1507. break;
  1508. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  1509. strncpy(dell_branding,
  1510. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
  1511. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1512. break;
  1513. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  1514. strncpy(dell_branding,
  1515. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
  1516. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1517. break;
  1518. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  1519. strncpy(dell_branding,
  1520. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
  1521. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1522. break;
  1523. case MPT2SAS_DELL_PERC_H200_SSDID:
  1524. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
  1525. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1526. break;
  1527. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  1528. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
  1529. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1530. break;
  1531. default:
  1532. sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
  1533. break;
  1534. }
  1535. printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
  1536. " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
  1537. ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
  1538. ioc->pdev->subsystem_device);
  1539. }
  1540. /**
  1541. * _base_display_intel_branding - Display branding string
  1542. * @ioc: per adapter object
  1543. *
  1544. * Return nothing.
  1545. */
  1546. static void
  1547. _base_display_intel_branding(struct MPT2SAS_ADAPTER *ioc)
  1548. {
  1549. if (ioc->pdev->subsystem_vendor == PCI_VENDOR_ID_INTEL &&
  1550. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008) {
  1551. switch (ioc->pdev->subsystem_device) {
  1552. case MPT2SAS_INTEL_RMS2LL080_SSDID:
  1553. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1554. MPT2SAS_INTEL_RMS2LL080_BRANDING);
  1555. break;
  1556. case MPT2SAS_INTEL_RMS2LL040_SSDID:
  1557. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1558. MPT2SAS_INTEL_RMS2LL040_BRANDING);
  1559. break;
  1560. }
  1561. }
  1562. }
  1563. /**
  1564. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1565. * @ioc: per adapter object
  1566. *
  1567. * Return nothing.
  1568. */
  1569. static void
  1570. _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
  1571. {
  1572. int i = 0;
  1573. char desc[16];
  1574. u8 revision;
  1575. u32 iounit_pg1_flags;
  1576. pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
  1577. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1578. printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
  1579. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  1580. ioc->name, desc,
  1581. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  1582. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  1583. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  1584. ioc->facts.FWVersion.Word & 0x000000FF,
  1585. revision,
  1586. (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24,
  1587. (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16,
  1588. (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
  1589. ioc->bios_pg3.BiosVersion & 0x000000FF);
  1590. _base_display_dell_branding(ioc);
  1591. _base_display_intel_branding(ioc);
  1592. printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
  1593. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  1594. printk("Initiator");
  1595. i++;
  1596. }
  1597. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  1598. printk("%sTarget", i ? "," : "");
  1599. i++;
  1600. }
  1601. i = 0;
  1602. printk("), ");
  1603. printk("Capabilities=(");
  1604. if (ioc->facts.IOCCapabilities &
  1605. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  1606. printk("Raid");
  1607. i++;
  1608. }
  1609. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  1610. printk("%sTLR", i ? "," : "");
  1611. i++;
  1612. }
  1613. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  1614. printk("%sMulticast", i ? "," : "");
  1615. i++;
  1616. }
  1617. if (ioc->facts.IOCCapabilities &
  1618. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  1619. printk("%sBIDI Target", i ? "," : "");
  1620. i++;
  1621. }
  1622. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  1623. printk("%sEEDP", i ? "," : "");
  1624. i++;
  1625. }
  1626. if (ioc->facts.IOCCapabilities &
  1627. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  1628. printk("%sSnapshot Buffer", i ? "," : "");
  1629. i++;
  1630. }
  1631. if (ioc->facts.IOCCapabilities &
  1632. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  1633. printk("%sDiag Trace Buffer", i ? "," : "");
  1634. i++;
  1635. }
  1636. if (ioc->facts.IOCCapabilities &
  1637. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  1638. printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
  1639. i++;
  1640. }
  1641. if (ioc->facts.IOCCapabilities &
  1642. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  1643. printk("%sTask Set Full", i ? "," : "");
  1644. i++;
  1645. }
  1646. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1647. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  1648. printk("%sNCQ", i ? "," : "");
  1649. i++;
  1650. }
  1651. printk(")\n");
  1652. }
  1653. /**
  1654. * _base_update_missing_delay - change the missing delay timers
  1655. * @ioc: per adapter object
  1656. * @device_missing_delay: amount of time till device is reported missing
  1657. * @io_missing_delay: interval IO is returned when there is a missing device
  1658. *
  1659. * Return nothing.
  1660. *
  1661. * Passed on the command line, this function will modify the device missing
  1662. * delay, as well as the io missing delay. This should be called at driver
  1663. * load time.
  1664. */
  1665. static void
  1666. _base_update_missing_delay(struct MPT2SAS_ADAPTER *ioc,
  1667. u16 device_missing_delay, u8 io_missing_delay)
  1668. {
  1669. u16 dmd, dmd_new, dmd_orignal;
  1670. u8 io_missing_delay_original;
  1671. u16 sz;
  1672. Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
  1673. Mpi2ConfigReply_t mpi_reply;
  1674. u8 num_phys = 0;
  1675. u16 ioc_status;
  1676. mpt2sas_config_get_number_hba_phys(ioc, &num_phys);
  1677. if (!num_phys)
  1678. return;
  1679. sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
  1680. sizeof(Mpi2SasIOUnit1PhyData_t));
  1681. sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
  1682. if (!sas_iounit_pg1) {
  1683. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  1684. ioc->name, __FILE__, __LINE__, __func__);
  1685. goto out;
  1686. }
  1687. if ((mpt2sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
  1688. sas_iounit_pg1, sz))) {
  1689. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  1690. ioc->name, __FILE__, __LINE__, __func__);
  1691. goto out;
  1692. }
  1693. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
  1694. MPI2_IOCSTATUS_MASK;
  1695. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  1696. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  1697. ioc->name, __FILE__, __LINE__, __func__);
  1698. goto out;
  1699. }
  1700. /* device missing delay */
  1701. dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
  1702. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  1703. dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  1704. else
  1705. dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  1706. dmd_orignal = dmd;
  1707. if (device_missing_delay > 0x7F) {
  1708. dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
  1709. device_missing_delay;
  1710. dmd = dmd / 16;
  1711. dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
  1712. } else
  1713. dmd = device_missing_delay;
  1714. sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
  1715. /* io missing delay */
  1716. io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
  1717. sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
  1718. if (!mpt2sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
  1719. sz)) {
  1720. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  1721. dmd_new = (dmd &
  1722. MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  1723. else
  1724. dmd_new =
  1725. dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  1726. printk(MPT2SAS_INFO_FMT "device_missing_delay: old(%d), "
  1727. "new(%d)\n", ioc->name, dmd_orignal, dmd_new);
  1728. printk(MPT2SAS_INFO_FMT "ioc_missing_delay: old(%d), "
  1729. "new(%d)\n", ioc->name, io_missing_delay_original,
  1730. io_missing_delay);
  1731. ioc->device_missing_delay = dmd_new;
  1732. ioc->io_missing_delay = io_missing_delay;
  1733. }
  1734. out:
  1735. kfree(sas_iounit_pg1);
  1736. }
  1737. /**
  1738. * _base_static_config_pages - static start of day config pages
  1739. * @ioc: per adapter object
  1740. *
  1741. * Return nothing.
  1742. */
  1743. static void
  1744. _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
  1745. {
  1746. Mpi2ConfigReply_t mpi_reply;
  1747. u32 iounit_pg1_flags;
  1748. mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  1749. if (ioc->ir_firmware)
  1750. mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  1751. &ioc->manu_pg10);
  1752. mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  1753. mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  1754. mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  1755. mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  1756. mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1757. _base_display_ioc_capabilities(ioc);
  1758. /*
  1759. * Enable task_set_full handling in iounit_pg1 when the
  1760. * facts capabilities indicate that its supported.
  1761. */
  1762. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1763. if ((ioc->facts.IOCCapabilities &
  1764. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  1765. iounit_pg1_flags &=
  1766. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1767. else
  1768. iounit_pg1_flags |=
  1769. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1770. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  1771. mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1772. }
  1773. /**
  1774. * _base_release_memory_pools - release memory
  1775. * @ioc: per adapter object
  1776. *
  1777. * Free memory allocated from _base_allocate_memory_pools.
  1778. *
  1779. * Return nothing.
  1780. */
  1781. static void
  1782. _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
  1783. {
  1784. int i;
  1785. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1786. __func__));
  1787. if (ioc->request) {
  1788. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  1789. ioc->request, ioc->request_dma);
  1790. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
  1791. ": free\n", ioc->name, ioc->request));
  1792. ioc->request = NULL;
  1793. }
  1794. if (ioc->sense) {
  1795. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  1796. if (ioc->sense_dma_pool)
  1797. pci_pool_destroy(ioc->sense_dma_pool);
  1798. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
  1799. ": free\n", ioc->name, ioc->sense));
  1800. ioc->sense = NULL;
  1801. }
  1802. if (ioc->reply) {
  1803. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  1804. if (ioc->reply_dma_pool)
  1805. pci_pool_destroy(ioc->reply_dma_pool);
  1806. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
  1807. ": free\n", ioc->name, ioc->reply));
  1808. ioc->reply = NULL;
  1809. }
  1810. if (ioc->reply_free) {
  1811. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  1812. ioc->reply_free_dma);
  1813. if (ioc->reply_free_dma_pool)
  1814. pci_pool_destroy(ioc->reply_free_dma_pool);
  1815. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
  1816. "(0x%p): free\n", ioc->name, ioc->reply_free));
  1817. ioc->reply_free = NULL;
  1818. }
  1819. if (ioc->reply_post_free) {
  1820. pci_pool_free(ioc->reply_post_free_dma_pool,
  1821. ioc->reply_post_free, ioc->reply_post_free_dma);
  1822. if (ioc->reply_post_free_dma_pool)
  1823. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  1824. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1825. "reply_post_free_pool(0x%p): free\n", ioc->name,
  1826. ioc->reply_post_free));
  1827. ioc->reply_post_free = NULL;
  1828. }
  1829. if (ioc->config_page) {
  1830. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1831. "config_page(0x%p): free\n", ioc->name,
  1832. ioc->config_page));
  1833. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  1834. ioc->config_page, ioc->config_page_dma);
  1835. }
  1836. if (ioc->scsi_lookup) {
  1837. free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
  1838. ioc->scsi_lookup = NULL;
  1839. }
  1840. kfree(ioc->hpr_lookup);
  1841. kfree(ioc->internal_lookup);
  1842. if (ioc->chain_lookup) {
  1843. for (i = 0; i < ioc->chain_depth; i++) {
  1844. if (ioc->chain_lookup[i].chain_buffer)
  1845. pci_pool_free(ioc->chain_dma_pool,
  1846. ioc->chain_lookup[i].chain_buffer,
  1847. ioc->chain_lookup[i].chain_buffer_dma);
  1848. }
  1849. if (ioc->chain_dma_pool)
  1850. pci_pool_destroy(ioc->chain_dma_pool);
  1851. }
  1852. if (ioc->chain_lookup) {
  1853. free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
  1854. ioc->chain_lookup = NULL;
  1855. }
  1856. }
  1857. /**
  1858. * _base_allocate_memory_pools - allocate start of day memory pools
  1859. * @ioc: per adapter object
  1860. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  1861. *
  1862. * Returns 0 success, anything else error
  1863. */
  1864. static int
  1865. _base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  1866. {
  1867. Mpi2IOCFactsReply_t *facts;
  1868. u32 queue_size, queue_diff;
  1869. u16 max_sge_elements;
  1870. u16 num_of_reply_frames;
  1871. u16 chains_needed_per_io;
  1872. u32 sz, total_sz;
  1873. u32 retry_sz;
  1874. u16 max_request_credit;
  1875. int i;
  1876. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1877. __func__));
  1878. retry_sz = 0;
  1879. facts = &ioc->facts;
  1880. /* command line tunables for max sgl entries */
  1881. if (max_sgl_entries != -1) {
  1882. ioc->shost->sg_tablesize = (max_sgl_entries <
  1883. MPT2SAS_SG_DEPTH) ? max_sgl_entries :
  1884. MPT2SAS_SG_DEPTH;
  1885. } else {
  1886. ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
  1887. }
  1888. /* command line tunables for max controller queue depth */
  1889. if (max_queue_depth != -1)
  1890. max_request_credit = (max_queue_depth < facts->RequestCredit)
  1891. ? max_queue_depth : facts->RequestCredit;
  1892. else
  1893. max_request_credit = facts->RequestCredit;
  1894. ioc->hba_queue_depth = max_request_credit;
  1895. ioc->hi_priority_depth = facts->HighPriorityCredit;
  1896. ioc->internal_depth = ioc->hi_priority_depth + 5;
  1897. /* request frame size */
  1898. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  1899. /* reply frame size */
  1900. ioc->reply_sz = facts->ReplyFrameSize * 4;
  1901. retry_allocation:
  1902. total_sz = 0;
  1903. /* calculate number of sg elements left over in the 1st frame */
  1904. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  1905. sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
  1906. ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
  1907. /* now do the same for a chain buffer */
  1908. max_sge_elements = ioc->request_sz - ioc->sge_size;
  1909. ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
  1910. ioc->chain_offset_value_for_main_message =
  1911. ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
  1912. (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
  1913. /*
  1914. * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  1915. */
  1916. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  1917. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  1918. + 1;
  1919. if (chains_needed_per_io > facts->MaxChainDepth) {
  1920. chains_needed_per_io = facts->MaxChainDepth;
  1921. ioc->shost->sg_tablesize = min_t(u16,
  1922. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  1923. * chains_needed_per_io), ioc->shost->sg_tablesize);
  1924. }
  1925. ioc->chains_needed_per_io = chains_needed_per_io;
  1926. /* reply free queue sizing - taking into account for events */
  1927. num_of_reply_frames = ioc->hba_queue_depth + 32;
  1928. /* number of replies frames can't be a multiple of 16 */
  1929. /* decrease number of reply frames by 1 */
  1930. if (!(num_of_reply_frames % 16))
  1931. num_of_reply_frames--;
  1932. /* calculate number of reply free queue entries
  1933. * (must be multiple of 16)
  1934. */
  1935. /* (we know reply_free_queue_depth is not a multiple of 16) */
  1936. queue_size = num_of_reply_frames;
  1937. queue_size += 16 - (queue_size % 16);
  1938. ioc->reply_free_queue_depth = queue_size;
  1939. /* reply descriptor post queue sizing */
  1940. /* this size should be the number of request frames + number of reply
  1941. * frames
  1942. */
  1943. queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
  1944. /* round up to 16 byte boundary */
  1945. if (queue_size % 16)
  1946. queue_size += 16 - (queue_size % 16);
  1947. /* check against IOC maximum reply post queue depth */
  1948. if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
  1949. queue_diff = queue_size -
  1950. facts->MaxReplyDescriptorPostQueueDepth;
  1951. /* round queue_diff up to multiple of 16 */
  1952. if (queue_diff % 16)
  1953. queue_diff += 16 - (queue_diff % 16);
  1954. /* adjust hba_queue_depth, reply_free_queue_depth,
  1955. * and queue_size
  1956. */
  1957. ioc->hba_queue_depth -= (queue_diff / 2);
  1958. ioc->reply_free_queue_depth -= (queue_diff / 2);
  1959. queue_size = facts->MaxReplyDescriptorPostQueueDepth;
  1960. }
  1961. ioc->reply_post_queue_depth = queue_size;
  1962. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
  1963. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  1964. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  1965. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  1966. ioc->chains_needed_per_io));
  1967. ioc->scsiio_depth = ioc->hba_queue_depth -
  1968. ioc->hi_priority_depth - ioc->internal_depth;
  1969. /* set the scsi host can_queue depth
  1970. * with some internal commands that could be outstanding
  1971. */
  1972. ioc->shost->can_queue = ioc->scsiio_depth - (2);
  1973. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
  1974. "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
  1975. /* contiguous pool for request and chains, 16 byte align, one extra "
  1976. * "frame for smid=0
  1977. */
  1978. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  1979. sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
  1980. /* hi-priority queue */
  1981. sz += (ioc->hi_priority_depth * ioc->request_sz);
  1982. /* internal queue */
  1983. sz += (ioc->internal_depth * ioc->request_sz);
  1984. ioc->request_dma_sz = sz;
  1985. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  1986. if (!ioc->request) {
  1987. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1988. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1989. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  1990. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1991. if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
  1992. goto out;
  1993. retry_sz += 64;
  1994. ioc->hba_queue_depth = max_request_credit - retry_sz;
  1995. goto retry_allocation;
  1996. }
  1997. if (retry_sz)
  1998. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1999. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  2000. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  2001. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  2002. /* hi-priority queue */
  2003. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  2004. ioc->request_sz);
  2005. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  2006. ioc->request_sz);
  2007. /* internal queue */
  2008. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  2009. ioc->request_sz);
  2010. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  2011. ioc->request_sz);
  2012. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
  2013. "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  2014. ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  2015. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  2016. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
  2017. ioc->name, (unsigned long long) ioc->request_dma));
  2018. total_sz += sz;
  2019. sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
  2020. ioc->scsi_lookup_pages = get_order(sz);
  2021. ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
  2022. GFP_KERNEL, ioc->scsi_lookup_pages);
  2023. if (!ioc->scsi_lookup) {
  2024. printk(MPT2SAS_ERR_FMT "scsi_lookup: get_free_pages failed, "
  2025. "sz(%d)\n", ioc->name, (int)sz);
  2026. goto out;
  2027. }
  2028. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
  2029. "depth(%d)\n", ioc->name, ioc->request,
  2030. ioc->scsiio_depth));
  2031. /* loop till the allocation succeeds */
  2032. do {
  2033. sz = ioc->chain_depth * sizeof(struct chain_tracker);
  2034. ioc->chain_pages = get_order(sz);
  2035. ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
  2036. GFP_KERNEL, ioc->chain_pages);
  2037. if (ioc->chain_lookup == NULL)
  2038. ioc->chain_depth -= 100;
  2039. } while (ioc->chain_lookup == NULL);
  2040. ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
  2041. ioc->request_sz, 16, 0);
  2042. if (!ioc->chain_dma_pool) {
  2043. printk(MPT2SAS_ERR_FMT "chain_dma_pool: pci_pool_create "
  2044. "failed\n", ioc->name);
  2045. goto out;
  2046. }
  2047. for (i = 0; i < ioc->chain_depth; i++) {
  2048. ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
  2049. ioc->chain_dma_pool , GFP_KERNEL,
  2050. &ioc->chain_lookup[i].chain_buffer_dma);
  2051. if (!ioc->chain_lookup[i].chain_buffer) {
  2052. ioc->chain_depth = i;
  2053. goto chain_done;
  2054. }
  2055. total_sz += ioc->request_sz;
  2056. }
  2057. chain_done:
  2058. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool depth"
  2059. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  2060. ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
  2061. ioc->request_sz))/1024));
  2062. /* initialize hi-priority queue smid's */
  2063. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  2064. sizeof(struct request_tracker), GFP_KERNEL);
  2065. if (!ioc->hpr_lookup) {
  2066. printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
  2067. ioc->name);
  2068. goto out;
  2069. }
  2070. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  2071. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
  2072. "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
  2073. ioc->hi_priority_depth, ioc->hi_priority_smid));
  2074. /* initialize internal queue smid's */
  2075. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  2076. sizeof(struct request_tracker), GFP_KERNEL);
  2077. if (!ioc->internal_lookup) {
  2078. printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
  2079. ioc->name);
  2080. goto out;
  2081. }
  2082. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  2083. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
  2084. "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
  2085. ioc->internal_depth, ioc->internal_smid));
  2086. /* sense buffers, 4 byte align */
  2087. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  2088. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  2089. 0);
  2090. if (!ioc->sense_dma_pool) {
  2091. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
  2092. ioc->name);
  2093. goto out;
  2094. }
  2095. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  2096. &ioc->sense_dma);
  2097. if (!ioc->sense) {
  2098. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
  2099. ioc->name);
  2100. goto out;
  2101. }
  2102. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2103. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  2104. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  2105. SCSI_SENSE_BUFFERSIZE, sz/1024));
  2106. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
  2107. ioc->name, (unsigned long long)ioc->sense_dma));
  2108. total_sz += sz;
  2109. /* reply pool, 4 byte align */
  2110. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  2111. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  2112. 0);
  2113. if (!ioc->reply_dma_pool) {
  2114. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
  2115. ioc->name);
  2116. goto out;
  2117. }
  2118. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  2119. &ioc->reply_dma);
  2120. if (!ioc->reply) {
  2121. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
  2122. ioc->name);
  2123. goto out;
  2124. }
  2125. ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
  2126. ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
  2127. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
  2128. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
  2129. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  2130. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
  2131. ioc->name, (unsigned long long)ioc->reply_dma));
  2132. total_sz += sz;
  2133. /* reply free queue, 16 byte align */
  2134. sz = ioc->reply_free_queue_depth * 4;
  2135. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  2136. ioc->pdev, sz, 16, 0);
  2137. if (!ioc->reply_free_dma_pool) {
  2138. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
  2139. "failed\n", ioc->name);
  2140. goto out;
  2141. }
  2142. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  2143. &ioc->reply_free_dma);
  2144. if (!ioc->reply_free) {
  2145. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
  2146. "failed\n", ioc->name);
  2147. goto out;
  2148. }
  2149. memset(ioc->reply_free, 0, sz);
  2150. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
  2151. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  2152. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  2153. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
  2154. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
  2155. total_sz += sz;
  2156. /* reply post queue, 16 byte align */
  2157. sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t);
  2158. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  2159. ioc->pdev, sz, 16, 0);
  2160. if (!ioc->reply_post_free_dma_pool) {
  2161. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
  2162. "failed\n", ioc->name);
  2163. goto out;
  2164. }
  2165. ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
  2166. GFP_KERNEL, &ioc->reply_post_free_dma);
  2167. if (!ioc->reply_post_free) {
  2168. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
  2169. "failed\n", ioc->name);
  2170. goto out;
  2171. }
  2172. memset(ioc->reply_post_free, 0, sz);
  2173. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
  2174. "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
  2175. ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
  2176. sz/1024));
  2177. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
  2178. "(0x%llx)\n", ioc->name, (unsigned long long)
  2179. ioc->reply_post_free_dma));
  2180. total_sz += sz;
  2181. ioc->config_page_sz = 512;
  2182. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  2183. ioc->config_page_sz, &ioc->config_page_dma);
  2184. if (!ioc->config_page) {
  2185. printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
  2186. "failed\n", ioc->name);
  2187. goto out;
  2188. }
  2189. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
  2190. "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
  2191. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
  2192. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
  2193. total_sz += ioc->config_page_sz;
  2194. printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
  2195. ioc->name, total_sz/1024);
  2196. printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
  2197. "Max Controller Queue Depth(%d)\n",
  2198. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  2199. printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
  2200. ioc->name, ioc->shost->sg_tablesize);
  2201. return 0;
  2202. out:
  2203. return -ENOMEM;
  2204. }
  2205. /**
  2206. * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter.
  2207. * @ioc: Pointer to MPT_ADAPTER structure
  2208. * @cooked: Request raw or cooked IOC state
  2209. *
  2210. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2211. * Doorbell bits in MPI_IOC_STATE_MASK.
  2212. */
  2213. u32
  2214. mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
  2215. {
  2216. u32 s, sc;
  2217. s = readl(&ioc->chip->Doorbell);
  2218. sc = s & MPI2_IOC_STATE_MASK;
  2219. return cooked ? sc : s;
  2220. }
  2221. /**
  2222. * _base_wait_on_iocstate - waiting on a particular ioc state
  2223. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  2224. * @timeout: timeout in second
  2225. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2226. *
  2227. * Returns 0 for success, non-zero for failure.
  2228. */
  2229. static int
  2230. _base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  2231. int sleep_flag)
  2232. {
  2233. u32 count, cntdn;
  2234. u32 current_state;
  2235. count = 0;
  2236. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2237. do {
  2238. current_state = mpt2sas_base_get_iocstate(ioc, 1);
  2239. if (current_state == ioc_state)
  2240. return 0;
  2241. if (count && current_state == MPI2_IOC_STATE_FAULT)
  2242. break;
  2243. if (sleep_flag == CAN_SLEEP)
  2244. msleep(1);
  2245. else
  2246. udelay(500);
  2247. count++;
  2248. } while (--cntdn);
  2249. return current_state;
  2250. }
  2251. /**
  2252. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2253. * a write to the doorbell)
  2254. * @ioc: per adapter object
  2255. * @timeout: timeout in second
  2256. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2257. *
  2258. * Returns 0 for success, non-zero for failure.
  2259. *
  2260. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2261. */
  2262. static int
  2263. _base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2264. int sleep_flag)
  2265. {
  2266. u32 cntdn, count;
  2267. u32 int_status;
  2268. count = 0;
  2269. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2270. do {
  2271. int_status = readl(&ioc->chip->HostInterruptStatus);
  2272. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2273. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2274. "successfull count(%d), timeout(%d)\n", ioc->name,
  2275. __func__, count, timeout));
  2276. return 0;
  2277. }
  2278. if (sleep_flag == CAN_SLEEP)
  2279. msleep(1);
  2280. else
  2281. udelay(500);
  2282. count++;
  2283. } while (--cntdn);
  2284. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2285. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2286. return -EFAULT;
  2287. }
  2288. /**
  2289. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2290. * @ioc: per adapter object
  2291. * @timeout: timeout in second
  2292. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2293. *
  2294. * Returns 0 for success, non-zero for failure.
  2295. *
  2296. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2297. * doorbell.
  2298. */
  2299. static int
  2300. _base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2301. int sleep_flag)
  2302. {
  2303. u32 cntdn, count;
  2304. u32 int_status;
  2305. u32 doorbell;
  2306. count = 0;
  2307. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2308. do {
  2309. int_status = readl(&ioc->chip->HostInterruptStatus);
  2310. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2311. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2312. "successfull count(%d), timeout(%d)\n", ioc->name,
  2313. __func__, count, timeout));
  2314. return 0;
  2315. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2316. doorbell = readl(&ioc->chip->Doorbell);
  2317. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2318. MPI2_IOC_STATE_FAULT) {
  2319. mpt2sas_base_fault_info(ioc , doorbell);
  2320. return -EFAULT;
  2321. }
  2322. } else if (int_status == 0xFFFFFFFF)
  2323. goto out;
  2324. if (sleep_flag == CAN_SLEEP)
  2325. msleep(1);
  2326. else
  2327. udelay(500);
  2328. count++;
  2329. } while (--cntdn);
  2330. out:
  2331. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2332. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2333. return -EFAULT;
  2334. }
  2335. /**
  2336. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2337. * @ioc: per adapter object
  2338. * @timeout: timeout in second
  2339. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2340. *
  2341. * Returns 0 for success, non-zero for failure.
  2342. *
  2343. */
  2344. static int
  2345. _base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2346. int sleep_flag)
  2347. {
  2348. u32 cntdn, count;
  2349. u32 doorbell_reg;
  2350. count = 0;
  2351. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2352. do {
  2353. doorbell_reg = readl(&ioc->chip->Doorbell);
  2354. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2355. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2356. "successfull count(%d), timeout(%d)\n", ioc->name,
  2357. __func__, count, timeout));
  2358. return 0;
  2359. }
  2360. if (sleep_flag == CAN_SLEEP)
  2361. msleep(1);
  2362. else
  2363. udelay(500);
  2364. count++;
  2365. } while (--cntdn);
  2366. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2367. "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
  2368. return -EFAULT;
  2369. }
  2370. /**
  2371. * _base_send_ioc_reset - send doorbell reset
  2372. * @ioc: per adapter object
  2373. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2374. * @timeout: timeout in second
  2375. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2376. *
  2377. * Returns 0 for success, non-zero for failure.
  2378. */
  2379. static int
  2380. _base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2381. int sleep_flag)
  2382. {
  2383. u32 ioc_state;
  2384. int r = 0;
  2385. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2386. printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
  2387. ioc->name, __func__);
  2388. return -EFAULT;
  2389. }
  2390. if (!(ioc->facts.IOCCapabilities &
  2391. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2392. return -EFAULT;
  2393. printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
  2394. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2395. &ioc->chip->Doorbell);
  2396. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2397. r = -EFAULT;
  2398. goto out;
  2399. }
  2400. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2401. timeout, sleep_flag);
  2402. if (ioc_state) {
  2403. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2404. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2405. r = -EFAULT;
  2406. goto out;
  2407. }
  2408. out:
  2409. printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
  2410. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2411. return r;
  2412. }
  2413. /**
  2414. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2415. * @ioc: per adapter object
  2416. * @request_bytes: request length
  2417. * @request: pointer having request payload
  2418. * @reply_bytes: reply length
  2419. * @reply: pointer to reply payload
  2420. * @timeout: timeout in second
  2421. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2422. *
  2423. * Returns 0 for success, non-zero for failure.
  2424. */
  2425. static int
  2426. _base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
  2427. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2428. {
  2429. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2430. int i;
  2431. u8 failed;
  2432. u16 dummy;
  2433. u32 *mfp;
  2434. /* make sure doorbell is not in use */
  2435. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2436. printk(MPT2SAS_ERR_FMT "doorbell is in use "
  2437. " (line=%d)\n", ioc->name, __LINE__);
  2438. return -EFAULT;
  2439. }
  2440. /* clear pending doorbell interrupts from previous state changes */
  2441. if (readl(&ioc->chip->HostInterruptStatus) &
  2442. MPI2_HIS_IOC2SYS_DB_STATUS)
  2443. writel(0, &ioc->chip->HostInterruptStatus);
  2444. /* send message to ioc */
  2445. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2446. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2447. &ioc->chip->Doorbell);
  2448. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2449. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2450. "int failed (line=%d)\n", ioc->name, __LINE__);
  2451. return -EFAULT;
  2452. }
  2453. writel(0, &ioc->chip->HostInterruptStatus);
  2454. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2455. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2456. "ack failed (line=%d)\n", ioc->name, __LINE__);
  2457. return -EFAULT;
  2458. }
  2459. /* send message 32-bits at a time */
  2460. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2461. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2462. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2463. failed = 1;
  2464. }
  2465. if (failed) {
  2466. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2467. "sending request failed (line=%d)\n", ioc->name, __LINE__);
  2468. return -EFAULT;
  2469. }
  2470. /* now wait for the reply */
  2471. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2472. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2473. "int failed (line=%d)\n", ioc->name, __LINE__);
  2474. return -EFAULT;
  2475. }
  2476. /* read the first two 16-bits, it gives the total length of the reply */
  2477. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2478. & MPI2_DOORBELL_DATA_MASK);
  2479. writel(0, &ioc->chip->HostInterruptStatus);
  2480. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2481. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2482. "int failed (line=%d)\n", ioc->name, __LINE__);
  2483. return -EFAULT;
  2484. }
  2485. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2486. & MPI2_DOORBELL_DATA_MASK);
  2487. writel(0, &ioc->chip->HostInterruptStatus);
  2488. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2489. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2490. printk(MPT2SAS_ERR_FMT "doorbell "
  2491. "handshake int failed (line=%d)\n", ioc->name,
  2492. __LINE__);
  2493. return -EFAULT;
  2494. }
  2495. if (i >= reply_bytes/2) /* overflow case */
  2496. dummy = readl(&ioc->chip->Doorbell);
  2497. else
  2498. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2499. & MPI2_DOORBELL_DATA_MASK);
  2500. writel(0, &ioc->chip->HostInterruptStatus);
  2501. }
  2502. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2503. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2504. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
  2505. " (line=%d)\n", ioc->name, __LINE__));
  2506. }
  2507. writel(0, &ioc->chip->HostInterruptStatus);
  2508. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2509. mfp = (u32 *)reply;
  2510. printk(KERN_INFO "\toffset:data\n");
  2511. for (i = 0; i < reply_bytes/4; i++)
  2512. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  2513. le32_to_cpu(mfp[i]));
  2514. }
  2515. return 0;
  2516. }
  2517. /**
  2518. * mpt2sas_base_sas_iounit_control - send sas iounit control to FW
  2519. * @ioc: per adapter object
  2520. * @mpi_reply: the reply payload from FW
  2521. * @mpi_request: the request payload sent to FW
  2522. *
  2523. * The SAS IO Unit Control Request message allows the host to perform low-level
  2524. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2525. * to obtain the IOC assigned device handles for a device if it has other
  2526. * identifying information about the device, in addition allows the host to
  2527. * remove IOC resources associated with the device.
  2528. *
  2529. * Returns 0 for success, non-zero for failure.
  2530. */
  2531. int
  2532. mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
  2533. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2534. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2535. {
  2536. u16 smid;
  2537. u32 ioc_state;
  2538. unsigned long timeleft;
  2539. u8 issue_reset;
  2540. int rc;
  2541. void *request;
  2542. u16 wait_state_count;
  2543. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2544. __func__));
  2545. mutex_lock(&ioc->base_cmds.mutex);
  2546. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2547. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2548. ioc->name, __func__);
  2549. rc = -EAGAIN;
  2550. goto out;
  2551. }
  2552. wait_state_count = 0;
  2553. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2554. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2555. if (wait_state_count++ == 10) {
  2556. printk(MPT2SAS_ERR_FMT
  2557. "%s: failed due to ioc not operational\n",
  2558. ioc->name, __func__);
  2559. rc = -EFAULT;
  2560. goto out;
  2561. }
  2562. ssleep(1);
  2563. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2564. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2565. "operational state(count=%d)\n", ioc->name,
  2566. __func__, wait_state_count);
  2567. }
  2568. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2569. if (!smid) {
  2570. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2571. ioc->name, __func__);
  2572. rc = -EAGAIN;
  2573. goto out;
  2574. }
  2575. rc = 0;
  2576. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2577. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2578. ioc->base_cmds.smid = smid;
  2579. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  2580. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2581. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  2582. ioc->ioc_link_reset_in_progress = 1;
  2583. mpt2sas_base_put_smid_default(ioc, smid);
  2584. init_completion(&ioc->base_cmds.done);
  2585. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2586. msecs_to_jiffies(10000));
  2587. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2588. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  2589. ioc->ioc_link_reset_in_progress)
  2590. ioc->ioc_link_reset_in_progress = 0;
  2591. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2592. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2593. ioc->name, __func__);
  2594. _debug_dump_mf(mpi_request,
  2595. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  2596. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2597. issue_reset = 1;
  2598. goto issue_host_reset;
  2599. }
  2600. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2601. memcpy(mpi_reply, ioc->base_cmds.reply,
  2602. sizeof(Mpi2SasIoUnitControlReply_t));
  2603. else
  2604. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  2605. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2606. goto out;
  2607. issue_host_reset:
  2608. if (issue_reset)
  2609. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2610. FORCE_BIG_HAMMER);
  2611. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2612. rc = -EFAULT;
  2613. out:
  2614. mutex_unlock(&ioc->base_cmds.mutex);
  2615. return rc;
  2616. }
  2617. /**
  2618. * mpt2sas_base_scsi_enclosure_processor - sending request to sep device
  2619. * @ioc: per adapter object
  2620. * @mpi_reply: the reply payload from FW
  2621. * @mpi_request: the request payload sent to FW
  2622. *
  2623. * The SCSI Enclosure Processor request message causes the IOC to
  2624. * communicate with SES devices to control LED status signals.
  2625. *
  2626. * Returns 0 for success, non-zero for failure.
  2627. */
  2628. int
  2629. mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
  2630. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  2631. {
  2632. u16 smid;
  2633. u32 ioc_state;
  2634. unsigned long timeleft;
  2635. u8 issue_reset;
  2636. int rc;
  2637. void *request;
  2638. u16 wait_state_count;
  2639. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2640. __func__));
  2641. mutex_lock(&ioc->base_cmds.mutex);
  2642. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2643. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2644. ioc->name, __func__);
  2645. rc = -EAGAIN;
  2646. goto out;
  2647. }
  2648. wait_state_count = 0;
  2649. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2650. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2651. if (wait_state_count++ == 10) {
  2652. printk(MPT2SAS_ERR_FMT
  2653. "%s: failed due to ioc not operational\n",
  2654. ioc->name, __func__);
  2655. rc = -EFAULT;
  2656. goto out;
  2657. }
  2658. ssleep(1);
  2659. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2660. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2661. "operational state(count=%d)\n", ioc->name,
  2662. __func__, wait_state_count);
  2663. }
  2664. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2665. if (!smid) {
  2666. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2667. ioc->name, __func__);
  2668. rc = -EAGAIN;
  2669. goto out;
  2670. }
  2671. rc = 0;
  2672. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2673. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2674. ioc->base_cmds.smid = smid;
  2675. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  2676. mpt2sas_base_put_smid_default(ioc, smid);
  2677. init_completion(&ioc->base_cmds.done);
  2678. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2679. msecs_to_jiffies(10000));
  2680. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2681. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2682. ioc->name, __func__);
  2683. _debug_dump_mf(mpi_request,
  2684. sizeof(Mpi2SepRequest_t)/4);
  2685. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2686. issue_reset = 1;
  2687. goto issue_host_reset;
  2688. }
  2689. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2690. memcpy(mpi_reply, ioc->base_cmds.reply,
  2691. sizeof(Mpi2SepReply_t));
  2692. else
  2693. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  2694. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2695. goto out;
  2696. issue_host_reset:
  2697. if (issue_reset)
  2698. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2699. FORCE_BIG_HAMMER);
  2700. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2701. rc = -EFAULT;
  2702. out:
  2703. mutex_unlock(&ioc->base_cmds.mutex);
  2704. return rc;
  2705. }
  2706. /**
  2707. * _base_get_port_facts - obtain port facts reply and save in ioc
  2708. * @ioc: per adapter object
  2709. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2710. *
  2711. * Returns 0 for success, non-zero for failure.
  2712. */
  2713. static int
  2714. _base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
  2715. {
  2716. Mpi2PortFactsRequest_t mpi_request;
  2717. Mpi2PortFactsReply_t mpi_reply, *pfacts;
  2718. int mpi_reply_sz, mpi_request_sz, r;
  2719. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2720. __func__));
  2721. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  2722. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  2723. memset(&mpi_request, 0, mpi_request_sz);
  2724. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  2725. mpi_request.PortNumber = port;
  2726. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2727. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2728. if (r != 0) {
  2729. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2730. ioc->name, __func__, r);
  2731. return r;
  2732. }
  2733. pfacts = &ioc->pfacts[port];
  2734. memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
  2735. pfacts->PortNumber = mpi_reply.PortNumber;
  2736. pfacts->VP_ID = mpi_reply.VP_ID;
  2737. pfacts->VF_ID = mpi_reply.VF_ID;
  2738. pfacts->MaxPostedCmdBuffers =
  2739. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  2740. return 0;
  2741. }
  2742. /**
  2743. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  2744. * @ioc: per adapter object
  2745. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2746. *
  2747. * Returns 0 for success, non-zero for failure.
  2748. */
  2749. static int
  2750. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2751. {
  2752. Mpi2IOCFactsRequest_t mpi_request;
  2753. Mpi2IOCFactsReply_t mpi_reply, *facts;
  2754. int mpi_reply_sz, mpi_request_sz, r;
  2755. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2756. __func__));
  2757. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  2758. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  2759. memset(&mpi_request, 0, mpi_request_sz);
  2760. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  2761. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2762. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2763. if (r != 0) {
  2764. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2765. ioc->name, __func__, r);
  2766. return r;
  2767. }
  2768. facts = &ioc->facts;
  2769. memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
  2770. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  2771. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  2772. facts->VP_ID = mpi_reply.VP_ID;
  2773. facts->VF_ID = mpi_reply.VF_ID;
  2774. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  2775. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  2776. facts->WhoInit = mpi_reply.WhoInit;
  2777. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  2778. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  2779. facts->MaxReplyDescriptorPostQueueDepth =
  2780. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  2781. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  2782. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  2783. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  2784. ioc->ir_firmware = 1;
  2785. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  2786. facts->IOCRequestFrameSize =
  2787. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  2788. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  2789. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  2790. ioc->shost->max_id = -1;
  2791. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  2792. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  2793. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  2794. facts->HighPriorityCredit =
  2795. le16_to_cpu(mpi_reply.HighPriorityCredit);
  2796. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  2797. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  2798. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
  2799. "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
  2800. facts->MaxChainDepth));
  2801. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
  2802. "reply frame size(%d)\n", ioc->name,
  2803. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  2804. return 0;
  2805. }
  2806. /**
  2807. * _base_send_ioc_init - send ioc_init to firmware
  2808. * @ioc: per adapter object
  2809. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2810. *
  2811. * Returns 0 for success, non-zero for failure.
  2812. */
  2813. static int
  2814. _base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2815. {
  2816. Mpi2IOCInitRequest_t mpi_request;
  2817. Mpi2IOCInitReply_t mpi_reply;
  2818. int r;
  2819. struct timeval current_time;
  2820. u16 ioc_status;
  2821. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2822. __func__));
  2823. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  2824. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  2825. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  2826. mpi_request.VF_ID = 0; /* TODO */
  2827. mpi_request.VP_ID = 0;
  2828. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  2829. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  2830. /* In MPI Revision I (0xA), the SystemReplyFrameSize(offset 0x18) was
  2831. * removed and made reserved. For those with older firmware will need
  2832. * this fix. It was decided that the Reply and Request frame sizes are
  2833. * the same.
  2834. */
  2835. if ((ioc->facts.HeaderVersion >> 8) < 0xA) {
  2836. mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz);
  2837. /* mpi_request.SystemReplyFrameSize =
  2838. * cpu_to_le16(ioc->reply_sz);
  2839. */
  2840. }
  2841. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  2842. mpi_request.ReplyDescriptorPostQueueDepth =
  2843. cpu_to_le16(ioc->reply_post_queue_depth);
  2844. mpi_request.ReplyFreeQueueDepth =
  2845. cpu_to_le16(ioc->reply_free_queue_depth);
  2846. #if BITS_PER_LONG > 32
  2847. mpi_request.SenseBufferAddressHigh =
  2848. cpu_to_le32(ioc->sense_dma >> 32);
  2849. mpi_request.SystemReplyAddressHigh =
  2850. cpu_to_le32(ioc->reply_dma >> 32);
  2851. mpi_request.SystemRequestFrameBaseAddress =
  2852. cpu_to_le64(ioc->request_dma);
  2853. mpi_request.ReplyFreeQueueAddress =
  2854. cpu_to_le64(ioc->reply_free_dma);
  2855. mpi_request.ReplyDescriptorPostQueueAddress =
  2856. cpu_to_le64(ioc->reply_post_free_dma);
  2857. #else
  2858. mpi_request.SystemRequestFrameBaseAddress =
  2859. cpu_to_le32(ioc->request_dma);
  2860. mpi_request.ReplyFreeQueueAddress =
  2861. cpu_to_le32(ioc->reply_free_dma);
  2862. mpi_request.ReplyDescriptorPostQueueAddress =
  2863. cpu_to_le32(ioc->reply_post_free_dma);
  2864. #endif
  2865. /* This time stamp specifies number of milliseconds
  2866. * since epoch ~ midnight January 1, 1970.
  2867. */
  2868. do_gettimeofday(&current_time);
  2869. mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
  2870. (current_time.tv_usec / 1000));
  2871. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2872. u32 *mfp;
  2873. int i;
  2874. mfp = (u32 *)&mpi_request;
  2875. printk(KERN_INFO "\toffset:data\n");
  2876. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  2877. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  2878. le32_to_cpu(mfp[i]));
  2879. }
  2880. r = _base_handshake_req_reply_wait(ioc,
  2881. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  2882. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  2883. sleep_flag);
  2884. if (r != 0) {
  2885. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2886. ioc->name, __func__, r);
  2887. return r;
  2888. }
  2889. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  2890. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  2891. mpi_reply.IOCLogInfo) {
  2892. printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
  2893. r = -EIO;
  2894. }
  2895. return 0;
  2896. }
  2897. /**
  2898. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  2899. * @ioc: per adapter object
  2900. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2901. *
  2902. * Returns 0 for success, non-zero for failure.
  2903. */
  2904. static int
  2905. _base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2906. {
  2907. Mpi2PortEnableRequest_t *mpi_request;
  2908. u32 ioc_state;
  2909. unsigned long timeleft;
  2910. int r = 0;
  2911. u16 smid;
  2912. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  2913. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2914. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2915. ioc->name, __func__);
  2916. return -EAGAIN;
  2917. }
  2918. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2919. if (!smid) {
  2920. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2921. ioc->name, __func__);
  2922. return -EAGAIN;
  2923. }
  2924. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2925. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2926. ioc->base_cmds.smid = smid;
  2927. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  2928. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  2929. mpi_request->VF_ID = 0; /* TODO */
  2930. mpi_request->VP_ID = 0;
  2931. mpt2sas_base_put_smid_default(ioc, smid);
  2932. init_completion(&ioc->base_cmds.done);
  2933. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2934. 300*HZ);
  2935. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2936. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2937. ioc->name, __func__);
  2938. _debug_dump_mf(mpi_request,
  2939. sizeof(Mpi2PortEnableRequest_t)/4);
  2940. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2941. r = -EFAULT;
  2942. else
  2943. r = -ETIME;
  2944. goto out;
  2945. } else
  2946. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
  2947. ioc->name, __func__));
  2948. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL,
  2949. 60, sleep_flag);
  2950. if (ioc_state) {
  2951. printk(MPT2SAS_ERR_FMT "%s: failed going to operational state "
  2952. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2953. r = -EFAULT;
  2954. }
  2955. out:
  2956. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2957. printk(MPT2SAS_INFO_FMT "port enable: %s\n",
  2958. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2959. return r;
  2960. }
  2961. /**
  2962. * _base_unmask_events - turn on notification for this event
  2963. * @ioc: per adapter object
  2964. * @event: firmware event
  2965. *
  2966. * The mask is stored in ioc->event_masks.
  2967. */
  2968. static void
  2969. _base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
  2970. {
  2971. u32 desired_event;
  2972. if (event >= 128)
  2973. return;
  2974. desired_event = (1 << (event % 32));
  2975. if (event < 32)
  2976. ioc->event_masks[0] &= ~desired_event;
  2977. else if (event < 64)
  2978. ioc->event_masks[1] &= ~desired_event;
  2979. else if (event < 96)
  2980. ioc->event_masks[2] &= ~desired_event;
  2981. else if (event < 128)
  2982. ioc->event_masks[3] &= ~desired_event;
  2983. }
  2984. /**
  2985. * _base_event_notification - send event notification
  2986. * @ioc: per adapter object
  2987. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2988. *
  2989. * Returns 0 for success, non-zero for failure.
  2990. */
  2991. static int
  2992. _base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2993. {
  2994. Mpi2EventNotificationRequest_t *mpi_request;
  2995. unsigned long timeleft;
  2996. u16 smid;
  2997. int r = 0;
  2998. int i;
  2999. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3000. __func__));
  3001. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3002. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  3003. ioc->name, __func__);
  3004. return -EAGAIN;
  3005. }
  3006. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  3007. if (!smid) {
  3008. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  3009. ioc->name, __func__);
  3010. return -EAGAIN;
  3011. }
  3012. ioc->base_cmds.status = MPT2_CMD_PENDING;
  3013. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  3014. ioc->base_cmds.smid = smid;
  3015. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  3016. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  3017. mpi_request->VF_ID = 0; /* TODO */
  3018. mpi_request->VP_ID = 0;
  3019. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3020. mpi_request->EventMasks[i] =
  3021. cpu_to_le32(ioc->event_masks[i]);
  3022. mpt2sas_base_put_smid_default(ioc, smid);
  3023. init_completion(&ioc->base_cmds.done);
  3024. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  3025. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  3026. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  3027. ioc->name, __func__);
  3028. _debug_dump_mf(mpi_request,
  3029. sizeof(Mpi2EventNotificationRequest_t)/4);
  3030. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  3031. r = -EFAULT;
  3032. else
  3033. r = -ETIME;
  3034. } else
  3035. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
  3036. ioc->name, __func__));
  3037. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3038. return r;
  3039. }
  3040. /**
  3041. * mpt2sas_base_validate_event_type - validating event types
  3042. * @ioc: per adapter object
  3043. * @event: firmware event
  3044. *
  3045. * This will turn on firmware event notification when application
  3046. * ask for that event. We don't mask events that are already enabled.
  3047. */
  3048. void
  3049. mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
  3050. {
  3051. int i, j;
  3052. u32 event_mask, desired_event;
  3053. u8 send_update_to_fw;
  3054. for (i = 0, send_update_to_fw = 0; i <
  3055. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  3056. event_mask = ~event_type[i];
  3057. desired_event = 1;
  3058. for (j = 0; j < 32; j++) {
  3059. if (!(event_mask & desired_event) &&
  3060. (ioc->event_masks[i] & desired_event)) {
  3061. ioc->event_masks[i] &= ~desired_event;
  3062. send_update_to_fw = 1;
  3063. }
  3064. desired_event = (desired_event << 1);
  3065. }
  3066. }
  3067. if (!send_update_to_fw)
  3068. return;
  3069. mutex_lock(&ioc->base_cmds.mutex);
  3070. _base_event_notification(ioc, CAN_SLEEP);
  3071. mutex_unlock(&ioc->base_cmds.mutex);
  3072. }
  3073. /**
  3074. * _base_diag_reset - the "big hammer" start of day reset
  3075. * @ioc: per adapter object
  3076. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3077. *
  3078. * Returns 0 for success, non-zero for failure.
  3079. */
  3080. static int
  3081. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3082. {
  3083. u32 host_diagnostic;
  3084. u32 ioc_state;
  3085. u32 count;
  3086. u32 hcb_size;
  3087. printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
  3088. _base_save_msix_table(ioc);
  3089. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "clear interrupts\n",
  3090. ioc->name));
  3091. count = 0;
  3092. do {
  3093. /* Write magic sequence to WriteSequence register
  3094. * Loop until in diagnostic mode
  3095. */
  3096. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "write magic "
  3097. "sequence\n", ioc->name));
  3098. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3099. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  3100. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  3101. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  3102. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3103. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3104. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3105. /* wait 100 msec */
  3106. if (sleep_flag == CAN_SLEEP)
  3107. msleep(100);
  3108. else
  3109. mdelay(100);
  3110. if (count++ > 20)
  3111. goto out;
  3112. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3113. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "wrote magic "
  3114. "sequence: count(%d), host_diagnostic(0x%08x)\n",
  3115. ioc->name, count, host_diagnostic));
  3116. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  3117. hcb_size = readl(&ioc->chip->HCBSize);
  3118. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "diag reset: issued\n",
  3119. ioc->name));
  3120. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  3121. &ioc->chip->HostDiagnostic);
  3122. /* don't access any registers for 50 milliseconds */
  3123. msleep(50);
  3124. /* 300 second max wait */
  3125. for (count = 0; count < 3000000 ; count++) {
  3126. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3127. if (host_diagnostic == 0xFFFFFFFF)
  3128. goto out;
  3129. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  3130. break;
  3131. /* wait 100 msec */
  3132. if (sleep_flag == CAN_SLEEP)
  3133. msleep(1);
  3134. else
  3135. mdelay(1);
  3136. }
  3137. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  3138. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter "
  3139. "assuming the HCB Address points to good F/W\n",
  3140. ioc->name));
  3141. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  3142. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  3143. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  3144. drsprintk(ioc, printk(MPT2SAS_INFO_FMT
  3145. "re-enable the HCDW\n", ioc->name));
  3146. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  3147. &ioc->chip->HCBSize);
  3148. }
  3149. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter\n",
  3150. ioc->name));
  3151. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  3152. &ioc->chip->HostDiagnostic);
  3153. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "disable writes to the "
  3154. "diagnostic register\n", ioc->name));
  3155. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3156. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "Wait for FW to go to the "
  3157. "READY state\n", ioc->name));
  3158. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  3159. sleep_flag);
  3160. if (ioc_state) {
  3161. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  3162. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  3163. goto out;
  3164. }
  3165. _base_restore_msix_table(ioc);
  3166. printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
  3167. return 0;
  3168. out:
  3169. printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
  3170. return -EFAULT;
  3171. }
  3172. /**
  3173. * _base_make_ioc_ready - put controller in READY state
  3174. * @ioc: per adapter object
  3175. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3176. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3177. *
  3178. * Returns 0 for success, non-zero for failure.
  3179. */
  3180. static int
  3181. _base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3182. enum reset_type type)
  3183. {
  3184. u32 ioc_state;
  3185. int rc;
  3186. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3187. __func__));
  3188. if (ioc->pci_error_recovery)
  3189. return 0;
  3190. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3191. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: ioc_state(0x%08x)\n",
  3192. ioc->name, __func__, ioc_state));
  3193. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  3194. return 0;
  3195. if (ioc_state & MPI2_DOORBELL_USED) {
  3196. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "unexpected doorbell "
  3197. "active!\n", ioc->name));
  3198. goto issue_diag_reset;
  3199. }
  3200. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3201. mpt2sas_base_fault_info(ioc, ioc_state &
  3202. MPI2_DOORBELL_DATA_MASK);
  3203. goto issue_diag_reset;
  3204. }
  3205. if (type == FORCE_BIG_HAMMER)
  3206. goto issue_diag_reset;
  3207. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3208. if (!(_base_send_ioc_reset(ioc,
  3209. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
  3210. ioc->ioc_reset_count++;
  3211. return 0;
  3212. }
  3213. issue_diag_reset:
  3214. rc = _base_diag_reset(ioc, CAN_SLEEP);
  3215. ioc->ioc_reset_count++;
  3216. return rc;
  3217. }
  3218. /**
  3219. * _base_make_ioc_operational - put controller in OPERATIONAL state
  3220. * @ioc: per adapter object
  3221. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3222. *
  3223. * Returns 0 for success, non-zero for failure.
  3224. */
  3225. static int
  3226. _base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3227. {
  3228. int r, i;
  3229. unsigned long flags;
  3230. u32 reply_address;
  3231. u16 smid;
  3232. struct _tr_list *delayed_tr, *delayed_tr_next;
  3233. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3234. __func__));
  3235. /* clean the delayed target reset list */
  3236. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3237. &ioc->delayed_tr_list, list) {
  3238. list_del(&delayed_tr->list);
  3239. kfree(delayed_tr);
  3240. }
  3241. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3242. &ioc->delayed_tr_volume_list, list) {
  3243. list_del(&delayed_tr->list);
  3244. kfree(delayed_tr);
  3245. }
  3246. /* initialize the scsi lookup free list */
  3247. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3248. INIT_LIST_HEAD(&ioc->free_list);
  3249. smid = 1;
  3250. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  3251. INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
  3252. ioc->scsi_lookup[i].cb_idx = 0xFF;
  3253. ioc->scsi_lookup[i].smid = smid;
  3254. ioc->scsi_lookup[i].scmd = NULL;
  3255. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  3256. &ioc->free_list);
  3257. }
  3258. /* hi-priority queue */
  3259. INIT_LIST_HEAD(&ioc->hpr_free_list);
  3260. smid = ioc->hi_priority_smid;
  3261. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  3262. ioc->hpr_lookup[i].cb_idx = 0xFF;
  3263. ioc->hpr_lookup[i].smid = smid;
  3264. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  3265. &ioc->hpr_free_list);
  3266. }
  3267. /* internal queue */
  3268. INIT_LIST_HEAD(&ioc->internal_free_list);
  3269. smid = ioc->internal_smid;
  3270. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  3271. ioc->internal_lookup[i].cb_idx = 0xFF;
  3272. ioc->internal_lookup[i].smid = smid;
  3273. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  3274. &ioc->internal_free_list);
  3275. }
  3276. /* chain pool */
  3277. INIT_LIST_HEAD(&ioc->free_chain_list);
  3278. for (i = 0; i < ioc->chain_depth; i++)
  3279. list_add_tail(&ioc->chain_lookup[i].tracker_list,
  3280. &ioc->free_chain_list);
  3281. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3282. /* initialize Reply Free Queue */
  3283. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3284. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3285. ioc->reply_sz)
  3286. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3287. /* initialize Reply Post Free Queue */
  3288. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3289. ioc->reply_post_free[i].Words = ULLONG_MAX;
  3290. r = _base_send_ioc_init(ioc, sleep_flag);
  3291. if (r)
  3292. return r;
  3293. /* initialize the index's */
  3294. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3295. ioc->reply_post_host_index = 0;
  3296. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3297. writel(0, &ioc->chip->ReplyPostHostIndex);
  3298. _base_unmask_interrupts(ioc);
  3299. r = _base_event_notification(ioc, sleep_flag);
  3300. if (r)
  3301. return r;
  3302. if (sleep_flag == CAN_SLEEP)
  3303. _base_static_config_pages(ioc);
  3304. if (ioc->wait_for_port_enable_to_complete) {
  3305. if (diag_buffer_enable != 0)
  3306. mpt2sas_enable_diag_buffer(ioc, diag_buffer_enable);
  3307. if (disable_discovery > 0)
  3308. return r;
  3309. }
  3310. r = _base_send_port_enable(ioc, sleep_flag);
  3311. if (r)
  3312. return r;
  3313. return r;
  3314. }
  3315. /**
  3316. * mpt2sas_base_free_resources - free resources controller resources (io/irq/memap)
  3317. * @ioc: per adapter object
  3318. *
  3319. * Return nothing.
  3320. */
  3321. void
  3322. mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
  3323. {
  3324. struct pci_dev *pdev = ioc->pdev;
  3325. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3326. __func__));
  3327. _base_mask_interrupts(ioc);
  3328. ioc->shost_recovery = 1;
  3329. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3330. ioc->shost_recovery = 0;
  3331. if (ioc->pci_irq) {
  3332. synchronize_irq(pdev->irq);
  3333. free_irq(ioc->pci_irq, ioc);
  3334. }
  3335. _base_disable_msix(ioc);
  3336. if (ioc->chip_phys)
  3337. iounmap(ioc->chip);
  3338. ioc->pci_irq = -1;
  3339. ioc->chip_phys = 0;
  3340. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3341. pci_disable_pcie_error_reporting(pdev);
  3342. pci_disable_device(pdev);
  3343. return;
  3344. }
  3345. /**
  3346. * mpt2sas_base_attach - attach controller instance
  3347. * @ioc: per adapter object
  3348. *
  3349. * Returns 0 for success, non-zero for failure.
  3350. */
  3351. int
  3352. mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
  3353. {
  3354. int r, i;
  3355. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3356. __func__));
  3357. r = mpt2sas_base_map_resources(ioc);
  3358. if (r)
  3359. return r;
  3360. pci_set_drvdata(ioc->pdev, ioc->shost);
  3361. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  3362. if (r)
  3363. goto out_free_resources;
  3364. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3365. if (r)
  3366. goto out_free_resources;
  3367. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  3368. sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
  3369. if (!ioc->pfacts) {
  3370. r = -ENOMEM;
  3371. goto out_free_resources;
  3372. }
  3373. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  3374. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  3375. if (r)
  3376. goto out_free_resources;
  3377. }
  3378. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  3379. if (r)
  3380. goto out_free_resources;
  3381. init_waitqueue_head(&ioc->reset_wq);
  3382. /* allocate memory pd handle bitmask list */
  3383. ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
  3384. if (ioc->facts.MaxDevHandle % 8)
  3385. ioc->pd_handles_sz++;
  3386. ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
  3387. GFP_KERNEL);
  3388. if (!ioc->pd_handles) {
  3389. r = -ENOMEM;
  3390. goto out_free_resources;
  3391. }
  3392. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  3393. /* base internal command bits */
  3394. mutex_init(&ioc->base_cmds.mutex);
  3395. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3396. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3397. /* transport internal command bits */
  3398. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3399. ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
  3400. mutex_init(&ioc->transport_cmds.mutex);
  3401. /* scsih internal command bits */
  3402. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3403. ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
  3404. mutex_init(&ioc->scsih_cmds.mutex);
  3405. /* task management internal command bits */
  3406. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3407. ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
  3408. mutex_init(&ioc->tm_cmds.mutex);
  3409. /* config page internal command bits */
  3410. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3411. ioc->config_cmds.status = MPT2_CMD_NOT_USED;
  3412. mutex_init(&ioc->config_cmds.mutex);
  3413. /* ctl module internal command bits */
  3414. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3415. ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  3416. ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
  3417. mutex_init(&ioc->ctl_cmds.mutex);
  3418. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  3419. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  3420. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
  3421. !ioc->ctl_cmds.sense) {
  3422. r = -ENOMEM;
  3423. goto out_free_resources;
  3424. }
  3425. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  3426. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  3427. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply) {
  3428. r = -ENOMEM;
  3429. goto out_free_resources;
  3430. }
  3431. init_completion(&ioc->shost_recovery_done);
  3432. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3433. ioc->event_masks[i] = -1;
  3434. /* here we enable the events we care about */
  3435. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  3436. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  3437. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  3438. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  3439. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  3440. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  3441. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  3442. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  3443. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  3444. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  3445. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  3446. if (r)
  3447. goto out_free_resources;
  3448. if (missing_delay[0] != -1 && missing_delay[1] != -1)
  3449. _base_update_missing_delay(ioc, missing_delay[0],
  3450. missing_delay[1]);
  3451. mpt2sas_base_start_watchdog(ioc);
  3452. return 0;
  3453. out_free_resources:
  3454. ioc->remove_host = 1;
  3455. mpt2sas_base_free_resources(ioc);
  3456. _base_release_memory_pools(ioc);
  3457. pci_set_drvdata(ioc->pdev, NULL);
  3458. kfree(ioc->pd_handles);
  3459. kfree(ioc->tm_cmds.reply);
  3460. kfree(ioc->transport_cmds.reply);
  3461. kfree(ioc->scsih_cmds.reply);
  3462. kfree(ioc->config_cmds.reply);
  3463. kfree(ioc->base_cmds.reply);
  3464. kfree(ioc->ctl_cmds.reply);
  3465. kfree(ioc->ctl_cmds.sense);
  3466. kfree(ioc->pfacts);
  3467. ioc->ctl_cmds.reply = NULL;
  3468. ioc->base_cmds.reply = NULL;
  3469. ioc->tm_cmds.reply = NULL;
  3470. ioc->scsih_cmds.reply = NULL;
  3471. ioc->transport_cmds.reply = NULL;
  3472. ioc->config_cmds.reply = NULL;
  3473. ioc->pfacts = NULL;
  3474. return r;
  3475. }
  3476. /**
  3477. * mpt2sas_base_detach - remove controller instance
  3478. * @ioc: per adapter object
  3479. *
  3480. * Return nothing.
  3481. */
  3482. void
  3483. mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
  3484. {
  3485. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3486. __func__));
  3487. mpt2sas_base_stop_watchdog(ioc);
  3488. mpt2sas_base_free_resources(ioc);
  3489. _base_release_memory_pools(ioc);
  3490. pci_set_drvdata(ioc->pdev, NULL);
  3491. kfree(ioc->pd_handles);
  3492. kfree(ioc->pfacts);
  3493. kfree(ioc->ctl_cmds.reply);
  3494. kfree(ioc->ctl_cmds.sense);
  3495. kfree(ioc->base_cmds.reply);
  3496. kfree(ioc->tm_cmds.reply);
  3497. kfree(ioc->transport_cmds.reply);
  3498. kfree(ioc->scsih_cmds.reply);
  3499. kfree(ioc->config_cmds.reply);
  3500. }
  3501. /**
  3502. * _base_reset_handler - reset callback handler (for base)
  3503. * @ioc: per adapter object
  3504. * @reset_phase: phase
  3505. *
  3506. * The handler for doing any required cleanup or initialization.
  3507. *
  3508. * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
  3509. * MPT2_IOC_DONE_RESET
  3510. *
  3511. * Return nothing.
  3512. */
  3513. static void
  3514. _base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
  3515. {
  3516. mpt2sas_scsih_reset_handler(ioc, reset_phase);
  3517. mpt2sas_ctl_reset_handler(ioc, reset_phase);
  3518. switch (reset_phase) {
  3519. case MPT2_IOC_PRE_RESET:
  3520. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3521. "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
  3522. break;
  3523. case MPT2_IOC_AFTER_RESET:
  3524. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3525. "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
  3526. if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
  3527. ioc->transport_cmds.status |= MPT2_CMD_RESET;
  3528. mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  3529. complete(&ioc->transport_cmds.done);
  3530. }
  3531. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3532. ioc->base_cmds.status |= MPT2_CMD_RESET;
  3533. mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
  3534. complete(&ioc->base_cmds.done);
  3535. }
  3536. if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
  3537. ioc->config_cmds.status |= MPT2_CMD_RESET;
  3538. mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
  3539. ioc->config_cmds.smid = USHRT_MAX;
  3540. complete(&ioc->config_cmds.done);
  3541. }
  3542. break;
  3543. case MPT2_IOC_DONE_RESET:
  3544. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3545. "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
  3546. break;
  3547. }
  3548. }
  3549. /**
  3550. * _wait_for_commands_to_complete - reset controller
  3551. * @ioc: Pointer to MPT_ADAPTER structure
  3552. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3553. *
  3554. * This function waiting(3s) for all pending commands to complete
  3555. * prior to putting controller in reset.
  3556. */
  3557. static void
  3558. _wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3559. {
  3560. u32 ioc_state;
  3561. unsigned long flags;
  3562. u16 i;
  3563. ioc->pending_io_count = 0;
  3564. if (sleep_flag != CAN_SLEEP)
  3565. return;
  3566. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3567. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  3568. return;
  3569. /* pending command count */
  3570. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3571. for (i = 0; i < ioc->scsiio_depth; i++)
  3572. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  3573. ioc->pending_io_count++;
  3574. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3575. if (!ioc->pending_io_count)
  3576. return;
  3577. /* wait for pending commands to complete */
  3578. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
  3579. }
  3580. /**
  3581. * mpt2sas_base_hard_reset_handler - reset controller
  3582. * @ioc: Pointer to MPT_ADAPTER structure
  3583. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3584. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3585. *
  3586. * Returns 0 for success, non-zero for failure.
  3587. */
  3588. int
  3589. mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3590. enum reset_type type)
  3591. {
  3592. int r;
  3593. unsigned long flags;
  3594. u8 pe_complete = ioc->wait_for_port_enable_to_complete;
  3595. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: enter\n", ioc->name,
  3596. __func__));
  3597. if (ioc->pci_error_recovery) {
  3598. printk(MPT2SAS_ERR_FMT "%s: pci error recovery reset\n",
  3599. ioc->name, __func__);
  3600. r = 0;
  3601. goto out;
  3602. }
  3603. if (mpt2sas_fwfault_debug)
  3604. mpt2sas_halt_firmware(ioc);
  3605. /* TODO - What we really should be doing is pulling
  3606. * out all the code associated with NO_SLEEP; its never used.
  3607. * That is legacy code from mpt fusion driver, ported over.
  3608. * I will leave this BUG_ON here for now till its been resolved.
  3609. */
  3610. BUG_ON(sleep_flag == NO_SLEEP);
  3611. /* wait for an active reset in progress to complete */
  3612. if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
  3613. do {
  3614. ssleep(1);
  3615. } while (ioc->shost_recovery == 1);
  3616. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  3617. __func__));
  3618. return ioc->ioc_reset_in_progress_status;
  3619. }
  3620. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3621. ioc->shost_recovery = 1;
  3622. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3623. _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
  3624. _wait_for_commands_to_complete(ioc, sleep_flag);
  3625. _base_mask_interrupts(ioc);
  3626. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  3627. if (r)
  3628. goto out;
  3629. _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
  3630. /* If this hard reset is called while port enable is active, then
  3631. * there is no reason to call make_ioc_operational
  3632. */
  3633. if (pe_complete) {
  3634. r = -EFAULT;
  3635. goto out;
  3636. }
  3637. r = _base_make_ioc_operational(ioc, sleep_flag);
  3638. if (!r)
  3639. _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
  3640. out:
  3641. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: %s\n",
  3642. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  3643. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3644. ioc->ioc_reset_in_progress_status = r;
  3645. ioc->shost_recovery = 0;
  3646. complete(&ioc->shost_recovery_done);
  3647. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3648. mutex_unlock(&ioc->reset_in_progress_mutex);
  3649. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  3650. __func__));
  3651. return r;
  3652. }