bnx2fc_hwi.c 52 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868
  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2010 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *conn_destroy);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ALERT PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = hba->netdev->mtu;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  87. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  88. ((u64) hba->hash_tbl_pbl_dma >> 32);
  89. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  90. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  91. ((u64) hba->t2_hash_tbl_dma >> 32);
  92. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  93. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  94. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  95. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  96. /* fill init3 KWQE */
  97. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  98. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  99. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  100. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  101. fcoe_init3.error_bit_map_lo = 0xffffffff;
  102. fcoe_init3.error_bit_map_hi = 0xffffffff;
  103. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  104. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  105. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  106. if (hba->cnic && hba->cnic->submit_kwqes)
  107. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  108. return rc;
  109. }
  110. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  111. {
  112. struct fcoe_kwqe_destroy fcoe_destroy;
  113. struct kwqe *kwqe_arr[2];
  114. int num_kwqes = 1;
  115. int rc = -1;
  116. /* fill destroy KWQE */
  117. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  118. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  119. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  120. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  121. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  122. if (hba->cnic && hba->cnic->submit_kwqes)
  123. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  124. return rc;
  125. }
  126. /**
  127. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  128. *
  129. * @port: port structure pointer
  130. * @tgt: bnx2fc_rport structure pointer
  131. */
  132. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  133. struct bnx2fc_rport *tgt)
  134. {
  135. struct fc_lport *lport = port->lport;
  136. struct bnx2fc_hba *hba = port->priv;
  137. struct kwqe *kwqe_arr[4];
  138. struct fcoe_kwqe_conn_offload1 ofld_req1;
  139. struct fcoe_kwqe_conn_offload2 ofld_req2;
  140. struct fcoe_kwqe_conn_offload3 ofld_req3;
  141. struct fcoe_kwqe_conn_offload4 ofld_req4;
  142. struct fc_rport_priv *rdata = tgt->rdata;
  143. struct fc_rport *rport = tgt->rport;
  144. int num_kwqes = 4;
  145. u32 port_id;
  146. int rc = 0;
  147. u16 conn_id;
  148. /* Initialize offload request 1 structure */
  149. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  150. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  151. ofld_req1.hdr.flags =
  152. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  153. conn_id = (u16)tgt->fcoe_conn_id;
  154. ofld_req1.fcoe_conn_id = conn_id;
  155. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  156. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  157. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  158. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  159. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  160. ofld_req1.rq_first_pbe_addr_hi =
  161. (u32)((u64) tgt->rq_dma >> 32);
  162. ofld_req1.rq_prod = 0x8000;
  163. /* Initialize offload request 2 structure */
  164. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  165. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  166. ofld_req2.hdr.flags =
  167. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  168. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  169. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  170. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  171. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  172. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  173. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  174. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  175. /* Initialize offload request 3 structure */
  176. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  177. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  178. ofld_req3.hdr.flags =
  179. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  180. ofld_req3.vlan_tag = hba->vlan_id <<
  181. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  182. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  183. port_id = fc_host_port_id(lport->host);
  184. if (port_id == 0) {
  185. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  186. return -EINVAL;
  187. }
  188. /*
  189. * Store s_id of the initiator for further reference. This will
  190. * be used during disable/destroy during linkdown processing as
  191. * when the lport is reset, the port_id also is reset to 0
  192. */
  193. tgt->sid = port_id;
  194. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  195. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  196. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  197. port_id = rport->port_id;
  198. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  199. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  200. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  201. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  202. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  203. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  204. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  205. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  206. ofld_req3.rx_open_seqs_exch_c3 = 1;
  207. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  208. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  209. /* set mul_n_port_ids supported flag to 0, until it is supported */
  210. ofld_req3.flags = 0;
  211. /*
  212. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  213. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  214. */
  215. /* Info from PLOGI response */
  216. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  217. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  218. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  219. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  220. /* vlan flag */
  221. ofld_req3.flags |= (hba->vlan_enabled <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  223. /* C2_VALID and ACK flags are not set as they are not suppported */
  224. /* Initialize offload request 4 structure */
  225. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  226. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  227. ofld_req4.hdr.flags =
  228. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  229. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  230. ofld_req4.src_mac_addr_lo32[0] = port->data_src_addr[5];
  231. /* local mac */
  232. ofld_req4.src_mac_addr_lo32[1] = port->data_src_addr[4];
  233. ofld_req4.src_mac_addr_lo32[2] = port->data_src_addr[3];
  234. ofld_req4.src_mac_addr_lo32[3] = port->data_src_addr[2];
  235. ofld_req4.src_mac_addr_hi16[0] = port->data_src_addr[1];
  236. ofld_req4.src_mac_addr_hi16[1] = port->data_src_addr[0];
  237. ofld_req4.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  238. ofld_req4.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  239. ofld_req4.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  240. ofld_req4.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  241. ofld_req4.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  242. ofld_req4.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  243. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  244. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  245. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  246. ofld_req4.confq_pbl_base_addr_hi =
  247. (u32)((u64) tgt->confq_pbl_dma >> 32);
  248. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  249. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  250. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  251. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  252. if (hba->cnic && hba->cnic->submit_kwqes)
  253. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  254. return rc;
  255. }
  256. /**
  257. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  258. *
  259. * @port: port structure pointer
  260. * @tgt: bnx2fc_rport structure pointer
  261. */
  262. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  263. struct bnx2fc_rport *tgt)
  264. {
  265. struct kwqe *kwqe_arr[2];
  266. struct bnx2fc_hba *hba = port->priv;
  267. struct fcoe_kwqe_conn_enable_disable enbl_req;
  268. struct fc_lport *lport = port->lport;
  269. struct fc_rport *rport = tgt->rport;
  270. int num_kwqes = 1;
  271. int rc = 0;
  272. u32 port_id;
  273. memset(&enbl_req, 0x00,
  274. sizeof(struct fcoe_kwqe_conn_enable_disable));
  275. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  276. enbl_req.hdr.flags =
  277. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  278. enbl_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  279. /* local mac */
  280. enbl_req.src_mac_addr_lo32[1] = port->data_src_addr[4];
  281. enbl_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  282. enbl_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  283. enbl_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  284. enbl_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  285. enbl_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  286. enbl_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  287. enbl_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  288. enbl_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  289. enbl_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  290. enbl_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  291. port_id = fc_host_port_id(lport->host);
  292. if (port_id != tgt->sid) {
  293. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  294. "sid = 0x%x\n", port_id, tgt->sid);
  295. port_id = tgt->sid;
  296. }
  297. enbl_req.s_id[0] = (port_id & 0x000000FF);
  298. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  299. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  300. port_id = rport->port_id;
  301. enbl_req.d_id[0] = (port_id & 0x000000FF);
  302. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  303. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  304. enbl_req.vlan_tag = hba->vlan_id <<
  305. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  306. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  307. enbl_req.vlan_flag = hba->vlan_enabled;
  308. enbl_req.context_id = tgt->context_id;
  309. enbl_req.conn_id = tgt->fcoe_conn_id;
  310. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  311. if (hba->cnic && hba->cnic->submit_kwqes)
  312. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  313. return rc;
  314. }
  315. /**
  316. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  317. *
  318. * @port: port structure pointer
  319. * @tgt: bnx2fc_rport structure pointer
  320. */
  321. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  322. struct bnx2fc_rport *tgt)
  323. {
  324. struct bnx2fc_hba *hba = port->priv;
  325. struct fcoe_kwqe_conn_enable_disable disable_req;
  326. struct kwqe *kwqe_arr[2];
  327. struct fc_rport *rport = tgt->rport;
  328. int num_kwqes = 1;
  329. int rc = 0;
  330. u32 port_id;
  331. memset(&disable_req, 0x00,
  332. sizeof(struct fcoe_kwqe_conn_enable_disable));
  333. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  334. disable_req.hdr.flags =
  335. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  336. disable_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  337. disable_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  338. disable_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  339. disable_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  340. disable_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  341. disable_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  342. disable_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  343. disable_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  344. disable_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  345. disable_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  346. disable_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  347. port_id = tgt->sid;
  348. disable_req.s_id[0] = (port_id & 0x000000FF);
  349. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  350. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  351. port_id = rport->port_id;
  352. disable_req.d_id[0] = (port_id & 0x000000FF);
  353. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  354. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  355. disable_req.context_id = tgt->context_id;
  356. disable_req.conn_id = tgt->fcoe_conn_id;
  357. disable_req.vlan_tag = hba->vlan_id <<
  358. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  359. disable_req.vlan_tag |=
  360. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  361. disable_req.vlan_flag = hba->vlan_enabled;
  362. kwqe_arr[0] = (struct kwqe *) &disable_req;
  363. if (hba->cnic && hba->cnic->submit_kwqes)
  364. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  365. return rc;
  366. }
  367. /**
  368. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  369. *
  370. * @port: port structure pointer
  371. * @tgt: bnx2fc_rport structure pointer
  372. */
  373. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  374. struct bnx2fc_rport *tgt)
  375. {
  376. struct fcoe_kwqe_conn_destroy destroy_req;
  377. struct kwqe *kwqe_arr[2];
  378. int num_kwqes = 1;
  379. int rc = 0;
  380. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  381. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  382. destroy_req.hdr.flags =
  383. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  384. destroy_req.context_id = tgt->context_id;
  385. destroy_req.conn_id = tgt->fcoe_conn_id;
  386. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  387. if (hba->cnic && hba->cnic->submit_kwqes)
  388. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  389. return rc;
  390. }
  391. static void bnx2fc_unsol_els_work(struct work_struct *work)
  392. {
  393. struct bnx2fc_unsol_els *unsol_els;
  394. struct fc_lport *lport;
  395. struct fc_frame *fp;
  396. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  397. lport = unsol_els->lport;
  398. fp = unsol_els->fp;
  399. fc_exch_recv(lport, fp);
  400. kfree(unsol_els);
  401. }
  402. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  403. unsigned char *buf,
  404. u32 frame_len, u16 l2_oxid)
  405. {
  406. struct fcoe_port *port = tgt->port;
  407. struct fc_lport *lport = port->lport;
  408. struct bnx2fc_unsol_els *unsol_els;
  409. struct fc_frame_header *fh;
  410. struct fc_frame *fp;
  411. struct sk_buff *skb;
  412. u32 payload_len;
  413. u32 crc;
  414. u8 op;
  415. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  416. if (!unsol_els) {
  417. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  418. return;
  419. }
  420. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  421. l2_oxid, frame_len);
  422. payload_len = frame_len - sizeof(struct fc_frame_header);
  423. fp = fc_frame_alloc(lport, payload_len);
  424. if (!fp) {
  425. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  426. return;
  427. }
  428. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  429. /* Copy FC Frame header and payload into the frame */
  430. memcpy(fh, buf, frame_len);
  431. if (l2_oxid != FC_XID_UNKNOWN)
  432. fh->fh_ox_id = htons(l2_oxid);
  433. skb = fp_skb(fp);
  434. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  435. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  436. if (fh->fh_type == FC_TYPE_ELS) {
  437. op = fc_frame_payload_op(fp);
  438. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  439. (op == ELS_FAN) || (op == ELS_CSU)) {
  440. /*
  441. * No need to reply for these
  442. * ELS requests
  443. */
  444. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  445. kfree_skb(skb);
  446. return;
  447. }
  448. }
  449. crc = fcoe_fc_crc(fp);
  450. fc_frame_init(fp);
  451. fr_dev(fp) = lport;
  452. fr_sof(fp) = FC_SOF_I3;
  453. fr_eof(fp) = FC_EOF_T;
  454. fr_crc(fp) = cpu_to_le32(~crc);
  455. unsol_els->lport = lport;
  456. unsol_els->fp = fp;
  457. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  458. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  459. } else {
  460. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  461. kfree_skb(skb);
  462. }
  463. }
  464. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  465. {
  466. u8 num_rq;
  467. struct fcoe_err_report_entry *err_entry;
  468. unsigned char *rq_data;
  469. unsigned char *buf = NULL, *buf1;
  470. int i;
  471. u16 xid;
  472. u32 frame_len, len;
  473. struct bnx2fc_cmd *io_req = NULL;
  474. struct fcoe_task_ctx_entry *task, *task_page;
  475. struct bnx2fc_hba *hba = tgt->port->priv;
  476. int task_idx, index;
  477. int rc = 0;
  478. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  479. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  480. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  481. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  482. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  483. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  484. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  485. if (rq_data) {
  486. buf = rq_data;
  487. } else {
  488. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  489. GFP_ATOMIC);
  490. if (!buf1) {
  491. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  492. break;
  493. }
  494. for (i = 0; i < num_rq; i++) {
  495. rq_data = (unsigned char *)
  496. bnx2fc_get_next_rqe(tgt, 1);
  497. len = BNX2FC_RQ_BUF_SZ;
  498. memcpy(buf1, rq_data, len);
  499. buf1 += len;
  500. }
  501. }
  502. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  503. FC_XID_UNKNOWN);
  504. if (buf != rq_data)
  505. kfree(buf);
  506. bnx2fc_return_rqe(tgt, num_rq);
  507. break;
  508. case FCOE_ERROR_DETECTION_CQE_TYPE:
  509. /*
  510. *In case of error reporting CQE a single RQ entry
  511. * is consumes.
  512. */
  513. spin_lock_bh(&tgt->tgt_lock);
  514. num_rq = 1;
  515. err_entry = (struct fcoe_err_report_entry *)
  516. bnx2fc_get_next_rqe(tgt, 1);
  517. xid = err_entry->fc_hdr.ox_id;
  518. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  519. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  520. err_entry->err_warn_bitmap_hi,
  521. err_entry->err_warn_bitmap_lo);
  522. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  523. err_entry->tx_buf_off, err_entry->rx_buf_off);
  524. bnx2fc_return_rqe(tgt, 1);
  525. if (xid > BNX2FC_MAX_XID) {
  526. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  527. xid);
  528. spin_unlock_bh(&tgt->tgt_lock);
  529. break;
  530. }
  531. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  532. index = xid % BNX2FC_TASKS_PER_PAGE;
  533. task_page = (struct fcoe_task_ctx_entry *)
  534. hba->task_ctx[task_idx];
  535. task = &(task_page[index]);
  536. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  537. if (!io_req) {
  538. spin_unlock_bh(&tgt->tgt_lock);
  539. break;
  540. }
  541. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  542. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  543. spin_unlock_bh(&tgt->tgt_lock);
  544. break;
  545. }
  546. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  547. &io_req->req_flags)) {
  548. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  549. "progress.. ignore unsol err\n");
  550. spin_unlock_bh(&tgt->tgt_lock);
  551. break;
  552. }
  553. /*
  554. * If ABTS is already in progress, and FW error is
  555. * received after that, do not cancel the timeout_work
  556. * and let the error recovery continue by explicitly
  557. * logging out the target, when the ABTS eventually
  558. * times out.
  559. */
  560. if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
  561. &io_req->req_flags)) {
  562. /*
  563. * Cancel the timeout_work, as we received IO
  564. * completion with FW error.
  565. */
  566. if (cancel_delayed_work(&io_req->timeout_work))
  567. kref_put(&io_req->refcount,
  568. bnx2fc_cmd_release); /* timer hold */
  569. rc = bnx2fc_initiate_abts(io_req);
  570. if (rc != SUCCESS) {
  571. BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
  572. "failed. issue cleanup\n");
  573. rc = bnx2fc_initiate_cleanup(io_req);
  574. BUG_ON(rc);
  575. }
  576. } else
  577. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  578. "in ABTS processing\n", xid);
  579. spin_unlock_bh(&tgt->tgt_lock);
  580. break;
  581. case FCOE_WARNING_DETECTION_CQE_TYPE:
  582. /*
  583. *In case of warning reporting CQE a single RQ entry
  584. * is consumes.
  585. */
  586. num_rq = 1;
  587. err_entry = (struct fcoe_err_report_entry *)
  588. bnx2fc_get_next_rqe(tgt, 1);
  589. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  590. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  591. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  592. err_entry->err_warn_bitmap_hi,
  593. err_entry->err_warn_bitmap_lo);
  594. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  595. err_entry->tx_buf_off, err_entry->rx_buf_off);
  596. bnx2fc_return_rqe(tgt, 1);
  597. break;
  598. default:
  599. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  600. break;
  601. }
  602. }
  603. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  604. {
  605. struct fcoe_task_ctx_entry *task;
  606. struct fcoe_task_ctx_entry *task_page;
  607. struct fcoe_port *port = tgt->port;
  608. struct bnx2fc_hba *hba = port->priv;
  609. struct bnx2fc_cmd *io_req;
  610. int task_idx, index;
  611. u16 xid;
  612. u8 cmd_type;
  613. u8 rx_state = 0;
  614. u8 num_rq;
  615. spin_lock_bh(&tgt->tgt_lock);
  616. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  617. if (xid >= BNX2FC_MAX_TASKS) {
  618. printk(KERN_ALERT PFX "ERROR:xid out of range\n");
  619. spin_unlock_bh(&tgt->tgt_lock);
  620. return;
  621. }
  622. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  623. index = xid % BNX2FC_TASKS_PER_PAGE;
  624. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  625. task = &(task_page[index]);
  626. num_rq = ((task->rx_wr_tx_rd.rx_flags &
  627. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE) >>
  628. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT);
  629. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  630. if (io_req == NULL) {
  631. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  632. spin_unlock_bh(&tgt->tgt_lock);
  633. return;
  634. }
  635. /* Timestamp IO completion time */
  636. cmd_type = io_req->cmd_type;
  637. /* optimized completion path */
  638. if (cmd_type == BNX2FC_SCSI_CMD) {
  639. rx_state = ((task->rx_wr_tx_rd.rx_flags &
  640. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE) >>
  641. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT);
  642. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  643. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  644. spin_unlock_bh(&tgt->tgt_lock);
  645. return;
  646. }
  647. }
  648. /* Process other IO completion types */
  649. switch (cmd_type) {
  650. case BNX2FC_SCSI_CMD:
  651. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  652. bnx2fc_process_abts_compl(io_req, task, num_rq);
  653. else if (rx_state ==
  654. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  655. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  656. else
  657. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  658. rx_state);
  659. break;
  660. case BNX2FC_TASK_MGMT_CMD:
  661. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  662. bnx2fc_process_tm_compl(io_req, task, num_rq);
  663. break;
  664. case BNX2FC_ABTS:
  665. /*
  666. * ABTS request received by firmware. ABTS response
  667. * will be delivered to the task belonging to the IO
  668. * that was aborted
  669. */
  670. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  671. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  672. break;
  673. case BNX2FC_ELS:
  674. BNX2FC_IO_DBG(io_req, "cq_compl - call process_els_compl\n");
  675. bnx2fc_process_els_compl(io_req, task, num_rq);
  676. break;
  677. case BNX2FC_CLEANUP:
  678. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  679. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  680. break;
  681. default:
  682. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  683. break;
  684. }
  685. spin_unlock_bh(&tgt->tgt_lock);
  686. }
  687. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  688. {
  689. struct bnx2fc_work *work;
  690. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  691. if (!work)
  692. return NULL;
  693. INIT_LIST_HEAD(&work->list);
  694. work->tgt = tgt;
  695. work->wqe = wqe;
  696. return work;
  697. }
  698. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  699. {
  700. struct fcoe_cqe *cq;
  701. u32 cq_cons;
  702. struct fcoe_cqe *cqe;
  703. u16 wqe;
  704. bool more_cqes_found = false;
  705. /*
  706. * cq_lock is a low contention lock used to protect
  707. * the CQ data structure from being freed up during
  708. * the upload operation
  709. */
  710. spin_lock_bh(&tgt->cq_lock);
  711. if (!tgt->cq) {
  712. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  713. spin_unlock_bh(&tgt->cq_lock);
  714. return 0;
  715. }
  716. cq = tgt->cq;
  717. cq_cons = tgt->cq_cons_idx;
  718. cqe = &cq[cq_cons];
  719. do {
  720. more_cqes_found ^= true;
  721. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  722. (tgt->cq_curr_toggle_bit <<
  723. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  724. /* new entry on the cq */
  725. if (wqe & FCOE_CQE_CQE_TYPE) {
  726. /* Unsolicited event notification */
  727. bnx2fc_process_unsol_compl(tgt, wqe);
  728. } else {
  729. struct bnx2fc_work *work = NULL;
  730. struct bnx2fc_percpu_s *fps = NULL;
  731. unsigned int cpu = wqe % num_possible_cpus();
  732. fps = &per_cpu(bnx2fc_percpu, cpu);
  733. spin_lock_bh(&fps->fp_work_lock);
  734. if (unlikely(!fps->iothread))
  735. goto unlock;
  736. work = bnx2fc_alloc_work(tgt, wqe);
  737. if (work)
  738. list_add_tail(&work->list,
  739. &fps->work_list);
  740. unlock:
  741. spin_unlock_bh(&fps->fp_work_lock);
  742. /* Pending work request completion */
  743. if (fps->iothread && work)
  744. wake_up_process(fps->iothread);
  745. else
  746. bnx2fc_process_cq_compl(tgt, wqe);
  747. }
  748. cqe++;
  749. tgt->cq_cons_idx++;
  750. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  751. tgt->cq_cons_idx = 0;
  752. cqe = cq;
  753. tgt->cq_curr_toggle_bit =
  754. 1 - tgt->cq_curr_toggle_bit;
  755. }
  756. }
  757. /* Re-arm CQ */
  758. if (more_cqes_found) {
  759. tgt->conn_db->cq_arm.lo = -1;
  760. wmb();
  761. }
  762. } while (more_cqes_found);
  763. /*
  764. * Commit tgt->cq_cons_idx change to the memory
  765. * spin_lock implies full memory barrier, no need to smp_wmb
  766. */
  767. spin_unlock_bh(&tgt->cq_lock);
  768. return 0;
  769. }
  770. /**
  771. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  772. *
  773. * @hba: adapter structure pointer
  774. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  775. *
  776. * Fast path event notification handler
  777. */
  778. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  779. struct fcoe_kcqe *new_cqe_kcqe)
  780. {
  781. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  782. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  783. if (!tgt) {
  784. printk(KERN_ALERT PFX "conn_id 0x%x not valid\n", conn_id);
  785. return;
  786. }
  787. bnx2fc_process_new_cqes(tgt);
  788. }
  789. /**
  790. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  791. *
  792. * @hba: adapter structure pointer
  793. * @ofld_kcqe: connection offload kcqe pointer
  794. *
  795. * handle session offload completion, enable the session if offload is
  796. * successful.
  797. */
  798. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  799. struct fcoe_kcqe *ofld_kcqe)
  800. {
  801. struct bnx2fc_rport *tgt;
  802. struct fcoe_port *port;
  803. u32 conn_id;
  804. u32 context_id;
  805. int rc;
  806. conn_id = ofld_kcqe->fcoe_conn_id;
  807. context_id = ofld_kcqe->fcoe_conn_context_id;
  808. tgt = hba->tgt_ofld_list[conn_id];
  809. if (!tgt) {
  810. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  811. return;
  812. }
  813. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  814. ofld_kcqe->fcoe_conn_context_id);
  815. port = tgt->port;
  816. if (hba != tgt->port->priv) {
  817. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  818. goto ofld_cmpl_err;
  819. }
  820. /*
  821. * cnic has allocated a context_id for this session; use this
  822. * while enabling the session.
  823. */
  824. tgt->context_id = context_id;
  825. if (ofld_kcqe->completion_status) {
  826. if (ofld_kcqe->completion_status ==
  827. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  828. printk(KERN_ERR PFX "unable to allocate FCoE context "
  829. "resources\n");
  830. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  831. }
  832. goto ofld_cmpl_err;
  833. } else {
  834. /* now enable the session */
  835. rc = bnx2fc_send_session_enable_req(port, tgt);
  836. if (rc) {
  837. printk(KERN_ALERT PFX "enable session failed\n");
  838. goto ofld_cmpl_err;
  839. }
  840. }
  841. return;
  842. ofld_cmpl_err:
  843. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  844. wake_up_interruptible(&tgt->ofld_wait);
  845. }
  846. /**
  847. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  848. *
  849. * @hba: adapter structure pointer
  850. * @ofld_kcqe: connection offload kcqe pointer
  851. *
  852. * handle session enable completion, mark the rport as ready
  853. */
  854. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  855. struct fcoe_kcqe *ofld_kcqe)
  856. {
  857. struct bnx2fc_rport *tgt;
  858. u32 conn_id;
  859. u32 context_id;
  860. context_id = ofld_kcqe->fcoe_conn_context_id;
  861. conn_id = ofld_kcqe->fcoe_conn_id;
  862. tgt = hba->tgt_ofld_list[conn_id];
  863. if (!tgt) {
  864. printk(KERN_ALERT PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  865. return;
  866. }
  867. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  868. ofld_kcqe->fcoe_conn_context_id);
  869. /*
  870. * context_id should be the same for this target during offload
  871. * and enable
  872. */
  873. if (tgt->context_id != context_id) {
  874. printk(KERN_ALERT PFX "context id mis-match\n");
  875. return;
  876. }
  877. if (hba != tgt->port->priv) {
  878. printk(KERN_ALERT PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  879. goto enbl_cmpl_err;
  880. }
  881. if (ofld_kcqe->completion_status) {
  882. goto enbl_cmpl_err;
  883. } else {
  884. /* enable successful - rport ready for issuing IOs */
  885. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  886. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  887. wake_up_interruptible(&tgt->ofld_wait);
  888. }
  889. return;
  890. enbl_cmpl_err:
  891. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  892. wake_up_interruptible(&tgt->ofld_wait);
  893. }
  894. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  895. struct fcoe_kcqe *disable_kcqe)
  896. {
  897. struct bnx2fc_rport *tgt;
  898. u32 conn_id;
  899. conn_id = disable_kcqe->fcoe_conn_id;
  900. tgt = hba->tgt_ofld_list[conn_id];
  901. if (!tgt) {
  902. printk(KERN_ALERT PFX "ERROR: disable_cmpl: No disable req\n");
  903. return;
  904. }
  905. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  906. if (disable_kcqe->completion_status) {
  907. printk(KERN_ALERT PFX "ERROR: Disable failed with cmpl status %d\n",
  908. disable_kcqe->completion_status);
  909. return;
  910. } else {
  911. /* disable successful */
  912. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  913. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  914. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  915. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  916. wake_up_interruptible(&tgt->upld_wait);
  917. }
  918. }
  919. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  920. struct fcoe_kcqe *destroy_kcqe)
  921. {
  922. struct bnx2fc_rport *tgt;
  923. u32 conn_id;
  924. conn_id = destroy_kcqe->fcoe_conn_id;
  925. tgt = hba->tgt_ofld_list[conn_id];
  926. if (!tgt) {
  927. printk(KERN_ALERT PFX "destroy_cmpl: No destroy req\n");
  928. return;
  929. }
  930. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  931. if (destroy_kcqe->completion_status) {
  932. printk(KERN_ALERT PFX "Destroy conn failed, cmpl status %d\n",
  933. destroy_kcqe->completion_status);
  934. return;
  935. } else {
  936. /* destroy successful */
  937. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  938. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  939. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  940. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  941. wake_up_interruptible(&tgt->upld_wait);
  942. }
  943. }
  944. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  945. {
  946. switch (err_code) {
  947. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  948. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  949. break;
  950. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  951. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  952. break;
  953. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  954. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  955. break;
  956. default:
  957. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  958. }
  959. }
  960. /**
  961. * bnx2fc_indicae_kcqe - process KCQE
  962. *
  963. * @hba: adapter structure pointer
  964. * @kcqe: kcqe pointer
  965. * @num_cqe: Number of completion queue elements
  966. *
  967. * Generic KCQ event handler
  968. */
  969. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  970. u32 num_cqe)
  971. {
  972. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  973. int i = 0;
  974. struct fcoe_kcqe *kcqe = NULL;
  975. while (i < num_cqe) {
  976. kcqe = (struct fcoe_kcqe *) kcq[i++];
  977. switch (kcqe->op_code) {
  978. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  979. bnx2fc_fastpath_notification(hba, kcqe);
  980. break;
  981. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  982. bnx2fc_process_ofld_cmpl(hba, kcqe);
  983. break;
  984. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  985. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  986. break;
  987. case FCOE_KCQE_OPCODE_INIT_FUNC:
  988. if (kcqe->completion_status !=
  989. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  990. bnx2fc_init_failure(hba,
  991. kcqe->completion_status);
  992. } else {
  993. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  994. bnx2fc_get_link_state(hba);
  995. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  996. (u8)hba->pcidev->bus->number);
  997. }
  998. break;
  999. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1000. if (kcqe->completion_status !=
  1001. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1002. printk(KERN_ERR PFX "DESTROY failed\n");
  1003. } else {
  1004. printk(KERN_ERR PFX "DESTROY success\n");
  1005. }
  1006. hba->flags |= BNX2FC_FLAG_DESTROY_CMPL;
  1007. wake_up_interruptible(&hba->destroy_wait);
  1008. break;
  1009. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1010. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1011. break;
  1012. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1013. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1014. break;
  1015. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1016. if (kcqe->completion_status !=
  1017. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1018. printk(KERN_ERR PFX "STAT failed\n");
  1019. complete(&hba->stat_req_done);
  1020. break;
  1021. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1022. /* fall thru */
  1023. default:
  1024. printk(KERN_ALERT PFX "unknown opcode 0x%x\n",
  1025. kcqe->op_code);
  1026. }
  1027. }
  1028. }
  1029. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1030. {
  1031. struct fcoe_sqe *sqe;
  1032. sqe = &tgt->sq[tgt->sq_prod_idx];
  1033. /* Fill SQ WQE */
  1034. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1035. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1036. /* Advance SQ Prod Idx */
  1037. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1038. tgt->sq_prod_idx = 0;
  1039. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1040. }
  1041. }
  1042. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1043. {
  1044. struct b577xx_doorbell_set_prod ev_doorbell;
  1045. u32 msg;
  1046. wmb();
  1047. memset(&ev_doorbell, 0, sizeof(struct b577xx_doorbell_set_prod));
  1048. ev_doorbell.header.header = B577XX_DOORBELL_HDR_DB_TYPE;
  1049. ev_doorbell.prod = tgt->sq_prod_idx |
  1050. (tgt->sq_curr_toggle_bit << 15);
  1051. ev_doorbell.header.header |= B577XX_FCOE_CONNECTION_TYPE <<
  1052. B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT;
  1053. msg = *((u32 *)&ev_doorbell);
  1054. writel(cpu_to_le32(msg), tgt->ctx_base);
  1055. mmiowb();
  1056. }
  1057. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1058. {
  1059. u32 context_id = tgt->context_id;
  1060. struct fcoe_port *port = tgt->port;
  1061. u32 reg_off;
  1062. resource_size_t reg_base;
  1063. struct bnx2fc_hba *hba = port->priv;
  1064. reg_base = pci_resource_start(hba->pcidev,
  1065. BNX2X_DOORBELL_PCI_BAR);
  1066. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1067. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1068. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1069. if (!tgt->ctx_base)
  1070. return -ENOMEM;
  1071. return 0;
  1072. }
  1073. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1074. {
  1075. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1076. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1077. return NULL;
  1078. tgt->rq_cons_idx += num_items;
  1079. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1080. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1081. return buf;
  1082. }
  1083. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1084. {
  1085. /* return the rq buffer */
  1086. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1087. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1088. /* Wrap around RQ */
  1089. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1090. }
  1091. tgt->rq_prod_idx = next_prod_idx;
  1092. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1093. }
  1094. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1095. struct fcoe_task_ctx_entry *task,
  1096. u16 orig_xid)
  1097. {
  1098. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1099. struct bnx2fc_rport *tgt = io_req->tgt;
  1100. u32 context_id = tgt->context_id;
  1101. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1102. /* Tx Write Rx Read */
  1103. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1104. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1105. task->tx_wr_rx_rd.init_flags = task_type <<
  1106. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1107. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1108. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1109. /* Common */
  1110. task->cmn.common_flags = context_id <<
  1111. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1112. task->cmn.general.cleanup_info.task_id = orig_xid;
  1113. }
  1114. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1115. struct fcoe_task_ctx_entry *task)
  1116. {
  1117. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1118. struct bnx2fc_rport *tgt = io_req->tgt;
  1119. struct fc_frame_header *fc_hdr;
  1120. u8 task_type = 0;
  1121. u64 *hdr;
  1122. u64 temp_hdr[3];
  1123. u32 context_id;
  1124. /* Obtain task_type */
  1125. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1126. (io_req->cmd_type == BNX2FC_ELS)) {
  1127. task_type = FCOE_TASK_TYPE_MIDPATH;
  1128. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1129. task_type = FCOE_TASK_TYPE_ABTS;
  1130. }
  1131. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1132. /* Setup the task from io_req for easy reference */
  1133. io_req->task = task;
  1134. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1135. io_req->cmd_type, task_type);
  1136. /* Tx only */
  1137. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1138. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1139. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1140. (u32)mp_req->mp_req_bd_dma;
  1141. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1142. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1143. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1144. BNX2FC_IO_DBG(io_req, "init_mp_task - bd_dma = 0x%llx\n",
  1145. (unsigned long long)mp_req->mp_req_bd_dma);
  1146. }
  1147. /* Tx Write Rx Read */
  1148. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1149. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1150. task->tx_wr_rx_rd.init_flags = task_type <<
  1151. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1152. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1153. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1154. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1155. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1156. /* Common */
  1157. task->cmn.data_2_trns = io_req->data_xfer_len;
  1158. context_id = tgt->context_id;
  1159. task->cmn.common_flags = context_id <<
  1160. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1161. task->cmn.common_flags |= 1 <<
  1162. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1163. task->cmn.common_flags |= 1 <<
  1164. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1165. /* Rx Write Tx Read */
  1166. fc_hdr = &(mp_req->req_fc_hdr);
  1167. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1168. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1169. fc_hdr->fh_rx_id = htons(0xffff);
  1170. task->rx_wr_tx_rd.rx_id = 0xffff;
  1171. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1172. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1173. }
  1174. /* Fill FC Header into middle path buffer */
  1175. hdr = (u64 *) &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr;
  1176. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1177. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1178. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1179. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1180. /* Rx Only */
  1181. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1182. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1183. (u32)mp_req->mp_resp_bd_dma;
  1184. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1185. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1186. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1187. }
  1188. }
  1189. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1190. struct fcoe_task_ctx_entry *task)
  1191. {
  1192. u8 task_type;
  1193. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1194. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1195. struct bnx2fc_rport *tgt = io_req->tgt;
  1196. u64 *fcp_cmnd;
  1197. u64 tmp_fcp_cmnd[4];
  1198. u32 context_id;
  1199. int cnt, i;
  1200. int bd_count;
  1201. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1202. /* Setup the task from io_req for easy reference */
  1203. io_req->task = task;
  1204. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1205. task_type = FCOE_TASK_TYPE_WRITE;
  1206. else
  1207. task_type = FCOE_TASK_TYPE_READ;
  1208. /* Tx only */
  1209. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1210. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1211. (u32)bd_tbl->bd_tbl_dma;
  1212. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1213. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1214. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1215. bd_tbl->bd_valid;
  1216. }
  1217. /*Tx Write Rx Read */
  1218. /* Init state to NORMAL */
  1219. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1220. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1221. task->tx_wr_rx_rd.init_flags = task_type <<
  1222. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1223. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1224. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1225. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1226. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1227. /* Common */
  1228. task->cmn.data_2_trns = io_req->data_xfer_len;
  1229. context_id = tgt->context_id;
  1230. task->cmn.common_flags = context_id <<
  1231. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1232. task->cmn.common_flags |= 1 <<
  1233. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1234. task->cmn.common_flags |= 1 <<
  1235. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1236. /* Set initiative ownership */
  1237. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT;
  1238. /* Set initial seq counter */
  1239. task->cmn.tx_low_seq_cnt = 1;
  1240. /* Set state to "waiting for the first packet" */
  1241. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME;
  1242. /* Fill FCP_CMND IU */
  1243. fcp_cmnd = (u64 *)
  1244. task->cmn.general.cmd_info.fcp_cmd_payload.opaque;
  1245. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1246. /* swap fcp_cmnd */
  1247. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1248. for (i = 0; i < cnt; i++) {
  1249. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1250. fcp_cmnd++;
  1251. }
  1252. /* Rx Write Tx Read */
  1253. task->rx_wr_tx_rd.rx_id = 0xffff;
  1254. /* Rx Only */
  1255. if (task_type == FCOE_TASK_TYPE_READ) {
  1256. bd_count = bd_tbl->bd_valid;
  1257. if (bd_count == 1) {
  1258. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1259. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.lo =
  1260. fcoe_bd_tbl->buf_addr_lo;
  1261. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.hi =
  1262. fcoe_bd_tbl->buf_addr_hi;
  1263. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_rem =
  1264. fcoe_bd_tbl->buf_len;
  1265. task->tx_wr_rx_rd.init_flags |= 1 <<
  1266. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT;
  1267. } else {
  1268. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1269. (u32)bd_tbl->bd_tbl_dma;
  1270. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1271. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1272. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1273. bd_tbl->bd_valid;
  1274. }
  1275. }
  1276. }
  1277. /**
  1278. * bnx2fc_setup_task_ctx - allocate and map task context
  1279. *
  1280. * @hba: pointer to adapter structure
  1281. *
  1282. * allocate memory for task context, and associated BD table to be used
  1283. * by firmware
  1284. *
  1285. */
  1286. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1287. {
  1288. int rc = 0;
  1289. struct regpair *task_ctx_bdt;
  1290. dma_addr_t addr;
  1291. int i;
  1292. /*
  1293. * Allocate task context bd table. A page size of bd table
  1294. * can map 256 buffers. Each buffer contains 32 task context
  1295. * entries. Hence the limit with one page is 8192 task context
  1296. * entries.
  1297. */
  1298. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1299. PAGE_SIZE,
  1300. &hba->task_ctx_bd_dma,
  1301. GFP_KERNEL);
  1302. if (!hba->task_ctx_bd_tbl) {
  1303. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1304. rc = -1;
  1305. goto out;
  1306. }
  1307. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1308. /*
  1309. * Allocate task_ctx which is an array of pointers pointing to
  1310. * a page containing 32 task contexts
  1311. */
  1312. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1313. GFP_KERNEL);
  1314. if (!hba->task_ctx) {
  1315. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1316. rc = -1;
  1317. goto out1;
  1318. }
  1319. /*
  1320. * Allocate task_ctx_dma which is an array of dma addresses
  1321. */
  1322. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1323. sizeof(dma_addr_t)), GFP_KERNEL);
  1324. if (!hba->task_ctx_dma) {
  1325. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1326. rc = -1;
  1327. goto out2;
  1328. }
  1329. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1330. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1331. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1332. PAGE_SIZE,
  1333. &hba->task_ctx_dma[i],
  1334. GFP_KERNEL);
  1335. if (!hba->task_ctx[i]) {
  1336. printk(KERN_ERR PFX "unable to alloc task context\n");
  1337. rc = -1;
  1338. goto out3;
  1339. }
  1340. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1341. addr = (u64)hba->task_ctx_dma[i];
  1342. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1343. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1344. task_ctx_bdt++;
  1345. }
  1346. return 0;
  1347. out3:
  1348. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1349. if (hba->task_ctx[i]) {
  1350. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1351. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1352. hba->task_ctx[i] = NULL;
  1353. }
  1354. }
  1355. kfree(hba->task_ctx_dma);
  1356. hba->task_ctx_dma = NULL;
  1357. out2:
  1358. kfree(hba->task_ctx);
  1359. hba->task_ctx = NULL;
  1360. out1:
  1361. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1362. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1363. hba->task_ctx_bd_tbl = NULL;
  1364. out:
  1365. return rc;
  1366. }
  1367. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1368. {
  1369. int i;
  1370. if (hba->task_ctx_bd_tbl) {
  1371. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1372. hba->task_ctx_bd_tbl,
  1373. hba->task_ctx_bd_dma);
  1374. hba->task_ctx_bd_tbl = NULL;
  1375. }
  1376. if (hba->task_ctx) {
  1377. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1378. if (hba->task_ctx[i]) {
  1379. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1380. hba->task_ctx[i],
  1381. hba->task_ctx_dma[i]);
  1382. hba->task_ctx[i] = NULL;
  1383. }
  1384. }
  1385. kfree(hba->task_ctx);
  1386. hba->task_ctx = NULL;
  1387. }
  1388. kfree(hba->task_ctx_dma);
  1389. hba->task_ctx_dma = NULL;
  1390. }
  1391. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1392. {
  1393. int i;
  1394. int segment_count;
  1395. int hash_table_size;
  1396. u32 *pbl;
  1397. segment_count = hba->hash_tbl_segment_count;
  1398. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1399. sizeof(struct fcoe_hash_table_entry);
  1400. pbl = hba->hash_tbl_pbl;
  1401. for (i = 0; i < segment_count; ++i) {
  1402. dma_addr_t dma_address;
  1403. dma_address = le32_to_cpu(*pbl);
  1404. ++pbl;
  1405. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1406. ++pbl;
  1407. dma_free_coherent(&hba->pcidev->dev,
  1408. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1409. hba->hash_tbl_segments[i],
  1410. dma_address);
  1411. }
  1412. if (hba->hash_tbl_pbl) {
  1413. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1414. hba->hash_tbl_pbl,
  1415. hba->hash_tbl_pbl_dma);
  1416. hba->hash_tbl_pbl = NULL;
  1417. }
  1418. }
  1419. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1420. {
  1421. int i;
  1422. int hash_table_size;
  1423. int segment_count;
  1424. int segment_array_size;
  1425. int dma_segment_array_size;
  1426. dma_addr_t *dma_segment_array;
  1427. u32 *pbl;
  1428. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1429. sizeof(struct fcoe_hash_table_entry);
  1430. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1431. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1432. hba->hash_tbl_segment_count = segment_count;
  1433. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1434. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1435. if (!hba->hash_tbl_segments) {
  1436. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1437. return -ENOMEM;
  1438. }
  1439. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1440. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1441. if (!dma_segment_array) {
  1442. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1443. return -ENOMEM;
  1444. }
  1445. for (i = 0; i < segment_count; ++i) {
  1446. hba->hash_tbl_segments[i] =
  1447. dma_alloc_coherent(&hba->pcidev->dev,
  1448. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1449. &dma_segment_array[i],
  1450. GFP_KERNEL);
  1451. if (!hba->hash_tbl_segments[i]) {
  1452. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1453. while (--i >= 0) {
  1454. dma_free_coherent(&hba->pcidev->dev,
  1455. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1456. hba->hash_tbl_segments[i],
  1457. dma_segment_array[i]);
  1458. hba->hash_tbl_segments[i] = NULL;
  1459. }
  1460. kfree(dma_segment_array);
  1461. return -ENOMEM;
  1462. }
  1463. memset(hba->hash_tbl_segments[i], 0,
  1464. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1465. }
  1466. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1467. PAGE_SIZE,
  1468. &hba->hash_tbl_pbl_dma,
  1469. GFP_KERNEL);
  1470. if (!hba->hash_tbl_pbl) {
  1471. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1472. kfree(dma_segment_array);
  1473. return -ENOMEM;
  1474. }
  1475. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1476. pbl = hba->hash_tbl_pbl;
  1477. for (i = 0; i < segment_count; ++i) {
  1478. u64 paddr = dma_segment_array[i];
  1479. *pbl = cpu_to_le32((u32) paddr);
  1480. ++pbl;
  1481. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1482. ++pbl;
  1483. }
  1484. pbl = hba->hash_tbl_pbl;
  1485. i = 0;
  1486. while (*pbl && *(pbl + 1)) {
  1487. u32 lo;
  1488. u32 hi;
  1489. lo = *pbl;
  1490. ++pbl;
  1491. hi = *pbl;
  1492. ++pbl;
  1493. ++i;
  1494. }
  1495. kfree(dma_segment_array);
  1496. return 0;
  1497. }
  1498. /**
  1499. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1500. *
  1501. * @hba: Pointer to adapter structure
  1502. *
  1503. */
  1504. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1505. {
  1506. u64 addr;
  1507. u32 mem_size;
  1508. int i;
  1509. if (bnx2fc_allocate_hash_table(hba))
  1510. return -ENOMEM;
  1511. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1512. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1513. &hba->t2_hash_tbl_ptr_dma,
  1514. GFP_KERNEL);
  1515. if (!hba->t2_hash_tbl_ptr) {
  1516. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1517. bnx2fc_free_fw_resc(hba);
  1518. return -ENOMEM;
  1519. }
  1520. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1521. mem_size = BNX2FC_NUM_MAX_SESS *
  1522. sizeof(struct fcoe_t2_hash_table_entry);
  1523. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1524. &hba->t2_hash_tbl_dma,
  1525. GFP_KERNEL);
  1526. if (!hba->t2_hash_tbl) {
  1527. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1528. bnx2fc_free_fw_resc(hba);
  1529. return -ENOMEM;
  1530. }
  1531. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1532. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1533. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1534. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1535. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1536. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1537. }
  1538. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1539. PAGE_SIZE, &hba->dummy_buf_dma,
  1540. GFP_KERNEL);
  1541. if (!hba->dummy_buffer) {
  1542. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1543. bnx2fc_free_fw_resc(hba);
  1544. return -ENOMEM;
  1545. }
  1546. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1547. PAGE_SIZE,
  1548. &hba->stats_buf_dma,
  1549. GFP_KERNEL);
  1550. if (!hba->stats_buffer) {
  1551. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1552. bnx2fc_free_fw_resc(hba);
  1553. return -ENOMEM;
  1554. }
  1555. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1556. return 0;
  1557. }
  1558. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1559. {
  1560. u32 mem_size;
  1561. if (hba->stats_buffer) {
  1562. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1563. hba->stats_buffer, hba->stats_buf_dma);
  1564. hba->stats_buffer = NULL;
  1565. }
  1566. if (hba->dummy_buffer) {
  1567. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1568. hba->dummy_buffer, hba->dummy_buf_dma);
  1569. hba->dummy_buffer = NULL;
  1570. }
  1571. if (hba->t2_hash_tbl_ptr) {
  1572. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1573. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1574. hba->t2_hash_tbl_ptr,
  1575. hba->t2_hash_tbl_ptr_dma);
  1576. hba->t2_hash_tbl_ptr = NULL;
  1577. }
  1578. if (hba->t2_hash_tbl) {
  1579. mem_size = BNX2FC_NUM_MAX_SESS *
  1580. sizeof(struct fcoe_t2_hash_table_entry);
  1581. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1582. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1583. hba->t2_hash_tbl = NULL;
  1584. }
  1585. bnx2fc_free_hash_table(hba);
  1586. }