access.c 11 KB

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  1. #include <linux/delay.h>
  2. #include <linux/pci.h>
  3. #include <linux/module.h>
  4. #include <linux/sched.h>
  5. #include <linux/slab.h>
  6. #include <linux/ioport.h>
  7. #include <linux/wait.h>
  8. #include "pci.h"
  9. /*
  10. * This interrupt-safe spinlock protects all accesses to PCI
  11. * configuration space.
  12. */
  13. static DEFINE_RAW_SPINLOCK(pci_lock);
  14. /*
  15. * Wrappers for all PCI configuration access functions. They just check
  16. * alignment, do locking and call the low-level functions pointed to
  17. * by pci_dev->ops.
  18. */
  19. #define PCI_byte_BAD 0
  20. #define PCI_word_BAD (pos & 1)
  21. #define PCI_dword_BAD (pos & 3)
  22. #define PCI_OP_READ(size,type,len) \
  23. int pci_bus_read_config_##size \
  24. (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
  25. { \
  26. int res; \
  27. unsigned long flags; \
  28. u32 data = 0; \
  29. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  30. raw_spin_lock_irqsave(&pci_lock, flags); \
  31. res = bus->ops->read(bus, devfn, pos, len, &data); \
  32. *value = (type)data; \
  33. raw_spin_unlock_irqrestore(&pci_lock, flags); \
  34. return res; \
  35. }
  36. #define PCI_OP_WRITE(size,type,len) \
  37. int pci_bus_write_config_##size \
  38. (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
  39. { \
  40. int res; \
  41. unsigned long flags; \
  42. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  43. raw_spin_lock_irqsave(&pci_lock, flags); \
  44. res = bus->ops->write(bus, devfn, pos, len, value); \
  45. raw_spin_unlock_irqrestore(&pci_lock, flags); \
  46. return res; \
  47. }
  48. PCI_OP_READ(byte, u8, 1)
  49. PCI_OP_READ(word, u16, 2)
  50. PCI_OP_READ(dword, u32, 4)
  51. PCI_OP_WRITE(byte, u8, 1)
  52. PCI_OP_WRITE(word, u16, 2)
  53. PCI_OP_WRITE(dword, u32, 4)
  54. EXPORT_SYMBOL(pci_bus_read_config_byte);
  55. EXPORT_SYMBOL(pci_bus_read_config_word);
  56. EXPORT_SYMBOL(pci_bus_read_config_dword);
  57. EXPORT_SYMBOL(pci_bus_write_config_byte);
  58. EXPORT_SYMBOL(pci_bus_write_config_word);
  59. EXPORT_SYMBOL(pci_bus_write_config_dword);
  60. /**
  61. * pci_bus_set_ops - Set raw operations of pci bus
  62. * @bus: pci bus struct
  63. * @ops: new raw operations
  64. *
  65. * Return previous raw operations
  66. */
  67. struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
  68. {
  69. struct pci_ops *old_ops;
  70. unsigned long flags;
  71. raw_spin_lock_irqsave(&pci_lock, flags);
  72. old_ops = bus->ops;
  73. bus->ops = ops;
  74. raw_spin_unlock_irqrestore(&pci_lock, flags);
  75. return old_ops;
  76. }
  77. EXPORT_SYMBOL(pci_bus_set_ops);
  78. /**
  79. * pci_read_vpd - Read one entry from Vital Product Data
  80. * @dev: pci device struct
  81. * @pos: offset in vpd space
  82. * @count: number of bytes to read
  83. * @buf: pointer to where to store result
  84. *
  85. */
  86. ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
  87. {
  88. if (!dev->vpd || !dev->vpd->ops)
  89. return -ENODEV;
  90. return dev->vpd->ops->read(dev, pos, count, buf);
  91. }
  92. EXPORT_SYMBOL(pci_read_vpd);
  93. /**
  94. * pci_write_vpd - Write entry to Vital Product Data
  95. * @dev: pci device struct
  96. * @pos: offset in vpd space
  97. * @count: number of bytes to write
  98. * @buf: buffer containing write data
  99. *
  100. */
  101. ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
  102. {
  103. if (!dev->vpd || !dev->vpd->ops)
  104. return -ENODEV;
  105. return dev->vpd->ops->write(dev, pos, count, buf);
  106. }
  107. EXPORT_SYMBOL(pci_write_vpd);
  108. /*
  109. * The following routines are to prevent the user from accessing PCI config
  110. * space when it's unsafe to do so. Some devices require this during BIST and
  111. * we're required to prevent it during D-state transitions.
  112. *
  113. * We have a bit per device to indicate it's blocked and a global wait queue
  114. * for callers to sleep on until devices are unblocked.
  115. */
  116. static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
  117. static noinline void pci_wait_ucfg(struct pci_dev *dev)
  118. {
  119. DECLARE_WAITQUEUE(wait, current);
  120. __add_wait_queue(&pci_ucfg_wait, &wait);
  121. do {
  122. set_current_state(TASK_UNINTERRUPTIBLE);
  123. raw_spin_unlock_irq(&pci_lock);
  124. schedule();
  125. raw_spin_lock_irq(&pci_lock);
  126. } while (dev->block_ucfg_access);
  127. __remove_wait_queue(&pci_ucfg_wait, &wait);
  128. }
  129. #define PCI_USER_READ_CONFIG(size,type) \
  130. int pci_user_read_config_##size \
  131. (struct pci_dev *dev, int pos, type *val) \
  132. { \
  133. int ret = 0; \
  134. u32 data = -1; \
  135. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  136. raw_spin_lock_irq(&pci_lock); \
  137. if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
  138. ret = dev->bus->ops->read(dev->bus, dev->devfn, \
  139. pos, sizeof(type), &data); \
  140. raw_spin_unlock_irq(&pci_lock); \
  141. *val = (type)data; \
  142. return ret; \
  143. }
  144. #define PCI_USER_WRITE_CONFIG(size,type) \
  145. int pci_user_write_config_##size \
  146. (struct pci_dev *dev, int pos, type val) \
  147. { \
  148. int ret = -EIO; \
  149. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  150. raw_spin_lock_irq(&pci_lock); \
  151. if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
  152. ret = dev->bus->ops->write(dev->bus, dev->devfn, \
  153. pos, sizeof(type), val); \
  154. raw_spin_unlock_irq(&pci_lock); \
  155. return ret; \
  156. }
  157. PCI_USER_READ_CONFIG(byte, u8)
  158. PCI_USER_READ_CONFIG(word, u16)
  159. PCI_USER_READ_CONFIG(dword, u32)
  160. PCI_USER_WRITE_CONFIG(byte, u8)
  161. PCI_USER_WRITE_CONFIG(word, u16)
  162. PCI_USER_WRITE_CONFIG(dword, u32)
  163. /* VPD access through PCI 2.2+ VPD capability */
  164. #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
  165. struct pci_vpd_pci22 {
  166. struct pci_vpd base;
  167. struct mutex lock;
  168. u16 flag;
  169. bool busy;
  170. u8 cap;
  171. };
  172. /*
  173. * Wait for last operation to complete.
  174. * This code has to spin since there is no other notification from the PCI
  175. * hardware. Since the VPD is often implemented by serial attachment to an
  176. * EEPROM, it may take many milliseconds to complete.
  177. */
  178. static int pci_vpd_pci22_wait(struct pci_dev *dev)
  179. {
  180. struct pci_vpd_pci22 *vpd =
  181. container_of(dev->vpd, struct pci_vpd_pci22, base);
  182. unsigned long timeout = jiffies + HZ/20 + 2;
  183. u16 status;
  184. int ret;
  185. if (!vpd->busy)
  186. return 0;
  187. for (;;) {
  188. ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  189. &status);
  190. if (ret)
  191. return ret;
  192. if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
  193. vpd->busy = false;
  194. return 0;
  195. }
  196. if (time_after(jiffies, timeout)) {
  197. dev_printk(KERN_DEBUG, &dev->dev,
  198. "vpd r/w failed. This is likely a firmware "
  199. "bug on this device. Contact the card "
  200. "vendor for a firmware update.");
  201. return -ETIMEDOUT;
  202. }
  203. if (fatal_signal_pending(current))
  204. return -EINTR;
  205. if (!cond_resched())
  206. udelay(10);
  207. }
  208. }
  209. static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
  210. void *arg)
  211. {
  212. struct pci_vpd_pci22 *vpd =
  213. container_of(dev->vpd, struct pci_vpd_pci22, base);
  214. int ret;
  215. loff_t end = pos + count;
  216. u8 *buf = arg;
  217. if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
  218. return -EINVAL;
  219. if (mutex_lock_killable(&vpd->lock))
  220. return -EINTR;
  221. ret = pci_vpd_pci22_wait(dev);
  222. if (ret < 0)
  223. goto out;
  224. while (pos < end) {
  225. u32 val;
  226. unsigned int i, skip;
  227. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  228. pos & ~3);
  229. if (ret < 0)
  230. break;
  231. vpd->busy = true;
  232. vpd->flag = PCI_VPD_ADDR_F;
  233. ret = pci_vpd_pci22_wait(dev);
  234. if (ret < 0)
  235. break;
  236. ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
  237. if (ret < 0)
  238. break;
  239. skip = pos & 3;
  240. for (i = 0; i < sizeof(u32); i++) {
  241. if (i >= skip) {
  242. *buf++ = val;
  243. if (++pos == end)
  244. break;
  245. }
  246. val >>= 8;
  247. }
  248. }
  249. out:
  250. mutex_unlock(&vpd->lock);
  251. return ret ? ret : count;
  252. }
  253. static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
  254. const void *arg)
  255. {
  256. struct pci_vpd_pci22 *vpd =
  257. container_of(dev->vpd, struct pci_vpd_pci22, base);
  258. const u8 *buf = arg;
  259. loff_t end = pos + count;
  260. int ret = 0;
  261. if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
  262. return -EINVAL;
  263. if (mutex_lock_killable(&vpd->lock))
  264. return -EINTR;
  265. ret = pci_vpd_pci22_wait(dev);
  266. if (ret < 0)
  267. goto out;
  268. while (pos < end) {
  269. u32 val;
  270. val = *buf++;
  271. val |= *buf++ << 8;
  272. val |= *buf++ << 16;
  273. val |= *buf++ << 24;
  274. ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
  275. if (ret < 0)
  276. break;
  277. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  278. pos | PCI_VPD_ADDR_F);
  279. if (ret < 0)
  280. break;
  281. vpd->busy = true;
  282. vpd->flag = 0;
  283. ret = pci_vpd_pci22_wait(dev);
  284. pos += sizeof(u32);
  285. }
  286. out:
  287. mutex_unlock(&vpd->lock);
  288. return ret ? ret : count;
  289. }
  290. static void pci_vpd_pci22_release(struct pci_dev *dev)
  291. {
  292. kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
  293. }
  294. static const struct pci_vpd_ops pci_vpd_pci22_ops = {
  295. .read = pci_vpd_pci22_read,
  296. .write = pci_vpd_pci22_write,
  297. .release = pci_vpd_pci22_release,
  298. };
  299. int pci_vpd_pci22_init(struct pci_dev *dev)
  300. {
  301. struct pci_vpd_pci22 *vpd;
  302. u8 cap;
  303. cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
  304. if (!cap)
  305. return -ENODEV;
  306. vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
  307. if (!vpd)
  308. return -ENOMEM;
  309. vpd->base.len = PCI_VPD_PCI22_SIZE;
  310. vpd->base.ops = &pci_vpd_pci22_ops;
  311. mutex_init(&vpd->lock);
  312. vpd->cap = cap;
  313. vpd->busy = false;
  314. dev->vpd = &vpd->base;
  315. return 0;
  316. }
  317. /**
  318. * pci_vpd_truncate - Set available Vital Product Data size
  319. * @dev: pci device struct
  320. * @size: available memory in bytes
  321. *
  322. * Adjust size of available VPD area.
  323. */
  324. int pci_vpd_truncate(struct pci_dev *dev, size_t size)
  325. {
  326. if (!dev->vpd)
  327. return -EINVAL;
  328. /* limited by the access method */
  329. if (size > dev->vpd->len)
  330. return -EINVAL;
  331. dev->vpd->len = size;
  332. if (dev->vpd->attr)
  333. dev->vpd->attr->size = size;
  334. return 0;
  335. }
  336. EXPORT_SYMBOL(pci_vpd_truncate);
  337. /**
  338. * pci_block_user_cfg_access - Block userspace PCI config reads/writes
  339. * @dev: pci device struct
  340. *
  341. * When user access is blocked, any reads or writes to config space will
  342. * sleep until access is unblocked again. We don't allow nesting of
  343. * block/unblock calls.
  344. */
  345. void pci_block_user_cfg_access(struct pci_dev *dev)
  346. {
  347. unsigned long flags;
  348. int was_blocked;
  349. raw_spin_lock_irqsave(&pci_lock, flags);
  350. was_blocked = dev->block_ucfg_access;
  351. dev->block_ucfg_access = 1;
  352. raw_spin_unlock_irqrestore(&pci_lock, flags);
  353. /* If we BUG() inside the pci_lock, we're guaranteed to hose
  354. * the machine */
  355. BUG_ON(was_blocked);
  356. }
  357. EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
  358. /**
  359. * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
  360. * @dev: pci device struct
  361. *
  362. * This function allows userspace PCI config accesses to resume.
  363. */
  364. void pci_unblock_user_cfg_access(struct pci_dev *dev)
  365. {
  366. unsigned long flags;
  367. raw_spin_lock_irqsave(&pci_lock, flags);
  368. /* This indicates a problem in the caller, but we don't need
  369. * to kill them, unlike a double-block above. */
  370. WARN_ON(!dev->block_ucfg_access);
  371. dev->block_ucfg_access = 0;
  372. wake_up_all(&pci_ucfg_wait);
  373. raw_spin_unlock_irqrestore(&pci_lock, flags);
  374. }
  375. EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);