dm_common.c 41 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "dm_common.h"
  30. struct dig_t dm_digtable;
  31. static struct ps_t dm_pstable;
  32. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  33. 0x7f8001fe,
  34. 0x788001e2,
  35. 0x71c001c7,
  36. 0x6b8001ae,
  37. 0x65400195,
  38. 0x5fc0017f,
  39. 0x5a400169,
  40. 0x55400155,
  41. 0x50800142,
  42. 0x4c000130,
  43. 0x47c0011f,
  44. 0x43c0010f,
  45. 0x40000100,
  46. 0x3c8000f2,
  47. 0x390000e4,
  48. 0x35c000d7,
  49. 0x32c000cb,
  50. 0x300000c0,
  51. 0x2d4000b5,
  52. 0x2ac000ab,
  53. 0x288000a2,
  54. 0x26000098,
  55. 0x24000090,
  56. 0x22000088,
  57. 0x20000080,
  58. 0x1e400079,
  59. 0x1c800072,
  60. 0x1b00006c,
  61. 0x19800066,
  62. 0x18000060,
  63. 0x16c0005b,
  64. 0x15800056,
  65. 0x14400051,
  66. 0x1300004c,
  67. 0x12000048,
  68. 0x11000044,
  69. 0x10000040,
  70. };
  71. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  72. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  73. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  74. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  75. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  76. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  77. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  78. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  79. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  80. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  81. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  82. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  83. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  84. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  85. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  86. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  87. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  88. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  89. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  90. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  91. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  92. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  93. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  94. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  95. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  96. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  97. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  98. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  99. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  100. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  101. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  102. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  103. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  104. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  105. };
  106. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  107. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  108. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  109. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  110. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  111. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  112. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  113. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  114. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  115. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  116. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  117. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  118. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  119. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  120. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  121. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  122. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  123. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  124. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  125. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  126. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  127. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  128. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  129. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  130. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  131. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  132. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  133. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  134. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  135. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  136. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  137. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  138. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  139. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  140. };
  141. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  142. {
  143. dm_digtable.dig_enable_flag = true;
  144. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  145. dm_digtable.cur_igvalue = 0x20;
  146. dm_digtable.pre_igvalue = 0x0;
  147. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  148. dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
  149. dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  150. dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  151. dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  152. dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  153. dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  154. dm_digtable.rx_gain_range_max = DM_DIG_MAX;
  155. dm_digtable.rx_gain_range_min = DM_DIG_MIN;
  156. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  157. dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  158. dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  159. dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
  160. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  161. }
  162. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  163. {
  164. struct rtl_priv *rtlpriv = rtl_priv(hw);
  165. long rssi_val_min = 0;
  166. if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  167. (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
  168. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  169. rssi_val_min =
  170. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  171. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  172. rtlpriv->dm.undecorated_smoothed_pwdb :
  173. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  174. else
  175. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  176. } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
  177. dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  178. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  179. } else if (dm_digtable.curmultista_connectstate ==
  180. DIG_MULTISTA_CONNECT) {
  181. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  182. }
  183. return (u8) rssi_val_min;
  184. }
  185. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  186. {
  187. u32 ret_value;
  188. struct rtl_priv *rtlpriv = rtl_priv(hw);
  189. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  190. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  191. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  192. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  193. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  194. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  195. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  196. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  197. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  198. falsealm_cnt->cnt_rate_illegal +
  199. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  200. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  201. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  202. falsealm_cnt->cnt_cck_fail = ret_value;
  203. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  204. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  205. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  206. falsealm_cnt->cnt_rate_illegal +
  207. falsealm_cnt->cnt_crc8_fail +
  208. falsealm_cnt->cnt_mcs_fail +
  209. falsealm_cnt->cnt_cck_fail);
  210. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  211. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  212. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  213. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  214. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  215. ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
  216. "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  217. falsealm_cnt->cnt_parity_fail,
  218. falsealm_cnt->cnt_rate_illegal,
  219. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
  220. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  221. ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  222. falsealm_cnt->cnt_ofdm_fail,
  223. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
  224. }
  225. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  226. {
  227. struct rtl_priv *rtlpriv = rtl_priv(hw);
  228. u8 value_igi = dm_digtable.cur_igvalue;
  229. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  230. value_igi--;
  231. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  232. value_igi += 0;
  233. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  234. value_igi++;
  235. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  236. value_igi += 2;
  237. if (value_igi > DM_DIG_FA_UPPER)
  238. value_igi = DM_DIG_FA_UPPER;
  239. else if (value_igi < DM_DIG_FA_LOWER)
  240. value_igi = DM_DIG_FA_LOWER;
  241. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  242. value_igi = 0x32;
  243. dm_digtable.cur_igvalue = value_igi;
  244. rtl92c_dm_write_dig(hw);
  245. }
  246. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  247. {
  248. struct rtl_priv *rtlpriv = rtl_priv(hw);
  249. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
  250. if ((dm_digtable.backoff_val - 2) <
  251. dm_digtable.backoff_val_range_min)
  252. dm_digtable.backoff_val =
  253. dm_digtable.backoff_val_range_min;
  254. else
  255. dm_digtable.backoff_val -= 2;
  256. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
  257. if ((dm_digtable.backoff_val + 2) >
  258. dm_digtable.backoff_val_range_max)
  259. dm_digtable.backoff_val =
  260. dm_digtable.backoff_val_range_max;
  261. else
  262. dm_digtable.backoff_val += 2;
  263. }
  264. if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
  265. dm_digtable.rx_gain_range_max)
  266. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
  267. else if ((dm_digtable.rssi_val_min + 10 -
  268. dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
  269. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
  270. else
  271. dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
  272. dm_digtable.backoff_val;
  273. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  274. ("rssi_val_min = %x backoff_val %x\n",
  275. dm_digtable.rssi_val_min, dm_digtable.backoff_val));
  276. rtl92c_dm_write_dig(hw);
  277. }
  278. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  279. {
  280. static u8 binitialized; /* initialized to false */
  281. struct rtl_priv *rtlpriv = rtl_priv(hw);
  282. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  283. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  284. bool multi_sta = false;
  285. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  286. multi_sta = true;
  287. if ((multi_sta == false) || (dm_digtable.cursta_connectctate !=
  288. DIG_STA_DISCONNECT)) {
  289. binitialized = false;
  290. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  291. return;
  292. } else if (binitialized == false) {
  293. binitialized = true;
  294. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  295. dm_digtable.cur_igvalue = 0x20;
  296. rtl92c_dm_write_dig(hw);
  297. }
  298. if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  299. if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
  300. (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  301. if (dm_digtable.dig_ext_port_stage ==
  302. DIG_EXT_PORT_STAGE_2) {
  303. dm_digtable.cur_igvalue = 0x20;
  304. rtl92c_dm_write_dig(hw);
  305. }
  306. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  307. } else if (rssi_strength > dm_digtable.rssi_highthresh) {
  308. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  309. rtl92c_dm_ctrl_initgain_by_fa(hw);
  310. }
  311. } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  312. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  313. dm_digtable.cur_igvalue = 0x20;
  314. rtl92c_dm_write_dig(hw);
  315. }
  316. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  317. ("curmultista_connectstate = "
  318. "%x dig_ext_port_stage %x\n",
  319. dm_digtable.curmultista_connectstate,
  320. dm_digtable.dig_ext_port_stage));
  321. }
  322. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  323. {
  324. struct rtl_priv *rtlpriv = rtl_priv(hw);
  325. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  326. ("presta_connectstate = %x,"
  327. " cursta_connectctate = %x\n",
  328. dm_digtable.presta_connectstate,
  329. dm_digtable.cursta_connectctate));
  330. if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
  331. || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
  332. || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  333. if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  334. dm_digtable.rssi_val_min =
  335. rtl92c_dm_initial_gain_min_pwdb(hw);
  336. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  337. }
  338. } else {
  339. dm_digtable.rssi_val_min = 0;
  340. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  341. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  342. dm_digtable.cur_igvalue = 0x20;
  343. dm_digtable.pre_igvalue = 0;
  344. rtl92c_dm_write_dig(hw);
  345. }
  346. }
  347. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  348. {
  349. struct rtl_priv *rtlpriv = rtl_priv(hw);
  350. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  351. if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  352. dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  353. if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  354. if (dm_digtable.rssi_val_min <= 25)
  355. dm_digtable.cur_cck_pd_state =
  356. CCK_PD_STAGE_LowRssi;
  357. else
  358. dm_digtable.cur_cck_pd_state =
  359. CCK_PD_STAGE_HighRssi;
  360. } else {
  361. if (dm_digtable.rssi_val_min <= 20)
  362. dm_digtable.cur_cck_pd_state =
  363. CCK_PD_STAGE_LowRssi;
  364. else
  365. dm_digtable.cur_cck_pd_state =
  366. CCK_PD_STAGE_HighRssi;
  367. }
  368. } else {
  369. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  370. }
  371. if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
  372. if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  373. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  374. dm_digtable.cur_cck_fa_state =
  375. CCK_FA_STAGE_High;
  376. else
  377. dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
  378. if (dm_digtable.pre_cck_fa_state !=
  379. dm_digtable.cur_cck_fa_state) {
  380. if (dm_digtable.cur_cck_fa_state ==
  381. CCK_FA_STAGE_Low)
  382. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  383. 0x83);
  384. else
  385. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  386. 0xcd);
  387. dm_digtable.pre_cck_fa_state =
  388. dm_digtable.cur_cck_fa_state;
  389. }
  390. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  391. if (IS_92C_SERIAL(rtlhal->version))
  392. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  393. MASKBYTE2, 0xd7);
  394. } else {
  395. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  396. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  397. if (IS_92C_SERIAL(rtlhal->version))
  398. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  399. MASKBYTE2, 0xd3);
  400. }
  401. dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
  402. }
  403. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  404. ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
  405. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  406. ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
  407. }
  408. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  409. {
  410. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  411. if (mac->act_scanning == true)
  412. return;
  413. if ((mac->link_state > MAC80211_NOLINK) &&
  414. (mac->link_state < MAC80211_LINKED))
  415. dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
  416. else if (mac->link_state >= MAC80211_LINKED)
  417. dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
  418. else
  419. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  420. rtl92c_dm_initial_gain_sta(hw);
  421. rtl92c_dm_initial_gain_multi_sta(hw);
  422. rtl92c_dm_cck_packet_detection_thresh(hw);
  423. dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
  424. }
  425. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  426. {
  427. struct rtl_priv *rtlpriv = rtl_priv(hw);
  428. if (rtlpriv->dm.dm_initialgain_enable == false)
  429. return;
  430. if (dm_digtable.dig_enable_flag == false)
  431. return;
  432. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  433. }
  434. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  435. {
  436. struct rtl_priv *rtlpriv = rtl_priv(hw);
  437. rtlpriv->dm.dynamic_txpower_enable = false;
  438. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  439. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  440. }
  441. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  442. {
  443. struct rtl_priv *rtlpriv = rtl_priv(hw);
  444. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  445. ("cur_igvalue = 0x%x, "
  446. "pre_igvalue = 0x%x, backoff_val = %d\n",
  447. dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
  448. dm_digtable.backoff_val));
  449. if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
  450. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  451. dm_digtable.cur_igvalue);
  452. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  453. dm_digtable.cur_igvalue);
  454. dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
  455. }
  456. }
  457. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  458. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  459. {
  460. struct rtl_priv *rtlpriv = rtl_priv(hw);
  461. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  462. u8 h2c_parameter[3] = { 0 };
  463. return;
  464. if (tmpentry_max_pwdb != 0) {
  465. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  466. tmpentry_max_pwdb;
  467. } else {
  468. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  469. }
  470. if (tmpentry_min_pwdb != 0xff) {
  471. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  472. tmpentry_min_pwdb;
  473. } else {
  474. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  475. }
  476. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  477. h2c_parameter[0] = 0;
  478. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  479. }
  480. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  481. {
  482. struct rtl_priv *rtlpriv = rtl_priv(hw);
  483. rtlpriv->dm.current_turbo_edca = false;
  484. rtlpriv->dm.is_any_nonbepkts = false;
  485. rtlpriv->dm.is_cur_rdlstate = false;
  486. }
  487. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  488. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  489. {
  490. struct rtl_priv *rtlpriv = rtl_priv(hw);
  491. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  492. static u64 last_txok_cnt;
  493. static u64 last_rxok_cnt;
  494. u64 cur_txok_cnt;
  495. u64 cur_rxok_cnt;
  496. u32 edca_be_ul = 0x5ea42b;
  497. u32 edca_be_dl = 0x5ea42b;
  498. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  499. goto dm_checkedcaturbo_exit;
  500. if (mac->link_state != MAC80211_LINKED) {
  501. rtlpriv->dm.current_turbo_edca = false;
  502. return;
  503. }
  504. if (!mac->ht_enable) { /*FIX MERGE */
  505. if (!(edca_be_ul & 0xffff0000))
  506. edca_be_ul |= 0x005e0000;
  507. if (!(edca_be_dl & 0xffff0000))
  508. edca_be_dl |= 0x005e0000;
  509. }
  510. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  511. (!rtlpriv->dm.disable_framebursting)) {
  512. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  513. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  514. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  515. if (!rtlpriv->dm.is_cur_rdlstate ||
  516. !rtlpriv->dm.current_turbo_edca) {
  517. rtl_write_dword(rtlpriv,
  518. REG_EDCA_BE_PARAM,
  519. edca_be_dl);
  520. rtlpriv->dm.is_cur_rdlstate = true;
  521. }
  522. } else {
  523. if (rtlpriv->dm.is_cur_rdlstate ||
  524. !rtlpriv->dm.current_turbo_edca) {
  525. rtl_write_dword(rtlpriv,
  526. REG_EDCA_BE_PARAM,
  527. edca_be_ul);
  528. rtlpriv->dm.is_cur_rdlstate = false;
  529. }
  530. }
  531. rtlpriv->dm.current_turbo_edca = true;
  532. } else {
  533. if (rtlpriv->dm.current_turbo_edca) {
  534. u8 tmp = AC0_BE;
  535. rtlpriv->cfg->ops->set_hw_reg(hw,
  536. HW_VAR_AC_PARAM,
  537. (u8 *) (&tmp));
  538. rtlpriv->dm.current_turbo_edca = false;
  539. }
  540. }
  541. dm_checkedcaturbo_exit:
  542. rtlpriv->dm.is_any_nonbepkts = false;
  543. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  544. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  545. }
  546. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  547. *hw)
  548. {
  549. struct rtl_priv *rtlpriv = rtl_priv(hw);
  550. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  551. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  552. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  553. u8 thermalvalue, delta, delta_lck, delta_iqk;
  554. long ele_a, ele_d, temp_cck, val_x, value32;
  555. long val_y, ele_c;
  556. u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
  557. int i;
  558. bool is2t = IS_92C_SERIAL(rtlhal->version);
  559. u8 txpwr_level[2] = {0, 0};
  560. u8 ofdm_min_index = 6, rf;
  561. rtlpriv->dm.txpower_trackingInit = true;
  562. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  563. ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
  564. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  565. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  566. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  567. "eeprom_thermalmeter 0x%x\n",
  568. thermalvalue, rtlpriv->dm.thermalvalue,
  569. rtlefuse->eeprom_thermalmeter));
  570. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  571. rtlefuse->eeprom_thermalmeter));
  572. if (is2t)
  573. rf = 2;
  574. else
  575. rf = 1;
  576. if (thermalvalue) {
  577. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  578. MASKDWORD) & MASKOFDM_D;
  579. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  580. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  581. ofdm_index_old[0] = (u8) i;
  582. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  583. ("Initial pathA ele_d reg0x%x = 0x%lx, "
  584. "ofdm_index=0x%x\n",
  585. ROFDM0_XATXIQIMBALANCE,
  586. ele_d, ofdm_index_old[0]));
  587. break;
  588. }
  589. }
  590. if (is2t) {
  591. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  592. MASKDWORD) & MASKOFDM_D;
  593. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  594. if (ele_d == (ofdmswing_table[i] &
  595. MASKOFDM_D)) {
  596. ofdm_index_old[1] = (u8) i;
  597. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  598. DBG_LOUD,
  599. ("Initial pathB ele_d reg0x%x = "
  600. "0x%lx, ofdm_index=0x%x\n",
  601. ROFDM0_XBTXIQIMBALANCE, ele_d,
  602. ofdm_index_old[1]));
  603. break;
  604. }
  605. }
  606. }
  607. temp_cck =
  608. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  609. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  610. if (rtlpriv->dm.cck_inch14) {
  611. if (memcmp((void *)&temp_cck,
  612. (void *)&cckswing_table_ch14[i][2],
  613. 4) == 0) {
  614. cck_index_old = (u8) i;
  615. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  616. DBG_LOUD,
  617. ("Initial reg0x%x = 0x%lx, "
  618. "cck_index=0x%x, ch 14 %d\n",
  619. RCCK0_TXFILTER2, temp_cck,
  620. cck_index_old,
  621. rtlpriv->dm.cck_inch14));
  622. break;
  623. }
  624. } else {
  625. if (memcmp((void *)&temp_cck,
  626. (void *)
  627. &cckswing_table_ch1ch13[i][2],
  628. 4) == 0) {
  629. cck_index_old = (u8) i;
  630. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  631. DBG_LOUD,
  632. ("Initial reg0x%x = 0x%lx, "
  633. "cck_index=0x%x, ch14 %d\n",
  634. RCCK0_TXFILTER2, temp_cck,
  635. cck_index_old,
  636. rtlpriv->dm.cck_inch14));
  637. break;
  638. }
  639. }
  640. }
  641. if (!rtlpriv->dm.thermalvalue) {
  642. rtlpriv->dm.thermalvalue =
  643. rtlefuse->eeprom_thermalmeter;
  644. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  645. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  646. for (i = 0; i < rf; i++)
  647. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  648. rtlpriv->dm.cck_index = cck_index_old;
  649. }
  650. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  651. (thermalvalue - rtlpriv->dm.thermalvalue) :
  652. (rtlpriv->dm.thermalvalue - thermalvalue);
  653. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  654. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  655. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  656. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  657. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  658. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  659. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  660. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  661. "eeprom_thermalmeter 0x%x delta 0x%x "
  662. "delta_lck 0x%x delta_iqk 0x%x\n",
  663. thermalvalue, rtlpriv->dm.thermalvalue,
  664. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  665. delta_iqk));
  666. if (delta_lck > 1) {
  667. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  668. rtl92c_phy_lc_calibrate(hw);
  669. }
  670. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  671. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  672. for (i = 0; i < rf; i++)
  673. rtlpriv->dm.ofdm_index[i] -= delta;
  674. rtlpriv->dm.cck_index -= delta;
  675. } else {
  676. for (i = 0; i < rf; i++)
  677. rtlpriv->dm.ofdm_index[i] += delta;
  678. rtlpriv->dm.cck_index += delta;
  679. }
  680. if (is2t) {
  681. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  682. ("temp OFDM_A_index=0x%x, "
  683. "OFDM_B_index=0x%x,"
  684. "cck_index=0x%x\n",
  685. rtlpriv->dm.ofdm_index[0],
  686. rtlpriv->dm.ofdm_index[1],
  687. rtlpriv->dm.cck_index));
  688. } else {
  689. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  690. ("temp OFDM_A_index=0x%x,"
  691. "cck_index=0x%x\n",
  692. rtlpriv->dm.ofdm_index[0],
  693. rtlpriv->dm.cck_index));
  694. }
  695. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  696. for (i = 0; i < rf; i++)
  697. ofdm_index[i] =
  698. rtlpriv->dm.ofdm_index[i]
  699. + 1;
  700. cck_index = rtlpriv->dm.cck_index + 1;
  701. } else {
  702. for (i = 0; i < rf; i++)
  703. ofdm_index[i] =
  704. rtlpriv->dm.ofdm_index[i];
  705. cck_index = rtlpriv->dm.cck_index;
  706. }
  707. for (i = 0; i < rf; i++) {
  708. if (txpwr_level[i] >= 0 &&
  709. txpwr_level[i] <= 26) {
  710. if (thermalvalue >
  711. rtlefuse->eeprom_thermalmeter) {
  712. if (delta < 5)
  713. ofdm_index[i] -= 1;
  714. else
  715. ofdm_index[i] -= 2;
  716. } else if (delta > 5 && thermalvalue <
  717. rtlefuse->
  718. eeprom_thermalmeter) {
  719. ofdm_index[i] += 1;
  720. }
  721. } else if (txpwr_level[i] >= 27 &&
  722. txpwr_level[i] <= 32
  723. && thermalvalue >
  724. rtlefuse->eeprom_thermalmeter) {
  725. if (delta < 5)
  726. ofdm_index[i] -= 1;
  727. else
  728. ofdm_index[i] -= 2;
  729. } else if (txpwr_level[i] >= 32 &&
  730. txpwr_level[i] <= 38 &&
  731. thermalvalue >
  732. rtlefuse->eeprom_thermalmeter
  733. && delta > 5) {
  734. ofdm_index[i] -= 1;
  735. }
  736. }
  737. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  738. if (thermalvalue >
  739. rtlefuse->eeprom_thermalmeter) {
  740. if (delta < 5)
  741. cck_index -= 1;
  742. else
  743. cck_index -= 2;
  744. } else if (delta > 5 && thermalvalue <
  745. rtlefuse->eeprom_thermalmeter) {
  746. cck_index += 1;
  747. }
  748. } else if (txpwr_level[i] >= 27 &&
  749. txpwr_level[i] <= 32 &&
  750. thermalvalue >
  751. rtlefuse->eeprom_thermalmeter) {
  752. if (delta < 5)
  753. cck_index -= 1;
  754. else
  755. cck_index -= 2;
  756. } else if (txpwr_level[i] >= 32 &&
  757. txpwr_level[i] <= 38 &&
  758. thermalvalue > rtlefuse->eeprom_thermalmeter
  759. && delta > 5) {
  760. cck_index -= 1;
  761. }
  762. for (i = 0; i < rf; i++) {
  763. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  764. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  765. else if (ofdm_index[i] < ofdm_min_index)
  766. ofdm_index[i] = ofdm_min_index;
  767. }
  768. if (cck_index > CCK_TABLE_SIZE - 1)
  769. cck_index = CCK_TABLE_SIZE - 1;
  770. else if (cck_index < 0)
  771. cck_index = 0;
  772. if (is2t) {
  773. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  774. ("new OFDM_A_index=0x%x, "
  775. "OFDM_B_index=0x%x,"
  776. "cck_index=0x%x\n",
  777. ofdm_index[0], ofdm_index[1],
  778. cck_index));
  779. } else {
  780. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  781. ("new OFDM_A_index=0x%x,"
  782. "cck_index=0x%x\n",
  783. ofdm_index[0], cck_index));
  784. }
  785. }
  786. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  787. ele_d =
  788. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  789. val_x = rtlphy->reg_e94;
  790. val_y = rtlphy->reg_e9c;
  791. if (val_x != 0) {
  792. if ((val_x & 0x00000200) != 0)
  793. val_x = val_x | 0xFFFFFC00;
  794. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  795. if ((val_y & 0x00000200) != 0)
  796. val_y = val_y | 0xFFFFFC00;
  797. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  798. value32 = (ele_d << 22) |
  799. ((ele_c & 0x3F) << 16) | ele_a;
  800. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  801. MASKDWORD, value32);
  802. value32 = (ele_c & 0x000003C0) >> 6;
  803. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  804. value32);
  805. value32 = ((val_x * ele_d) >> 7) & 0x01;
  806. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  807. BIT(31), value32);
  808. value32 = ((val_y * ele_d) >> 7) & 0x01;
  809. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  810. BIT(29), value32);
  811. } else {
  812. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  813. MASKDWORD,
  814. ofdmswing_table[ofdm_index[0]]);
  815. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  816. 0x00);
  817. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  818. BIT(31) | BIT(29), 0x00);
  819. }
  820. if (!rtlpriv->dm.cck_inch14) {
  821. rtl_write_byte(rtlpriv, 0xa22,
  822. cckswing_table_ch1ch13[cck_index]
  823. [0]);
  824. rtl_write_byte(rtlpriv, 0xa23,
  825. cckswing_table_ch1ch13[cck_index]
  826. [1]);
  827. rtl_write_byte(rtlpriv, 0xa24,
  828. cckswing_table_ch1ch13[cck_index]
  829. [2]);
  830. rtl_write_byte(rtlpriv, 0xa25,
  831. cckswing_table_ch1ch13[cck_index]
  832. [3]);
  833. rtl_write_byte(rtlpriv, 0xa26,
  834. cckswing_table_ch1ch13[cck_index]
  835. [4]);
  836. rtl_write_byte(rtlpriv, 0xa27,
  837. cckswing_table_ch1ch13[cck_index]
  838. [5]);
  839. rtl_write_byte(rtlpriv, 0xa28,
  840. cckswing_table_ch1ch13[cck_index]
  841. [6]);
  842. rtl_write_byte(rtlpriv, 0xa29,
  843. cckswing_table_ch1ch13[cck_index]
  844. [7]);
  845. } else {
  846. rtl_write_byte(rtlpriv, 0xa22,
  847. cckswing_table_ch14[cck_index]
  848. [0]);
  849. rtl_write_byte(rtlpriv, 0xa23,
  850. cckswing_table_ch14[cck_index]
  851. [1]);
  852. rtl_write_byte(rtlpriv, 0xa24,
  853. cckswing_table_ch14[cck_index]
  854. [2]);
  855. rtl_write_byte(rtlpriv, 0xa25,
  856. cckswing_table_ch14[cck_index]
  857. [3]);
  858. rtl_write_byte(rtlpriv, 0xa26,
  859. cckswing_table_ch14[cck_index]
  860. [4]);
  861. rtl_write_byte(rtlpriv, 0xa27,
  862. cckswing_table_ch14[cck_index]
  863. [5]);
  864. rtl_write_byte(rtlpriv, 0xa28,
  865. cckswing_table_ch14[cck_index]
  866. [6]);
  867. rtl_write_byte(rtlpriv, 0xa29,
  868. cckswing_table_ch14[cck_index]
  869. [7]);
  870. }
  871. if (is2t) {
  872. ele_d = (ofdmswing_table[ofdm_index[1]] &
  873. 0xFFC00000) >> 22;
  874. val_x = rtlphy->reg_eb4;
  875. val_y = rtlphy->reg_ebc;
  876. if (val_x != 0) {
  877. if ((val_x & 0x00000200) != 0)
  878. val_x = val_x | 0xFFFFFC00;
  879. ele_a = ((val_x * ele_d) >> 8) &
  880. 0x000003FF;
  881. if ((val_y & 0x00000200) != 0)
  882. val_y = val_y | 0xFFFFFC00;
  883. ele_c = ((val_y * ele_d) >> 8) &
  884. 0x00003FF;
  885. value32 = (ele_d << 22) |
  886. ((ele_c & 0x3F) << 16) | ele_a;
  887. rtl_set_bbreg(hw,
  888. ROFDM0_XBTXIQIMBALANCE,
  889. MASKDWORD, value32);
  890. value32 = (ele_c & 0x000003C0) >> 6;
  891. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  892. MASKH4BITS, value32);
  893. value32 = ((val_x * ele_d) >> 7) & 0x01;
  894. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  895. BIT(27), value32);
  896. value32 = ((val_y * ele_d) >> 7) & 0x01;
  897. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  898. BIT(25), value32);
  899. } else {
  900. rtl_set_bbreg(hw,
  901. ROFDM0_XBTXIQIMBALANCE,
  902. MASKDWORD,
  903. ofdmswing_table[ofdm_index
  904. [1]]);
  905. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  906. MASKH4BITS, 0x00);
  907. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  908. BIT(27) | BIT(25), 0x00);
  909. }
  910. }
  911. }
  912. if (delta_iqk > 3) {
  913. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  914. rtl92c_phy_iq_calibrate(hw, false);
  915. }
  916. if (rtlpriv->dm.txpower_track_control)
  917. rtlpriv->dm.thermalvalue = thermalvalue;
  918. }
  919. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
  920. }
  921. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  922. struct ieee80211_hw *hw)
  923. {
  924. struct rtl_priv *rtlpriv = rtl_priv(hw);
  925. rtlpriv->dm.txpower_tracking = true;
  926. rtlpriv->dm.txpower_trackingInit = false;
  927. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  928. ("pMgntInfo->txpower_tracking = %d\n",
  929. rtlpriv->dm.txpower_tracking));
  930. }
  931. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  932. {
  933. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  934. }
  935. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  936. {
  937. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  938. }
  939. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  940. struct ieee80211_hw *hw)
  941. {
  942. struct rtl_priv *rtlpriv = rtl_priv(hw);
  943. static u8 tm_trigger;
  944. if (!rtlpriv->dm.txpower_tracking)
  945. return;
  946. if (!tm_trigger) {
  947. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  948. 0x60);
  949. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  950. ("Trigger 92S Thermal Meter!!\n"));
  951. tm_trigger = 1;
  952. return;
  953. } else {
  954. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  955. ("Schedule TxPowerTracking direct call!!\n"));
  956. rtl92c_dm_txpower_tracking_directcall(hw);
  957. tm_trigger = 0;
  958. }
  959. }
  960. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  961. {
  962. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  963. }
  964. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  965. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  966. {
  967. struct rtl_priv *rtlpriv = rtl_priv(hw);
  968. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  969. p_ra->ratr_state = DM_RATR_STA_INIT;
  970. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  971. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  972. rtlpriv->dm.useramask = true;
  973. else
  974. rtlpriv->dm.useramask = false;
  975. }
  976. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  977. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  978. {
  979. struct rtl_priv *rtlpriv = rtl_priv(hw);
  980. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  981. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  982. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  983. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  984. if (is_hal_stop(rtlhal)) {
  985. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  986. ("<---- driver is going to unload\n"));
  987. return;
  988. }
  989. if (!rtlpriv->dm.useramask) {
  990. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  991. ("<---- driver does not control rate adaptive mask\n"));
  992. return;
  993. }
  994. if (mac->link_state == MAC80211_LINKED) {
  995. switch (p_ra->pre_ratr_state) {
  996. case DM_RATR_STA_HIGH:
  997. high_rssithresh_for_ra = 50;
  998. low_rssithresh_for_ra = 20;
  999. break;
  1000. case DM_RATR_STA_MIDDLE:
  1001. high_rssithresh_for_ra = 55;
  1002. low_rssithresh_for_ra = 20;
  1003. break;
  1004. case DM_RATR_STA_LOW:
  1005. high_rssithresh_for_ra = 50;
  1006. low_rssithresh_for_ra = 25;
  1007. break;
  1008. default:
  1009. high_rssithresh_for_ra = 50;
  1010. low_rssithresh_for_ra = 20;
  1011. break;
  1012. }
  1013. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1014. (long)high_rssithresh_for_ra)
  1015. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1016. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1017. (long)low_rssithresh_for_ra)
  1018. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1019. else
  1020. p_ra->ratr_state = DM_RATR_STA_LOW;
  1021. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1022. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1023. ("RSSI = %ld\n",
  1024. rtlpriv->dm.undecorated_smoothed_pwdb));
  1025. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1026. ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
  1027. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1028. ("PreState = %d, CurState = %d\n",
  1029. p_ra->pre_ratr_state, p_ra->ratr_state));
  1030. rtlpriv->cfg->ops->update_rate_mask(hw,
  1031. p_ra->ratr_state);
  1032. p_ra->pre_ratr_state = p_ra->ratr_state;
  1033. }
  1034. }
  1035. }
  1036. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1037. {
  1038. dm_pstable.pre_ccastate = CCA_MAX;
  1039. dm_pstable.cur_ccasate = CCA_MAX;
  1040. dm_pstable.pre_rfstate = RF_MAX;
  1041. dm_pstable.cur_rfstate = RF_MAX;
  1042. dm_pstable.rssi_val_min = 0;
  1043. }
  1044. static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
  1045. {
  1046. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1047. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1048. if (dm_pstable.rssi_val_min != 0) {
  1049. if (dm_pstable.pre_ccastate == CCA_2R) {
  1050. if (dm_pstable.rssi_val_min >= 35)
  1051. dm_pstable.cur_ccasate = CCA_1R;
  1052. else
  1053. dm_pstable.cur_ccasate = CCA_2R;
  1054. } else {
  1055. if (dm_pstable.rssi_val_min <= 30)
  1056. dm_pstable.cur_ccasate = CCA_2R;
  1057. else
  1058. dm_pstable.cur_ccasate = CCA_1R;
  1059. }
  1060. } else {
  1061. dm_pstable.cur_ccasate = CCA_MAX;
  1062. }
  1063. if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
  1064. if (dm_pstable.cur_ccasate == CCA_1R) {
  1065. if (get_rf_type(rtlphy) == RF_2T2R) {
  1066. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1067. MASKBYTE0, 0x13);
  1068. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
  1069. } else {
  1070. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1071. MASKBYTE0, 0x23);
  1072. rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
  1073. }
  1074. } else {
  1075. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
  1076. 0x33);
  1077. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
  1078. }
  1079. dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
  1080. }
  1081. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
  1082. (dm_pstable.cur_ccasate ==
  1083. 0) ? "1RCCA" : "2RCCA"));
  1084. }
  1085. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1086. {
  1087. static u8 initialize;
  1088. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1089. if (initialize == 0) {
  1090. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1091. MASKDWORD) & 0x1CC000) >> 14;
  1092. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1093. MASKDWORD) & BIT(3)) >> 3;
  1094. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1095. MASKDWORD) & 0xFF000000) >> 24;
  1096. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1097. initialize = 1;
  1098. }
  1099. if (!bforce_in_normal) {
  1100. if (dm_pstable.rssi_val_min != 0) {
  1101. if (dm_pstable.pre_rfstate == RF_NORMAL) {
  1102. if (dm_pstable.rssi_val_min >= 30)
  1103. dm_pstable.cur_rfstate = RF_SAVE;
  1104. else
  1105. dm_pstable.cur_rfstate = RF_NORMAL;
  1106. } else {
  1107. if (dm_pstable.rssi_val_min <= 25)
  1108. dm_pstable.cur_rfstate = RF_NORMAL;
  1109. else
  1110. dm_pstable.cur_rfstate = RF_SAVE;
  1111. }
  1112. } else {
  1113. dm_pstable.cur_rfstate = RF_MAX;
  1114. }
  1115. } else {
  1116. dm_pstable.cur_rfstate = RF_NORMAL;
  1117. }
  1118. if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
  1119. if (dm_pstable.cur_rfstate == RF_SAVE) {
  1120. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1121. 0x1C0000, 0x2);
  1122. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1123. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1124. 0xFF000000, 0x63);
  1125. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1126. 0xC000, 0x2);
  1127. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1128. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1129. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1130. } else {
  1131. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1132. 0x1CC000, reg_874);
  1133. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1134. reg_c70);
  1135. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1136. reg_85c);
  1137. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1138. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1139. }
  1140. dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
  1141. }
  1142. }
  1143. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1144. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1145. {
  1146. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1147. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1148. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1149. if (((mac->link_state == MAC80211_NOLINK)) &&
  1150. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1151. dm_pstable.rssi_val_min = 0;
  1152. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1153. ("Not connected to any\n"));
  1154. }
  1155. if (mac->link_state == MAC80211_LINKED) {
  1156. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1157. dm_pstable.rssi_val_min =
  1158. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1159. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1160. ("AP Client PWDB = 0x%lx\n",
  1161. dm_pstable.rssi_val_min));
  1162. } else {
  1163. dm_pstable.rssi_val_min =
  1164. rtlpriv->dm.undecorated_smoothed_pwdb;
  1165. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1166. ("STA Default Port PWDB = 0x%lx\n",
  1167. dm_pstable.rssi_val_min));
  1168. }
  1169. } else {
  1170. dm_pstable.rssi_val_min =
  1171. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1172. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1173. ("AP Ext Port PWDB = 0x%lx\n",
  1174. dm_pstable.rssi_val_min));
  1175. }
  1176. if (IS_92C_SERIAL(rtlhal->version))
  1177. rtl92c_dm_1r_cca(hw);
  1178. }
  1179. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1180. {
  1181. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1182. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1183. rtl92c_dm_diginit(hw);
  1184. rtl92c_dm_init_dynamic_txpower(hw);
  1185. rtl92c_dm_init_edca_turbo(hw);
  1186. rtl92c_dm_init_rate_adaptive_mask(hw);
  1187. rtl92c_dm_initialize_txpower_tracking(hw);
  1188. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1189. }
  1190. EXPORT_SYMBOL(rtl92c_dm_init);
  1191. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1192. {
  1193. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1194. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1195. bool fw_current_inpsmode = false;
  1196. bool fw_ps_awake = true;
  1197. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1198. (u8 *) (&fw_current_inpsmode));
  1199. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1200. (u8 *) (&fw_ps_awake));
  1201. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1202. fw_ps_awake)
  1203. && (!ppsc->rfchange_inprogress)) {
  1204. rtl92c_dm_pwdb_monitor(hw);
  1205. rtl92c_dm_dig(hw);
  1206. rtl92c_dm_false_alarm_counter_statistics(hw);
  1207. rtl92c_dm_dynamic_bb_powersaving(hw);
  1208. rtlpriv->cfg->ops->dm_dynamic_txpower(hw);
  1209. rtl92c_dm_check_txpower_tracking(hw);
  1210. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1211. rtl92c_dm_check_edca_turbo(hw);
  1212. }
  1213. }
  1214. EXPORT_SYMBOL(rtl92c_dm_watchdog);