rt2x00pci.c 8.4 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include <linux/slab.h>
  26. #include "rt2x00.h"
  27. #include "rt2x00pci.h"
  28. /*
  29. * Register access.
  30. */
  31. int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
  32. const unsigned int offset,
  33. const struct rt2x00_field32 field,
  34. u32 *reg)
  35. {
  36. unsigned int i;
  37. if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
  38. return 0;
  39. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  40. rt2x00pci_register_read(rt2x00dev, offset, reg);
  41. if (!rt2x00_get_field32(*reg, field))
  42. return 1;
  43. udelay(REGISTER_BUSY_DELAY);
  44. }
  45. ERROR(rt2x00dev, "Indirect register access failed: "
  46. "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
  47. *reg = ~0;
  48. return 0;
  49. }
  50. EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
  51. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  52. {
  53. struct data_queue *queue = rt2x00dev->rx;
  54. struct queue_entry *entry;
  55. struct queue_entry_priv_pci *entry_priv;
  56. struct skb_frame_desc *skbdesc;
  57. while (1) {
  58. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  59. entry_priv = entry->priv_data;
  60. if (rt2x00dev->ops->lib->get_entry_state(entry))
  61. break;
  62. /*
  63. * Fill in desc fields of the skb descriptor
  64. */
  65. skbdesc = get_skb_frame_desc(entry->skb);
  66. skbdesc->desc = entry_priv->desc;
  67. skbdesc->desc_len = entry->queue->desc_size;
  68. /*
  69. * DMA is already done, notify rt2x00lib that
  70. * it finished successfully.
  71. */
  72. rt2x00lib_dmastart(entry);
  73. rt2x00lib_dmadone(entry);
  74. /*
  75. * Send the frame to rt2x00lib for further processing.
  76. */
  77. rt2x00lib_rxdone(entry);
  78. }
  79. }
  80. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  81. /*
  82. * Device initialization handlers.
  83. */
  84. static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
  85. struct data_queue *queue)
  86. {
  87. struct queue_entry_priv_pci *entry_priv;
  88. void *addr;
  89. dma_addr_t dma;
  90. unsigned int i;
  91. /*
  92. * Allocate DMA memory for descriptor and buffer.
  93. */
  94. addr = dma_alloc_coherent(rt2x00dev->dev,
  95. queue->limit * queue->desc_size,
  96. &dma, GFP_KERNEL);
  97. if (!addr)
  98. return -ENOMEM;
  99. memset(addr, 0, queue->limit * queue->desc_size);
  100. /*
  101. * Initialize all queue entries to contain valid addresses.
  102. */
  103. for (i = 0; i < queue->limit; i++) {
  104. entry_priv = queue->entries[i].priv_data;
  105. entry_priv->desc = addr + i * queue->desc_size;
  106. entry_priv->desc_dma = dma + i * queue->desc_size;
  107. }
  108. return 0;
  109. }
  110. static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
  111. struct data_queue *queue)
  112. {
  113. struct queue_entry_priv_pci *entry_priv =
  114. queue->entries[0].priv_data;
  115. if (entry_priv->desc)
  116. dma_free_coherent(rt2x00dev->dev,
  117. queue->limit * queue->desc_size,
  118. entry_priv->desc, entry_priv->desc_dma);
  119. entry_priv->desc = NULL;
  120. }
  121. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  122. {
  123. struct data_queue *queue;
  124. int status;
  125. /*
  126. * Allocate DMA
  127. */
  128. queue_for_each(rt2x00dev, queue) {
  129. status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
  130. if (status)
  131. goto exit;
  132. }
  133. /*
  134. * Register interrupt handler.
  135. */
  136. status = request_irq(rt2x00dev->irq,
  137. rt2x00dev->ops->lib->irq_handler,
  138. IRQF_SHARED, rt2x00dev->name, rt2x00dev);
  139. if (status) {
  140. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  141. rt2x00dev->irq, status);
  142. goto exit;
  143. }
  144. return 0;
  145. exit:
  146. queue_for_each(rt2x00dev, queue)
  147. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  148. return status;
  149. }
  150. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  151. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  152. {
  153. struct data_queue *queue;
  154. /*
  155. * Free irq line.
  156. */
  157. free_irq(rt2x00dev->irq, rt2x00dev);
  158. /*
  159. * Free DMA
  160. */
  161. queue_for_each(rt2x00dev, queue)
  162. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  163. }
  164. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  165. /*
  166. * PCI driver handlers.
  167. */
  168. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  169. {
  170. kfree(rt2x00dev->rf);
  171. rt2x00dev->rf = NULL;
  172. kfree(rt2x00dev->eeprom);
  173. rt2x00dev->eeprom = NULL;
  174. if (rt2x00dev->csr.base) {
  175. iounmap(rt2x00dev->csr.base);
  176. rt2x00dev->csr.base = NULL;
  177. }
  178. }
  179. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  180. {
  181. struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
  182. rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);
  183. if (!rt2x00dev->csr.base)
  184. goto exit;
  185. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  186. if (!rt2x00dev->eeprom)
  187. goto exit;
  188. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  189. if (!rt2x00dev->rf)
  190. goto exit;
  191. return 0;
  192. exit:
  193. ERROR_PROBE("Failed to allocate registers.\n");
  194. rt2x00pci_free_reg(rt2x00dev);
  195. return -ENOMEM;
  196. }
  197. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  198. {
  199. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  200. struct ieee80211_hw *hw;
  201. struct rt2x00_dev *rt2x00dev;
  202. int retval;
  203. retval = pci_enable_device(pci_dev);
  204. if (retval) {
  205. ERROR_PROBE("Enable device failed.\n");
  206. return retval;
  207. }
  208. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  209. if (retval) {
  210. ERROR_PROBE("PCI request regions failed.\n");
  211. goto exit_disable_device;
  212. }
  213. pci_set_master(pci_dev);
  214. if (pci_set_mwi(pci_dev))
  215. ERROR_PROBE("MWI not available.\n");
  216. if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
  217. ERROR_PROBE("PCI DMA not supported.\n");
  218. retval = -EIO;
  219. goto exit_release_regions;
  220. }
  221. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  222. if (!hw) {
  223. ERROR_PROBE("Failed to allocate hardware.\n");
  224. retval = -ENOMEM;
  225. goto exit_release_regions;
  226. }
  227. pci_set_drvdata(pci_dev, hw);
  228. rt2x00dev = hw->priv;
  229. rt2x00dev->dev = &pci_dev->dev;
  230. rt2x00dev->ops = ops;
  231. rt2x00dev->hw = hw;
  232. rt2x00dev->irq = pci_dev->irq;
  233. rt2x00dev->name = pci_name(pci_dev);
  234. if (pci_is_pcie(pci_dev))
  235. rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
  236. else
  237. rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
  238. retval = rt2x00pci_alloc_reg(rt2x00dev);
  239. if (retval)
  240. goto exit_free_device;
  241. retval = rt2x00lib_probe_dev(rt2x00dev);
  242. if (retval)
  243. goto exit_free_reg;
  244. return 0;
  245. exit_free_reg:
  246. rt2x00pci_free_reg(rt2x00dev);
  247. exit_free_device:
  248. ieee80211_free_hw(hw);
  249. exit_release_regions:
  250. pci_release_regions(pci_dev);
  251. exit_disable_device:
  252. pci_disable_device(pci_dev);
  253. pci_set_drvdata(pci_dev, NULL);
  254. return retval;
  255. }
  256. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  257. void rt2x00pci_remove(struct pci_dev *pci_dev)
  258. {
  259. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  260. struct rt2x00_dev *rt2x00dev = hw->priv;
  261. /*
  262. * Free all allocated data.
  263. */
  264. rt2x00lib_remove_dev(rt2x00dev);
  265. rt2x00pci_free_reg(rt2x00dev);
  266. ieee80211_free_hw(hw);
  267. /*
  268. * Free the PCI device data.
  269. */
  270. pci_set_drvdata(pci_dev, NULL);
  271. pci_disable_device(pci_dev);
  272. pci_release_regions(pci_dev);
  273. }
  274. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  275. #ifdef CONFIG_PM
  276. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  277. {
  278. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  279. struct rt2x00_dev *rt2x00dev = hw->priv;
  280. int retval;
  281. retval = rt2x00lib_suspend(rt2x00dev, state);
  282. if (retval)
  283. return retval;
  284. pci_save_state(pci_dev);
  285. pci_disable_device(pci_dev);
  286. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  287. }
  288. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  289. int rt2x00pci_resume(struct pci_dev *pci_dev)
  290. {
  291. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  292. struct rt2x00_dev *rt2x00dev = hw->priv;
  293. if (pci_set_power_state(pci_dev, PCI_D0) ||
  294. pci_enable_device(pci_dev)) {
  295. ERROR(rt2x00dev, "Failed to resume device.\n");
  296. return -EIO;
  297. }
  298. pci_restore_state(pci_dev);
  299. return rt2x00lib_resume(rt2x00dev);
  300. }
  301. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  302. #endif /* CONFIG_PM */
  303. /*
  304. * rt2x00pci module information.
  305. */
  306. MODULE_AUTHOR(DRV_PROJECT);
  307. MODULE_VERSION(DRV_VERSION);
  308. MODULE_DESCRIPTION("rt2x00 pci library");
  309. MODULE_LICENSE("GPL");