iwl3945-base.c 122 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/ieee80211_radiotap.h>
  46. #include <net/mac80211.h>
  47. #include <asm/div64.h>
  48. #define DRV_NAME "iwl3945"
  49. #include "iwl-fh.h"
  50. #include "iwl-3945-fh.h"
  51. #include "iwl-commands.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-3945.h"
  54. #include "iwl-core.h"
  55. #include "iwl-helpers.h"
  56. #include "iwl-dev.h"
  57. #include "iwl-spectrum.h"
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION \
  62. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  63. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  64. #define VD "d"
  65. #else
  66. #define VD
  67. #endif
  68. /*
  69. * add "s" to indicate spectrum measurement included.
  70. * we add it here to be consistent with previous releases in which
  71. * this was configurable.
  72. */
  73. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  74. #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
  75. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  76. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  77. MODULE_VERSION(DRV_VERSION);
  78. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  79. MODULE_LICENSE("GPL");
  80. /* module parameters */
  81. struct iwl_mod_params iwl3945_mod_params = {
  82. .sw_crypto = 1,
  83. .restart_fw = 1,
  84. /* the rest are 0 by default */
  85. };
  86. /**
  87. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  88. * @priv: eeprom and antenna fields are used to determine antenna flags
  89. *
  90. * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  91. * iwl3945_mod_params.antenna specifies the antenna diversity mode:
  92. *
  93. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  94. * IWL_ANTENNA_MAIN - Force MAIN antenna
  95. * IWL_ANTENNA_AUX - Force AUX antenna
  96. */
  97. __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
  98. {
  99. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  100. switch (iwl3945_mod_params.antenna) {
  101. case IWL_ANTENNA_DIVERSITY:
  102. return 0;
  103. case IWL_ANTENNA_MAIN:
  104. if (eeprom->antenna_switch_type)
  105. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  106. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  107. case IWL_ANTENNA_AUX:
  108. if (eeprom->antenna_switch_type)
  109. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  110. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  111. }
  112. /* bad antenna selector value */
  113. IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
  114. iwl3945_mod_params.antenna);
  115. return 0; /* "diversity" is default if error */
  116. }
  117. static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
  118. struct ieee80211_key_conf *keyconf,
  119. u8 sta_id)
  120. {
  121. unsigned long flags;
  122. __le16 key_flags = 0;
  123. int ret;
  124. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  125. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  126. if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
  127. key_flags |= STA_KEY_MULTICAST_MSK;
  128. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  129. keyconf->hw_key_idx = keyconf->keyidx;
  130. key_flags &= ~STA_KEY_FLG_INVALID;
  131. spin_lock_irqsave(&priv->sta_lock, flags);
  132. priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  133. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  134. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  135. keyconf->keylen);
  136. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  137. keyconf->keylen);
  138. if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  139. == STA_KEY_FLG_NO_ENC)
  140. priv->stations[sta_id].sta.key.key_offset =
  141. iwl_legacy_get_free_ucode_key_index(priv);
  142. /* else, we are overriding an existing key => no need to allocated room
  143. * in uCode. */
  144. WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  145. "no space for a new key");
  146. priv->stations[sta_id].sta.key.key_flags = key_flags;
  147. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  148. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  149. IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
  150. ret = iwl_legacy_send_add_sta(priv,
  151. &priv->stations[sta_id].sta, CMD_ASYNC);
  152. spin_unlock_irqrestore(&priv->sta_lock, flags);
  153. return ret;
  154. }
  155. static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
  156. struct ieee80211_key_conf *keyconf,
  157. u8 sta_id)
  158. {
  159. return -EOPNOTSUPP;
  160. }
  161. static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
  162. struct ieee80211_key_conf *keyconf,
  163. u8 sta_id)
  164. {
  165. return -EOPNOTSUPP;
  166. }
  167. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  168. {
  169. unsigned long flags;
  170. struct iwl_legacy_addsta_cmd sta_cmd;
  171. spin_lock_irqsave(&priv->sta_lock, flags);
  172. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
  173. memset(&priv->stations[sta_id].sta.key, 0,
  174. sizeof(struct iwl4965_keyinfo));
  175. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  176. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  177. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  178. memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_legacy_addsta_cmd));
  179. spin_unlock_irqrestore(&priv->sta_lock, flags);
  180. IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
  181. return iwl_legacy_send_add_sta(priv, &sta_cmd, CMD_SYNC);
  182. }
  183. static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
  184. struct ieee80211_key_conf *keyconf, u8 sta_id)
  185. {
  186. int ret = 0;
  187. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  188. switch (keyconf->cipher) {
  189. case WLAN_CIPHER_SUITE_CCMP:
  190. ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
  191. break;
  192. case WLAN_CIPHER_SUITE_TKIP:
  193. ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
  194. break;
  195. case WLAN_CIPHER_SUITE_WEP40:
  196. case WLAN_CIPHER_SUITE_WEP104:
  197. ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
  198. break;
  199. default:
  200. IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
  201. keyconf->cipher);
  202. ret = -EINVAL;
  203. }
  204. IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  205. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  206. sta_id, ret);
  207. return ret;
  208. }
  209. static int iwl3945_remove_static_key(struct iwl_priv *priv)
  210. {
  211. int ret = -EOPNOTSUPP;
  212. return ret;
  213. }
  214. static int iwl3945_set_static_key(struct iwl_priv *priv,
  215. struct ieee80211_key_conf *key)
  216. {
  217. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  218. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  219. return -EOPNOTSUPP;
  220. IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
  221. return -EINVAL;
  222. }
  223. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  224. {
  225. struct list_head *element;
  226. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  227. priv->frames_count);
  228. while (!list_empty(&priv->free_frames)) {
  229. element = priv->free_frames.next;
  230. list_del(element);
  231. kfree(list_entry(element, struct iwl3945_frame, list));
  232. priv->frames_count--;
  233. }
  234. if (priv->frames_count) {
  235. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  236. priv->frames_count);
  237. priv->frames_count = 0;
  238. }
  239. }
  240. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  241. {
  242. struct iwl3945_frame *frame;
  243. struct list_head *element;
  244. if (list_empty(&priv->free_frames)) {
  245. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  246. if (!frame) {
  247. IWL_ERR(priv, "Could not allocate frame!\n");
  248. return NULL;
  249. }
  250. priv->frames_count++;
  251. return frame;
  252. }
  253. element = priv->free_frames.next;
  254. list_del(element);
  255. return list_entry(element, struct iwl3945_frame, list);
  256. }
  257. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  258. {
  259. memset(frame, 0, sizeof(*frame));
  260. list_add(&frame->list, &priv->free_frames);
  261. }
  262. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  263. struct ieee80211_hdr *hdr,
  264. int left)
  265. {
  266. if (!iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->beacon_skb)
  267. return 0;
  268. if (priv->beacon_skb->len > left)
  269. return 0;
  270. memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
  271. return priv->beacon_skb->len;
  272. }
  273. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  274. {
  275. struct iwl3945_frame *frame;
  276. unsigned int frame_size;
  277. int rc;
  278. u8 rate;
  279. frame = iwl3945_get_free_frame(priv);
  280. if (!frame) {
  281. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  282. "command.\n");
  283. return -ENOMEM;
  284. }
  285. rate = iwl_legacy_get_lowest_plcp(priv,
  286. &priv->contexts[IWL_RXON_CTX_BSS]);
  287. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  288. rc = iwl_legacy_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  289. &frame->u.cmd[0]);
  290. iwl3945_free_frame(priv, frame);
  291. return rc;
  292. }
  293. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  294. {
  295. if (priv->_3945.shared_virt)
  296. dma_free_coherent(&priv->pci_dev->dev,
  297. sizeof(struct iwl3945_shared),
  298. priv->_3945.shared_virt,
  299. priv->_3945.shared_phys);
  300. }
  301. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  302. struct ieee80211_tx_info *info,
  303. struct iwl_device_cmd *cmd,
  304. struct sk_buff *skb_frag,
  305. int sta_id)
  306. {
  307. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  308. struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
  309. tx_cmd->sec_ctl = 0;
  310. switch (keyinfo->cipher) {
  311. case WLAN_CIPHER_SUITE_CCMP:
  312. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  313. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  314. IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
  315. break;
  316. case WLAN_CIPHER_SUITE_TKIP:
  317. break;
  318. case WLAN_CIPHER_SUITE_WEP104:
  319. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  320. /* fall through */
  321. case WLAN_CIPHER_SUITE_WEP40:
  322. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  323. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  324. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  325. IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
  326. "with key %d\n", info->control.hw_key->hw_key_idx);
  327. break;
  328. default:
  329. IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
  330. break;
  331. }
  332. }
  333. /*
  334. * handle build REPLY_TX command notification.
  335. */
  336. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  337. struct iwl_device_cmd *cmd,
  338. struct ieee80211_tx_info *info,
  339. struct ieee80211_hdr *hdr, u8 std_id)
  340. {
  341. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  342. __le32 tx_flags = tx_cmd->tx_flags;
  343. __le16 fc = hdr->frame_control;
  344. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  345. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  346. tx_flags |= TX_CMD_FLG_ACK_MSK;
  347. if (ieee80211_is_mgmt(fc))
  348. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  349. if (ieee80211_is_probe_resp(fc) &&
  350. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  351. tx_flags |= TX_CMD_FLG_TSF_MSK;
  352. } else {
  353. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  354. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  355. }
  356. tx_cmd->sta_id = std_id;
  357. if (ieee80211_has_morefrags(fc))
  358. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  359. if (ieee80211_is_data_qos(fc)) {
  360. u8 *qc = ieee80211_get_qos_ctl(hdr);
  361. tx_cmd->tid_tspec = qc[0] & 0xf;
  362. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  363. } else {
  364. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  365. }
  366. iwl_legacy_tx_cmd_protection(priv, info, fc, &tx_flags);
  367. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  368. if (ieee80211_is_mgmt(fc)) {
  369. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  370. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  371. else
  372. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  373. } else {
  374. tx_cmd->timeout.pm_frame_timeout = 0;
  375. }
  376. tx_cmd->driver_txop = 0;
  377. tx_cmd->tx_flags = tx_flags;
  378. tx_cmd->next_frame_len = 0;
  379. }
  380. /*
  381. * start REPLY_TX command process
  382. */
  383. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  384. {
  385. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  386. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  387. struct iwl3945_tx_cmd *tx_cmd;
  388. struct iwl_tx_queue *txq = NULL;
  389. struct iwl_queue *q = NULL;
  390. struct iwl_device_cmd *out_cmd;
  391. struct iwl_cmd_meta *out_meta;
  392. dma_addr_t phys_addr;
  393. dma_addr_t txcmd_phys;
  394. int txq_id = skb_get_queue_mapping(skb);
  395. u16 len, idx, hdr_len;
  396. u8 id;
  397. u8 unicast;
  398. u8 sta_id;
  399. u8 tid = 0;
  400. __le16 fc;
  401. u8 wait_write_ptr = 0;
  402. unsigned long flags;
  403. spin_lock_irqsave(&priv->lock, flags);
  404. if (iwl_legacy_is_rfkill(priv)) {
  405. IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
  406. goto drop_unlock;
  407. }
  408. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  409. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  410. goto drop_unlock;
  411. }
  412. unicast = !is_multicast_ether_addr(hdr->addr1);
  413. id = 0;
  414. fc = hdr->frame_control;
  415. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  416. if (ieee80211_is_auth(fc))
  417. IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
  418. else if (ieee80211_is_assoc_req(fc))
  419. IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
  420. else if (ieee80211_is_reassoc_req(fc))
  421. IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
  422. #endif
  423. spin_unlock_irqrestore(&priv->lock, flags);
  424. hdr_len = ieee80211_hdrlen(fc);
  425. /* Find index into station table for destination station */
  426. sta_id = iwl_legacy_sta_id_or_broadcast(
  427. priv, &priv->contexts[IWL_RXON_CTX_BSS],
  428. info->control.sta);
  429. if (sta_id == IWL_INVALID_STATION) {
  430. IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
  431. hdr->addr1);
  432. goto drop;
  433. }
  434. IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
  435. if (ieee80211_is_data_qos(fc)) {
  436. u8 *qc = ieee80211_get_qos_ctl(hdr);
  437. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  438. if (unlikely(tid >= MAX_TID_COUNT))
  439. goto drop;
  440. }
  441. /* Descriptor for chosen Tx queue */
  442. txq = &priv->txq[txq_id];
  443. q = &txq->q;
  444. if ((iwl_legacy_queue_space(q) < q->high_mark))
  445. goto drop;
  446. spin_lock_irqsave(&priv->lock, flags);
  447. idx = iwl_legacy_get_cmd_index(q, q->write_ptr, 0);
  448. /* Set up driver data for this TFD */
  449. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  450. txq->txb[q->write_ptr].skb = skb;
  451. txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  452. /* Init first empty entry in queue's array of Tx/cmd buffers */
  453. out_cmd = txq->cmd[idx];
  454. out_meta = &txq->meta[idx];
  455. tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  456. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  457. memset(tx_cmd, 0, sizeof(*tx_cmd));
  458. /*
  459. * Set up the Tx-command (not MAC!) header.
  460. * Store the chosen Tx queue and TFD index within the sequence field;
  461. * after Tx, uCode's Tx response will return this value so driver can
  462. * locate the frame within the tx queue and do post-tx processing.
  463. */
  464. out_cmd->hdr.cmd = REPLY_TX;
  465. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  466. INDEX_TO_SEQ(q->write_ptr)));
  467. /* Copy MAC header from skb into command buffer */
  468. memcpy(tx_cmd->hdr, hdr, hdr_len);
  469. if (info->control.hw_key)
  470. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
  471. /* TODO need this for burst mode later on */
  472. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  473. /* set is_hcca to 0; it probably will never be implemented */
  474. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  475. /* Total # bytes to be transmitted */
  476. len = (u16)skb->len;
  477. tx_cmd->len = cpu_to_le16(len);
  478. iwl_legacy_dbg_log_tx_data_frame(priv, len, hdr);
  479. iwl_legacy_update_stats(priv, true, fc, len);
  480. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  481. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  482. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  483. txq->need_update = 1;
  484. } else {
  485. wait_write_ptr = 1;
  486. txq->need_update = 0;
  487. }
  488. IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
  489. le16_to_cpu(out_cmd->hdr.sequence));
  490. IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  491. iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  492. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
  493. ieee80211_hdrlen(fc));
  494. /*
  495. * Use the first empty entry in this queue's command buffer array
  496. * to contain the Tx command and MAC header concatenated together
  497. * (payload data will be in another buffer).
  498. * Size of this varies, due to varying MAC header length.
  499. * If end is not dword aligned, we'll have 2 extra bytes at the end
  500. * of the MAC header (device reads on dword boundaries).
  501. * We'll tell device about this padding later.
  502. */
  503. len = sizeof(struct iwl3945_tx_cmd) +
  504. sizeof(struct iwl_cmd_header) + hdr_len;
  505. len = (len + 3) & ~3;
  506. /* Physical address of this Tx command's header (not MAC header!),
  507. * within command buffer array. */
  508. txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  509. len, PCI_DMA_TODEVICE);
  510. /* we do not map meta data ... so we can safely access address to
  511. * provide to unmap command*/
  512. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  513. dma_unmap_len_set(out_meta, len, len);
  514. /* Add buffer containing Tx command and MAC(!) header to TFD's
  515. * first entry */
  516. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  517. txcmd_phys, len, 1, 0);
  518. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  519. * if any (802.11 null frames have no payload). */
  520. len = skb->len - hdr_len;
  521. if (len) {
  522. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  523. len, PCI_DMA_TODEVICE);
  524. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  525. phys_addr, len,
  526. 0, U32_PAD(len));
  527. }
  528. /* Tell device the write index *just past* this latest filled TFD */
  529. q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd);
  530. iwl_legacy_txq_update_write_ptr(priv, txq);
  531. spin_unlock_irqrestore(&priv->lock, flags);
  532. if ((iwl_legacy_queue_space(q) < q->high_mark)
  533. && priv->mac80211_registered) {
  534. if (wait_write_ptr) {
  535. spin_lock_irqsave(&priv->lock, flags);
  536. txq->need_update = 1;
  537. iwl_legacy_txq_update_write_ptr(priv, txq);
  538. spin_unlock_irqrestore(&priv->lock, flags);
  539. }
  540. iwl_legacy_stop_queue(priv, txq);
  541. }
  542. return 0;
  543. drop_unlock:
  544. spin_unlock_irqrestore(&priv->lock, flags);
  545. drop:
  546. return -1;
  547. }
  548. static int iwl3945_get_measurement(struct iwl_priv *priv,
  549. struct ieee80211_measurement_params *params,
  550. u8 type)
  551. {
  552. struct iwl_spectrum_cmd spectrum;
  553. struct iwl_rx_packet *pkt;
  554. struct iwl_host_cmd cmd = {
  555. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  556. .data = (void *)&spectrum,
  557. .flags = CMD_WANT_SKB,
  558. };
  559. u32 add_time = le64_to_cpu(params->start_time);
  560. int rc;
  561. int spectrum_resp_status;
  562. int duration = le16_to_cpu(params->duration);
  563. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  564. if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS))
  565. add_time = iwl_legacy_usecs_to_beacons(priv,
  566. le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
  567. le16_to_cpu(ctx->timing.beacon_interval));
  568. memset(&spectrum, 0, sizeof(spectrum));
  569. spectrum.channel_count = cpu_to_le16(1);
  570. spectrum.flags =
  571. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  572. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  573. cmd.len = sizeof(spectrum);
  574. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  575. if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS))
  576. spectrum.start_time =
  577. iwl_legacy_add_beacon_time(priv,
  578. priv->_3945.last_beacon_time, add_time,
  579. le16_to_cpu(ctx->timing.beacon_interval));
  580. else
  581. spectrum.start_time = 0;
  582. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  583. spectrum.channels[0].channel = params->channel;
  584. spectrum.channels[0].type = type;
  585. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  586. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  587. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  588. rc = iwl_legacy_send_cmd_sync(priv, &cmd);
  589. if (rc)
  590. return rc;
  591. pkt = (struct iwl_rx_packet *)cmd.reply_page;
  592. if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
  593. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  594. rc = -EIO;
  595. }
  596. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  597. switch (spectrum_resp_status) {
  598. case 0: /* Command will be handled */
  599. if (pkt->u.spectrum.id != 0xff) {
  600. IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
  601. pkt->u.spectrum.id);
  602. priv->measurement_status &= ~MEASUREMENT_READY;
  603. }
  604. priv->measurement_status |= MEASUREMENT_ACTIVE;
  605. rc = 0;
  606. break;
  607. case 1: /* Command will not be handled */
  608. rc = -EAGAIN;
  609. break;
  610. }
  611. iwl_legacy_free_pages(priv, cmd.reply_page);
  612. return rc;
  613. }
  614. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  615. struct iwl_rx_mem_buffer *rxb)
  616. {
  617. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  618. struct iwl_alive_resp *palive;
  619. struct delayed_work *pwork;
  620. palive = &pkt->u.alive_frame;
  621. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  622. "0x%01X 0x%01X\n",
  623. palive->is_valid, palive->ver_type,
  624. palive->ver_subtype);
  625. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  626. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  627. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  628. sizeof(struct iwl_alive_resp));
  629. pwork = &priv->init_alive_start;
  630. } else {
  631. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  632. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  633. sizeof(struct iwl_alive_resp));
  634. pwork = &priv->alive_start;
  635. iwl3945_disable_events(priv);
  636. }
  637. /* We delay the ALIVE response by 5ms to
  638. * give the HW RF Kill time to activate... */
  639. if (palive->is_valid == UCODE_VALID_OK)
  640. queue_delayed_work(priv->workqueue, pwork,
  641. msecs_to_jiffies(5));
  642. else
  643. IWL_WARN(priv, "uCode did not respond OK.\n");
  644. }
  645. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  646. struct iwl_rx_mem_buffer *rxb)
  647. {
  648. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  649. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  650. #endif
  651. IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  652. }
  653. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  654. struct iwl_rx_mem_buffer *rxb)
  655. {
  656. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  657. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  658. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  659. u8 rate = beacon->beacon_notify_hdr.rate;
  660. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  661. "tsf %d %d rate %d\n",
  662. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  663. beacon->beacon_notify_hdr.failure_frame,
  664. le32_to_cpu(beacon->ibss_mgr_status),
  665. le32_to_cpu(beacon->high_tsf),
  666. le32_to_cpu(beacon->low_tsf), rate);
  667. #endif
  668. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  669. }
  670. /* Handle notification from uCode that card's power state is changing
  671. * due to software, hardware, or critical temperature RFKILL */
  672. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  673. struct iwl_rx_mem_buffer *rxb)
  674. {
  675. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  676. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  677. unsigned long status = priv->status;
  678. IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
  679. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  680. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  681. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  682. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  683. if (flags & HW_CARD_DISABLED)
  684. set_bit(STATUS_RF_KILL_HW, &priv->status);
  685. else
  686. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  687. iwl_legacy_scan_cancel(priv);
  688. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  689. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  690. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  691. test_bit(STATUS_RF_KILL_HW, &priv->status));
  692. else
  693. wake_up_interruptible(&priv->wait_command_queue);
  694. }
  695. /**
  696. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  697. *
  698. * Setup the RX handlers for each of the reply types sent from the uCode
  699. * to the host.
  700. *
  701. * This function chains into the hardware specific files for them to setup
  702. * any hardware specific handlers as well.
  703. */
  704. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  705. {
  706. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  707. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  708. priv->rx_handlers[REPLY_ERROR] = iwl_legacy_rx_reply_error;
  709. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_legacy_rx_csa;
  710. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  711. iwl_legacy_rx_spectrum_measure_notif;
  712. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_legacy_rx_pm_sleep_notif;
  713. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  714. iwl_legacy_rx_pm_debug_statistics_notif;
  715. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  716. /*
  717. * The same handler is used for both the REPLY to a discrete
  718. * statistics request from the host as well as for the periodic
  719. * statistics notifications (after received beacons) from the uCode.
  720. */
  721. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
  722. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  723. iwl_legacy_setup_rx_scan_handlers(priv);
  724. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  725. /* Set up hardware specific Rx handlers */
  726. iwl3945_hw_rx_handler_setup(priv);
  727. }
  728. /************************** RX-FUNCTIONS ****************************/
  729. /*
  730. * Rx theory of operation
  731. *
  732. * The host allocates 32 DMA target addresses and passes the host address
  733. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  734. * 0 to 31
  735. *
  736. * Rx Queue Indexes
  737. * The host/firmware share two index registers for managing the Rx buffers.
  738. *
  739. * The READ index maps to the first position that the firmware may be writing
  740. * to -- the driver can read up to (but not including) this position and get
  741. * good data.
  742. * The READ index is managed by the firmware once the card is enabled.
  743. *
  744. * The WRITE index maps to the last position the driver has read from -- the
  745. * position preceding WRITE is the last slot the firmware can place a packet.
  746. *
  747. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  748. * WRITE = READ.
  749. *
  750. * During initialization, the host sets up the READ queue position to the first
  751. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  752. *
  753. * When the firmware places a packet in a buffer, it will advance the READ index
  754. * and fire the RX interrupt. The driver can then query the READ index and
  755. * process as many packets as possible, moving the WRITE index forward as it
  756. * resets the Rx queue buffers with new memory.
  757. *
  758. * The management in the driver is as follows:
  759. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  760. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  761. * to replenish the iwl->rxq->rx_free.
  762. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  763. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  764. * 'processed' and 'read' driver indexes as well)
  765. * + A received packet is processed and handed to the kernel network stack,
  766. * detached from the iwl->rxq. The driver 'processed' index is updated.
  767. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  768. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  769. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  770. * were enough free buffers and RX_STALLED is set it is cleared.
  771. *
  772. *
  773. * Driver sequence:
  774. *
  775. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  776. * iwl3945_rx_queue_restock
  777. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  778. * queue, updates firmware pointers, and updates
  779. * the WRITE index. If insufficient rx_free buffers
  780. * are available, schedules iwl3945_rx_replenish
  781. *
  782. * -- enable interrupts --
  783. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  784. * READ INDEX, detaching the SKB from the pool.
  785. * Moves the packet buffer from queue to rx_used.
  786. * Calls iwl3945_rx_queue_restock to refill any empty
  787. * slots.
  788. * ...
  789. *
  790. */
  791. /**
  792. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  793. */
  794. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  795. dma_addr_t dma_addr)
  796. {
  797. return cpu_to_le32((u32)dma_addr);
  798. }
  799. /**
  800. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  801. *
  802. * If there are slots in the RX queue that need to be restocked,
  803. * and we have free pre-allocated buffers, fill the ranks as much
  804. * as we can, pulling from rx_free.
  805. *
  806. * This moves the 'write' index forward to catch up with 'processed', and
  807. * also updates the memory address in the firmware to reference the new
  808. * target buffer.
  809. */
  810. static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
  811. {
  812. struct iwl_rx_queue *rxq = &priv->rxq;
  813. struct list_head *element;
  814. struct iwl_rx_mem_buffer *rxb;
  815. unsigned long flags;
  816. int write;
  817. spin_lock_irqsave(&rxq->lock, flags);
  818. write = rxq->write & ~0x7;
  819. while ((iwl_legacy_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  820. /* Get next free Rx buffer, remove from free list */
  821. element = rxq->rx_free.next;
  822. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  823. list_del(element);
  824. /* Point to Rx buffer via next RBD in circular buffer */
  825. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
  826. rxq->queue[rxq->write] = rxb;
  827. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  828. rxq->free_count--;
  829. }
  830. spin_unlock_irqrestore(&rxq->lock, flags);
  831. /* If the pre-allocated buffer pool is dropping low, schedule to
  832. * refill it */
  833. if (rxq->free_count <= RX_LOW_WATERMARK)
  834. queue_work(priv->workqueue, &priv->rx_replenish);
  835. /* If we've added more space for the firmware to place data, tell it.
  836. * Increment device's write pointer in multiples of 8. */
  837. if ((rxq->write_actual != (rxq->write & ~0x7))
  838. || (abs(rxq->write - rxq->read) > 7)) {
  839. spin_lock_irqsave(&rxq->lock, flags);
  840. rxq->need_update = 1;
  841. spin_unlock_irqrestore(&rxq->lock, flags);
  842. iwl_legacy_rx_queue_update_write_ptr(priv, rxq);
  843. }
  844. }
  845. /**
  846. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  847. *
  848. * When moving to rx_free an SKB is allocated for the slot.
  849. *
  850. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  851. * This is called as a scheduled work item (except for during initialization)
  852. */
  853. static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  854. {
  855. struct iwl_rx_queue *rxq = &priv->rxq;
  856. struct list_head *element;
  857. struct iwl_rx_mem_buffer *rxb;
  858. struct page *page;
  859. unsigned long flags;
  860. gfp_t gfp_mask = priority;
  861. while (1) {
  862. spin_lock_irqsave(&rxq->lock, flags);
  863. if (list_empty(&rxq->rx_used)) {
  864. spin_unlock_irqrestore(&rxq->lock, flags);
  865. return;
  866. }
  867. spin_unlock_irqrestore(&rxq->lock, flags);
  868. if (rxq->free_count > RX_LOW_WATERMARK)
  869. gfp_mask |= __GFP_NOWARN;
  870. if (priv->hw_params.rx_page_order > 0)
  871. gfp_mask |= __GFP_COMP;
  872. /* Alloc a new receive buffer */
  873. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  874. if (!page) {
  875. if (net_ratelimit())
  876. IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
  877. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  878. net_ratelimit())
  879. IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  880. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  881. rxq->free_count);
  882. /* We don't reschedule replenish work here -- we will
  883. * call the restock method and if it still needs
  884. * more buffers it will schedule replenish */
  885. break;
  886. }
  887. spin_lock_irqsave(&rxq->lock, flags);
  888. if (list_empty(&rxq->rx_used)) {
  889. spin_unlock_irqrestore(&rxq->lock, flags);
  890. __free_pages(page, priv->hw_params.rx_page_order);
  891. return;
  892. }
  893. element = rxq->rx_used.next;
  894. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  895. list_del(element);
  896. spin_unlock_irqrestore(&rxq->lock, flags);
  897. rxb->page = page;
  898. /* Get physical address of RB/SKB */
  899. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  900. PAGE_SIZE << priv->hw_params.rx_page_order,
  901. PCI_DMA_FROMDEVICE);
  902. spin_lock_irqsave(&rxq->lock, flags);
  903. list_add_tail(&rxb->list, &rxq->rx_free);
  904. rxq->free_count++;
  905. priv->alloc_rxb_page++;
  906. spin_unlock_irqrestore(&rxq->lock, flags);
  907. }
  908. }
  909. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  910. {
  911. unsigned long flags;
  912. int i;
  913. spin_lock_irqsave(&rxq->lock, flags);
  914. INIT_LIST_HEAD(&rxq->rx_free);
  915. INIT_LIST_HEAD(&rxq->rx_used);
  916. /* Fill the rx_used queue with _all_ of the Rx buffers */
  917. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  918. /* In the reset function, these buffers may have been allocated
  919. * to an SKB, so we need to unmap and free potential storage */
  920. if (rxq->pool[i].page != NULL) {
  921. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  922. PAGE_SIZE << priv->hw_params.rx_page_order,
  923. PCI_DMA_FROMDEVICE);
  924. __iwl_legacy_free_pages(priv, rxq->pool[i].page);
  925. rxq->pool[i].page = NULL;
  926. }
  927. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  928. }
  929. /* Set us so that we have processed and used all buffers, but have
  930. * not restocked the Rx queue with fresh buffers */
  931. rxq->read = rxq->write = 0;
  932. rxq->write_actual = 0;
  933. rxq->free_count = 0;
  934. spin_unlock_irqrestore(&rxq->lock, flags);
  935. }
  936. void iwl3945_rx_replenish(void *data)
  937. {
  938. struct iwl_priv *priv = data;
  939. unsigned long flags;
  940. iwl3945_rx_allocate(priv, GFP_KERNEL);
  941. spin_lock_irqsave(&priv->lock, flags);
  942. iwl3945_rx_queue_restock(priv);
  943. spin_unlock_irqrestore(&priv->lock, flags);
  944. }
  945. static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
  946. {
  947. iwl3945_rx_allocate(priv, GFP_ATOMIC);
  948. iwl3945_rx_queue_restock(priv);
  949. }
  950. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  951. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  952. * This free routine walks the list of POOL entries and if SKB is set to
  953. * non NULL it is unmapped and freed
  954. */
  955. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  956. {
  957. int i;
  958. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  959. if (rxq->pool[i].page != NULL) {
  960. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  961. PAGE_SIZE << priv->hw_params.rx_page_order,
  962. PCI_DMA_FROMDEVICE);
  963. __iwl_legacy_free_pages(priv, rxq->pool[i].page);
  964. rxq->pool[i].page = NULL;
  965. }
  966. }
  967. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  968. rxq->bd_dma);
  969. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  970. rxq->rb_stts, rxq->rb_stts_dma);
  971. rxq->bd = NULL;
  972. rxq->rb_stts = NULL;
  973. }
  974. /* Convert linear signal-to-noise ratio into dB */
  975. static u8 ratio2dB[100] = {
  976. /* 0 1 2 3 4 5 6 7 8 9 */
  977. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  978. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  979. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  980. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  981. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  982. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  983. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  984. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  985. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  986. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  987. };
  988. /* Calculates a relative dB value from a ratio of linear
  989. * (i.e. not dB) signal levels.
  990. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  991. int iwl3945_calc_db_from_ratio(int sig_ratio)
  992. {
  993. /* 1000:1 or higher just report as 60 dB */
  994. if (sig_ratio >= 1000)
  995. return 60;
  996. /* 100:1 or higher, divide by 10 and use table,
  997. * add 20 dB to make up for divide by 10 */
  998. if (sig_ratio >= 100)
  999. return 20 + (int)ratio2dB[sig_ratio/10];
  1000. /* We shouldn't see this */
  1001. if (sig_ratio < 1)
  1002. return 0;
  1003. /* Use table for ratios 1:1 - 99:1 */
  1004. return (int)ratio2dB[sig_ratio];
  1005. }
  1006. /**
  1007. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  1008. *
  1009. * Uses the priv->rx_handlers callback function array to invoke
  1010. * the appropriate handlers, including command responses,
  1011. * frame-received notifications, and other notifications.
  1012. */
  1013. static void iwl3945_rx_handle(struct iwl_priv *priv)
  1014. {
  1015. struct iwl_rx_mem_buffer *rxb;
  1016. struct iwl_rx_packet *pkt;
  1017. struct iwl_rx_queue *rxq = &priv->rxq;
  1018. u32 r, i;
  1019. int reclaim;
  1020. unsigned long flags;
  1021. u8 fill_rx = 0;
  1022. u32 count = 8;
  1023. int total_empty = 0;
  1024. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  1025. * buffer that the driver may process (last buffer filled by ucode). */
  1026. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1027. i = rxq->read;
  1028. /* calculate total frames need to be restock after handling RX */
  1029. total_empty = r - rxq->write_actual;
  1030. if (total_empty < 0)
  1031. total_empty += RX_QUEUE_SIZE;
  1032. if (total_empty > (RX_QUEUE_SIZE / 2))
  1033. fill_rx = 1;
  1034. /* Rx interrupt, but nothing sent from uCode */
  1035. if (i == r)
  1036. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  1037. while (i != r) {
  1038. int len;
  1039. rxb = rxq->queue[i];
  1040. /* If an RXB doesn't have a Rx queue slot associated with it,
  1041. * then a bug has been introduced in the queue refilling
  1042. * routines -- catch it here */
  1043. BUG_ON(rxb == NULL);
  1044. rxq->queue[i] = NULL;
  1045. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  1046. PAGE_SIZE << priv->hw_params.rx_page_order,
  1047. PCI_DMA_FROMDEVICE);
  1048. pkt = rxb_addr(rxb);
  1049. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1050. len += sizeof(u32); /* account for status word */
  1051. trace_iwlwifi_legacy_dev_rx(priv, pkt, len);
  1052. /* Reclaim a command buffer only if this packet is a response
  1053. * to a (driver-originated) command.
  1054. * If the packet (e.g. Rx frame) originated from uCode,
  1055. * there is no command buffer to reclaim.
  1056. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1057. * but apparently a few don't get set; catch them here. */
  1058. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1059. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1060. (pkt->hdr.cmd != REPLY_TX);
  1061. /* Based on type of command response or notification,
  1062. * handle those that need handling via function in
  1063. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  1064. if (priv->rx_handlers[pkt->hdr.cmd]) {
  1065. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
  1066. iwl_legacy_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1067. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1068. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  1069. } else {
  1070. /* No handling needed */
  1071. IWL_DEBUG_RX(priv,
  1072. "r %d i %d No handler needed for %s, 0x%02x\n",
  1073. r, i, iwl_legacy_get_cmd_string(pkt->hdr.cmd),
  1074. pkt->hdr.cmd);
  1075. }
  1076. /*
  1077. * XXX: After here, we should always check rxb->page
  1078. * against NULL before touching it or its virtual
  1079. * memory (pkt). Because some rx_handler might have
  1080. * already taken or freed the pages.
  1081. */
  1082. if (reclaim) {
  1083. /* Invoke any callbacks, transfer the buffer to caller,
  1084. * and fire off the (possibly) blocking iwl_legacy_send_cmd()
  1085. * as we reclaim the driver command queue */
  1086. if (rxb->page)
  1087. iwl_legacy_tx_cmd_complete(priv, rxb);
  1088. else
  1089. IWL_WARN(priv, "Claim null rxb?\n");
  1090. }
  1091. /* Reuse the page if possible. For notification packets and
  1092. * SKBs that fail to Rx correctly, add them back into the
  1093. * rx_free list for reuse later. */
  1094. spin_lock_irqsave(&rxq->lock, flags);
  1095. if (rxb->page != NULL) {
  1096. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  1097. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  1098. PCI_DMA_FROMDEVICE);
  1099. list_add_tail(&rxb->list, &rxq->rx_free);
  1100. rxq->free_count++;
  1101. } else
  1102. list_add_tail(&rxb->list, &rxq->rx_used);
  1103. spin_unlock_irqrestore(&rxq->lock, flags);
  1104. i = (i + 1) & RX_QUEUE_MASK;
  1105. /* If there are a lot of unused frames,
  1106. * restock the Rx queue so ucode won't assert. */
  1107. if (fill_rx) {
  1108. count++;
  1109. if (count >= 8) {
  1110. rxq->read = i;
  1111. iwl3945_rx_replenish_now(priv);
  1112. count = 0;
  1113. }
  1114. }
  1115. }
  1116. /* Backtrack one entry */
  1117. rxq->read = i;
  1118. if (fill_rx)
  1119. iwl3945_rx_replenish_now(priv);
  1120. else
  1121. iwl3945_rx_queue_restock(priv);
  1122. }
  1123. /* call this function to flush any scheduled tasklet */
  1124. static inline void iwl3945_synchronize_irq(struct iwl_priv *priv)
  1125. {
  1126. /* wait to make sure we flush pending tasklet*/
  1127. synchronize_irq(priv->pci_dev->irq);
  1128. tasklet_kill(&priv->irq_tasklet);
  1129. }
  1130. static const char *iwl3945_desc_lookup(int i)
  1131. {
  1132. switch (i) {
  1133. case 1:
  1134. return "FAIL";
  1135. case 2:
  1136. return "BAD_PARAM";
  1137. case 3:
  1138. return "BAD_CHECKSUM";
  1139. case 4:
  1140. return "NMI_INTERRUPT";
  1141. case 5:
  1142. return "SYSASSERT";
  1143. case 6:
  1144. return "FATAL_ERROR";
  1145. }
  1146. return "UNKNOWN";
  1147. }
  1148. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1149. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1150. void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  1151. {
  1152. u32 i;
  1153. u32 desc, time, count, base, data1;
  1154. u32 blink1, blink2, ilink1, ilink2;
  1155. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1156. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1157. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1158. return;
  1159. }
  1160. count = iwl_legacy_read_targ_mem(priv, base);
  1161. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1162. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1163. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1164. priv->status, count);
  1165. }
  1166. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  1167. "ilink1 nmiPC Line\n");
  1168. for (i = ERROR_START_OFFSET;
  1169. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1170. i += ERROR_ELEM_SIZE) {
  1171. desc = iwl_legacy_read_targ_mem(priv, base + i);
  1172. time =
  1173. iwl_legacy_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  1174. blink1 =
  1175. iwl_legacy_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  1176. blink2 =
  1177. iwl_legacy_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  1178. ilink1 =
  1179. iwl_legacy_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  1180. ilink2 =
  1181. iwl_legacy_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  1182. data1 =
  1183. iwl_legacy_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  1184. IWL_ERR(priv,
  1185. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1186. iwl3945_desc_lookup(desc), desc, time, blink1, blink2,
  1187. ilink1, ilink2, data1);
  1188. trace_iwlwifi_legacy_dev_ucode_error(priv, desc, time, data1, 0,
  1189. 0, blink1, blink2, ilink1, ilink2);
  1190. }
  1191. }
  1192. #define EVENT_START_OFFSET (6 * sizeof(u32))
  1193. /**
  1194. * iwl3945_print_event_log - Dump error event log to syslog
  1195. *
  1196. */
  1197. static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1198. u32 num_events, u32 mode,
  1199. int pos, char **buf, size_t bufsz)
  1200. {
  1201. u32 i;
  1202. u32 base; /* SRAM byte address of event log header */
  1203. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1204. u32 ptr; /* SRAM byte address of log data */
  1205. u32 ev, time, data; /* event log data */
  1206. unsigned long reg_flags;
  1207. if (num_events == 0)
  1208. return pos;
  1209. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1210. if (mode == 0)
  1211. event_size = 2 * sizeof(u32);
  1212. else
  1213. event_size = 3 * sizeof(u32);
  1214. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1215. /* Make sure device is powered up for SRAM reads */
  1216. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1217. iwl_grab_nic_access(priv);
  1218. /* Set starting address; reads will auto-increment */
  1219. _iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1220. rmb();
  1221. /* "time" is actually "data" for mode 0 (no timestamp).
  1222. * place event id # at far right for easier visual parsing. */
  1223. for (i = 0; i < num_events; i++) {
  1224. ev = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1225. time = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1226. if (mode == 0) {
  1227. /* data, ev */
  1228. if (bufsz) {
  1229. pos += scnprintf(*buf + pos, bufsz - pos,
  1230. "0x%08x:%04u\n",
  1231. time, ev);
  1232. } else {
  1233. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  1234. trace_iwlwifi_legacy_dev_ucode_event(priv, 0,
  1235. time, ev);
  1236. }
  1237. } else {
  1238. data = _iwl_legacy_read_direct32(priv,
  1239. HBUS_TARG_MEM_RDAT);
  1240. if (bufsz) {
  1241. pos += scnprintf(*buf + pos, bufsz - pos,
  1242. "%010u:0x%08x:%04u\n",
  1243. time, data, ev);
  1244. } else {
  1245. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
  1246. time, data, ev);
  1247. trace_iwlwifi_legacy_dev_ucode_event(priv, time,
  1248. data, ev);
  1249. }
  1250. }
  1251. }
  1252. /* Allow device to power down */
  1253. iwl_release_nic_access(priv);
  1254. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1255. return pos;
  1256. }
  1257. /**
  1258. * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
  1259. */
  1260. static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1261. u32 num_wraps, u32 next_entry,
  1262. u32 size, u32 mode,
  1263. int pos, char **buf, size_t bufsz)
  1264. {
  1265. /*
  1266. * display the newest DEFAULT_LOG_ENTRIES entries
  1267. * i.e the entries just before the next ont that uCode would fill.
  1268. */
  1269. if (num_wraps) {
  1270. if (next_entry < size) {
  1271. pos = iwl3945_print_event_log(priv,
  1272. capacity - (size - next_entry),
  1273. size - next_entry, mode,
  1274. pos, buf, bufsz);
  1275. pos = iwl3945_print_event_log(priv, 0,
  1276. next_entry, mode,
  1277. pos, buf, bufsz);
  1278. } else
  1279. pos = iwl3945_print_event_log(priv, next_entry - size,
  1280. size, mode,
  1281. pos, buf, bufsz);
  1282. } else {
  1283. if (next_entry < size)
  1284. pos = iwl3945_print_event_log(priv, 0,
  1285. next_entry, mode,
  1286. pos, buf, bufsz);
  1287. else
  1288. pos = iwl3945_print_event_log(priv, next_entry - size,
  1289. size, mode,
  1290. pos, buf, bufsz);
  1291. }
  1292. return pos;
  1293. }
  1294. #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
  1295. int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1296. char **buf, bool display)
  1297. {
  1298. u32 base; /* SRAM byte address of event log header */
  1299. u32 capacity; /* event log capacity in # entries */
  1300. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1301. u32 num_wraps; /* # times uCode wrapped to top of log */
  1302. u32 next_entry; /* index of next entry to be written by uCode */
  1303. u32 size; /* # entries that we'll print */
  1304. int pos = 0;
  1305. size_t bufsz = 0;
  1306. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1307. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1308. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1309. return -EINVAL;
  1310. }
  1311. /* event log header */
  1312. capacity = iwl_legacy_read_targ_mem(priv, base);
  1313. mode = iwl_legacy_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1314. num_wraps = iwl_legacy_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1315. next_entry = iwl_legacy_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1316. if (capacity > priv->cfg->base_params->max_event_log_size) {
  1317. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1318. capacity, priv->cfg->base_params->max_event_log_size);
  1319. capacity = priv->cfg->base_params->max_event_log_size;
  1320. }
  1321. if (next_entry > priv->cfg->base_params->max_event_log_size) {
  1322. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1323. next_entry, priv->cfg->base_params->max_event_log_size);
  1324. next_entry = priv->cfg->base_params->max_event_log_size;
  1325. }
  1326. size = num_wraps ? capacity : next_entry;
  1327. /* bail out if nothing in log */
  1328. if (size == 0) {
  1329. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1330. return pos;
  1331. }
  1332. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1333. if (!(iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1334. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1335. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1336. #else
  1337. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1338. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1339. #endif
  1340. IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
  1341. size);
  1342. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1343. if (display) {
  1344. if (full_log)
  1345. bufsz = capacity * 48;
  1346. else
  1347. bufsz = size * 48;
  1348. *buf = kmalloc(bufsz, GFP_KERNEL);
  1349. if (!*buf)
  1350. return -ENOMEM;
  1351. }
  1352. if ((iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1353. /* if uCode has wrapped back to top of log,
  1354. * start at the oldest entry,
  1355. * i.e the next one that uCode would fill.
  1356. */
  1357. if (num_wraps)
  1358. pos = iwl3945_print_event_log(priv, next_entry,
  1359. capacity - next_entry, mode,
  1360. pos, buf, bufsz);
  1361. /* (then/else) start at top of log */
  1362. pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
  1363. pos, buf, bufsz);
  1364. } else
  1365. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1366. next_entry, size, mode,
  1367. pos, buf, bufsz);
  1368. #else
  1369. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1370. next_entry, size, mode,
  1371. pos, buf, bufsz);
  1372. #endif
  1373. return pos;
  1374. }
  1375. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  1376. {
  1377. u32 inta, handled = 0;
  1378. u32 inta_fh;
  1379. unsigned long flags;
  1380. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1381. u32 inta_mask;
  1382. #endif
  1383. spin_lock_irqsave(&priv->lock, flags);
  1384. /* Ack/clear/reset pending uCode interrupts.
  1385. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1386. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1387. inta = iwl_read32(priv, CSR_INT);
  1388. iwl_write32(priv, CSR_INT, inta);
  1389. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1390. * Any new interrupts that happen after this, either while we're
  1391. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1392. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1393. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  1394. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1395. if (iwl_legacy_get_debug_level(priv) & IWL_DL_ISR) {
  1396. /* just for debug */
  1397. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1398. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1399. inta, inta_mask, inta_fh);
  1400. }
  1401. #endif
  1402. spin_unlock_irqrestore(&priv->lock, flags);
  1403. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1404. * atomic, make sure that inta covers all the interrupts that
  1405. * we've discovered, even if FH interrupt came in just after
  1406. * reading CSR_INT. */
  1407. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1408. inta |= CSR_INT_BIT_FH_RX;
  1409. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1410. inta |= CSR_INT_BIT_FH_TX;
  1411. /* Now service all interrupt bits discovered above. */
  1412. if (inta & CSR_INT_BIT_HW_ERR) {
  1413. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1414. /* Tell the device to stop sending interrupts */
  1415. iwl_legacy_disable_interrupts(priv);
  1416. priv->isr_stats.hw++;
  1417. iwl_legacy_irq_handle_error(priv);
  1418. handled |= CSR_INT_BIT_HW_ERR;
  1419. return;
  1420. }
  1421. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1422. if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
  1423. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1424. if (inta & CSR_INT_BIT_SCD) {
  1425. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1426. "the frame/frames.\n");
  1427. priv->isr_stats.sch++;
  1428. }
  1429. /* Alive notification via Rx interrupt will do the real work */
  1430. if (inta & CSR_INT_BIT_ALIVE) {
  1431. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1432. priv->isr_stats.alive++;
  1433. }
  1434. }
  1435. #endif
  1436. /* Safely ignore these bits for debug checks below */
  1437. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1438. /* Error detected by uCode */
  1439. if (inta & CSR_INT_BIT_SW_ERR) {
  1440. IWL_ERR(priv, "Microcode SW error detected. "
  1441. "Restarting 0x%X.\n", inta);
  1442. priv->isr_stats.sw++;
  1443. iwl_legacy_irq_handle_error(priv);
  1444. handled |= CSR_INT_BIT_SW_ERR;
  1445. }
  1446. /* uCode wakes up after power-down sleep */
  1447. if (inta & CSR_INT_BIT_WAKEUP) {
  1448. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1449. iwl_legacy_rx_queue_update_write_ptr(priv, &priv->rxq);
  1450. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[0]);
  1451. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[1]);
  1452. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[2]);
  1453. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[3]);
  1454. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[4]);
  1455. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[5]);
  1456. priv->isr_stats.wakeup++;
  1457. handled |= CSR_INT_BIT_WAKEUP;
  1458. }
  1459. /* All uCode command responses, including Tx command responses,
  1460. * Rx "responses" (frame-received notification), and other
  1461. * notifications from uCode come through here*/
  1462. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1463. iwl3945_rx_handle(priv);
  1464. priv->isr_stats.rx++;
  1465. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1466. }
  1467. if (inta & CSR_INT_BIT_FH_TX) {
  1468. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1469. priv->isr_stats.tx++;
  1470. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  1471. iwl_legacy_write_direct32(priv, FH39_TCSR_CREDIT
  1472. (FH39_SRVC_CHNL), 0x0);
  1473. handled |= CSR_INT_BIT_FH_TX;
  1474. }
  1475. if (inta & ~handled) {
  1476. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1477. priv->isr_stats.unhandled++;
  1478. }
  1479. if (inta & ~priv->inta_mask) {
  1480. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1481. inta & ~priv->inta_mask);
  1482. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1483. }
  1484. /* Re-enable all interrupts */
  1485. /* only Re-enable if disabled by irq */
  1486. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1487. iwl_legacy_enable_interrupts(priv);
  1488. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1489. if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
  1490. inta = iwl_read32(priv, CSR_INT);
  1491. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1492. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1493. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1494. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1495. }
  1496. #endif
  1497. }
  1498. static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
  1499. struct ieee80211_vif *vif,
  1500. enum ieee80211_band band,
  1501. struct iwl3945_scan_channel *scan_ch)
  1502. {
  1503. const struct ieee80211_supported_band *sband;
  1504. u16 passive_dwell = 0;
  1505. u16 active_dwell = 0;
  1506. int added = 0;
  1507. u8 channel = 0;
  1508. sband = iwl_get_hw_mode(priv, band);
  1509. if (!sband) {
  1510. IWL_ERR(priv, "invalid band\n");
  1511. return added;
  1512. }
  1513. active_dwell = iwl_legacy_get_active_dwell_time(priv, band, 0);
  1514. passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
  1515. if (passive_dwell <= active_dwell)
  1516. passive_dwell = active_dwell + 1;
  1517. channel = iwl_legacy_get_single_channel_number(priv, band);
  1518. if (channel) {
  1519. scan_ch->channel = channel;
  1520. scan_ch->type = 0; /* passive */
  1521. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1522. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1523. /* Set txpower levels to defaults */
  1524. scan_ch->tpc.dsp_atten = 110;
  1525. if (band == IEEE80211_BAND_5GHZ)
  1526. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1527. else
  1528. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1529. added++;
  1530. } else
  1531. IWL_ERR(priv, "no valid channel found\n");
  1532. return added;
  1533. }
  1534. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  1535. enum ieee80211_band band,
  1536. u8 is_active, u8 n_probes,
  1537. struct iwl3945_scan_channel *scan_ch,
  1538. struct ieee80211_vif *vif)
  1539. {
  1540. struct ieee80211_channel *chan;
  1541. const struct ieee80211_supported_band *sband;
  1542. const struct iwl_channel_info *ch_info;
  1543. u16 passive_dwell = 0;
  1544. u16 active_dwell = 0;
  1545. int added, i;
  1546. sband = iwl_get_hw_mode(priv, band);
  1547. if (!sband)
  1548. return 0;
  1549. active_dwell = iwl_legacy_get_active_dwell_time(priv, band, n_probes);
  1550. passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
  1551. if (passive_dwell <= active_dwell)
  1552. passive_dwell = active_dwell + 1;
  1553. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1554. chan = priv->scan_request->channels[i];
  1555. if (chan->band != band)
  1556. continue;
  1557. scan_ch->channel = chan->hw_value;
  1558. ch_info = iwl_legacy_get_channel_info(priv, band,
  1559. scan_ch->channel);
  1560. if (!iwl_legacy_is_channel_valid(ch_info)) {
  1561. IWL_DEBUG_SCAN(priv,
  1562. "Channel %d is INVALID for this band.\n",
  1563. scan_ch->channel);
  1564. continue;
  1565. }
  1566. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1567. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1568. /* If passive , set up for auto-switch
  1569. * and use long active_dwell time.
  1570. */
  1571. if (!is_active || iwl_legacy_is_channel_passive(ch_info) ||
  1572. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1573. scan_ch->type = 0; /* passive */
  1574. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  1575. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1576. } else {
  1577. scan_ch->type = 1; /* active */
  1578. }
  1579. /* Set direct probe bits. These may be used both for active
  1580. * scan channels (probes gets sent right away),
  1581. * or for passive channels (probes get se sent only after
  1582. * hearing clear Rx packet).*/
  1583. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  1584. if (n_probes)
  1585. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1586. } else {
  1587. /* uCode v1 does not allow setting direct probe bits on
  1588. * passive channel. */
  1589. if ((scan_ch->type & 1) && n_probes)
  1590. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1591. }
  1592. /* Set txpower levels to defaults */
  1593. scan_ch->tpc.dsp_atten = 110;
  1594. /* scan_pwr_info->tpc.dsp_atten; */
  1595. /*scan_pwr_info->tpc.tx_gain; */
  1596. if (band == IEEE80211_BAND_5GHZ)
  1597. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1598. else {
  1599. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1600. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1601. * power level:
  1602. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1603. */
  1604. }
  1605. IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
  1606. scan_ch->channel,
  1607. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1608. (scan_ch->type & 1) ?
  1609. active_dwell : passive_dwell);
  1610. scan_ch++;
  1611. added++;
  1612. }
  1613. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1614. return added;
  1615. }
  1616. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  1617. struct ieee80211_rate *rates)
  1618. {
  1619. int i;
  1620. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  1621. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  1622. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  1623. rates[i].hw_value_short = i;
  1624. rates[i].flags = 0;
  1625. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  1626. /*
  1627. * If CCK != 1M then set short preamble rate flag.
  1628. */
  1629. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  1630. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1631. }
  1632. }
  1633. }
  1634. /******************************************************************************
  1635. *
  1636. * uCode download functions
  1637. *
  1638. ******************************************************************************/
  1639. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  1640. {
  1641. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1642. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1643. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1644. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1645. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1646. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1647. }
  1648. /**
  1649. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1650. * looking at all data.
  1651. */
  1652. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  1653. {
  1654. u32 val;
  1655. u32 save_len = len;
  1656. int rc = 0;
  1657. u32 errcnt;
  1658. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1659. iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1660. IWL39_RTC_INST_LOWER_BOUND);
  1661. errcnt = 0;
  1662. for (; len > 0; len -= sizeof(u32), image++) {
  1663. /* read data comes through single port, auto-incr addr */
  1664. /* NOTE: Use the debugless read so we don't flood kernel log
  1665. * if IWL_DL_IO is set */
  1666. val = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1667. if (val != le32_to_cpu(*image)) {
  1668. IWL_ERR(priv, "uCode INST section is invalid at "
  1669. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1670. save_len - len, val, le32_to_cpu(*image));
  1671. rc = -EIO;
  1672. errcnt++;
  1673. if (errcnt >= 20)
  1674. break;
  1675. }
  1676. }
  1677. if (!errcnt)
  1678. IWL_DEBUG_INFO(priv,
  1679. "ucode image in INSTRUCTION memory is good\n");
  1680. return rc;
  1681. }
  1682. /**
  1683. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1684. * using sample data 100 bytes apart. If these sample points are good,
  1685. * it's a pretty good bet that everything between them is good, too.
  1686. */
  1687. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1688. {
  1689. u32 val;
  1690. int rc = 0;
  1691. u32 errcnt = 0;
  1692. u32 i;
  1693. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1694. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1695. /* read data comes through single port, auto-incr addr */
  1696. /* NOTE: Use the debugless read so we don't flood kernel log
  1697. * if IWL_DL_IO is set */
  1698. iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1699. i + IWL39_RTC_INST_LOWER_BOUND);
  1700. val = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1701. if (val != le32_to_cpu(*image)) {
  1702. #if 0 /* Enable this if you want to see details */
  1703. IWL_ERR(priv, "uCode INST section is invalid at "
  1704. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1705. i, val, *image);
  1706. #endif
  1707. rc = -EIO;
  1708. errcnt++;
  1709. if (errcnt >= 3)
  1710. break;
  1711. }
  1712. }
  1713. return rc;
  1714. }
  1715. /**
  1716. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  1717. * and verify its contents
  1718. */
  1719. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  1720. {
  1721. __le32 *image;
  1722. u32 len;
  1723. int rc = 0;
  1724. /* Try bootstrap */
  1725. image = (__le32 *)priv->ucode_boot.v_addr;
  1726. len = priv->ucode_boot.len;
  1727. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1728. if (rc == 0) {
  1729. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1730. return 0;
  1731. }
  1732. /* Try initialize */
  1733. image = (__le32 *)priv->ucode_init.v_addr;
  1734. len = priv->ucode_init.len;
  1735. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1736. if (rc == 0) {
  1737. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1738. return 0;
  1739. }
  1740. /* Try runtime/protocol */
  1741. image = (__le32 *)priv->ucode_code.v_addr;
  1742. len = priv->ucode_code.len;
  1743. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1744. if (rc == 0) {
  1745. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1746. return 0;
  1747. }
  1748. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1749. /* Since nothing seems to match, show first several data entries in
  1750. * instruction SRAM, so maybe visual inspection will give a clue.
  1751. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1752. image = (__le32 *)priv->ucode_boot.v_addr;
  1753. len = priv->ucode_boot.len;
  1754. rc = iwl3945_verify_inst_full(priv, image, len);
  1755. return rc;
  1756. }
  1757. static void iwl3945_nic_start(struct iwl_priv *priv)
  1758. {
  1759. /* Remove all resets to allow NIC to operate */
  1760. iwl_write32(priv, CSR_RESET, 0);
  1761. }
  1762. #define IWL3945_UCODE_GET(item) \
  1763. static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
  1764. { \
  1765. return le32_to_cpu(ucode->v1.item); \
  1766. }
  1767. static u32 iwl3945_ucode_get_header_size(u32 api_ver)
  1768. {
  1769. return 24;
  1770. }
  1771. static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
  1772. {
  1773. return (u8 *) ucode->v1.data;
  1774. }
  1775. IWL3945_UCODE_GET(inst_size);
  1776. IWL3945_UCODE_GET(data_size);
  1777. IWL3945_UCODE_GET(init_size);
  1778. IWL3945_UCODE_GET(init_data_size);
  1779. IWL3945_UCODE_GET(boot_size);
  1780. /**
  1781. * iwl3945_read_ucode - Read uCode images from disk file.
  1782. *
  1783. * Copy into buffers for card to fetch via bus-mastering
  1784. */
  1785. static int iwl3945_read_ucode(struct iwl_priv *priv)
  1786. {
  1787. const struct iwl_ucode_header *ucode;
  1788. int ret = -EINVAL, index;
  1789. const struct firmware *ucode_raw;
  1790. /* firmware file name contains uCode/driver compatibility version */
  1791. const char *name_pre = priv->cfg->fw_name_pre;
  1792. const unsigned int api_max = priv->cfg->ucode_api_max;
  1793. const unsigned int api_min = priv->cfg->ucode_api_min;
  1794. char buf[25];
  1795. u8 *src;
  1796. size_t len;
  1797. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1798. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1799. * request_firmware() is synchronous, file is in memory on return. */
  1800. for (index = api_max; index >= api_min; index--) {
  1801. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  1802. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1803. if (ret < 0) {
  1804. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1805. buf, ret);
  1806. if (ret == -ENOENT)
  1807. continue;
  1808. else
  1809. goto error;
  1810. } else {
  1811. if (index < api_max)
  1812. IWL_ERR(priv, "Loaded firmware %s, "
  1813. "which is deprecated. "
  1814. " Please use API v%u instead.\n",
  1815. buf, api_max);
  1816. IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
  1817. "(%zd bytes) from disk\n",
  1818. buf, ucode_raw->size);
  1819. break;
  1820. }
  1821. }
  1822. if (ret < 0)
  1823. goto error;
  1824. /* Make sure that we got at least our header! */
  1825. if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
  1826. IWL_ERR(priv, "File size way too small!\n");
  1827. ret = -EINVAL;
  1828. goto err_release;
  1829. }
  1830. /* Data from ucode file: header followed by uCode images */
  1831. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1832. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1833. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1834. inst_size = iwl3945_ucode_get_inst_size(ucode);
  1835. data_size = iwl3945_ucode_get_data_size(ucode);
  1836. init_size = iwl3945_ucode_get_init_size(ucode);
  1837. init_data_size = iwl3945_ucode_get_init_data_size(ucode);
  1838. boot_size = iwl3945_ucode_get_boot_size(ucode);
  1839. src = iwl3945_ucode_get_data(ucode);
  1840. /* api_ver should match the api version forming part of the
  1841. * firmware filename ... but we don't check for that and only rely
  1842. * on the API version read from firmware header from here on forward */
  1843. if (api_ver < api_min || api_ver > api_max) {
  1844. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1845. "Driver supports v%u, firmware is v%u.\n",
  1846. api_max, api_ver);
  1847. priv->ucode_ver = 0;
  1848. ret = -EINVAL;
  1849. goto err_release;
  1850. }
  1851. if (api_ver != api_max)
  1852. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  1853. "got %u. New firmware can be obtained "
  1854. "from http://www.intellinuxwireless.org.\n",
  1855. api_max, api_ver);
  1856. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1857. IWL_UCODE_MAJOR(priv->ucode_ver),
  1858. IWL_UCODE_MINOR(priv->ucode_ver),
  1859. IWL_UCODE_API(priv->ucode_ver),
  1860. IWL_UCODE_SERIAL(priv->ucode_ver));
  1861. snprintf(priv->hw->wiphy->fw_version,
  1862. sizeof(priv->hw->wiphy->fw_version),
  1863. "%u.%u.%u.%u",
  1864. IWL_UCODE_MAJOR(priv->ucode_ver),
  1865. IWL_UCODE_MINOR(priv->ucode_ver),
  1866. IWL_UCODE_API(priv->ucode_ver),
  1867. IWL_UCODE_SERIAL(priv->ucode_ver));
  1868. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1869. priv->ucode_ver);
  1870. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1871. inst_size);
  1872. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1873. data_size);
  1874. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1875. init_size);
  1876. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1877. init_data_size);
  1878. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1879. boot_size);
  1880. /* Verify size of file vs. image size info in file's header */
  1881. if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
  1882. inst_size + data_size + init_size +
  1883. init_data_size + boot_size) {
  1884. IWL_DEBUG_INFO(priv,
  1885. "uCode file size %zd does not match expected size\n",
  1886. ucode_raw->size);
  1887. ret = -EINVAL;
  1888. goto err_release;
  1889. }
  1890. /* Verify that uCode images will fit in card's SRAM */
  1891. if (inst_size > IWL39_MAX_INST_SIZE) {
  1892. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1893. inst_size);
  1894. ret = -EINVAL;
  1895. goto err_release;
  1896. }
  1897. if (data_size > IWL39_MAX_DATA_SIZE) {
  1898. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1899. data_size);
  1900. ret = -EINVAL;
  1901. goto err_release;
  1902. }
  1903. if (init_size > IWL39_MAX_INST_SIZE) {
  1904. IWL_DEBUG_INFO(priv,
  1905. "uCode init instr len %d too large to fit in\n",
  1906. init_size);
  1907. ret = -EINVAL;
  1908. goto err_release;
  1909. }
  1910. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  1911. IWL_DEBUG_INFO(priv,
  1912. "uCode init data len %d too large to fit in\n",
  1913. init_data_size);
  1914. ret = -EINVAL;
  1915. goto err_release;
  1916. }
  1917. if (boot_size > IWL39_MAX_BSM_SIZE) {
  1918. IWL_DEBUG_INFO(priv,
  1919. "uCode boot instr len %d too large to fit in\n",
  1920. boot_size);
  1921. ret = -EINVAL;
  1922. goto err_release;
  1923. }
  1924. /* Allocate ucode buffers for card's bus-master loading ... */
  1925. /* Runtime instructions and 2 copies of data:
  1926. * 1) unmodified from disk
  1927. * 2) backup cache for save/restore during power-downs */
  1928. priv->ucode_code.len = inst_size;
  1929. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1930. priv->ucode_data.len = data_size;
  1931. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1932. priv->ucode_data_backup.len = data_size;
  1933. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1934. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1935. !priv->ucode_data_backup.v_addr)
  1936. goto err_pci_alloc;
  1937. /* Initialization instructions and data */
  1938. if (init_size && init_data_size) {
  1939. priv->ucode_init.len = init_size;
  1940. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1941. priv->ucode_init_data.len = init_data_size;
  1942. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1943. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1944. goto err_pci_alloc;
  1945. }
  1946. /* Bootstrap (instructions only, no data) */
  1947. if (boot_size) {
  1948. priv->ucode_boot.len = boot_size;
  1949. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1950. if (!priv->ucode_boot.v_addr)
  1951. goto err_pci_alloc;
  1952. }
  1953. /* Copy images into buffers for card's bus-master reads ... */
  1954. /* Runtime instructions (first block of data in file) */
  1955. len = inst_size;
  1956. IWL_DEBUG_INFO(priv,
  1957. "Copying (but not loading) uCode instr len %zd\n", len);
  1958. memcpy(priv->ucode_code.v_addr, src, len);
  1959. src += len;
  1960. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1961. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1962. /* Runtime data (2nd block)
  1963. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  1964. len = data_size;
  1965. IWL_DEBUG_INFO(priv,
  1966. "Copying (but not loading) uCode data len %zd\n", len);
  1967. memcpy(priv->ucode_data.v_addr, src, len);
  1968. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1969. src += len;
  1970. /* Initialization instructions (3rd block) */
  1971. if (init_size) {
  1972. len = init_size;
  1973. IWL_DEBUG_INFO(priv,
  1974. "Copying (but not loading) init instr len %zd\n", len);
  1975. memcpy(priv->ucode_init.v_addr, src, len);
  1976. src += len;
  1977. }
  1978. /* Initialization data (4th block) */
  1979. if (init_data_size) {
  1980. len = init_data_size;
  1981. IWL_DEBUG_INFO(priv,
  1982. "Copying (but not loading) init data len %zd\n", len);
  1983. memcpy(priv->ucode_init_data.v_addr, src, len);
  1984. src += len;
  1985. }
  1986. /* Bootstrap instructions (5th block) */
  1987. len = boot_size;
  1988. IWL_DEBUG_INFO(priv,
  1989. "Copying (but not loading) boot instr len %zd\n", len);
  1990. memcpy(priv->ucode_boot.v_addr, src, len);
  1991. /* We have our copies now, allow OS release its copies */
  1992. release_firmware(ucode_raw);
  1993. return 0;
  1994. err_pci_alloc:
  1995. IWL_ERR(priv, "failed to allocate pci memory\n");
  1996. ret = -ENOMEM;
  1997. iwl3945_dealloc_ucode_pci(priv);
  1998. err_release:
  1999. release_firmware(ucode_raw);
  2000. error:
  2001. return ret;
  2002. }
  2003. /**
  2004. * iwl3945_set_ucode_ptrs - Set uCode address location
  2005. *
  2006. * Tell initialization uCode where to find runtime uCode.
  2007. *
  2008. * BSM registers initially contain pointers to initialization uCode.
  2009. * We need to replace them to load runtime uCode inst and data,
  2010. * and to save runtime data when powering down.
  2011. */
  2012. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  2013. {
  2014. dma_addr_t pinst;
  2015. dma_addr_t pdata;
  2016. /* bits 31:0 for 3945 */
  2017. pinst = priv->ucode_code.p_addr;
  2018. pdata = priv->ucode_data_backup.p_addr;
  2019. /* Tell bootstrap uCode where to find image to load */
  2020. iwl_legacy_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  2021. iwl_legacy_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  2022. iwl_legacy_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  2023. priv->ucode_data.len);
  2024. /* Inst byte count must be last to set up, bit 31 signals uCode
  2025. * that all new ptr/size info is in place */
  2026. iwl_legacy_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  2027. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  2028. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  2029. return 0;
  2030. }
  2031. /**
  2032. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  2033. *
  2034. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  2035. *
  2036. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  2037. */
  2038. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  2039. {
  2040. /* Check alive response for "valid" sign from uCode */
  2041. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  2042. /* We had an error bringing up the hardware, so take it
  2043. * all the way back down so we can try again */
  2044. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  2045. goto restart;
  2046. }
  2047. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  2048. * This is a paranoid check, because we would not have gotten the
  2049. * "initialize" alive if code weren't properly loaded. */
  2050. if (iwl3945_verify_ucode(priv)) {
  2051. /* Runtime instruction load was bad;
  2052. * take it all the way back down so we can try again */
  2053. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  2054. goto restart;
  2055. }
  2056. /* Send pointers to protocol/runtime uCode image ... init code will
  2057. * load and launch runtime uCode, which will send us another "Alive"
  2058. * notification. */
  2059. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  2060. if (iwl3945_set_ucode_ptrs(priv)) {
  2061. /* Runtime instruction load won't happen;
  2062. * take it all the way back down so we can try again */
  2063. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  2064. goto restart;
  2065. }
  2066. return;
  2067. restart:
  2068. queue_work(priv->workqueue, &priv->restart);
  2069. }
  2070. /**
  2071. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  2072. * from protocol/runtime uCode (initialization uCode's
  2073. * Alive gets handled by iwl3945_init_alive_start()).
  2074. */
  2075. static void iwl3945_alive_start(struct iwl_priv *priv)
  2076. {
  2077. int thermal_spin = 0;
  2078. u32 rfkill;
  2079. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2080. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2081. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2082. /* We had an error bringing up the hardware, so take it
  2083. * all the way back down so we can try again */
  2084. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2085. goto restart;
  2086. }
  2087. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2088. * This is a paranoid check, because we would not have gotten the
  2089. * "runtime" alive if code weren't properly loaded. */
  2090. if (iwl3945_verify_ucode(priv)) {
  2091. /* Runtime instruction load was bad;
  2092. * take it all the way back down so we can try again */
  2093. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2094. goto restart;
  2095. }
  2096. rfkill = iwl_legacy_read_prph(priv, APMG_RFKILL_REG);
  2097. IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
  2098. if (rfkill & 0x1) {
  2099. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2100. /* if RFKILL is not on, then wait for thermal
  2101. * sensor in adapter to kick in */
  2102. while (iwl3945_hw_get_temperature(priv) == 0) {
  2103. thermal_spin++;
  2104. udelay(10);
  2105. }
  2106. if (thermal_spin)
  2107. IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
  2108. thermal_spin * 10);
  2109. } else
  2110. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2111. /* After the ALIVE response, we can send commands to 3945 uCode */
  2112. set_bit(STATUS_ALIVE, &priv->status);
  2113. /* Enable watchdog to monitor the driver tx queues */
  2114. iwl_legacy_setup_watchdog(priv);
  2115. if (iwl_legacy_is_rfkill(priv))
  2116. return;
  2117. ieee80211_wake_queues(priv->hw);
  2118. priv->active_rate = IWL_RATES_MASK_3945;
  2119. iwl_legacy_power_update_mode(priv, true);
  2120. if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2121. struct iwl3945_rxon_cmd *active_rxon =
  2122. (struct iwl3945_rxon_cmd *)(&ctx->active);
  2123. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2124. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2125. } else {
  2126. /* Initialize our rx_config data */
  2127. iwl_legacy_connection_init_rx_config(priv, ctx);
  2128. }
  2129. /* Configure Bluetooth device coexistence support */
  2130. iwl_legacy_send_bt_config(priv);
  2131. set_bit(STATUS_READY, &priv->status);
  2132. /* Configure the adapter for unassociated operation */
  2133. iwl3945_commit_rxon(priv, ctx);
  2134. iwl3945_reg_txpower_periodic(priv);
  2135. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2136. wake_up_interruptible(&priv->wait_command_queue);
  2137. return;
  2138. restart:
  2139. queue_work(priv->workqueue, &priv->restart);
  2140. }
  2141. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  2142. static void __iwl3945_down(struct iwl_priv *priv)
  2143. {
  2144. unsigned long flags;
  2145. int exit_pending;
  2146. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2147. iwl_legacy_scan_cancel_timeout(priv, 200);
  2148. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  2149. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2150. * to prevent rearm timer */
  2151. del_timer_sync(&priv->watchdog);
  2152. /* Station information will now be cleared in device */
  2153. iwl_legacy_clear_ucode_stations(priv, NULL);
  2154. iwl_legacy_dealloc_bcast_stations(priv);
  2155. iwl_legacy_clear_driver_stations(priv);
  2156. /* Unblock any waiting calls */
  2157. wake_up_interruptible_all(&priv->wait_command_queue);
  2158. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2159. * exiting the module */
  2160. if (!exit_pending)
  2161. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2162. /* stop and reset the on-board processor */
  2163. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2164. /* tell the device to stop sending interrupts */
  2165. spin_lock_irqsave(&priv->lock, flags);
  2166. iwl_legacy_disable_interrupts(priv);
  2167. spin_unlock_irqrestore(&priv->lock, flags);
  2168. iwl3945_synchronize_irq(priv);
  2169. if (priv->mac80211_registered)
  2170. ieee80211_stop_queues(priv->hw);
  2171. /* If we have not previously called iwl3945_init() then
  2172. * clear all bits but the RF Kill bits and return */
  2173. if (!iwl_legacy_is_init(priv)) {
  2174. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2175. STATUS_RF_KILL_HW |
  2176. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2177. STATUS_GEO_CONFIGURED |
  2178. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2179. STATUS_EXIT_PENDING;
  2180. goto exit;
  2181. }
  2182. /* ...otherwise clear out all the status bits but the RF Kill
  2183. * bit and continue taking the NIC down. */
  2184. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2185. STATUS_RF_KILL_HW |
  2186. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2187. STATUS_GEO_CONFIGURED |
  2188. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2189. STATUS_FW_ERROR |
  2190. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2191. STATUS_EXIT_PENDING;
  2192. iwl3945_hw_txq_ctx_stop(priv);
  2193. iwl3945_hw_rxq_stop(priv);
  2194. /* Power-down device's busmaster DMA clocks */
  2195. iwl_legacy_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2196. udelay(5);
  2197. /* Stop the device, and put it in low power state */
  2198. iwl_legacy_apm_stop(priv);
  2199. exit:
  2200. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2201. if (priv->beacon_skb)
  2202. dev_kfree_skb(priv->beacon_skb);
  2203. priv->beacon_skb = NULL;
  2204. /* clear out any free frames */
  2205. iwl3945_clear_free_frames(priv);
  2206. }
  2207. static void iwl3945_down(struct iwl_priv *priv)
  2208. {
  2209. mutex_lock(&priv->mutex);
  2210. __iwl3945_down(priv);
  2211. mutex_unlock(&priv->mutex);
  2212. iwl3945_cancel_deferred_work(priv);
  2213. }
  2214. #define MAX_HW_RESTARTS 5
  2215. static int iwl3945_alloc_bcast_station(struct iwl_priv *priv)
  2216. {
  2217. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2218. unsigned long flags;
  2219. u8 sta_id;
  2220. spin_lock_irqsave(&priv->sta_lock, flags);
  2221. sta_id = iwl_legacy_prep_station(priv, ctx,
  2222. iwlegacy_bcast_addr, false, NULL);
  2223. if (sta_id == IWL_INVALID_STATION) {
  2224. IWL_ERR(priv, "Unable to prepare broadcast station\n");
  2225. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2226. return -EINVAL;
  2227. }
  2228. priv->stations[sta_id].used |= IWL_STA_DRIVER_ACTIVE;
  2229. priv->stations[sta_id].used |= IWL_STA_BCAST;
  2230. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2231. return 0;
  2232. }
  2233. static int __iwl3945_up(struct iwl_priv *priv)
  2234. {
  2235. int rc, i;
  2236. rc = iwl3945_alloc_bcast_station(priv);
  2237. if (rc)
  2238. return rc;
  2239. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2240. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2241. return -EIO;
  2242. }
  2243. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2244. IWL_ERR(priv, "ucode not available for device bring up\n");
  2245. return -EIO;
  2246. }
  2247. /* If platform's RF_KILL switch is NOT set to KILL */
  2248. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2249. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2250. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2251. else {
  2252. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2253. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2254. return -ENODEV;
  2255. }
  2256. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2257. rc = iwl3945_hw_nic_init(priv);
  2258. if (rc) {
  2259. IWL_ERR(priv, "Unable to int nic\n");
  2260. return rc;
  2261. }
  2262. /* make sure rfkill handshake bits are cleared */
  2263. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2264. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2265. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2266. /* clear (again), then enable host interrupts */
  2267. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2268. iwl_legacy_enable_interrupts(priv);
  2269. /* really make sure rfkill handshake bits are cleared */
  2270. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2271. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2272. /* Copy original ucode data image from disk into backup cache.
  2273. * This will be used to initialize the on-board processor's
  2274. * data SRAM for a clean start when the runtime program first loads. */
  2275. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2276. priv->ucode_data.len);
  2277. /* We return success when we resume from suspend and rf_kill is on. */
  2278. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  2279. return 0;
  2280. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2281. /* load bootstrap state machine,
  2282. * load bootstrap program into processor's memory,
  2283. * prepare to load the "initialize" uCode */
  2284. rc = priv->cfg->ops->lib->load_ucode(priv);
  2285. if (rc) {
  2286. IWL_ERR(priv,
  2287. "Unable to set up bootstrap uCode: %d\n", rc);
  2288. continue;
  2289. }
  2290. /* start card; "initialize" will load runtime ucode */
  2291. iwl3945_nic_start(priv);
  2292. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2293. return 0;
  2294. }
  2295. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2296. __iwl3945_down(priv);
  2297. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2298. /* tried to restart and config the device for as long as our
  2299. * patience could withstand */
  2300. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2301. return -EIO;
  2302. }
  2303. /*****************************************************************************
  2304. *
  2305. * Workqueue callbacks
  2306. *
  2307. *****************************************************************************/
  2308. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  2309. {
  2310. struct iwl_priv *priv =
  2311. container_of(data, struct iwl_priv, init_alive_start.work);
  2312. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2313. return;
  2314. mutex_lock(&priv->mutex);
  2315. iwl3945_init_alive_start(priv);
  2316. mutex_unlock(&priv->mutex);
  2317. }
  2318. static void iwl3945_bg_alive_start(struct work_struct *data)
  2319. {
  2320. struct iwl_priv *priv =
  2321. container_of(data, struct iwl_priv, alive_start.work);
  2322. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2323. return;
  2324. mutex_lock(&priv->mutex);
  2325. iwl3945_alive_start(priv);
  2326. mutex_unlock(&priv->mutex);
  2327. }
  2328. /*
  2329. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2330. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2331. * *is* readable even when device has been SW_RESET into low power mode
  2332. * (e.g. during RF KILL).
  2333. */
  2334. static void iwl3945_rfkill_poll(struct work_struct *data)
  2335. {
  2336. struct iwl_priv *priv =
  2337. container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
  2338. bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
  2339. bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
  2340. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2341. if (new_rfkill != old_rfkill) {
  2342. if (new_rfkill)
  2343. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2344. else
  2345. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2346. wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
  2347. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  2348. new_rfkill ? "disable radio" : "enable radio");
  2349. }
  2350. /* Keep this running, even if radio now enabled. This will be
  2351. * cancelled in mac_start() if system decides to start again */
  2352. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2353. round_jiffies_relative(2 * HZ));
  2354. }
  2355. int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2356. {
  2357. struct iwl_host_cmd cmd = {
  2358. .id = REPLY_SCAN_CMD,
  2359. .len = sizeof(struct iwl3945_scan_cmd),
  2360. .flags = CMD_SIZE_HUGE,
  2361. };
  2362. struct iwl3945_scan_cmd *scan;
  2363. u8 n_probes = 0;
  2364. enum ieee80211_band band;
  2365. bool is_active = false;
  2366. int ret;
  2367. lockdep_assert_held(&priv->mutex);
  2368. if (!priv->scan_cmd) {
  2369. priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  2370. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  2371. if (!priv->scan_cmd) {
  2372. IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
  2373. return -ENOMEM;
  2374. }
  2375. }
  2376. scan = priv->scan_cmd;
  2377. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  2378. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  2379. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  2380. if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2381. u16 interval = 0;
  2382. u32 extra;
  2383. u32 suspend_time = 100;
  2384. u32 scan_suspend_time = 100;
  2385. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  2386. if (priv->is_internal_short_scan)
  2387. interval = 0;
  2388. else
  2389. interval = vif->bss_conf.beacon_int;
  2390. scan->suspend_time = 0;
  2391. scan->max_out_time = cpu_to_le32(200 * 1024);
  2392. if (!interval)
  2393. interval = suspend_time;
  2394. /*
  2395. * suspend time format:
  2396. * 0-19: beacon interval in usec (time before exec.)
  2397. * 20-23: 0
  2398. * 24-31: number of beacons (suspend between channels)
  2399. */
  2400. extra = (suspend_time / interval) << 24;
  2401. scan_suspend_time = 0xFF0FFFFF &
  2402. (extra | ((suspend_time % interval) * 1024));
  2403. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2404. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  2405. scan_suspend_time, interval);
  2406. }
  2407. if (priv->is_internal_short_scan) {
  2408. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  2409. } else if (priv->scan_request->n_ssids) {
  2410. int i, p = 0;
  2411. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  2412. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  2413. /* always does wildcard anyway */
  2414. if (!priv->scan_request->ssids[i].ssid_len)
  2415. continue;
  2416. scan->direct_scan[p].id = WLAN_EID_SSID;
  2417. scan->direct_scan[p].len =
  2418. priv->scan_request->ssids[i].ssid_len;
  2419. memcpy(scan->direct_scan[p].ssid,
  2420. priv->scan_request->ssids[i].ssid,
  2421. priv->scan_request->ssids[i].ssid_len);
  2422. n_probes++;
  2423. p++;
  2424. }
  2425. is_active = true;
  2426. } else
  2427. IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
  2428. /* We don't build a direct scan probe request; the uCode will do
  2429. * that based on the direct_mask added to each channel entry */
  2430. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2431. scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
  2432. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2433. /* flags + rate selection */
  2434. switch (priv->scan_band) {
  2435. case IEEE80211_BAND_2GHZ:
  2436. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2437. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  2438. band = IEEE80211_BAND_2GHZ;
  2439. break;
  2440. case IEEE80211_BAND_5GHZ:
  2441. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  2442. band = IEEE80211_BAND_5GHZ;
  2443. break;
  2444. default:
  2445. IWL_WARN(priv, "Invalid scan band\n");
  2446. return -EIO;
  2447. }
  2448. /*
  2449. * If active scaning is requested but a certain channel
  2450. * is marked passive, we can do active scanning if we
  2451. * detect transmissions.
  2452. */
  2453. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  2454. IWL_GOOD_CRC_TH_DISABLED;
  2455. if (!priv->is_internal_short_scan) {
  2456. scan->tx_cmd.len = cpu_to_le16(
  2457. iwl_legacy_fill_probe_req(priv,
  2458. (struct ieee80211_mgmt *)scan->data,
  2459. vif->addr,
  2460. priv->scan_request->ie,
  2461. priv->scan_request->ie_len,
  2462. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2463. } else {
  2464. /* use bcast addr, will not be transmitted but must be valid */
  2465. scan->tx_cmd.len = cpu_to_le16(
  2466. iwl_legacy_fill_probe_req(priv,
  2467. (struct ieee80211_mgmt *)scan->data,
  2468. iwlegacy_bcast_addr, NULL, 0,
  2469. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2470. }
  2471. /* select Rx antennas */
  2472. scan->flags |= iwl3945_get_antenna_flags(priv);
  2473. if (priv->is_internal_short_scan) {
  2474. scan->channel_count =
  2475. iwl3945_get_single_channel_for_scan(priv, vif, band,
  2476. (void *)&scan->data[le16_to_cpu(
  2477. scan->tx_cmd.len)]);
  2478. } else {
  2479. scan->channel_count =
  2480. iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
  2481. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
  2482. }
  2483. if (scan->channel_count == 0) {
  2484. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  2485. return -EIO;
  2486. }
  2487. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2488. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  2489. cmd.data = scan;
  2490. scan->len = cpu_to_le16(cmd.len);
  2491. set_bit(STATUS_SCAN_HW, &priv->status);
  2492. ret = iwl_legacy_send_cmd_sync(priv, &cmd);
  2493. if (ret)
  2494. clear_bit(STATUS_SCAN_HW, &priv->status);
  2495. return ret;
  2496. }
  2497. void iwl3945_post_scan(struct iwl_priv *priv)
  2498. {
  2499. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2500. /*
  2501. * Since setting the RXON may have been deferred while
  2502. * performing the scan, fire one off if needed
  2503. */
  2504. if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
  2505. iwl3945_commit_rxon(priv, ctx);
  2506. }
  2507. static void iwl3945_bg_restart(struct work_struct *data)
  2508. {
  2509. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2510. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2511. return;
  2512. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2513. struct iwl_rxon_context *ctx;
  2514. mutex_lock(&priv->mutex);
  2515. for_each_context(priv, ctx)
  2516. ctx->vif = NULL;
  2517. priv->is_open = 0;
  2518. mutex_unlock(&priv->mutex);
  2519. iwl3945_down(priv);
  2520. ieee80211_restart_hw(priv->hw);
  2521. } else {
  2522. iwl3945_down(priv);
  2523. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2524. return;
  2525. mutex_lock(&priv->mutex);
  2526. __iwl3945_up(priv);
  2527. mutex_unlock(&priv->mutex);
  2528. }
  2529. }
  2530. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  2531. {
  2532. struct iwl_priv *priv =
  2533. container_of(data, struct iwl_priv, rx_replenish);
  2534. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2535. return;
  2536. mutex_lock(&priv->mutex);
  2537. iwl3945_rx_replenish(priv);
  2538. mutex_unlock(&priv->mutex);
  2539. }
  2540. void iwl3945_post_associate(struct iwl_priv *priv)
  2541. {
  2542. int rc = 0;
  2543. struct ieee80211_conf *conf = NULL;
  2544. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2545. if (!ctx->vif || !priv->is_open)
  2546. return;
  2547. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2548. ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
  2549. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2550. return;
  2551. iwl_legacy_scan_cancel_timeout(priv, 200);
  2552. conf = iwl_legacy_ieee80211_get_hw_conf(priv->hw);
  2553. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2554. iwl3945_commit_rxon(priv, ctx);
  2555. rc = iwl_legacy_send_rxon_timing(priv, ctx);
  2556. if (rc)
  2557. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2558. "Attempting to continue.\n");
  2559. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2560. ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
  2561. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2562. ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
  2563. if (ctx->vif->bss_conf.use_short_preamble)
  2564. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2565. else
  2566. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2567. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2568. if (ctx->vif->bss_conf.use_short_slot)
  2569. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2570. else
  2571. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2572. }
  2573. iwl3945_commit_rxon(priv, ctx);
  2574. switch (ctx->vif->type) {
  2575. case NL80211_IFTYPE_STATION:
  2576. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  2577. break;
  2578. case NL80211_IFTYPE_ADHOC:
  2579. iwl3945_send_beacon_cmd(priv);
  2580. break;
  2581. default:
  2582. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2583. __func__, ctx->vif->type);
  2584. break;
  2585. }
  2586. }
  2587. /*****************************************************************************
  2588. *
  2589. * mac80211 entry point functions
  2590. *
  2591. *****************************************************************************/
  2592. #define UCODE_READY_TIMEOUT (2 * HZ)
  2593. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  2594. {
  2595. struct iwl_priv *priv = hw->priv;
  2596. int ret;
  2597. IWL_DEBUG_MAC80211(priv, "enter\n");
  2598. /* we should be verifying the device is ready to be opened */
  2599. mutex_lock(&priv->mutex);
  2600. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2601. * ucode filename and max sizes are card-specific. */
  2602. if (!priv->ucode_code.len) {
  2603. ret = iwl3945_read_ucode(priv);
  2604. if (ret) {
  2605. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2606. mutex_unlock(&priv->mutex);
  2607. goto out_release_irq;
  2608. }
  2609. }
  2610. ret = __iwl3945_up(priv);
  2611. mutex_unlock(&priv->mutex);
  2612. if (ret)
  2613. goto out_release_irq;
  2614. IWL_DEBUG_INFO(priv, "Start UP work.\n");
  2615. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2616. * mac80211 will not be run successfully. */
  2617. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2618. test_bit(STATUS_READY, &priv->status),
  2619. UCODE_READY_TIMEOUT);
  2620. if (!ret) {
  2621. if (!test_bit(STATUS_READY, &priv->status)) {
  2622. IWL_ERR(priv,
  2623. "Wait for START_ALIVE timeout after %dms.\n",
  2624. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2625. ret = -ETIMEDOUT;
  2626. goto out_release_irq;
  2627. }
  2628. }
  2629. /* ucode is running and will send rfkill notifications,
  2630. * no need to poll the killswitch state anymore */
  2631. cancel_delayed_work(&priv->_3945.rfkill_poll);
  2632. priv->is_open = 1;
  2633. IWL_DEBUG_MAC80211(priv, "leave\n");
  2634. return 0;
  2635. out_release_irq:
  2636. priv->is_open = 0;
  2637. IWL_DEBUG_MAC80211(priv, "leave - failed\n");
  2638. return ret;
  2639. }
  2640. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  2641. {
  2642. struct iwl_priv *priv = hw->priv;
  2643. IWL_DEBUG_MAC80211(priv, "enter\n");
  2644. if (!priv->is_open) {
  2645. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  2646. return;
  2647. }
  2648. priv->is_open = 0;
  2649. iwl3945_down(priv);
  2650. flush_workqueue(priv->workqueue);
  2651. /* start polling the killswitch state again */
  2652. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2653. round_jiffies_relative(2 * HZ));
  2654. IWL_DEBUG_MAC80211(priv, "leave\n");
  2655. }
  2656. static void iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2657. {
  2658. struct iwl_priv *priv = hw->priv;
  2659. IWL_DEBUG_MAC80211(priv, "enter\n");
  2660. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2661. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2662. if (iwl3945_tx_skb(priv, skb))
  2663. dev_kfree_skb_any(skb);
  2664. IWL_DEBUG_MAC80211(priv, "leave\n");
  2665. }
  2666. void iwl3945_config_ap(struct iwl_priv *priv)
  2667. {
  2668. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2669. struct ieee80211_vif *vif = ctx->vif;
  2670. int rc = 0;
  2671. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2672. return;
  2673. /* The following should be done only at AP bring up */
  2674. if (!(iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS))) {
  2675. /* RXON - unassoc (to set timing command) */
  2676. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2677. iwl3945_commit_rxon(priv, ctx);
  2678. /* RXON Timing */
  2679. rc = iwl_legacy_send_rxon_timing(priv, ctx);
  2680. if (rc)
  2681. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2682. "Attempting to continue.\n");
  2683. ctx->staging.assoc_id = 0;
  2684. if (vif->bss_conf.use_short_preamble)
  2685. ctx->staging.flags |=
  2686. RXON_FLG_SHORT_PREAMBLE_MSK;
  2687. else
  2688. ctx->staging.flags &=
  2689. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2690. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2691. if (vif->bss_conf.use_short_slot)
  2692. ctx->staging.flags |=
  2693. RXON_FLG_SHORT_SLOT_MSK;
  2694. else
  2695. ctx->staging.flags &=
  2696. ~RXON_FLG_SHORT_SLOT_MSK;
  2697. }
  2698. /* restore RXON assoc */
  2699. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2700. iwl3945_commit_rxon(priv, ctx);
  2701. }
  2702. iwl3945_send_beacon_cmd(priv);
  2703. }
  2704. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2705. struct ieee80211_vif *vif,
  2706. struct ieee80211_sta *sta,
  2707. struct ieee80211_key_conf *key)
  2708. {
  2709. struct iwl_priv *priv = hw->priv;
  2710. int ret = 0;
  2711. u8 sta_id = IWL_INVALID_STATION;
  2712. u8 static_key;
  2713. IWL_DEBUG_MAC80211(priv, "enter\n");
  2714. if (iwl3945_mod_params.sw_crypto) {
  2715. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2716. return -EOPNOTSUPP;
  2717. }
  2718. /*
  2719. * To support IBSS RSN, don't program group keys in IBSS, the
  2720. * hardware will then not attempt to decrypt the frames.
  2721. */
  2722. if (vif->type == NL80211_IFTYPE_ADHOC &&
  2723. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  2724. return -EOPNOTSUPP;
  2725. static_key = !iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS);
  2726. if (!static_key) {
  2727. sta_id = iwl_legacy_sta_id_or_broadcast(
  2728. priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
  2729. if (sta_id == IWL_INVALID_STATION)
  2730. return -EINVAL;
  2731. }
  2732. mutex_lock(&priv->mutex);
  2733. iwl_legacy_scan_cancel_timeout(priv, 100);
  2734. switch (cmd) {
  2735. case SET_KEY:
  2736. if (static_key)
  2737. ret = iwl3945_set_static_key(priv, key);
  2738. else
  2739. ret = iwl3945_set_dynamic_key(priv, key, sta_id);
  2740. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2741. break;
  2742. case DISABLE_KEY:
  2743. if (static_key)
  2744. ret = iwl3945_remove_static_key(priv);
  2745. else
  2746. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  2747. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2748. break;
  2749. default:
  2750. ret = -EINVAL;
  2751. }
  2752. mutex_unlock(&priv->mutex);
  2753. IWL_DEBUG_MAC80211(priv, "leave\n");
  2754. return ret;
  2755. }
  2756. static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
  2757. struct ieee80211_vif *vif,
  2758. struct ieee80211_sta *sta)
  2759. {
  2760. struct iwl_priv *priv = hw->priv;
  2761. struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2762. int ret;
  2763. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2764. u8 sta_id;
  2765. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2766. sta->addr);
  2767. mutex_lock(&priv->mutex);
  2768. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2769. sta->addr);
  2770. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2771. ret = iwl_legacy_add_station_common(priv,
  2772. &priv->contexts[IWL_RXON_CTX_BSS],
  2773. sta->addr, is_ap, sta, &sta_id);
  2774. if (ret) {
  2775. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2776. sta->addr, ret);
  2777. /* Should we return success if return code is EEXIST ? */
  2778. mutex_unlock(&priv->mutex);
  2779. return ret;
  2780. }
  2781. sta_priv->common.sta_id = sta_id;
  2782. /* Initialize rate scaling */
  2783. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2784. sta->addr);
  2785. iwl3945_rs_rate_init(priv, sta, sta_id);
  2786. mutex_unlock(&priv->mutex);
  2787. return 0;
  2788. }
  2789. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  2790. unsigned int changed_flags,
  2791. unsigned int *total_flags,
  2792. u64 multicast)
  2793. {
  2794. struct iwl_priv *priv = hw->priv;
  2795. __le32 filter_or = 0, filter_nand = 0;
  2796. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2797. #define CHK(test, flag) do { \
  2798. if (*total_flags & (test)) \
  2799. filter_or |= (flag); \
  2800. else \
  2801. filter_nand |= (flag); \
  2802. } while (0)
  2803. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2804. changed_flags, *total_flags);
  2805. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2806. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2807. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2808. #undef CHK
  2809. mutex_lock(&priv->mutex);
  2810. ctx->staging.filter_flags &= ~filter_nand;
  2811. ctx->staging.filter_flags |= filter_or;
  2812. /*
  2813. * Not committing directly because hardware can perform a scan,
  2814. * but even if hw is ready, committing here breaks for some reason,
  2815. * we'll eventually commit the filter flags change anyway.
  2816. */
  2817. mutex_unlock(&priv->mutex);
  2818. /*
  2819. * Receiving all multicast frames is always enabled by the
  2820. * default flags setup in iwl_legacy_connection_init_rx_config()
  2821. * since we currently do not support programming multicast
  2822. * filters into the device.
  2823. */
  2824. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2825. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2826. }
  2827. /*****************************************************************************
  2828. *
  2829. * sysfs attributes
  2830. *
  2831. *****************************************************************************/
  2832. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  2833. /*
  2834. * The following adds a new attribute to the sysfs representation
  2835. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2836. * used for controlling the debug level.
  2837. *
  2838. * See the level definitions in iwl for details.
  2839. *
  2840. * The debug_level being managed using sysfs below is a per device debug
  2841. * level that is used instead of the global debug level if it (the per
  2842. * device debug level) is set.
  2843. */
  2844. static ssize_t iwl3945_show_debug_level(struct device *d,
  2845. struct device_attribute *attr, char *buf)
  2846. {
  2847. struct iwl_priv *priv = dev_get_drvdata(d);
  2848. return sprintf(buf, "0x%08X\n", iwl_legacy_get_debug_level(priv));
  2849. }
  2850. static ssize_t iwl3945_store_debug_level(struct device *d,
  2851. struct device_attribute *attr,
  2852. const char *buf, size_t count)
  2853. {
  2854. struct iwl_priv *priv = dev_get_drvdata(d);
  2855. unsigned long val;
  2856. int ret;
  2857. ret = strict_strtoul(buf, 0, &val);
  2858. if (ret)
  2859. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  2860. else {
  2861. priv->debug_level = val;
  2862. if (iwl_legacy_alloc_traffic_mem(priv))
  2863. IWL_ERR(priv,
  2864. "Not enough memory to generate traffic log\n");
  2865. }
  2866. return strnlen(buf, count);
  2867. }
  2868. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2869. iwl3945_show_debug_level, iwl3945_store_debug_level);
  2870. #endif /* CONFIG_IWLWIFI_LEGACY_DEBUG */
  2871. static ssize_t iwl3945_show_temperature(struct device *d,
  2872. struct device_attribute *attr, char *buf)
  2873. {
  2874. struct iwl_priv *priv = dev_get_drvdata(d);
  2875. if (!iwl_legacy_is_alive(priv))
  2876. return -EAGAIN;
  2877. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  2878. }
  2879. static DEVICE_ATTR(temperature, S_IRUGO, iwl3945_show_temperature, NULL);
  2880. static ssize_t iwl3945_show_tx_power(struct device *d,
  2881. struct device_attribute *attr, char *buf)
  2882. {
  2883. struct iwl_priv *priv = dev_get_drvdata(d);
  2884. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2885. }
  2886. static ssize_t iwl3945_store_tx_power(struct device *d,
  2887. struct device_attribute *attr,
  2888. const char *buf, size_t count)
  2889. {
  2890. struct iwl_priv *priv = dev_get_drvdata(d);
  2891. char *p = (char *)buf;
  2892. u32 val;
  2893. val = simple_strtoul(p, &p, 10);
  2894. if (p == buf)
  2895. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  2896. else
  2897. iwl3945_hw_reg_set_txpower(priv, val);
  2898. return count;
  2899. }
  2900. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, iwl3945_show_tx_power, iwl3945_store_tx_power);
  2901. static ssize_t iwl3945_show_flags(struct device *d,
  2902. struct device_attribute *attr, char *buf)
  2903. {
  2904. struct iwl_priv *priv = dev_get_drvdata(d);
  2905. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2906. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2907. }
  2908. static ssize_t iwl3945_store_flags(struct device *d,
  2909. struct device_attribute *attr,
  2910. const char *buf, size_t count)
  2911. {
  2912. struct iwl_priv *priv = dev_get_drvdata(d);
  2913. u32 flags = simple_strtoul(buf, NULL, 0);
  2914. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2915. mutex_lock(&priv->mutex);
  2916. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2917. /* Cancel any currently running scans... */
  2918. if (iwl_legacy_scan_cancel_timeout(priv, 100))
  2919. IWL_WARN(priv, "Could not cancel scan.\n");
  2920. else {
  2921. IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
  2922. flags);
  2923. ctx->staging.flags = cpu_to_le32(flags);
  2924. iwl3945_commit_rxon(priv, ctx);
  2925. }
  2926. }
  2927. mutex_unlock(&priv->mutex);
  2928. return count;
  2929. }
  2930. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, iwl3945_show_flags, iwl3945_store_flags);
  2931. static ssize_t iwl3945_show_filter_flags(struct device *d,
  2932. struct device_attribute *attr, char *buf)
  2933. {
  2934. struct iwl_priv *priv = dev_get_drvdata(d);
  2935. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2936. return sprintf(buf, "0x%04X\n",
  2937. le32_to_cpu(ctx->active.filter_flags));
  2938. }
  2939. static ssize_t iwl3945_store_filter_flags(struct device *d,
  2940. struct device_attribute *attr,
  2941. const char *buf, size_t count)
  2942. {
  2943. struct iwl_priv *priv = dev_get_drvdata(d);
  2944. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2945. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  2946. mutex_lock(&priv->mutex);
  2947. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  2948. /* Cancel any currently running scans... */
  2949. if (iwl_legacy_scan_cancel_timeout(priv, 100))
  2950. IWL_WARN(priv, "Could not cancel scan.\n");
  2951. else {
  2952. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2953. "0x%04X\n", filter_flags);
  2954. ctx->staging.filter_flags =
  2955. cpu_to_le32(filter_flags);
  2956. iwl3945_commit_rxon(priv, ctx);
  2957. }
  2958. }
  2959. mutex_unlock(&priv->mutex);
  2960. return count;
  2961. }
  2962. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, iwl3945_show_filter_flags,
  2963. iwl3945_store_filter_flags);
  2964. static ssize_t iwl3945_show_measurement(struct device *d,
  2965. struct device_attribute *attr, char *buf)
  2966. {
  2967. struct iwl_priv *priv = dev_get_drvdata(d);
  2968. struct iwl_spectrum_notification measure_report;
  2969. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  2970. u8 *data = (u8 *)&measure_report;
  2971. unsigned long flags;
  2972. spin_lock_irqsave(&priv->lock, flags);
  2973. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  2974. spin_unlock_irqrestore(&priv->lock, flags);
  2975. return 0;
  2976. }
  2977. memcpy(&measure_report, &priv->measure_report, size);
  2978. priv->measurement_status = 0;
  2979. spin_unlock_irqrestore(&priv->lock, flags);
  2980. while (size && (PAGE_SIZE - len)) {
  2981. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2982. PAGE_SIZE - len, 1);
  2983. len = strlen(buf);
  2984. if (PAGE_SIZE - len)
  2985. buf[len++] = '\n';
  2986. ofs += 16;
  2987. size -= min(size, 16U);
  2988. }
  2989. return len;
  2990. }
  2991. static ssize_t iwl3945_store_measurement(struct device *d,
  2992. struct device_attribute *attr,
  2993. const char *buf, size_t count)
  2994. {
  2995. struct iwl_priv *priv = dev_get_drvdata(d);
  2996. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2997. struct ieee80211_measurement_params params = {
  2998. .channel = le16_to_cpu(ctx->active.channel),
  2999. .start_time = cpu_to_le64(priv->_3945.last_tsf),
  3000. .duration = cpu_to_le16(1),
  3001. };
  3002. u8 type = IWL_MEASURE_BASIC;
  3003. u8 buffer[32];
  3004. u8 channel;
  3005. if (count) {
  3006. char *p = buffer;
  3007. strncpy(buffer, buf, min(sizeof(buffer), count));
  3008. channel = simple_strtoul(p, NULL, 0);
  3009. if (channel)
  3010. params.channel = channel;
  3011. p = buffer;
  3012. while (*p && *p != ' ')
  3013. p++;
  3014. if (*p)
  3015. type = simple_strtoul(p + 1, NULL, 0);
  3016. }
  3017. IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
  3018. "channel %d (for '%s')\n", type, params.channel, buf);
  3019. iwl3945_get_measurement(priv, &params, type);
  3020. return count;
  3021. }
  3022. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  3023. iwl3945_show_measurement, iwl3945_store_measurement);
  3024. static ssize_t iwl3945_store_retry_rate(struct device *d,
  3025. struct device_attribute *attr,
  3026. const char *buf, size_t count)
  3027. {
  3028. struct iwl_priv *priv = dev_get_drvdata(d);
  3029. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  3030. if (priv->retry_rate <= 0)
  3031. priv->retry_rate = 1;
  3032. return count;
  3033. }
  3034. static ssize_t iwl3945_show_retry_rate(struct device *d,
  3035. struct device_attribute *attr, char *buf)
  3036. {
  3037. struct iwl_priv *priv = dev_get_drvdata(d);
  3038. return sprintf(buf, "%d", priv->retry_rate);
  3039. }
  3040. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, iwl3945_show_retry_rate,
  3041. iwl3945_store_retry_rate);
  3042. static ssize_t iwl3945_show_channels(struct device *d,
  3043. struct device_attribute *attr, char *buf)
  3044. {
  3045. /* all this shit doesn't belong into sysfs anyway */
  3046. return 0;
  3047. }
  3048. static DEVICE_ATTR(channels, S_IRUSR, iwl3945_show_channels, NULL);
  3049. static ssize_t iwl3945_show_antenna(struct device *d,
  3050. struct device_attribute *attr, char *buf)
  3051. {
  3052. struct iwl_priv *priv = dev_get_drvdata(d);
  3053. if (!iwl_legacy_is_alive(priv))
  3054. return -EAGAIN;
  3055. return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
  3056. }
  3057. static ssize_t iwl3945_store_antenna(struct device *d,
  3058. struct device_attribute *attr,
  3059. const char *buf, size_t count)
  3060. {
  3061. struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
  3062. int ant;
  3063. if (count == 0)
  3064. return 0;
  3065. if (sscanf(buf, "%1i", &ant) != 1) {
  3066. IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
  3067. return count;
  3068. }
  3069. if ((ant >= 0) && (ant <= 2)) {
  3070. IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
  3071. iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
  3072. } else
  3073. IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
  3074. return count;
  3075. }
  3076. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, iwl3945_show_antenna, iwl3945_store_antenna);
  3077. static ssize_t iwl3945_show_status(struct device *d,
  3078. struct device_attribute *attr, char *buf)
  3079. {
  3080. struct iwl_priv *priv = dev_get_drvdata(d);
  3081. if (!iwl_legacy_is_alive(priv))
  3082. return -EAGAIN;
  3083. return sprintf(buf, "0x%08x\n", (int)priv->status);
  3084. }
  3085. static DEVICE_ATTR(status, S_IRUGO, iwl3945_show_status, NULL);
  3086. static ssize_t iwl3945_dump_error_log(struct device *d,
  3087. struct device_attribute *attr,
  3088. const char *buf, size_t count)
  3089. {
  3090. struct iwl_priv *priv = dev_get_drvdata(d);
  3091. char *p = (char *)buf;
  3092. if (p[0] == '1')
  3093. iwl3945_dump_nic_error_log(priv);
  3094. return strnlen(buf, count);
  3095. }
  3096. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, iwl3945_dump_error_log);
  3097. /*****************************************************************************
  3098. *
  3099. * driver setup and tear down
  3100. *
  3101. *****************************************************************************/
  3102. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  3103. {
  3104. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3105. init_waitqueue_head(&priv->wait_command_queue);
  3106. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  3107. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  3108. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  3109. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  3110. INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
  3111. iwl_legacy_setup_scan_deferred_work(priv);
  3112. iwl3945_hw_setup_deferred_work(priv);
  3113. init_timer(&priv->watchdog);
  3114. priv->watchdog.data = (unsigned long)priv;
  3115. priv->watchdog.function = iwl_legacy_bg_watchdog;
  3116. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3117. iwl3945_irq_tasklet, (unsigned long)priv);
  3118. }
  3119. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  3120. {
  3121. iwl3945_hw_cancel_deferred_work(priv);
  3122. cancel_delayed_work_sync(&priv->init_alive_start);
  3123. cancel_delayed_work(&priv->alive_start);
  3124. iwl_legacy_cancel_scan_deferred_work(priv);
  3125. }
  3126. static struct attribute *iwl3945_sysfs_entries[] = {
  3127. &dev_attr_antenna.attr,
  3128. &dev_attr_channels.attr,
  3129. &dev_attr_dump_errors.attr,
  3130. &dev_attr_flags.attr,
  3131. &dev_attr_filter_flags.attr,
  3132. &dev_attr_measurement.attr,
  3133. &dev_attr_retry_rate.attr,
  3134. &dev_attr_status.attr,
  3135. &dev_attr_temperature.attr,
  3136. &dev_attr_tx_power.attr,
  3137. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  3138. &dev_attr_debug_level.attr,
  3139. #endif
  3140. NULL
  3141. };
  3142. static struct attribute_group iwl3945_attribute_group = {
  3143. .name = NULL, /* put in device directory */
  3144. .attrs = iwl3945_sysfs_entries,
  3145. };
  3146. struct ieee80211_ops iwl3945_hw_ops = {
  3147. .tx = iwl3945_mac_tx,
  3148. .start = iwl3945_mac_start,
  3149. .stop = iwl3945_mac_stop,
  3150. .add_interface = iwl_legacy_mac_add_interface,
  3151. .remove_interface = iwl_legacy_mac_remove_interface,
  3152. .change_interface = iwl_legacy_mac_change_interface,
  3153. .config = iwl_legacy_mac_config,
  3154. .configure_filter = iwl3945_configure_filter,
  3155. .set_key = iwl3945_mac_set_key,
  3156. .conf_tx = iwl_legacy_mac_conf_tx,
  3157. .reset_tsf = iwl_legacy_mac_reset_tsf,
  3158. .bss_info_changed = iwl_legacy_mac_bss_info_changed,
  3159. .hw_scan = iwl_legacy_mac_hw_scan,
  3160. .sta_add = iwl3945_mac_sta_add,
  3161. .sta_remove = iwl_legacy_mac_sta_remove,
  3162. .tx_last_beacon = iwl_legacy_mac_tx_last_beacon,
  3163. };
  3164. static int iwl3945_init_drv(struct iwl_priv *priv)
  3165. {
  3166. int ret;
  3167. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3168. priv->retry_rate = 1;
  3169. priv->beacon_skb = NULL;
  3170. spin_lock_init(&priv->sta_lock);
  3171. spin_lock_init(&priv->hcmd_lock);
  3172. INIT_LIST_HEAD(&priv->free_frames);
  3173. mutex_init(&priv->mutex);
  3174. mutex_init(&priv->sync_cmd_mutex);
  3175. priv->ieee_channels = NULL;
  3176. priv->ieee_rates = NULL;
  3177. priv->band = IEEE80211_BAND_2GHZ;
  3178. priv->iw_mode = NL80211_IFTYPE_STATION;
  3179. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3180. /* initialize force reset */
  3181. priv->force_reset[IWL_RF_RESET].reset_duration =
  3182. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3183. priv->force_reset[IWL_FW_RESET].reset_duration =
  3184. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3185. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  3186. priv->tx_power_next = IWL_DEFAULT_TX_POWER;
  3187. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  3188. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3189. eeprom->version);
  3190. ret = -EINVAL;
  3191. goto err;
  3192. }
  3193. ret = iwl_legacy_init_channel_map(priv);
  3194. if (ret) {
  3195. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3196. goto err;
  3197. }
  3198. /* Set up txpower settings in driver for all channels */
  3199. if (iwl3945_txpower_set_from_eeprom(priv)) {
  3200. ret = -EIO;
  3201. goto err_free_channel_map;
  3202. }
  3203. ret = iwl_legacy_init_geos(priv);
  3204. if (ret) {
  3205. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3206. goto err_free_channel_map;
  3207. }
  3208. iwl3945_init_hw_rates(priv, priv->ieee_rates);
  3209. return 0;
  3210. err_free_channel_map:
  3211. iwl_legacy_free_channel_map(priv);
  3212. err:
  3213. return ret;
  3214. }
  3215. #define IWL3945_MAX_PROBE_REQUEST 200
  3216. static int iwl3945_setup_mac(struct iwl_priv *priv)
  3217. {
  3218. int ret;
  3219. struct ieee80211_hw *hw = priv->hw;
  3220. hw->rate_control_algorithm = "iwl-3945-rs";
  3221. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  3222. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  3223. /* Tell mac80211 our characteristics */
  3224. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  3225. IEEE80211_HW_SPECTRUM_MGMT;
  3226. hw->wiphy->interface_modes =
  3227. priv->contexts[IWL_RXON_CTX_BSS].interface_modes;
  3228. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  3229. WIPHY_FLAG_DISABLE_BEACON_HINTS |
  3230. WIPHY_FLAG_IBSS_RSN;
  3231. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  3232. /* we create the 802.11 header and a zero-length SSID element */
  3233. hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
  3234. /* Default value; 4 EDCA QOS priorities */
  3235. hw->queues = 4;
  3236. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3237. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3238. &priv->bands[IEEE80211_BAND_2GHZ];
  3239. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3240. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3241. &priv->bands[IEEE80211_BAND_5GHZ];
  3242. iwl_legacy_leds_init(priv);
  3243. ret = ieee80211_register_hw(priv->hw);
  3244. if (ret) {
  3245. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  3246. return ret;
  3247. }
  3248. priv->mac80211_registered = 1;
  3249. return 0;
  3250. }
  3251. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3252. {
  3253. int err = 0, i;
  3254. struct iwl_priv *priv;
  3255. struct ieee80211_hw *hw;
  3256. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3257. struct iwl3945_eeprom *eeprom;
  3258. unsigned long flags;
  3259. /***********************
  3260. * 1. Allocating HW data
  3261. * ********************/
  3262. /* mac80211 allocates memory for this device instance, including
  3263. * space for this driver's private structure */
  3264. hw = iwl_legacy_alloc_all(cfg);
  3265. if (hw == NULL) {
  3266. pr_err("Can not allocate network device\n");
  3267. err = -ENOMEM;
  3268. goto out;
  3269. }
  3270. priv = hw->priv;
  3271. SET_IEEE80211_DEV(hw, &pdev->dev);
  3272. priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
  3273. /* 3945 has only one valid context */
  3274. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3275. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3276. priv->contexts[i].ctxid = i;
  3277. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3278. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3279. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3280. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3281. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  3282. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  3283. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  3284. BIT(NL80211_IFTYPE_STATION) |
  3285. BIT(NL80211_IFTYPE_ADHOC);
  3286. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  3287. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  3288. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  3289. /*
  3290. * Disabling hardware scan means that mac80211 will perform scans
  3291. * "the hard way", rather than using device's scan.
  3292. */
  3293. if (iwl3945_mod_params.disable_hw_scan) {
  3294. dev_printk(KERN_DEBUG, &(pdev->dev),
  3295. "sw scan support is deprecated\n");
  3296. iwl3945_hw_ops.hw_scan = NULL;
  3297. }
  3298. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3299. priv->cfg = cfg;
  3300. priv->pci_dev = pdev;
  3301. priv->inta_mask = CSR_INI_SET_MASK;
  3302. if (iwl_legacy_alloc_traffic_mem(priv))
  3303. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3304. /***************************
  3305. * 2. Initializing PCI bus
  3306. * *************************/
  3307. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3308. PCIE_LINK_STATE_CLKPM);
  3309. if (pci_enable_device(pdev)) {
  3310. err = -ENODEV;
  3311. goto out_ieee80211_free_hw;
  3312. }
  3313. pci_set_master(pdev);
  3314. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3315. if (!err)
  3316. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3317. if (err) {
  3318. IWL_WARN(priv, "No suitable DMA available.\n");
  3319. goto out_pci_disable_device;
  3320. }
  3321. pci_set_drvdata(pdev, priv);
  3322. err = pci_request_regions(pdev, DRV_NAME);
  3323. if (err)
  3324. goto out_pci_disable_device;
  3325. /***********************
  3326. * 3. Read REV Register
  3327. * ********************/
  3328. priv->hw_base = pci_iomap(pdev, 0, 0);
  3329. if (!priv->hw_base) {
  3330. err = -ENODEV;
  3331. goto out_pci_release_regions;
  3332. }
  3333. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3334. (unsigned long long) pci_resource_len(pdev, 0));
  3335. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3336. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3337. * PCI Tx retries from interfering with C3 CPU state */
  3338. pci_write_config_byte(pdev, 0x41, 0x00);
  3339. /* these spin locks will be used in apm_ops.init and EEPROM access
  3340. * we should init now
  3341. */
  3342. spin_lock_init(&priv->reg_lock);
  3343. spin_lock_init(&priv->lock);
  3344. /*
  3345. * stop and reset the on-board processor just in case it is in a
  3346. * strange state ... like being left stranded by a primary kernel
  3347. * and this is now the kdump kernel trying to start up
  3348. */
  3349. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3350. /***********************
  3351. * 4. Read EEPROM
  3352. * ********************/
  3353. /* Read the EEPROM */
  3354. err = iwl_legacy_eeprom_init(priv);
  3355. if (err) {
  3356. IWL_ERR(priv, "Unable to init EEPROM\n");
  3357. goto out_iounmap;
  3358. }
  3359. /* MAC Address location in EEPROM same for 3945/4965 */
  3360. eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3361. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
  3362. SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
  3363. /***********************
  3364. * 5. Setup HW Constants
  3365. * ********************/
  3366. /* Device-specific setup */
  3367. if (iwl3945_hw_set_hw_params(priv)) {
  3368. IWL_ERR(priv, "failed to set hw settings\n");
  3369. goto out_eeprom_free;
  3370. }
  3371. /***********************
  3372. * 6. Setup priv
  3373. * ********************/
  3374. err = iwl3945_init_drv(priv);
  3375. if (err) {
  3376. IWL_ERR(priv, "initializing driver failed\n");
  3377. goto out_unset_hw_params;
  3378. }
  3379. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  3380. priv->cfg->name);
  3381. /***********************
  3382. * 7. Setup Services
  3383. * ********************/
  3384. spin_lock_irqsave(&priv->lock, flags);
  3385. iwl_legacy_disable_interrupts(priv);
  3386. spin_unlock_irqrestore(&priv->lock, flags);
  3387. pci_enable_msi(priv->pci_dev);
  3388. err = request_irq(priv->pci_dev->irq, iwl_legacy_isr,
  3389. IRQF_SHARED, DRV_NAME, priv);
  3390. if (err) {
  3391. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3392. goto out_disable_msi;
  3393. }
  3394. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3395. if (err) {
  3396. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3397. goto out_release_irq;
  3398. }
  3399. iwl_legacy_set_rxon_channel(priv,
  3400. &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
  3401. &priv->contexts[IWL_RXON_CTX_BSS]);
  3402. iwl3945_setup_deferred_work(priv);
  3403. iwl3945_setup_rx_handlers(priv);
  3404. iwl_legacy_power_initialize(priv);
  3405. /*********************************
  3406. * 8. Setup and Register mac80211
  3407. * *******************************/
  3408. iwl_legacy_enable_interrupts(priv);
  3409. err = iwl3945_setup_mac(priv);
  3410. if (err)
  3411. goto out_remove_sysfs;
  3412. err = iwl_legacy_dbgfs_register(priv, DRV_NAME);
  3413. if (err)
  3414. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3415. /* Start monitoring the killswitch */
  3416. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  3417. 2 * HZ);
  3418. return 0;
  3419. out_remove_sysfs:
  3420. destroy_workqueue(priv->workqueue);
  3421. priv->workqueue = NULL;
  3422. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3423. out_release_irq:
  3424. free_irq(priv->pci_dev->irq, priv);
  3425. out_disable_msi:
  3426. pci_disable_msi(priv->pci_dev);
  3427. iwl_legacy_free_geos(priv);
  3428. iwl_legacy_free_channel_map(priv);
  3429. out_unset_hw_params:
  3430. iwl3945_unset_hw_params(priv);
  3431. out_eeprom_free:
  3432. iwl_legacy_eeprom_free(priv);
  3433. out_iounmap:
  3434. pci_iounmap(pdev, priv->hw_base);
  3435. out_pci_release_regions:
  3436. pci_release_regions(pdev);
  3437. out_pci_disable_device:
  3438. pci_set_drvdata(pdev, NULL);
  3439. pci_disable_device(pdev);
  3440. out_ieee80211_free_hw:
  3441. iwl_legacy_free_traffic_mem(priv);
  3442. ieee80211_free_hw(priv->hw);
  3443. out:
  3444. return err;
  3445. }
  3446. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  3447. {
  3448. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3449. unsigned long flags;
  3450. if (!priv)
  3451. return;
  3452. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3453. iwl_legacy_dbgfs_unregister(priv);
  3454. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3455. iwl_legacy_leds_exit(priv);
  3456. if (priv->mac80211_registered) {
  3457. ieee80211_unregister_hw(priv->hw);
  3458. priv->mac80211_registered = 0;
  3459. } else {
  3460. iwl3945_down(priv);
  3461. }
  3462. /*
  3463. * Make sure device is reset to low power before unloading driver.
  3464. * This may be redundant with iwl_down(), but there are paths to
  3465. * run iwl_down() without calling apm_ops.stop(), and there are
  3466. * paths to avoid running iwl_down() at all before leaving driver.
  3467. * This (inexpensive) call *makes sure* device is reset.
  3468. */
  3469. iwl_legacy_apm_stop(priv);
  3470. /* make sure we flush any pending irq or
  3471. * tasklet for the driver
  3472. */
  3473. spin_lock_irqsave(&priv->lock, flags);
  3474. iwl_legacy_disable_interrupts(priv);
  3475. spin_unlock_irqrestore(&priv->lock, flags);
  3476. iwl3945_synchronize_irq(priv);
  3477. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3478. cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
  3479. iwl3945_dealloc_ucode_pci(priv);
  3480. if (priv->rxq.bd)
  3481. iwl3945_rx_queue_free(priv, &priv->rxq);
  3482. iwl3945_hw_txq_ctx_free(priv);
  3483. iwl3945_unset_hw_params(priv);
  3484. /*netif_stop_queue(dev); */
  3485. flush_workqueue(priv->workqueue);
  3486. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  3487. * priv->workqueue... so we can't take down the workqueue
  3488. * until now... */
  3489. destroy_workqueue(priv->workqueue);
  3490. priv->workqueue = NULL;
  3491. iwl_legacy_free_traffic_mem(priv);
  3492. free_irq(pdev->irq, priv);
  3493. pci_disable_msi(pdev);
  3494. pci_iounmap(pdev, priv->hw_base);
  3495. pci_release_regions(pdev);
  3496. pci_disable_device(pdev);
  3497. pci_set_drvdata(pdev, NULL);
  3498. iwl_legacy_free_channel_map(priv);
  3499. iwl_legacy_free_geos(priv);
  3500. kfree(priv->scan_cmd);
  3501. if (priv->beacon_skb)
  3502. dev_kfree_skb(priv->beacon_skb);
  3503. ieee80211_free_hw(priv->hw);
  3504. }
  3505. /*****************************************************************************
  3506. *
  3507. * driver and module entry point
  3508. *
  3509. *****************************************************************************/
  3510. static struct pci_driver iwl3945_driver = {
  3511. .name = DRV_NAME,
  3512. .id_table = iwl3945_hw_card_ids,
  3513. .probe = iwl3945_pci_probe,
  3514. .remove = __devexit_p(iwl3945_pci_remove),
  3515. .driver.pm = IWL_LEGACY_PM_OPS,
  3516. };
  3517. static int __init iwl3945_init(void)
  3518. {
  3519. int ret;
  3520. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3521. pr_info(DRV_COPYRIGHT "\n");
  3522. ret = iwl3945_rate_control_register();
  3523. if (ret) {
  3524. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3525. return ret;
  3526. }
  3527. ret = pci_register_driver(&iwl3945_driver);
  3528. if (ret) {
  3529. pr_err("Unable to initialize PCI module\n");
  3530. goto error_register;
  3531. }
  3532. return ret;
  3533. error_register:
  3534. iwl3945_rate_control_unregister();
  3535. return ret;
  3536. }
  3537. static void __exit iwl3945_exit(void)
  3538. {
  3539. pci_unregister_driver(&iwl3945_driver);
  3540. iwl3945_rate_control_unregister();
  3541. }
  3542. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  3543. module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
  3544. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3545. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
  3546. MODULE_PARM_DESC(swcrypto,
  3547. "using software crypto (default 1 [software])");
  3548. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
  3549. int, S_IRUGO);
  3550. MODULE_PARM_DESC(disable_hw_scan,
  3551. "disable hardware scanning (default 0) (deprecated)");
  3552. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  3553. module_param_named(debug, iwlegacy_debug_level, uint, S_IRUGO | S_IWUSR);
  3554. MODULE_PARM_DESC(debug, "debug output mask");
  3555. #endif
  3556. module_param_named(fw_restart, iwl3945_mod_params.restart_fw, int, S_IRUGO);
  3557. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3558. module_exit(iwl3945_exit);
  3559. module_init(iwl3945_init);