smsc911x.c 58 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. *
  30. */
  31. #include <linux/crc32.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/init.h>
  37. #include <linux/ioport.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/sched.h>
  43. #include <linux/timer.h>
  44. #include <linux/bug.h>
  45. #include <linux/bitops.h>
  46. #include <linux/irq.h>
  47. #include <linux/io.h>
  48. #include <linux/swab.h>
  49. #include <linux/phy.h>
  50. #include <linux/smsc911x.h>
  51. #include <linux/device.h>
  52. #include "smsc911x.h"
  53. #define SMSC_CHIPNAME "smsc911x"
  54. #define SMSC_MDIONAME "smsc911x-mdio"
  55. #define SMSC_DRV_VERSION "2008-10-21"
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(SMSC_DRV_VERSION);
  58. MODULE_ALIAS("platform:smsc911x");
  59. #if USE_DEBUG > 0
  60. static int debug = 16;
  61. #else
  62. static int debug = 3;
  63. #endif
  64. module_param(debug, int, 0);
  65. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  66. struct smsc911x_data {
  67. void __iomem *ioaddr;
  68. unsigned int idrev;
  69. /* used to decide which workarounds apply */
  70. unsigned int generation;
  71. /* device configuration (copied from platform_data during probe) */
  72. struct smsc911x_platform_config config;
  73. /* This needs to be acquired before calling any of below:
  74. * smsc911x_mac_read(), smsc911x_mac_write()
  75. */
  76. spinlock_t mac_lock;
  77. /* spinlock to ensure register accesses are serialised */
  78. spinlock_t dev_lock;
  79. struct phy_device *phy_dev;
  80. struct mii_bus *mii_bus;
  81. int phy_irq[PHY_MAX_ADDR];
  82. unsigned int using_extphy;
  83. int last_duplex;
  84. int last_carrier;
  85. u32 msg_enable;
  86. unsigned int gpio_setting;
  87. unsigned int gpio_orig_setting;
  88. struct net_device *dev;
  89. struct napi_struct napi;
  90. unsigned int software_irq_signal;
  91. #ifdef USE_PHY_WORK_AROUND
  92. #define MIN_PACKET_SIZE (64)
  93. char loopback_tx_pkt[MIN_PACKET_SIZE];
  94. char loopback_rx_pkt[MIN_PACKET_SIZE];
  95. unsigned int resetcount;
  96. #endif
  97. /* Members for Multicast filter workaround */
  98. unsigned int multicast_update_pending;
  99. unsigned int set_bits_mask;
  100. unsigned int clear_bits_mask;
  101. unsigned int hashhi;
  102. unsigned int hashlo;
  103. };
  104. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  105. {
  106. if (pdata->config.flags & SMSC911X_USE_32BIT)
  107. return readl(pdata->ioaddr + reg);
  108. if (pdata->config.flags & SMSC911X_USE_16BIT)
  109. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  110. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  111. BUG();
  112. return 0;
  113. }
  114. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  115. {
  116. u32 data;
  117. unsigned long flags;
  118. spin_lock_irqsave(&pdata->dev_lock, flags);
  119. data = __smsc911x_reg_read(pdata, reg);
  120. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  121. return data;
  122. }
  123. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  124. u32 val)
  125. {
  126. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  127. writel(val, pdata->ioaddr + reg);
  128. return;
  129. }
  130. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  131. writew(val & 0xFFFF, pdata->ioaddr + reg);
  132. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  133. return;
  134. }
  135. BUG();
  136. }
  137. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  138. u32 val)
  139. {
  140. unsigned long flags;
  141. spin_lock_irqsave(&pdata->dev_lock, flags);
  142. __smsc911x_reg_write(pdata, reg, val);
  143. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  144. }
  145. /* Writes a packet to the TX_DATA_FIFO */
  146. static inline void
  147. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  148. unsigned int wordcount)
  149. {
  150. unsigned long flags;
  151. spin_lock_irqsave(&pdata->dev_lock, flags);
  152. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  153. while (wordcount--)
  154. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  155. swab32(*buf++));
  156. goto out;
  157. }
  158. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  159. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  160. goto out;
  161. }
  162. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  163. while (wordcount--)
  164. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  165. goto out;
  166. }
  167. BUG();
  168. out:
  169. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  170. }
  171. /* Reads a packet out of the RX_DATA_FIFO */
  172. static inline void
  173. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  174. unsigned int wordcount)
  175. {
  176. unsigned long flags;
  177. spin_lock_irqsave(&pdata->dev_lock, flags);
  178. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  179. while (wordcount--)
  180. *buf++ = swab32(__smsc911x_reg_read(pdata,
  181. RX_DATA_FIFO));
  182. goto out;
  183. }
  184. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  185. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  186. goto out;
  187. }
  188. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  189. while (wordcount--)
  190. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  191. goto out;
  192. }
  193. BUG();
  194. out:
  195. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  196. }
  197. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  198. * and smsc911x_mac_write, so assumes mac_lock is held */
  199. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  200. {
  201. int i;
  202. u32 val;
  203. SMSC_ASSERT_MAC_LOCK(pdata);
  204. for (i = 0; i < 40; i++) {
  205. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  206. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  207. return 0;
  208. }
  209. SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
  210. "MAC_CSR_CMD: 0x%08X", val);
  211. return -EIO;
  212. }
  213. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  214. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  215. {
  216. unsigned int temp;
  217. SMSC_ASSERT_MAC_LOCK(pdata);
  218. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  219. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  220. SMSC_WARNING(HW, "MAC busy at entry");
  221. return 0xFFFFFFFF;
  222. }
  223. /* Send the MAC cmd */
  224. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  225. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  226. /* Workaround for hardware read-after-write restriction */
  227. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  228. /* Wait for the read to complete */
  229. if (likely(smsc911x_mac_complete(pdata) == 0))
  230. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  231. SMSC_WARNING(HW, "MAC busy after read");
  232. return 0xFFFFFFFF;
  233. }
  234. /* Set a mac register, mac_lock must be acquired before calling */
  235. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  236. unsigned int offset, u32 val)
  237. {
  238. unsigned int temp;
  239. SMSC_ASSERT_MAC_LOCK(pdata);
  240. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  241. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  242. SMSC_WARNING(HW,
  243. "smsc911x_mac_write failed, MAC busy at entry");
  244. return;
  245. }
  246. /* Send data to write */
  247. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  248. /* Write the actual data */
  249. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  250. MAC_CSR_CMD_CSR_BUSY_));
  251. /* Workaround for hardware read-after-write restriction */
  252. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  253. /* Wait for the write to complete */
  254. if (likely(smsc911x_mac_complete(pdata) == 0))
  255. return;
  256. SMSC_WARNING(HW,
  257. "smsc911x_mac_write failed, MAC busy after write");
  258. }
  259. /* Get a phy register */
  260. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  261. {
  262. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  263. unsigned long flags;
  264. unsigned int addr;
  265. int i, reg;
  266. spin_lock_irqsave(&pdata->mac_lock, flags);
  267. /* Confirm MII not busy */
  268. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  269. SMSC_WARNING(HW,
  270. "MII is busy in smsc911x_mii_read???");
  271. reg = -EIO;
  272. goto out;
  273. }
  274. /* Set the address, index & direction (read from PHY) */
  275. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  276. smsc911x_mac_write(pdata, MII_ACC, addr);
  277. /* Wait for read to complete w/ timeout */
  278. for (i = 0; i < 100; i++)
  279. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  280. reg = smsc911x_mac_read(pdata, MII_DATA);
  281. goto out;
  282. }
  283. SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
  284. reg = -EIO;
  285. out:
  286. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  287. return reg;
  288. }
  289. /* Set a phy register */
  290. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  291. u16 val)
  292. {
  293. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  294. unsigned long flags;
  295. unsigned int addr;
  296. int i, reg;
  297. spin_lock_irqsave(&pdata->mac_lock, flags);
  298. /* Confirm MII not busy */
  299. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  300. SMSC_WARNING(HW,
  301. "MII is busy in smsc911x_mii_write???");
  302. reg = -EIO;
  303. goto out;
  304. }
  305. /* Put the data to write in the MAC */
  306. smsc911x_mac_write(pdata, MII_DATA, val);
  307. /* Set the address, index & direction (write to PHY) */
  308. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  309. MII_ACC_MII_WRITE_;
  310. smsc911x_mac_write(pdata, MII_ACC, addr);
  311. /* Wait for write to complete w/ timeout */
  312. for (i = 0; i < 100; i++)
  313. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  314. reg = 0;
  315. goto out;
  316. }
  317. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  318. reg = -EIO;
  319. out:
  320. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  321. return reg;
  322. }
  323. /* Switch to external phy. Assumes tx and rx are stopped. */
  324. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  325. {
  326. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  327. /* Disable phy clocks to the MAC */
  328. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  329. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  330. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  331. udelay(10); /* Enough time for clocks to stop */
  332. /* Switch to external phy */
  333. hwcfg |= HW_CFG_EXT_PHY_EN_;
  334. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  335. /* Enable phy clocks to the MAC */
  336. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  337. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  338. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  339. udelay(10); /* Enough time for clocks to restart */
  340. hwcfg |= HW_CFG_SMI_SEL_;
  341. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  342. }
  343. /* Autodetects and enables external phy if present on supported chips.
  344. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  345. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  346. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  347. {
  348. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  349. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  350. SMSC_TRACE(HW, "Forcing internal PHY");
  351. pdata->using_extphy = 0;
  352. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  353. SMSC_TRACE(HW, "Forcing external PHY");
  354. smsc911x_phy_enable_external(pdata);
  355. pdata->using_extphy = 1;
  356. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  357. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
  358. smsc911x_phy_enable_external(pdata);
  359. pdata->using_extphy = 1;
  360. } else {
  361. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
  362. pdata->using_extphy = 0;
  363. }
  364. }
  365. /* Fetches a tx status out of the status fifo */
  366. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  367. {
  368. unsigned int result =
  369. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  370. if (result != 0)
  371. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  372. return result;
  373. }
  374. /* Fetches the next rx status */
  375. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  376. {
  377. unsigned int result =
  378. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  379. if (result != 0)
  380. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  381. return result;
  382. }
  383. #ifdef USE_PHY_WORK_AROUND
  384. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  385. {
  386. unsigned int tries;
  387. u32 wrsz;
  388. u32 rdsz;
  389. ulong bufp;
  390. for (tries = 0; tries < 10; tries++) {
  391. unsigned int txcmd_a;
  392. unsigned int txcmd_b;
  393. unsigned int status;
  394. unsigned int pktlength;
  395. unsigned int i;
  396. /* Zero-out rx packet memory */
  397. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  398. /* Write tx packet to 118 */
  399. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  400. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  401. txcmd_a |= MIN_PACKET_SIZE;
  402. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  403. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  404. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  405. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  406. wrsz = MIN_PACKET_SIZE + 3;
  407. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  408. wrsz >>= 2;
  409. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  410. /* Wait till transmit is done */
  411. i = 60;
  412. do {
  413. udelay(5);
  414. status = smsc911x_tx_get_txstatus(pdata);
  415. } while ((i--) && (!status));
  416. if (!status) {
  417. SMSC_WARNING(HW, "Failed to transmit "
  418. "during loopback test");
  419. continue;
  420. }
  421. if (status & TX_STS_ES_) {
  422. SMSC_WARNING(HW, "Transmit encountered "
  423. "errors during loopback test");
  424. continue;
  425. }
  426. /* Wait till receive is done */
  427. i = 60;
  428. do {
  429. udelay(5);
  430. status = smsc911x_rx_get_rxstatus(pdata);
  431. } while ((i--) && (!status));
  432. if (!status) {
  433. SMSC_WARNING(HW,
  434. "Failed to receive during loopback test");
  435. continue;
  436. }
  437. if (status & RX_STS_ES_) {
  438. SMSC_WARNING(HW, "Receive encountered "
  439. "errors during loopback test");
  440. continue;
  441. }
  442. pktlength = ((status & 0x3FFF0000UL) >> 16);
  443. bufp = (ulong)pdata->loopback_rx_pkt;
  444. rdsz = pktlength + 3;
  445. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  446. rdsz >>= 2;
  447. smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  448. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  449. SMSC_WARNING(HW, "Unexpected packet size "
  450. "during loop back test, size=%d, will retry",
  451. pktlength);
  452. } else {
  453. unsigned int j;
  454. int mismatch = 0;
  455. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  456. if (pdata->loopback_tx_pkt[j]
  457. != pdata->loopback_rx_pkt[j]) {
  458. mismatch = 1;
  459. break;
  460. }
  461. }
  462. if (!mismatch) {
  463. SMSC_TRACE(HW, "Successfully verified "
  464. "loopback packet");
  465. return 0;
  466. } else {
  467. SMSC_WARNING(HW, "Data mismatch "
  468. "during loop back test, will retry");
  469. }
  470. }
  471. }
  472. return -EIO;
  473. }
  474. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  475. {
  476. struct phy_device *phy_dev = pdata->phy_dev;
  477. unsigned int temp;
  478. unsigned int i = 100000;
  479. BUG_ON(!phy_dev);
  480. BUG_ON(!phy_dev->bus);
  481. SMSC_TRACE(HW, "Performing PHY BCR Reset");
  482. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  483. do {
  484. msleep(1);
  485. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  486. MII_BMCR);
  487. } while ((i--) && (temp & BMCR_RESET));
  488. if (temp & BMCR_RESET) {
  489. SMSC_WARNING(HW, "PHY reset failed to complete.");
  490. return -EIO;
  491. }
  492. /* Extra delay required because the phy may not be completed with
  493. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  494. * enough delay but using 1ms here to be safe */
  495. msleep(1);
  496. return 0;
  497. }
  498. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  499. {
  500. struct smsc911x_data *pdata = netdev_priv(dev);
  501. struct phy_device *phy_dev = pdata->phy_dev;
  502. int result = -EIO;
  503. unsigned int i, val;
  504. unsigned long flags;
  505. /* Initialise tx packet using broadcast destination address */
  506. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  507. /* Use incrementing source address */
  508. for (i = 6; i < 12; i++)
  509. pdata->loopback_tx_pkt[i] = (char)i;
  510. /* Set length type field */
  511. pdata->loopback_tx_pkt[12] = 0x00;
  512. pdata->loopback_tx_pkt[13] = 0x00;
  513. for (i = 14; i < MIN_PACKET_SIZE; i++)
  514. pdata->loopback_tx_pkt[i] = (char)i;
  515. val = smsc911x_reg_read(pdata, HW_CFG);
  516. val &= HW_CFG_TX_FIF_SZ_;
  517. val |= HW_CFG_SF_;
  518. smsc911x_reg_write(pdata, HW_CFG, val);
  519. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  520. smsc911x_reg_write(pdata, RX_CFG,
  521. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  522. for (i = 0; i < 10; i++) {
  523. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  524. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  525. BMCR_LOOPBACK | BMCR_FULLDPLX);
  526. /* Enable MAC tx/rx, FD */
  527. spin_lock_irqsave(&pdata->mac_lock, flags);
  528. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  529. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  530. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  531. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  532. result = 0;
  533. break;
  534. }
  535. pdata->resetcount++;
  536. /* Disable MAC rx */
  537. spin_lock_irqsave(&pdata->mac_lock, flags);
  538. smsc911x_mac_write(pdata, MAC_CR, 0);
  539. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  540. smsc911x_phy_reset(pdata);
  541. }
  542. /* Disable MAC */
  543. spin_lock_irqsave(&pdata->mac_lock, flags);
  544. smsc911x_mac_write(pdata, MAC_CR, 0);
  545. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  546. /* Cancel PHY loopback mode */
  547. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  548. smsc911x_reg_write(pdata, TX_CFG, 0);
  549. smsc911x_reg_write(pdata, RX_CFG, 0);
  550. return result;
  551. }
  552. #endif /* USE_PHY_WORK_AROUND */
  553. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  554. {
  555. struct phy_device *phy_dev = pdata->phy_dev;
  556. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  557. u32 flow;
  558. unsigned long flags;
  559. if (phy_dev->duplex == DUPLEX_FULL) {
  560. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  561. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  562. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  563. if (cap & FLOW_CTRL_RX)
  564. flow = 0xFFFF0002;
  565. else
  566. flow = 0;
  567. if (cap & FLOW_CTRL_TX)
  568. afc |= 0xF;
  569. else
  570. afc &= ~0xF;
  571. SMSC_TRACE(HW, "rx pause %s, tx pause %s",
  572. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  573. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  574. } else {
  575. SMSC_TRACE(HW, "half duplex");
  576. flow = 0;
  577. afc |= 0xF;
  578. }
  579. spin_lock_irqsave(&pdata->mac_lock, flags);
  580. smsc911x_mac_write(pdata, FLOW, flow);
  581. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  582. smsc911x_reg_write(pdata, AFC_CFG, afc);
  583. }
  584. /* Update link mode if anything has changed. Called periodically when the
  585. * PHY is in polling mode, even if nothing has changed. */
  586. static void smsc911x_phy_adjust_link(struct net_device *dev)
  587. {
  588. struct smsc911x_data *pdata = netdev_priv(dev);
  589. struct phy_device *phy_dev = pdata->phy_dev;
  590. unsigned long flags;
  591. int carrier;
  592. if (phy_dev->duplex != pdata->last_duplex) {
  593. unsigned int mac_cr;
  594. SMSC_TRACE(HW, "duplex state has changed");
  595. spin_lock_irqsave(&pdata->mac_lock, flags);
  596. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  597. if (phy_dev->duplex) {
  598. SMSC_TRACE(HW,
  599. "configuring for full duplex mode");
  600. mac_cr |= MAC_CR_FDPX_;
  601. } else {
  602. SMSC_TRACE(HW,
  603. "configuring for half duplex mode");
  604. mac_cr &= ~MAC_CR_FDPX_;
  605. }
  606. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  607. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  608. smsc911x_phy_update_flowcontrol(pdata);
  609. pdata->last_duplex = phy_dev->duplex;
  610. }
  611. carrier = netif_carrier_ok(dev);
  612. if (carrier != pdata->last_carrier) {
  613. SMSC_TRACE(HW, "carrier state has changed");
  614. if (carrier) {
  615. SMSC_TRACE(HW, "configuring for carrier OK");
  616. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  617. (!pdata->using_extphy)) {
  618. /* Restore original GPIO configuration */
  619. pdata->gpio_setting = pdata->gpio_orig_setting;
  620. smsc911x_reg_write(pdata, GPIO_CFG,
  621. pdata->gpio_setting);
  622. }
  623. } else {
  624. SMSC_TRACE(HW, "configuring for no carrier");
  625. /* Check global setting that LED1
  626. * usage is 10/100 indicator */
  627. pdata->gpio_setting = smsc911x_reg_read(pdata,
  628. GPIO_CFG);
  629. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  630. (!pdata->using_extphy)) {
  631. /* Force 10/100 LED off, after saving
  632. * original GPIO configuration */
  633. pdata->gpio_orig_setting = pdata->gpio_setting;
  634. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  635. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  636. | GPIO_CFG_GPIODIR0_
  637. | GPIO_CFG_GPIOD0_);
  638. smsc911x_reg_write(pdata, GPIO_CFG,
  639. pdata->gpio_setting);
  640. }
  641. }
  642. pdata->last_carrier = carrier;
  643. }
  644. }
  645. static int smsc911x_mii_probe(struct net_device *dev)
  646. {
  647. struct smsc911x_data *pdata = netdev_priv(dev);
  648. struct phy_device *phydev = NULL;
  649. int ret;
  650. /* find the first phy */
  651. phydev = phy_find_first(pdata->mii_bus);
  652. if (!phydev) {
  653. pr_err("%s: no PHY found\n", dev->name);
  654. return -ENODEV;
  655. }
  656. SMSC_TRACE(PROBE, "PHY: addr %d, phy_id 0x%08X",
  657. phydev->addr, phydev->phy_id);
  658. ret = phy_connect_direct(dev, phydev,
  659. &smsc911x_phy_adjust_link, 0,
  660. pdata->config.phy_interface);
  661. if (ret) {
  662. pr_err("%s: Could not attach to PHY\n", dev->name);
  663. return ret;
  664. }
  665. pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  666. dev->name, phydev->drv->name,
  667. dev_name(&phydev->dev), phydev->irq);
  668. /* mask with MAC supported features */
  669. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  670. SUPPORTED_Asym_Pause);
  671. phydev->advertising = phydev->supported;
  672. pdata->phy_dev = phydev;
  673. pdata->last_duplex = -1;
  674. pdata->last_carrier = -1;
  675. #ifdef USE_PHY_WORK_AROUND
  676. if (smsc911x_phy_loopbacktest(dev) < 0) {
  677. SMSC_WARNING(HW, "Failed Loop Back Test");
  678. return -ENODEV;
  679. }
  680. SMSC_TRACE(HW, "Passed Loop Back Test");
  681. #endif /* USE_PHY_WORK_AROUND */
  682. SMSC_TRACE(HW, "phy initialised successfully");
  683. return 0;
  684. }
  685. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  686. struct net_device *dev)
  687. {
  688. struct smsc911x_data *pdata = netdev_priv(dev);
  689. int err = -ENXIO, i;
  690. pdata->mii_bus = mdiobus_alloc();
  691. if (!pdata->mii_bus) {
  692. err = -ENOMEM;
  693. goto err_out_1;
  694. }
  695. pdata->mii_bus->name = SMSC_MDIONAME;
  696. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  697. pdata->mii_bus->priv = pdata;
  698. pdata->mii_bus->read = smsc911x_mii_read;
  699. pdata->mii_bus->write = smsc911x_mii_write;
  700. pdata->mii_bus->irq = pdata->phy_irq;
  701. for (i = 0; i < PHY_MAX_ADDR; ++i)
  702. pdata->mii_bus->irq[i] = PHY_POLL;
  703. pdata->mii_bus->parent = &pdev->dev;
  704. switch (pdata->idrev & 0xFFFF0000) {
  705. case 0x01170000:
  706. case 0x01150000:
  707. case 0x117A0000:
  708. case 0x115A0000:
  709. /* External PHY supported, try to autodetect */
  710. smsc911x_phy_initialise_external(pdata);
  711. break;
  712. default:
  713. SMSC_TRACE(HW, "External PHY is not supported, "
  714. "using internal PHY");
  715. pdata->using_extphy = 0;
  716. break;
  717. }
  718. if (!pdata->using_extphy) {
  719. /* Mask all PHYs except ID 1 (internal) */
  720. pdata->mii_bus->phy_mask = ~(1 << 1);
  721. }
  722. if (mdiobus_register(pdata->mii_bus)) {
  723. SMSC_WARNING(PROBE, "Error registering mii bus");
  724. goto err_out_free_bus_2;
  725. }
  726. if (smsc911x_mii_probe(dev) < 0) {
  727. SMSC_WARNING(PROBE, "Error registering mii bus");
  728. goto err_out_unregister_bus_3;
  729. }
  730. return 0;
  731. err_out_unregister_bus_3:
  732. mdiobus_unregister(pdata->mii_bus);
  733. err_out_free_bus_2:
  734. mdiobus_free(pdata->mii_bus);
  735. err_out_1:
  736. return err;
  737. }
  738. /* Gets the number of tx statuses in the fifo */
  739. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  740. {
  741. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  742. & TX_FIFO_INF_TSUSED_) >> 16;
  743. }
  744. /* Reads tx statuses and increments counters where necessary */
  745. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  746. {
  747. struct smsc911x_data *pdata = netdev_priv(dev);
  748. unsigned int tx_stat;
  749. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  750. if (unlikely(tx_stat & 0x80000000)) {
  751. /* In this driver the packet tag is used as the packet
  752. * length. Since a packet length can never reach the
  753. * size of 0x8000, this bit is reserved. It is worth
  754. * noting that the "reserved bit" in the warning above
  755. * does not reference a hardware defined reserved bit
  756. * but rather a driver defined one.
  757. */
  758. SMSC_WARNING(HW,
  759. "Packet tag reserved bit is high");
  760. } else {
  761. if (unlikely(tx_stat & TX_STS_ES_)) {
  762. dev->stats.tx_errors++;
  763. } else {
  764. dev->stats.tx_packets++;
  765. dev->stats.tx_bytes += (tx_stat >> 16);
  766. }
  767. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  768. dev->stats.collisions += 16;
  769. dev->stats.tx_aborted_errors += 1;
  770. } else {
  771. dev->stats.collisions +=
  772. ((tx_stat >> 3) & 0xF);
  773. }
  774. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  775. dev->stats.tx_carrier_errors += 1;
  776. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  777. dev->stats.collisions++;
  778. dev->stats.tx_aborted_errors++;
  779. }
  780. }
  781. }
  782. }
  783. /* Increments the Rx error counters */
  784. static void
  785. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  786. {
  787. int crc_err = 0;
  788. if (unlikely(rxstat & RX_STS_ES_)) {
  789. dev->stats.rx_errors++;
  790. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  791. dev->stats.rx_crc_errors++;
  792. crc_err = 1;
  793. }
  794. }
  795. if (likely(!crc_err)) {
  796. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  797. (rxstat & RX_STS_LENGTH_ERR_)))
  798. dev->stats.rx_length_errors++;
  799. if (rxstat & RX_STS_MCAST_)
  800. dev->stats.multicast++;
  801. }
  802. }
  803. /* Quickly dumps bad packets */
  804. static void
  805. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  806. {
  807. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  808. if (likely(pktwords >= 4)) {
  809. unsigned int timeout = 500;
  810. unsigned int val;
  811. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  812. do {
  813. udelay(1);
  814. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  815. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  816. if (unlikely(timeout == 0))
  817. SMSC_WARNING(HW, "Timed out waiting for "
  818. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  819. } else {
  820. unsigned int temp;
  821. while (pktwords--)
  822. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  823. }
  824. }
  825. /* NAPI poll function */
  826. static int smsc911x_poll(struct napi_struct *napi, int budget)
  827. {
  828. struct smsc911x_data *pdata =
  829. container_of(napi, struct smsc911x_data, napi);
  830. struct net_device *dev = pdata->dev;
  831. int npackets = 0;
  832. while (npackets < budget) {
  833. unsigned int pktlength;
  834. unsigned int pktwords;
  835. struct sk_buff *skb;
  836. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  837. if (!rxstat) {
  838. unsigned int temp;
  839. /* We processed all packets available. Tell NAPI it can
  840. * stop polling then re-enable rx interrupts */
  841. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  842. napi_complete(napi);
  843. temp = smsc911x_reg_read(pdata, INT_EN);
  844. temp |= INT_EN_RSFL_EN_;
  845. smsc911x_reg_write(pdata, INT_EN, temp);
  846. break;
  847. }
  848. /* Count packet for NAPI scheduling, even if it has an error.
  849. * Error packets still require cycles to discard */
  850. npackets++;
  851. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  852. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  853. smsc911x_rx_counterrors(dev, rxstat);
  854. if (unlikely(rxstat & RX_STS_ES_)) {
  855. SMSC_WARNING(RX_ERR,
  856. "Discarding packet with error bit set");
  857. /* Packet has an error, discard it and continue with
  858. * the next */
  859. smsc911x_rx_fastforward(pdata, pktwords);
  860. dev->stats.rx_dropped++;
  861. continue;
  862. }
  863. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  864. if (unlikely(!skb)) {
  865. SMSC_WARNING(RX_ERR,
  866. "Unable to allocate skb for rx packet");
  867. /* Drop the packet and stop this polling iteration */
  868. smsc911x_rx_fastforward(pdata, pktwords);
  869. dev->stats.rx_dropped++;
  870. break;
  871. }
  872. skb->data = skb->head;
  873. skb_reset_tail_pointer(skb);
  874. /* Align IP on 16B boundary */
  875. skb_reserve(skb, NET_IP_ALIGN);
  876. skb_put(skb, pktlength - 4);
  877. smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
  878. pktwords);
  879. skb->protocol = eth_type_trans(skb, dev);
  880. skb_checksum_none_assert(skb);
  881. netif_receive_skb(skb);
  882. /* Update counters */
  883. dev->stats.rx_packets++;
  884. dev->stats.rx_bytes += (pktlength - 4);
  885. }
  886. /* Return total received packets */
  887. return npackets;
  888. }
  889. /* Returns hash bit number for given MAC address
  890. * Example:
  891. * 01 00 5E 00 00 01 -> returns bit number 31 */
  892. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  893. {
  894. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  895. }
  896. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  897. {
  898. /* Performs the multicast & mac_cr update. This is called when
  899. * safe on the current hardware, and with the mac_lock held */
  900. unsigned int mac_cr;
  901. SMSC_ASSERT_MAC_LOCK(pdata);
  902. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  903. mac_cr |= pdata->set_bits_mask;
  904. mac_cr &= ~(pdata->clear_bits_mask);
  905. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  906. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  907. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  908. SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  909. mac_cr, pdata->hashhi, pdata->hashlo);
  910. }
  911. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  912. {
  913. unsigned int mac_cr;
  914. /* This function is only called for older LAN911x devices
  915. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  916. * be modified during Rx - newer devices immediately update the
  917. * registers.
  918. *
  919. * This is called from interrupt context */
  920. spin_lock(&pdata->mac_lock);
  921. /* Check Rx has stopped */
  922. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  923. SMSC_WARNING(DRV, "Rx not stopped");
  924. /* Perform the update - safe to do now Rx has stopped */
  925. smsc911x_rx_multicast_update(pdata);
  926. /* Re-enable Rx */
  927. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  928. mac_cr |= MAC_CR_RXEN_;
  929. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  930. pdata->multicast_update_pending = 0;
  931. spin_unlock(&pdata->mac_lock);
  932. }
  933. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  934. {
  935. unsigned int timeout;
  936. unsigned int temp;
  937. /* Reset the LAN911x */
  938. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  939. timeout = 10;
  940. do {
  941. udelay(10);
  942. temp = smsc911x_reg_read(pdata, HW_CFG);
  943. } while ((--timeout) && (temp & HW_CFG_SRST_));
  944. if (unlikely(temp & HW_CFG_SRST_)) {
  945. SMSC_WARNING(DRV, "Failed to complete reset");
  946. return -EIO;
  947. }
  948. return 0;
  949. }
  950. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  951. static void
  952. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  953. {
  954. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  955. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  956. (dev_addr[1] << 8) | dev_addr[0];
  957. SMSC_ASSERT_MAC_LOCK(pdata);
  958. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  959. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  960. }
  961. static int smsc911x_open(struct net_device *dev)
  962. {
  963. struct smsc911x_data *pdata = netdev_priv(dev);
  964. unsigned int timeout;
  965. unsigned int temp;
  966. unsigned int intcfg;
  967. /* if the phy is not yet registered, retry later*/
  968. if (!pdata->phy_dev) {
  969. SMSC_WARNING(HW, "phy_dev is NULL");
  970. return -EAGAIN;
  971. }
  972. if (!is_valid_ether_addr(dev->dev_addr)) {
  973. SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
  974. return -EADDRNOTAVAIL;
  975. }
  976. /* Reset the LAN911x */
  977. if (smsc911x_soft_reset(pdata)) {
  978. SMSC_WARNING(HW, "soft reset failed");
  979. return -EIO;
  980. }
  981. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  982. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  983. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  984. spin_lock_irq(&pdata->mac_lock);
  985. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  986. spin_unlock_irq(&pdata->mac_lock);
  987. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  988. timeout = 50;
  989. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  990. --timeout) {
  991. udelay(10);
  992. }
  993. if (unlikely(timeout == 0))
  994. SMSC_WARNING(IFUP,
  995. "Timed out waiting for EEPROM busy bit to clear");
  996. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  997. /* The soft reset above cleared the device's MAC address,
  998. * restore it from local copy (set in probe) */
  999. spin_lock_irq(&pdata->mac_lock);
  1000. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1001. spin_unlock_irq(&pdata->mac_lock);
  1002. /* Initialise irqs, but leave all sources disabled */
  1003. smsc911x_reg_write(pdata, INT_EN, 0);
  1004. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1005. /* Set interrupt deassertion to 100uS */
  1006. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1007. if (pdata->config.irq_polarity) {
  1008. SMSC_TRACE(IFUP, "irq polarity: active high");
  1009. intcfg |= INT_CFG_IRQ_POL_;
  1010. } else {
  1011. SMSC_TRACE(IFUP, "irq polarity: active low");
  1012. }
  1013. if (pdata->config.irq_type) {
  1014. SMSC_TRACE(IFUP, "irq type: push-pull");
  1015. intcfg |= INT_CFG_IRQ_TYPE_;
  1016. } else {
  1017. SMSC_TRACE(IFUP, "irq type: open drain");
  1018. }
  1019. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1020. SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
  1021. pdata->software_irq_signal = 0;
  1022. smp_wmb();
  1023. temp = smsc911x_reg_read(pdata, INT_EN);
  1024. temp |= INT_EN_SW_INT_EN_;
  1025. smsc911x_reg_write(pdata, INT_EN, temp);
  1026. timeout = 1000;
  1027. while (timeout--) {
  1028. if (pdata->software_irq_signal)
  1029. break;
  1030. msleep(1);
  1031. }
  1032. if (!pdata->software_irq_signal) {
  1033. dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
  1034. dev->irq);
  1035. return -ENODEV;
  1036. }
  1037. SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
  1038. dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1039. (unsigned long)pdata->ioaddr, dev->irq);
  1040. /* Reset the last known duplex and carrier */
  1041. pdata->last_duplex = -1;
  1042. pdata->last_carrier = -1;
  1043. /* Bring the PHY up */
  1044. phy_start(pdata->phy_dev);
  1045. temp = smsc911x_reg_read(pdata, HW_CFG);
  1046. /* Preserve TX FIFO size and external PHY configuration */
  1047. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1048. temp |= HW_CFG_SF_;
  1049. smsc911x_reg_write(pdata, HW_CFG, temp);
  1050. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1051. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1052. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1053. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1054. /* set RX Data offset to 2 bytes for alignment */
  1055. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1056. /* enable NAPI polling before enabling RX interrupts */
  1057. napi_enable(&pdata->napi);
  1058. temp = smsc911x_reg_read(pdata, INT_EN);
  1059. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1060. smsc911x_reg_write(pdata, INT_EN, temp);
  1061. spin_lock_irq(&pdata->mac_lock);
  1062. temp = smsc911x_mac_read(pdata, MAC_CR);
  1063. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1064. smsc911x_mac_write(pdata, MAC_CR, temp);
  1065. spin_unlock_irq(&pdata->mac_lock);
  1066. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1067. netif_start_queue(dev);
  1068. return 0;
  1069. }
  1070. /* Entry point for stopping the interface */
  1071. static int smsc911x_stop(struct net_device *dev)
  1072. {
  1073. struct smsc911x_data *pdata = netdev_priv(dev);
  1074. unsigned int temp;
  1075. /* Disable all device interrupts */
  1076. temp = smsc911x_reg_read(pdata, INT_CFG);
  1077. temp &= ~INT_CFG_IRQ_EN_;
  1078. smsc911x_reg_write(pdata, INT_CFG, temp);
  1079. /* Stop Tx and Rx polling */
  1080. netif_stop_queue(dev);
  1081. napi_disable(&pdata->napi);
  1082. /* At this point all Rx and Tx activity is stopped */
  1083. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1084. smsc911x_tx_update_txcounters(dev);
  1085. /* Bring the PHY down */
  1086. if (pdata->phy_dev)
  1087. phy_stop(pdata->phy_dev);
  1088. SMSC_TRACE(IFDOWN, "Interface stopped");
  1089. return 0;
  1090. }
  1091. /* Entry point for transmitting a packet */
  1092. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1093. {
  1094. struct smsc911x_data *pdata = netdev_priv(dev);
  1095. unsigned int freespace;
  1096. unsigned int tx_cmd_a;
  1097. unsigned int tx_cmd_b;
  1098. unsigned int temp;
  1099. u32 wrsz;
  1100. ulong bufp;
  1101. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1102. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1103. SMSC_WARNING(TX_ERR,
  1104. "Tx data fifo low, space available: %d", freespace);
  1105. /* Word alignment adjustment */
  1106. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1107. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1108. tx_cmd_a |= (unsigned int)skb->len;
  1109. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1110. tx_cmd_b |= (unsigned int)skb->len;
  1111. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1112. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1113. bufp = (ulong)skb->data & (~0x3);
  1114. wrsz = (u32)skb->len + 3;
  1115. wrsz += (u32)((ulong)skb->data & 0x3);
  1116. wrsz >>= 2;
  1117. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1118. freespace -= (skb->len + 32);
  1119. dev_kfree_skb(skb);
  1120. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1121. smsc911x_tx_update_txcounters(dev);
  1122. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1123. netif_stop_queue(dev);
  1124. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1125. temp &= 0x00FFFFFF;
  1126. temp |= 0x32000000;
  1127. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1128. }
  1129. return NETDEV_TX_OK;
  1130. }
  1131. /* Entry point for getting status counters */
  1132. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1133. {
  1134. struct smsc911x_data *pdata = netdev_priv(dev);
  1135. smsc911x_tx_update_txcounters(dev);
  1136. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1137. return &dev->stats;
  1138. }
  1139. /* Entry point for setting addressing modes */
  1140. static void smsc911x_set_multicast_list(struct net_device *dev)
  1141. {
  1142. struct smsc911x_data *pdata = netdev_priv(dev);
  1143. unsigned long flags;
  1144. if (dev->flags & IFF_PROMISC) {
  1145. /* Enabling promiscuous mode */
  1146. pdata->set_bits_mask = MAC_CR_PRMS_;
  1147. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1148. pdata->hashhi = 0;
  1149. pdata->hashlo = 0;
  1150. } else if (dev->flags & IFF_ALLMULTI) {
  1151. /* Enabling all multicast mode */
  1152. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1153. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1154. pdata->hashhi = 0;
  1155. pdata->hashlo = 0;
  1156. } else if (!netdev_mc_empty(dev)) {
  1157. /* Enabling specific multicast addresses */
  1158. unsigned int hash_high = 0;
  1159. unsigned int hash_low = 0;
  1160. struct netdev_hw_addr *ha;
  1161. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1162. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1163. netdev_for_each_mc_addr(ha, dev) {
  1164. unsigned int bitnum = smsc911x_hash(ha->addr);
  1165. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1166. if (bitnum & 0x20)
  1167. hash_high |= mask;
  1168. else
  1169. hash_low |= mask;
  1170. }
  1171. pdata->hashhi = hash_high;
  1172. pdata->hashlo = hash_low;
  1173. } else {
  1174. /* Enabling local MAC address only */
  1175. pdata->set_bits_mask = 0;
  1176. pdata->clear_bits_mask =
  1177. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1178. pdata->hashhi = 0;
  1179. pdata->hashlo = 0;
  1180. }
  1181. spin_lock_irqsave(&pdata->mac_lock, flags);
  1182. if (pdata->generation <= 1) {
  1183. /* Older hardware revision - cannot change these flags while
  1184. * receiving data */
  1185. if (!pdata->multicast_update_pending) {
  1186. unsigned int temp;
  1187. SMSC_TRACE(HW, "scheduling mcast update");
  1188. pdata->multicast_update_pending = 1;
  1189. /* Request the hardware to stop, then perform the
  1190. * update when we get an RX_STOP interrupt */
  1191. temp = smsc911x_mac_read(pdata, MAC_CR);
  1192. temp &= ~(MAC_CR_RXEN_);
  1193. smsc911x_mac_write(pdata, MAC_CR, temp);
  1194. } else {
  1195. /* There is another update pending, this should now
  1196. * use the newer values */
  1197. }
  1198. } else {
  1199. /* Newer hardware revision - can write immediately */
  1200. smsc911x_rx_multicast_update(pdata);
  1201. }
  1202. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1203. }
  1204. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1205. {
  1206. struct net_device *dev = dev_id;
  1207. struct smsc911x_data *pdata = netdev_priv(dev);
  1208. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1209. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1210. int serviced = IRQ_NONE;
  1211. u32 temp;
  1212. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1213. temp = smsc911x_reg_read(pdata, INT_EN);
  1214. temp &= (~INT_EN_SW_INT_EN_);
  1215. smsc911x_reg_write(pdata, INT_EN, temp);
  1216. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1217. pdata->software_irq_signal = 1;
  1218. smp_wmb();
  1219. serviced = IRQ_HANDLED;
  1220. }
  1221. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1222. /* Called when there is a multicast update scheduled and
  1223. * it is now safe to complete the update */
  1224. SMSC_TRACE(INTR, "RX Stop interrupt");
  1225. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1226. if (pdata->multicast_update_pending)
  1227. smsc911x_rx_multicast_update_workaround(pdata);
  1228. serviced = IRQ_HANDLED;
  1229. }
  1230. if (intsts & inten & INT_STS_TDFA_) {
  1231. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1232. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1233. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1234. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1235. netif_wake_queue(dev);
  1236. serviced = IRQ_HANDLED;
  1237. }
  1238. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1239. SMSC_TRACE(INTR, "RX Error interrupt");
  1240. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1241. serviced = IRQ_HANDLED;
  1242. }
  1243. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1244. if (likely(napi_schedule_prep(&pdata->napi))) {
  1245. /* Disable Rx interrupts */
  1246. temp = smsc911x_reg_read(pdata, INT_EN);
  1247. temp &= (~INT_EN_RSFL_EN_);
  1248. smsc911x_reg_write(pdata, INT_EN, temp);
  1249. /* Schedule a NAPI poll */
  1250. __napi_schedule(&pdata->napi);
  1251. } else {
  1252. SMSC_WARNING(RX_ERR,
  1253. "napi_schedule_prep failed");
  1254. }
  1255. serviced = IRQ_HANDLED;
  1256. }
  1257. return serviced;
  1258. }
  1259. #ifdef CONFIG_NET_POLL_CONTROLLER
  1260. static void smsc911x_poll_controller(struct net_device *dev)
  1261. {
  1262. disable_irq(dev->irq);
  1263. smsc911x_irqhandler(0, dev);
  1264. enable_irq(dev->irq);
  1265. }
  1266. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1267. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1268. {
  1269. struct smsc911x_data *pdata = netdev_priv(dev);
  1270. struct sockaddr *addr = p;
  1271. /* On older hardware revisions we cannot change the mac address
  1272. * registers while receiving data. Newer devices can safely change
  1273. * this at any time. */
  1274. if (pdata->generation <= 1 && netif_running(dev))
  1275. return -EBUSY;
  1276. if (!is_valid_ether_addr(addr->sa_data))
  1277. return -EADDRNOTAVAIL;
  1278. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1279. spin_lock_irq(&pdata->mac_lock);
  1280. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1281. spin_unlock_irq(&pdata->mac_lock);
  1282. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1283. return 0;
  1284. }
  1285. /* Standard ioctls for mii-tool */
  1286. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1287. {
  1288. struct smsc911x_data *pdata = netdev_priv(dev);
  1289. if (!netif_running(dev) || !pdata->phy_dev)
  1290. return -EINVAL;
  1291. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1292. }
  1293. static int
  1294. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1295. {
  1296. struct smsc911x_data *pdata = netdev_priv(dev);
  1297. cmd->maxtxpkt = 1;
  1298. cmd->maxrxpkt = 1;
  1299. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1300. }
  1301. static int
  1302. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1303. {
  1304. struct smsc911x_data *pdata = netdev_priv(dev);
  1305. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1306. }
  1307. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1308. struct ethtool_drvinfo *info)
  1309. {
  1310. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1311. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1312. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1313. sizeof(info->bus_info));
  1314. }
  1315. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1316. {
  1317. struct smsc911x_data *pdata = netdev_priv(dev);
  1318. return phy_start_aneg(pdata->phy_dev);
  1319. }
  1320. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1321. {
  1322. struct smsc911x_data *pdata = netdev_priv(dev);
  1323. return pdata->msg_enable;
  1324. }
  1325. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1326. {
  1327. struct smsc911x_data *pdata = netdev_priv(dev);
  1328. pdata->msg_enable = level;
  1329. }
  1330. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1331. {
  1332. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1333. sizeof(u32);
  1334. }
  1335. static void
  1336. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1337. void *buf)
  1338. {
  1339. struct smsc911x_data *pdata = netdev_priv(dev);
  1340. struct phy_device *phy_dev = pdata->phy_dev;
  1341. unsigned long flags;
  1342. unsigned int i;
  1343. unsigned int j = 0;
  1344. u32 *data = buf;
  1345. regs->version = pdata->idrev;
  1346. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1347. data[j++] = smsc911x_reg_read(pdata, i);
  1348. for (i = MAC_CR; i <= WUCSR; i++) {
  1349. spin_lock_irqsave(&pdata->mac_lock, flags);
  1350. data[j++] = smsc911x_mac_read(pdata, i);
  1351. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1352. }
  1353. for (i = 0; i <= 31; i++)
  1354. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1355. }
  1356. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1357. {
  1358. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1359. temp &= ~GPIO_CFG_EEPR_EN_;
  1360. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1361. msleep(1);
  1362. }
  1363. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1364. {
  1365. int timeout = 100;
  1366. u32 e2cmd;
  1367. SMSC_TRACE(DRV, "op 0x%08x", op);
  1368. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1369. SMSC_WARNING(DRV, "Busy at start");
  1370. return -EBUSY;
  1371. }
  1372. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1373. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1374. do {
  1375. msleep(1);
  1376. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1377. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1378. if (!timeout) {
  1379. SMSC_TRACE(DRV, "TIMED OUT");
  1380. return -EAGAIN;
  1381. }
  1382. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1383. SMSC_TRACE(DRV, "Error occured during eeprom operation");
  1384. return -EINVAL;
  1385. }
  1386. return 0;
  1387. }
  1388. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1389. u8 address, u8 *data)
  1390. {
  1391. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1392. int ret;
  1393. SMSC_TRACE(DRV, "address 0x%x", address);
  1394. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1395. if (!ret)
  1396. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1397. return ret;
  1398. }
  1399. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1400. u8 address, u8 data)
  1401. {
  1402. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1403. u32 temp;
  1404. int ret;
  1405. SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
  1406. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1407. if (!ret) {
  1408. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1409. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1410. /* Workaround for hardware read-after-write restriction */
  1411. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1412. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1413. }
  1414. return ret;
  1415. }
  1416. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1417. {
  1418. return SMSC911X_EEPROM_SIZE;
  1419. }
  1420. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1421. struct ethtool_eeprom *eeprom, u8 *data)
  1422. {
  1423. struct smsc911x_data *pdata = netdev_priv(dev);
  1424. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1425. int len;
  1426. int i;
  1427. smsc911x_eeprom_enable_access(pdata);
  1428. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1429. for (i = 0; i < len; i++) {
  1430. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1431. if (ret < 0) {
  1432. eeprom->len = 0;
  1433. return ret;
  1434. }
  1435. }
  1436. memcpy(data, &eeprom_data[eeprom->offset], len);
  1437. eeprom->len = len;
  1438. return 0;
  1439. }
  1440. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1441. struct ethtool_eeprom *eeprom, u8 *data)
  1442. {
  1443. int ret;
  1444. struct smsc911x_data *pdata = netdev_priv(dev);
  1445. smsc911x_eeprom_enable_access(pdata);
  1446. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1447. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1448. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1449. /* Single byte write, according to man page */
  1450. eeprom->len = 1;
  1451. return ret;
  1452. }
  1453. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1454. .get_settings = smsc911x_ethtool_getsettings,
  1455. .set_settings = smsc911x_ethtool_setsettings,
  1456. .get_link = ethtool_op_get_link,
  1457. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1458. .nway_reset = smsc911x_ethtool_nwayreset,
  1459. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1460. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1461. .get_regs_len = smsc911x_ethtool_getregslen,
  1462. .get_regs = smsc911x_ethtool_getregs,
  1463. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1464. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1465. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1466. };
  1467. static const struct net_device_ops smsc911x_netdev_ops = {
  1468. .ndo_open = smsc911x_open,
  1469. .ndo_stop = smsc911x_stop,
  1470. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1471. .ndo_get_stats = smsc911x_get_stats,
  1472. .ndo_set_multicast_list = smsc911x_set_multicast_list,
  1473. .ndo_do_ioctl = smsc911x_do_ioctl,
  1474. .ndo_change_mtu = eth_change_mtu,
  1475. .ndo_validate_addr = eth_validate_addr,
  1476. .ndo_set_mac_address = smsc911x_set_mac_address,
  1477. #ifdef CONFIG_NET_POLL_CONTROLLER
  1478. .ndo_poll_controller = smsc911x_poll_controller,
  1479. #endif
  1480. };
  1481. /* copies the current mac address from hardware to dev->dev_addr */
  1482. static void __devinit smsc911x_read_mac_address(struct net_device *dev)
  1483. {
  1484. struct smsc911x_data *pdata = netdev_priv(dev);
  1485. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1486. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1487. dev->dev_addr[0] = (u8)(mac_low32);
  1488. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1489. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1490. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1491. dev->dev_addr[4] = (u8)(mac_high16);
  1492. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1493. }
  1494. /* Initializing private device structures, only called from probe */
  1495. static int __devinit smsc911x_init(struct net_device *dev)
  1496. {
  1497. struct smsc911x_data *pdata = netdev_priv(dev);
  1498. unsigned int byte_test;
  1499. SMSC_TRACE(PROBE, "Driver Parameters:");
  1500. SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
  1501. (unsigned long)pdata->ioaddr);
  1502. SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
  1503. SMSC_TRACE(PROBE, "PHY will be autodetected.");
  1504. spin_lock_init(&pdata->dev_lock);
  1505. if (pdata->ioaddr == 0) {
  1506. SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
  1507. return -ENODEV;
  1508. }
  1509. /* Check byte ordering */
  1510. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1511. SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
  1512. if (byte_test == 0x43218765) {
  1513. SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
  1514. "applying WORD_SWAP");
  1515. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1516. /* 1 dummy read of BYTE_TEST is needed after a write to
  1517. * WORD_SWAP before its contents are valid */
  1518. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1519. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1520. }
  1521. if (byte_test != 0x87654321) {
  1522. SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
  1523. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1524. SMSC_WARNING(PROBE,
  1525. "top 16 bits equal to bottom 16 bits");
  1526. SMSC_TRACE(PROBE, "This may mean the chip is set "
  1527. "for 32 bit while the bus is reading 16 bit");
  1528. }
  1529. return -ENODEV;
  1530. }
  1531. /* Default generation to zero (all workarounds apply) */
  1532. pdata->generation = 0;
  1533. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1534. switch (pdata->idrev & 0xFFFF0000) {
  1535. case 0x01180000:
  1536. case 0x01170000:
  1537. case 0x01160000:
  1538. case 0x01150000:
  1539. /* LAN911[5678] family */
  1540. pdata->generation = pdata->idrev & 0x0000FFFF;
  1541. break;
  1542. case 0x118A0000:
  1543. case 0x117A0000:
  1544. case 0x116A0000:
  1545. case 0x115A0000:
  1546. /* LAN921[5678] family */
  1547. pdata->generation = 3;
  1548. break;
  1549. case 0x92100000:
  1550. case 0x92110000:
  1551. case 0x92200000:
  1552. case 0x92210000:
  1553. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1554. pdata->generation = 4;
  1555. break;
  1556. default:
  1557. SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
  1558. pdata->idrev);
  1559. return -ENODEV;
  1560. }
  1561. SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
  1562. pdata->idrev, pdata->generation);
  1563. if (pdata->generation == 0)
  1564. SMSC_WARNING(PROBE,
  1565. "This driver is not intended for this chip revision");
  1566. /* workaround for platforms without an eeprom, where the mac address
  1567. * is stored elsewhere and set by the bootloader. This saves the
  1568. * mac address before resetting the device */
  1569. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
  1570. smsc911x_read_mac_address(dev);
  1571. /* Reset the LAN911x */
  1572. if (smsc911x_soft_reset(pdata))
  1573. return -ENODEV;
  1574. /* Disable all interrupt sources until we bring the device up */
  1575. smsc911x_reg_write(pdata, INT_EN, 0);
  1576. ether_setup(dev);
  1577. dev->flags |= IFF_MULTICAST;
  1578. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1579. dev->netdev_ops = &smsc911x_netdev_ops;
  1580. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1581. return 0;
  1582. }
  1583. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1584. {
  1585. struct net_device *dev;
  1586. struct smsc911x_data *pdata;
  1587. struct resource *res;
  1588. dev = platform_get_drvdata(pdev);
  1589. BUG_ON(!dev);
  1590. pdata = netdev_priv(dev);
  1591. BUG_ON(!pdata);
  1592. BUG_ON(!pdata->ioaddr);
  1593. BUG_ON(!pdata->phy_dev);
  1594. SMSC_TRACE(IFDOWN, "Stopping driver.");
  1595. phy_disconnect(pdata->phy_dev);
  1596. pdata->phy_dev = NULL;
  1597. mdiobus_unregister(pdata->mii_bus);
  1598. mdiobus_free(pdata->mii_bus);
  1599. platform_set_drvdata(pdev, NULL);
  1600. unregister_netdev(dev);
  1601. free_irq(dev->irq, dev);
  1602. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1603. "smsc911x-memory");
  1604. if (!res)
  1605. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1606. release_mem_region(res->start, resource_size(res));
  1607. iounmap(pdata->ioaddr);
  1608. free_netdev(dev);
  1609. return 0;
  1610. }
  1611. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1612. {
  1613. struct net_device *dev;
  1614. struct smsc911x_data *pdata;
  1615. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1616. struct resource *res, *irq_res;
  1617. unsigned int intcfg = 0;
  1618. int res_size, irq_flags;
  1619. int retval;
  1620. pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
  1621. /* platform data specifies irq & dynamic bus configuration */
  1622. if (!pdev->dev.platform_data) {
  1623. pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
  1624. retval = -ENODEV;
  1625. goto out_0;
  1626. }
  1627. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1628. "smsc911x-memory");
  1629. if (!res)
  1630. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1631. if (!res) {
  1632. pr_warning("%s: Could not allocate resource.\n",
  1633. SMSC_CHIPNAME);
  1634. retval = -ENODEV;
  1635. goto out_0;
  1636. }
  1637. res_size = resource_size(res);
  1638. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1639. if (!irq_res) {
  1640. pr_warning("%s: Could not allocate irq resource.\n",
  1641. SMSC_CHIPNAME);
  1642. retval = -ENODEV;
  1643. goto out_0;
  1644. }
  1645. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1646. retval = -EBUSY;
  1647. goto out_0;
  1648. }
  1649. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1650. if (!dev) {
  1651. pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
  1652. retval = -ENOMEM;
  1653. goto out_release_io_1;
  1654. }
  1655. SET_NETDEV_DEV(dev, &pdev->dev);
  1656. pdata = netdev_priv(dev);
  1657. dev->irq = irq_res->start;
  1658. irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
  1659. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1660. /* copy config parameters across to pdata */
  1661. memcpy(&pdata->config, config, sizeof(pdata->config));
  1662. pdata->dev = dev;
  1663. pdata->msg_enable = ((1 << debug) - 1);
  1664. if (pdata->ioaddr == NULL) {
  1665. SMSC_WARNING(PROBE,
  1666. "Error smsc911x base address invalid");
  1667. retval = -ENOMEM;
  1668. goto out_free_netdev_2;
  1669. }
  1670. retval = smsc911x_init(dev);
  1671. if (retval < 0)
  1672. goto out_unmap_io_3;
  1673. /* configure irq polarity and type before connecting isr */
  1674. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1675. intcfg |= INT_CFG_IRQ_POL_;
  1676. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1677. intcfg |= INT_CFG_IRQ_TYPE_;
  1678. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1679. /* Ensure interrupts are globally disabled before connecting ISR */
  1680. smsc911x_reg_write(pdata, INT_EN, 0);
  1681. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1682. retval = request_irq(dev->irq, smsc911x_irqhandler,
  1683. irq_flags | IRQF_SHARED, dev->name, dev);
  1684. if (retval) {
  1685. SMSC_WARNING(PROBE,
  1686. "Unable to claim requested irq: %d", dev->irq);
  1687. goto out_unmap_io_3;
  1688. }
  1689. platform_set_drvdata(pdev, dev);
  1690. retval = register_netdev(dev);
  1691. if (retval) {
  1692. SMSC_WARNING(PROBE,
  1693. "Error %i registering device", retval);
  1694. goto out_unset_drvdata_4;
  1695. } else {
  1696. SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
  1697. }
  1698. spin_lock_init(&pdata->mac_lock);
  1699. retval = smsc911x_mii_init(pdev, dev);
  1700. if (retval) {
  1701. SMSC_WARNING(PROBE,
  1702. "Error %i initialising mii", retval);
  1703. goto out_unregister_netdev_5;
  1704. }
  1705. spin_lock_irq(&pdata->mac_lock);
  1706. /* Check if mac address has been specified when bringing interface up */
  1707. if (is_valid_ether_addr(dev->dev_addr)) {
  1708. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1709. SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
  1710. } else if (is_valid_ether_addr(pdata->config.mac)) {
  1711. memcpy(dev->dev_addr, pdata->config.mac, 6);
  1712. SMSC_TRACE(PROBE, "MAC Address specified by platform data");
  1713. } else {
  1714. /* Try reading mac address from device. if EEPROM is present
  1715. * it will already have been set */
  1716. smsc_get_mac(dev);
  1717. if (is_valid_ether_addr(dev->dev_addr)) {
  1718. /* eeprom values are valid so use them */
  1719. SMSC_TRACE(PROBE,
  1720. "Mac Address is read from LAN911x EEPROM");
  1721. } else {
  1722. /* eeprom values are invalid, generate random MAC */
  1723. random_ether_addr(dev->dev_addr);
  1724. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1725. SMSC_TRACE(PROBE,
  1726. "MAC Address is set to random_ether_addr");
  1727. }
  1728. }
  1729. spin_unlock_irq(&pdata->mac_lock);
  1730. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1731. return 0;
  1732. out_unregister_netdev_5:
  1733. unregister_netdev(dev);
  1734. out_unset_drvdata_4:
  1735. platform_set_drvdata(pdev, NULL);
  1736. free_irq(dev->irq, dev);
  1737. out_unmap_io_3:
  1738. iounmap(pdata->ioaddr);
  1739. out_free_netdev_2:
  1740. free_netdev(dev);
  1741. out_release_io_1:
  1742. release_mem_region(res->start, resource_size(res));
  1743. out_0:
  1744. return retval;
  1745. }
  1746. #ifdef CONFIG_PM
  1747. /* This implementation assumes the devices remains powered on its VDDVARIO
  1748. * pins during suspend. */
  1749. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  1750. static int smsc911x_suspend(struct device *dev)
  1751. {
  1752. struct net_device *ndev = dev_get_drvdata(dev);
  1753. struct smsc911x_data *pdata = netdev_priv(ndev);
  1754. /* enable wake on LAN, energy detection and the external PME
  1755. * signal. */
  1756. smsc911x_reg_write(pdata, PMT_CTRL,
  1757. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  1758. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  1759. return 0;
  1760. }
  1761. static int smsc911x_resume(struct device *dev)
  1762. {
  1763. struct net_device *ndev = dev_get_drvdata(dev);
  1764. struct smsc911x_data *pdata = netdev_priv(ndev);
  1765. unsigned int to = 100;
  1766. /* Note 3.11 from the datasheet:
  1767. * "When the LAN9220 is in a power saving state, a write of any
  1768. * data to the BYTE_TEST register will wake-up the device."
  1769. */
  1770. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  1771. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  1772. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  1773. * if it failed. */
  1774. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  1775. udelay(1000);
  1776. return (to == 0) ? -EIO : 0;
  1777. }
  1778. static const struct dev_pm_ops smsc911x_pm_ops = {
  1779. .suspend = smsc911x_suspend,
  1780. .resume = smsc911x_resume,
  1781. };
  1782. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  1783. #else
  1784. #define SMSC911X_PM_OPS NULL
  1785. #endif
  1786. static struct platform_driver smsc911x_driver = {
  1787. .probe = smsc911x_drv_probe,
  1788. .remove = __devexit_p(smsc911x_drv_remove),
  1789. .driver = {
  1790. .name = SMSC_CHIPNAME,
  1791. .owner = THIS_MODULE,
  1792. .pm = SMSC911X_PM_OPS,
  1793. },
  1794. };
  1795. /* Entry point for loading the module */
  1796. static int __init smsc911x_init_module(void)
  1797. {
  1798. SMSC_INITIALIZE();
  1799. return platform_driver_register(&smsc911x_driver);
  1800. }
  1801. /* entry point for unloading the module */
  1802. static void __exit smsc911x_cleanup_module(void)
  1803. {
  1804. platform_driver_unregister(&smsc911x_driver);
  1805. }
  1806. module_init(smsc911x_init_module);
  1807. module_exit(smsc911x_cleanup_module);