rx.c 22 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2011 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/tcp.h>
  15. #include <linux/udp.h>
  16. #include <net/ip.h>
  17. #include <net/checksum.h>
  18. #include "net_driver.h"
  19. #include "efx.h"
  20. #include "nic.h"
  21. #include "selftest.h"
  22. #include "workarounds.h"
  23. /* Number of RX descriptors pushed at once. */
  24. #define EFX_RX_BATCH 8
  25. /* Maximum size of a buffer sharing a page */
  26. #define EFX_RX_HALF_PAGE ((PAGE_SIZE >> 1) - sizeof(struct efx_rx_page_state))
  27. /* Size of buffer allocated for skb header area. */
  28. #define EFX_SKB_HEADERS 64u
  29. /*
  30. * rx_alloc_method - RX buffer allocation method
  31. *
  32. * This driver supports two methods for allocating and using RX buffers:
  33. * each RX buffer may be backed by an skb or by an order-n page.
  34. *
  35. * When GRO is in use then the second method has a lower overhead,
  36. * since we don't have to allocate then free skbs on reassembled frames.
  37. *
  38. * Values:
  39. * - RX_ALLOC_METHOD_AUTO = 0
  40. * - RX_ALLOC_METHOD_SKB = 1
  41. * - RX_ALLOC_METHOD_PAGE = 2
  42. *
  43. * The heuristic for %RX_ALLOC_METHOD_AUTO is a simple hysteresis count
  44. * controlled by the parameters below.
  45. *
  46. * - Since pushing and popping descriptors are separated by the rx_queue
  47. * size, so the watermarks should be ~rxd_size.
  48. * - The performance win by using page-based allocation for GRO is less
  49. * than the performance hit of using page-based allocation of non-GRO,
  50. * so the watermarks should reflect this.
  51. *
  52. * Per channel we maintain a single variable, updated by each channel:
  53. *
  54. * rx_alloc_level += (gro_performed ? RX_ALLOC_FACTOR_GRO :
  55. * RX_ALLOC_FACTOR_SKB)
  56. * Per NAPI poll interval, we constrain rx_alloc_level to 0..MAX (which
  57. * limits the hysteresis), and update the allocation strategy:
  58. *
  59. * rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_GRO ?
  60. * RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB)
  61. */
  62. static int rx_alloc_method = RX_ALLOC_METHOD_AUTO;
  63. #define RX_ALLOC_LEVEL_GRO 0x2000
  64. #define RX_ALLOC_LEVEL_MAX 0x3000
  65. #define RX_ALLOC_FACTOR_GRO 1
  66. #define RX_ALLOC_FACTOR_SKB (-2)
  67. /* This is the percentage fill level below which new RX descriptors
  68. * will be added to the RX descriptor ring.
  69. */
  70. static unsigned int rx_refill_threshold = 90;
  71. /* This is the percentage fill level to which an RX queue will be refilled
  72. * when the "RX refill threshold" is reached.
  73. */
  74. static unsigned int rx_refill_limit = 95;
  75. /*
  76. * RX maximum head room required.
  77. *
  78. * This must be at least 1 to prevent overflow and at least 2 to allow
  79. * pipelined receives.
  80. */
  81. #define EFX_RXD_HEAD_ROOM 2
  82. /* Offset of ethernet header within page */
  83. static inline unsigned int efx_rx_buf_offset(struct efx_nic *efx,
  84. struct efx_rx_buffer *buf)
  85. {
  86. /* Offset is always within one page, so we don't need to consider
  87. * the page order.
  88. */
  89. return (((__force unsigned long) buf->dma_addr & (PAGE_SIZE - 1)) +
  90. efx->type->rx_buffer_hash_size);
  91. }
  92. static inline unsigned int efx_rx_buf_size(struct efx_nic *efx)
  93. {
  94. return PAGE_SIZE << efx->rx_buffer_order;
  95. }
  96. static u8 *efx_rx_buf_eh(struct efx_nic *efx, struct efx_rx_buffer *buf)
  97. {
  98. if (buf->is_page)
  99. return page_address(buf->u.page) + efx_rx_buf_offset(efx, buf);
  100. else
  101. return ((u8 *)buf->u.skb->data +
  102. efx->type->rx_buffer_hash_size);
  103. }
  104. static inline u32 efx_rx_buf_hash(const u8 *eh)
  105. {
  106. /* The ethernet header is always directly after any hash. */
  107. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || NET_IP_ALIGN % 4 == 0
  108. return __le32_to_cpup((const __le32 *)(eh - 4));
  109. #else
  110. const u8 *data = eh - 4;
  111. return ((u32)data[0] |
  112. (u32)data[1] << 8 |
  113. (u32)data[2] << 16 |
  114. (u32)data[3] << 24);
  115. #endif
  116. }
  117. /**
  118. * efx_init_rx_buffers_skb - create EFX_RX_BATCH skb-based RX buffers
  119. *
  120. * @rx_queue: Efx RX queue
  121. *
  122. * This allocates EFX_RX_BATCH skbs, maps them for DMA, and populates a
  123. * struct efx_rx_buffer for each one. Return a negative error code or 0
  124. * on success. May fail having only inserted fewer than EFX_RX_BATCH
  125. * buffers.
  126. */
  127. static int efx_init_rx_buffers_skb(struct efx_rx_queue *rx_queue)
  128. {
  129. struct efx_nic *efx = rx_queue->efx;
  130. struct net_device *net_dev = efx->net_dev;
  131. struct efx_rx_buffer *rx_buf;
  132. struct sk_buff *skb;
  133. int skb_len = efx->rx_buffer_len;
  134. unsigned index, count;
  135. for (count = 0; count < EFX_RX_BATCH; ++count) {
  136. index = rx_queue->added_count & rx_queue->ptr_mask;
  137. rx_buf = efx_rx_buffer(rx_queue, index);
  138. rx_buf->u.skb = skb = netdev_alloc_skb(net_dev, skb_len);
  139. if (unlikely(!skb))
  140. return -ENOMEM;
  141. /* Adjust the SKB for padding and checksum */
  142. skb_reserve(skb, NET_IP_ALIGN);
  143. rx_buf->len = skb_len - NET_IP_ALIGN;
  144. rx_buf->is_page = false;
  145. skb->ip_summed = CHECKSUM_UNNECESSARY;
  146. rx_buf->dma_addr = pci_map_single(efx->pci_dev,
  147. skb->data, rx_buf->len,
  148. PCI_DMA_FROMDEVICE);
  149. if (unlikely(pci_dma_mapping_error(efx->pci_dev,
  150. rx_buf->dma_addr))) {
  151. dev_kfree_skb_any(skb);
  152. rx_buf->u.skb = NULL;
  153. return -EIO;
  154. }
  155. ++rx_queue->added_count;
  156. ++rx_queue->alloc_skb_count;
  157. }
  158. return 0;
  159. }
  160. /**
  161. * efx_init_rx_buffers_page - create EFX_RX_BATCH page-based RX buffers
  162. *
  163. * @rx_queue: Efx RX queue
  164. *
  165. * This allocates memory for EFX_RX_BATCH receive buffers, maps them for DMA,
  166. * and populates struct efx_rx_buffers for each one. Return a negative error
  167. * code or 0 on success. If a single page can be split between two buffers,
  168. * then the page will either be inserted fully, or not at at all.
  169. */
  170. static int efx_init_rx_buffers_page(struct efx_rx_queue *rx_queue)
  171. {
  172. struct efx_nic *efx = rx_queue->efx;
  173. struct efx_rx_buffer *rx_buf;
  174. struct page *page;
  175. void *page_addr;
  176. struct efx_rx_page_state *state;
  177. dma_addr_t dma_addr;
  178. unsigned index, count;
  179. /* We can split a page between two buffers */
  180. BUILD_BUG_ON(EFX_RX_BATCH & 1);
  181. for (count = 0; count < EFX_RX_BATCH; ++count) {
  182. page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC,
  183. efx->rx_buffer_order);
  184. if (unlikely(page == NULL))
  185. return -ENOMEM;
  186. dma_addr = pci_map_page(efx->pci_dev, page, 0,
  187. efx_rx_buf_size(efx),
  188. PCI_DMA_FROMDEVICE);
  189. if (unlikely(pci_dma_mapping_error(efx->pci_dev, dma_addr))) {
  190. __free_pages(page, efx->rx_buffer_order);
  191. return -EIO;
  192. }
  193. page_addr = page_address(page);
  194. state = page_addr;
  195. state->refcnt = 0;
  196. state->dma_addr = dma_addr;
  197. page_addr += sizeof(struct efx_rx_page_state);
  198. dma_addr += sizeof(struct efx_rx_page_state);
  199. split:
  200. index = rx_queue->added_count & rx_queue->ptr_mask;
  201. rx_buf = efx_rx_buffer(rx_queue, index);
  202. rx_buf->dma_addr = dma_addr + EFX_PAGE_IP_ALIGN;
  203. rx_buf->u.page = page;
  204. rx_buf->len = efx->rx_buffer_len - EFX_PAGE_IP_ALIGN;
  205. rx_buf->is_page = true;
  206. ++rx_queue->added_count;
  207. ++rx_queue->alloc_page_count;
  208. ++state->refcnt;
  209. if ((~count & 1) && (efx->rx_buffer_len <= EFX_RX_HALF_PAGE)) {
  210. /* Use the second half of the page */
  211. get_page(page);
  212. dma_addr += (PAGE_SIZE >> 1);
  213. page_addr += (PAGE_SIZE >> 1);
  214. ++count;
  215. goto split;
  216. }
  217. }
  218. return 0;
  219. }
  220. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  221. struct efx_rx_buffer *rx_buf)
  222. {
  223. if (rx_buf->is_page && rx_buf->u.page) {
  224. struct efx_rx_page_state *state;
  225. state = page_address(rx_buf->u.page);
  226. if (--state->refcnt == 0) {
  227. pci_unmap_page(efx->pci_dev,
  228. state->dma_addr,
  229. efx_rx_buf_size(efx),
  230. PCI_DMA_FROMDEVICE);
  231. }
  232. } else if (!rx_buf->is_page && rx_buf->u.skb) {
  233. pci_unmap_single(efx->pci_dev, rx_buf->dma_addr,
  234. rx_buf->len, PCI_DMA_FROMDEVICE);
  235. }
  236. }
  237. static void efx_free_rx_buffer(struct efx_nic *efx,
  238. struct efx_rx_buffer *rx_buf)
  239. {
  240. if (rx_buf->is_page && rx_buf->u.page) {
  241. __free_pages(rx_buf->u.page, efx->rx_buffer_order);
  242. rx_buf->u.page = NULL;
  243. } else if (!rx_buf->is_page && rx_buf->u.skb) {
  244. dev_kfree_skb_any(rx_buf->u.skb);
  245. rx_buf->u.skb = NULL;
  246. }
  247. }
  248. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  249. struct efx_rx_buffer *rx_buf)
  250. {
  251. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  252. efx_free_rx_buffer(rx_queue->efx, rx_buf);
  253. }
  254. /* Attempt to resurrect the other receive buffer that used to share this page,
  255. * which had previously been passed up to the kernel and freed. */
  256. static void efx_resurrect_rx_buffer(struct efx_rx_queue *rx_queue,
  257. struct efx_rx_buffer *rx_buf)
  258. {
  259. struct efx_rx_page_state *state = page_address(rx_buf->u.page);
  260. struct efx_rx_buffer *new_buf;
  261. unsigned fill_level, index;
  262. /* +1 because efx_rx_packet() incremented removed_count. +1 because
  263. * we'd like to insert an additional descriptor whilst leaving
  264. * EFX_RXD_HEAD_ROOM for the non-recycle path */
  265. fill_level = (rx_queue->added_count - rx_queue->removed_count + 2);
  266. if (unlikely(fill_level > rx_queue->max_fill)) {
  267. /* We could place "state" on a list, and drain the list in
  268. * efx_fast_push_rx_descriptors(). For now, this will do. */
  269. return;
  270. }
  271. ++state->refcnt;
  272. get_page(rx_buf->u.page);
  273. index = rx_queue->added_count & rx_queue->ptr_mask;
  274. new_buf = efx_rx_buffer(rx_queue, index);
  275. new_buf->dma_addr = rx_buf->dma_addr ^ (PAGE_SIZE >> 1);
  276. new_buf->u.page = rx_buf->u.page;
  277. new_buf->len = rx_buf->len;
  278. new_buf->is_page = true;
  279. ++rx_queue->added_count;
  280. }
  281. /* Recycle the given rx buffer directly back into the rx_queue. There is
  282. * always room to add this buffer, because we've just popped a buffer. */
  283. static void efx_recycle_rx_buffer(struct efx_channel *channel,
  284. struct efx_rx_buffer *rx_buf)
  285. {
  286. struct efx_nic *efx = channel->efx;
  287. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  288. struct efx_rx_buffer *new_buf;
  289. unsigned index;
  290. if (rx_buf->is_page && efx->rx_buffer_len <= EFX_RX_HALF_PAGE &&
  291. page_count(rx_buf->u.page) == 1)
  292. efx_resurrect_rx_buffer(rx_queue, rx_buf);
  293. index = rx_queue->added_count & rx_queue->ptr_mask;
  294. new_buf = efx_rx_buffer(rx_queue, index);
  295. memcpy(new_buf, rx_buf, sizeof(*new_buf));
  296. rx_buf->u.page = NULL;
  297. ++rx_queue->added_count;
  298. }
  299. /**
  300. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  301. * @rx_queue: RX descriptor queue
  302. * This will aim to fill the RX descriptor queue up to
  303. * @rx_queue->@fast_fill_limit. If there is insufficient atomic
  304. * memory to do so, a slow fill will be scheduled.
  305. *
  306. * The caller must provide serialisation (none is used here). In practise,
  307. * this means this function must run from the NAPI handler, or be called
  308. * when NAPI is disabled.
  309. */
  310. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue)
  311. {
  312. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  313. unsigned fill_level;
  314. int space, rc = 0;
  315. /* Calculate current fill level, and exit if we don't need to fill */
  316. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  317. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  318. if (fill_level >= rx_queue->fast_fill_trigger)
  319. goto out;
  320. /* Record minimum fill level */
  321. if (unlikely(fill_level < rx_queue->min_fill)) {
  322. if (fill_level)
  323. rx_queue->min_fill = fill_level;
  324. }
  325. space = rx_queue->fast_fill_limit - fill_level;
  326. if (space < EFX_RX_BATCH)
  327. goto out;
  328. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  329. "RX queue %d fast-filling descriptor ring from"
  330. " level %d to level %d using %s allocation\n",
  331. efx_rx_queue_index(rx_queue), fill_level,
  332. rx_queue->fast_fill_limit,
  333. channel->rx_alloc_push_pages ? "page" : "skb");
  334. do {
  335. if (channel->rx_alloc_push_pages)
  336. rc = efx_init_rx_buffers_page(rx_queue);
  337. else
  338. rc = efx_init_rx_buffers_skb(rx_queue);
  339. if (unlikely(rc)) {
  340. /* Ensure that we don't leave the rx queue empty */
  341. if (rx_queue->added_count == rx_queue->removed_count)
  342. efx_schedule_slow_fill(rx_queue);
  343. goto out;
  344. }
  345. } while ((space -= EFX_RX_BATCH) >= EFX_RX_BATCH);
  346. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  347. "RX queue %d fast-filled descriptor ring "
  348. "to level %d\n", efx_rx_queue_index(rx_queue),
  349. rx_queue->added_count - rx_queue->removed_count);
  350. out:
  351. if (rx_queue->notified_count != rx_queue->added_count)
  352. efx_nic_notify_rx_desc(rx_queue);
  353. }
  354. void efx_rx_slow_fill(unsigned long context)
  355. {
  356. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  357. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  358. /* Post an event to cause NAPI to run and refill the queue */
  359. efx_nic_generate_fill_event(channel);
  360. ++rx_queue->slow_fill_count;
  361. }
  362. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  363. struct efx_rx_buffer *rx_buf,
  364. int len, bool *discard,
  365. bool *leak_packet)
  366. {
  367. struct efx_nic *efx = rx_queue->efx;
  368. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  369. if (likely(len <= max_len))
  370. return;
  371. /* The packet must be discarded, but this is only a fatal error
  372. * if the caller indicated it was
  373. */
  374. *discard = true;
  375. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  376. if (net_ratelimit())
  377. netif_err(efx, rx_err, efx->net_dev,
  378. " RX queue %d seriously overlength "
  379. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  380. efx_rx_queue_index(rx_queue), len, max_len,
  381. efx->type->rx_buffer_padding);
  382. /* If this buffer was skb-allocated, then the meta
  383. * data at the end of the skb will be trashed. So
  384. * we have no choice but to leak the fragment.
  385. */
  386. *leak_packet = !rx_buf->is_page;
  387. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  388. } else {
  389. if (net_ratelimit())
  390. netif_err(efx, rx_err, efx->net_dev,
  391. " RX queue %d overlength RX event "
  392. "(0x%x > 0x%x)\n",
  393. efx_rx_queue_index(rx_queue), len, max_len);
  394. }
  395. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  396. }
  397. /* Pass a received packet up through the generic GRO stack
  398. *
  399. * Handles driverlink veto, and passes the fragment up via
  400. * the appropriate GRO method
  401. */
  402. static void efx_rx_packet_gro(struct efx_channel *channel,
  403. struct efx_rx_buffer *rx_buf,
  404. const u8 *eh, bool checksummed)
  405. {
  406. struct napi_struct *napi = &channel->napi_str;
  407. gro_result_t gro_result;
  408. /* Pass the skb/page into the GRO engine */
  409. if (rx_buf->is_page) {
  410. struct efx_nic *efx = channel->efx;
  411. struct page *page = rx_buf->u.page;
  412. struct sk_buff *skb;
  413. rx_buf->u.page = NULL;
  414. skb = napi_get_frags(napi);
  415. if (!skb) {
  416. put_page(page);
  417. return;
  418. }
  419. if (efx->net_dev->features & NETIF_F_RXHASH)
  420. skb->rxhash = efx_rx_buf_hash(eh);
  421. skb_shinfo(skb)->frags[0].page = page;
  422. skb_shinfo(skb)->frags[0].page_offset =
  423. efx_rx_buf_offset(efx, rx_buf);
  424. skb_shinfo(skb)->frags[0].size = rx_buf->len;
  425. skb_shinfo(skb)->nr_frags = 1;
  426. skb->len = rx_buf->len;
  427. skb->data_len = rx_buf->len;
  428. skb->truesize += rx_buf->len;
  429. skb->ip_summed =
  430. checksummed ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE;
  431. skb_record_rx_queue(skb, channel->channel);
  432. gro_result = napi_gro_frags(napi);
  433. } else {
  434. struct sk_buff *skb = rx_buf->u.skb;
  435. EFX_BUG_ON_PARANOID(!checksummed);
  436. rx_buf->u.skb = NULL;
  437. gro_result = napi_gro_receive(napi, skb);
  438. }
  439. if (gro_result == GRO_NORMAL) {
  440. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  441. } else if (gro_result != GRO_DROP) {
  442. channel->rx_alloc_level += RX_ALLOC_FACTOR_GRO;
  443. channel->irq_mod_score += 2;
  444. }
  445. }
  446. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  447. unsigned int len, bool checksummed, bool discard)
  448. {
  449. struct efx_nic *efx = rx_queue->efx;
  450. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  451. struct efx_rx_buffer *rx_buf;
  452. bool leak_packet = false;
  453. rx_buf = efx_rx_buffer(rx_queue, index);
  454. /* This allows the refill path to post another buffer.
  455. * EFX_RXD_HEAD_ROOM ensures that the slot we are using
  456. * isn't overwritten yet.
  457. */
  458. rx_queue->removed_count++;
  459. /* Validate the length encoded in the event vs the descriptor pushed */
  460. efx_rx_packet__check_len(rx_queue, rx_buf, len,
  461. &discard, &leak_packet);
  462. netif_vdbg(efx, rx_status, efx->net_dev,
  463. "RX queue %d received id %x at %llx+%x %s%s\n",
  464. efx_rx_queue_index(rx_queue), index,
  465. (unsigned long long)rx_buf->dma_addr, len,
  466. (checksummed ? " [SUMMED]" : ""),
  467. (discard ? " [DISCARD]" : ""));
  468. /* Discard packet, if instructed to do so */
  469. if (unlikely(discard)) {
  470. if (unlikely(leak_packet))
  471. channel->n_skbuff_leaks++;
  472. else
  473. efx_recycle_rx_buffer(channel, rx_buf);
  474. /* Don't hold off the previous receive */
  475. rx_buf = NULL;
  476. goto out;
  477. }
  478. /* Release card resources - assumes all RX buffers consumed in-order
  479. * per RX queue
  480. */
  481. efx_unmap_rx_buffer(efx, rx_buf);
  482. /* Prefetch nice and early so data will (hopefully) be in cache by
  483. * the time we look at it.
  484. */
  485. prefetch(efx_rx_buf_eh(efx, rx_buf));
  486. /* Pipeline receives so that we give time for packet headers to be
  487. * prefetched into cache.
  488. */
  489. rx_buf->len = len - efx->type->rx_buffer_hash_size;
  490. out:
  491. if (channel->rx_pkt)
  492. __efx_rx_packet(channel,
  493. channel->rx_pkt, channel->rx_pkt_csummed);
  494. channel->rx_pkt = rx_buf;
  495. channel->rx_pkt_csummed = checksummed;
  496. }
  497. /* Handle a received packet. Second half: Touches packet payload. */
  498. void __efx_rx_packet(struct efx_channel *channel,
  499. struct efx_rx_buffer *rx_buf, bool checksummed)
  500. {
  501. struct efx_nic *efx = channel->efx;
  502. struct sk_buff *skb;
  503. u8 *eh = efx_rx_buf_eh(efx, rx_buf);
  504. /* If we're in loopback test, then pass the packet directly to the
  505. * loopback layer, and free the rx_buf here
  506. */
  507. if (unlikely(efx->loopback_selftest)) {
  508. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  509. efx_free_rx_buffer(efx, rx_buf);
  510. return;
  511. }
  512. if (!rx_buf->is_page) {
  513. skb = rx_buf->u.skb;
  514. prefetch(skb_shinfo(skb));
  515. skb_reserve(skb, efx->type->rx_buffer_hash_size);
  516. skb_put(skb, rx_buf->len);
  517. if (efx->net_dev->features & NETIF_F_RXHASH)
  518. skb->rxhash = efx_rx_buf_hash(eh);
  519. /* Move past the ethernet header. rx_buf->data still points
  520. * at the ethernet header */
  521. skb->protocol = eth_type_trans(skb, efx->net_dev);
  522. skb_record_rx_queue(skb, channel->channel);
  523. }
  524. if (likely(checksummed || rx_buf->is_page)) {
  525. efx_rx_packet_gro(channel, rx_buf, eh, checksummed);
  526. return;
  527. }
  528. /* We now own the SKB */
  529. skb = rx_buf->u.skb;
  530. rx_buf->u.skb = NULL;
  531. /* Set the SKB flags */
  532. skb_checksum_none_assert(skb);
  533. /* Pass the packet up */
  534. netif_receive_skb(skb);
  535. /* Update allocation strategy method */
  536. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  537. }
  538. void efx_rx_strategy(struct efx_channel *channel)
  539. {
  540. enum efx_rx_alloc_method method = rx_alloc_method;
  541. /* Only makes sense to use page based allocation if GRO is enabled */
  542. if (!(channel->efx->net_dev->features & NETIF_F_GRO)) {
  543. method = RX_ALLOC_METHOD_SKB;
  544. } else if (method == RX_ALLOC_METHOD_AUTO) {
  545. /* Constrain the rx_alloc_level */
  546. if (channel->rx_alloc_level < 0)
  547. channel->rx_alloc_level = 0;
  548. else if (channel->rx_alloc_level > RX_ALLOC_LEVEL_MAX)
  549. channel->rx_alloc_level = RX_ALLOC_LEVEL_MAX;
  550. /* Decide on the allocation method */
  551. method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_GRO) ?
  552. RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB);
  553. }
  554. /* Push the option */
  555. channel->rx_alloc_push_pages = (method == RX_ALLOC_METHOD_PAGE);
  556. }
  557. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  558. {
  559. struct efx_nic *efx = rx_queue->efx;
  560. unsigned int entries;
  561. int rc;
  562. /* Create the smallest power-of-two aligned ring */
  563. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  564. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  565. rx_queue->ptr_mask = entries - 1;
  566. netif_dbg(efx, probe, efx->net_dev,
  567. "creating RX queue %d size %#x mask %#x\n",
  568. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  569. rx_queue->ptr_mask);
  570. /* Allocate RX buffers */
  571. rx_queue->buffer = kzalloc(entries * sizeof(*rx_queue->buffer),
  572. GFP_KERNEL);
  573. if (!rx_queue->buffer)
  574. return -ENOMEM;
  575. rc = efx_nic_probe_rx(rx_queue);
  576. if (rc) {
  577. kfree(rx_queue->buffer);
  578. rx_queue->buffer = NULL;
  579. }
  580. return rc;
  581. }
  582. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  583. {
  584. struct efx_nic *efx = rx_queue->efx;
  585. unsigned int max_fill, trigger, limit;
  586. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  587. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  588. /* Initialise ptr fields */
  589. rx_queue->added_count = 0;
  590. rx_queue->notified_count = 0;
  591. rx_queue->removed_count = 0;
  592. rx_queue->min_fill = -1U;
  593. /* Initialise limit fields */
  594. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  595. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  596. limit = max_fill * min(rx_refill_limit, 100U) / 100U;
  597. rx_queue->max_fill = max_fill;
  598. rx_queue->fast_fill_trigger = trigger;
  599. rx_queue->fast_fill_limit = limit;
  600. /* Set up RX descriptor ring */
  601. efx_nic_init_rx(rx_queue);
  602. }
  603. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  604. {
  605. int i;
  606. struct efx_rx_buffer *rx_buf;
  607. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  608. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  609. del_timer_sync(&rx_queue->slow_fill);
  610. efx_nic_fini_rx(rx_queue);
  611. /* Release RX buffers NB start at index 0 not current HW ptr */
  612. if (rx_queue->buffer) {
  613. for (i = 0; i <= rx_queue->ptr_mask; i++) {
  614. rx_buf = efx_rx_buffer(rx_queue, i);
  615. efx_fini_rx_buffer(rx_queue, rx_buf);
  616. }
  617. }
  618. }
  619. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  620. {
  621. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  622. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  623. efx_nic_remove_rx(rx_queue);
  624. kfree(rx_queue->buffer);
  625. rx_queue->buffer = NULL;
  626. }
  627. module_param(rx_alloc_method, int, 0644);
  628. MODULE_PARM_DESC(rx_alloc_method, "Allocation method used for RX buffers");
  629. module_param(rx_refill_threshold, uint, 0444);
  630. MODULE_PARM_DESC(rx_refill_threshold,
  631. "RX descriptor ring fast/slow fill threshold (%)");