mcdi.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= 0x100);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4) {
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* use wmb() within loop to inhibit write combining */
  83. wmb();
  84. }
  85. /* ring the doorbell with a distinctive value */
  86. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  87. wmb();
  88. }
  89. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  90. {
  91. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  92. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  93. int i;
  94. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  95. BUG_ON(outlen & 3 || outlen >= 0x100);
  96. for (i = 0; i < outlen; i += 4)
  97. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  98. }
  99. static int efx_mcdi_poll(struct efx_nic *efx)
  100. {
  101. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  102. unsigned int time, finish;
  103. unsigned int respseq, respcmd, error;
  104. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  105. unsigned int rc, spins;
  106. efx_dword_t reg;
  107. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  108. rc = -efx_mcdi_poll_reboot(efx);
  109. if (rc)
  110. goto out;
  111. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  112. * because generally mcdi responses are fast. After that, back off
  113. * and poll once a jiffy (approximately)
  114. */
  115. spins = TICK_USEC;
  116. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  117. while (1) {
  118. if (spins != 0) {
  119. --spins;
  120. udelay(1);
  121. } else {
  122. schedule_timeout_uninterruptible(1);
  123. }
  124. time = get_seconds();
  125. rmb();
  126. efx_readd(efx, &reg, pdu);
  127. /* All 1's indicates that shared memory is in reset (and is
  128. * not a valid header). Wait for it to come out reset before
  129. * completing the command */
  130. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  131. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  132. break;
  133. if (time >= finish)
  134. return -ETIMEDOUT;
  135. }
  136. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  137. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  138. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  139. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  140. if (error && mcdi->resplen == 0) {
  141. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  142. rc = EIO;
  143. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  144. netif_err(efx, hw, efx->net_dev,
  145. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  146. respseq, mcdi->seqno);
  147. rc = EIO;
  148. } else if (error) {
  149. efx_readd(efx, &reg, pdu + 4);
  150. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  151. #define TRANSLATE_ERROR(name) \
  152. case MC_CMD_ERR_ ## name: \
  153. rc = name; \
  154. break
  155. TRANSLATE_ERROR(ENOENT);
  156. TRANSLATE_ERROR(EINTR);
  157. TRANSLATE_ERROR(EACCES);
  158. TRANSLATE_ERROR(EBUSY);
  159. TRANSLATE_ERROR(EINVAL);
  160. TRANSLATE_ERROR(EDEADLK);
  161. TRANSLATE_ERROR(ENOSYS);
  162. TRANSLATE_ERROR(ETIME);
  163. #undef TRANSLATE_ERROR
  164. default:
  165. rc = EIO;
  166. break;
  167. }
  168. } else
  169. rc = 0;
  170. out:
  171. mcdi->resprc = rc;
  172. if (rc)
  173. mcdi->resplen = 0;
  174. /* Return rc=0 like wait_event_timeout() */
  175. return 0;
  176. }
  177. /* Test and clear MC-rebooted flag for this port/function */
  178. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  179. {
  180. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
  181. efx_dword_t reg;
  182. uint32_t value;
  183. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  184. return false;
  185. efx_readd(efx, &reg, addr);
  186. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  187. if (value == 0)
  188. return 0;
  189. EFX_ZERO_DWORD(reg);
  190. efx_writed(efx, &reg, addr);
  191. if (value == MC_STATUS_DWORD_ASSERT)
  192. return -EINTR;
  193. else
  194. return -EIO;
  195. }
  196. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  197. {
  198. /* Wait until the interface becomes QUIESCENT and we win the race
  199. * to mark it RUNNING. */
  200. wait_event(mcdi->wq,
  201. atomic_cmpxchg(&mcdi->state,
  202. MCDI_STATE_QUIESCENT,
  203. MCDI_STATE_RUNNING)
  204. == MCDI_STATE_QUIESCENT);
  205. }
  206. static int efx_mcdi_await_completion(struct efx_nic *efx)
  207. {
  208. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  209. if (wait_event_timeout(
  210. mcdi->wq,
  211. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  212. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  213. return -ETIMEDOUT;
  214. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  215. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  216. * completed the request first, then we'll just end up completing the
  217. * request again, which is safe.
  218. *
  219. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  220. * wait_event_timeout() implicitly provides.
  221. */
  222. if (mcdi->mode == MCDI_MODE_POLL)
  223. return efx_mcdi_poll(efx);
  224. return 0;
  225. }
  226. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  227. {
  228. /* If the interface is RUNNING, then move to COMPLETED and wake any
  229. * waiters. If the interface isn't in RUNNING then we've received a
  230. * duplicate completion after we've already transitioned back to
  231. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  232. * have failed the seqno check].
  233. */
  234. if (atomic_cmpxchg(&mcdi->state,
  235. MCDI_STATE_RUNNING,
  236. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  237. wake_up(&mcdi->wq);
  238. return true;
  239. }
  240. return false;
  241. }
  242. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  243. {
  244. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  245. wake_up(&mcdi->wq);
  246. }
  247. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  248. unsigned int datalen, unsigned int errno)
  249. {
  250. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  251. bool wake = false;
  252. spin_lock(&mcdi->iface_lock);
  253. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  254. if (mcdi->credits)
  255. /* The request has been cancelled */
  256. --mcdi->credits;
  257. else
  258. netif_err(efx, hw, efx->net_dev,
  259. "MC response mismatch tx seq 0x%x rx "
  260. "seq 0x%x\n", seqno, mcdi->seqno);
  261. } else {
  262. mcdi->resprc = errno;
  263. mcdi->resplen = datalen;
  264. wake = true;
  265. }
  266. spin_unlock(&mcdi->iface_lock);
  267. if (wake)
  268. efx_mcdi_complete(mcdi);
  269. }
  270. /* Issue the given command by writing the data into the shared memory PDU,
  271. * ring the doorbell and wait for completion. Copyout the result. */
  272. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  273. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  274. size_t *outlen_actual)
  275. {
  276. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  277. int rc;
  278. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  279. efx_mcdi_acquire(mcdi);
  280. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  281. spin_lock_bh(&mcdi->iface_lock);
  282. ++mcdi->seqno;
  283. spin_unlock_bh(&mcdi->iface_lock);
  284. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  285. if (mcdi->mode == MCDI_MODE_POLL)
  286. rc = efx_mcdi_poll(efx);
  287. else
  288. rc = efx_mcdi_await_completion(efx);
  289. if (rc != 0) {
  290. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  291. * and completing a request we've just cancelled, by ensuring
  292. * that the seqno check therein fails.
  293. */
  294. spin_lock_bh(&mcdi->iface_lock);
  295. ++mcdi->seqno;
  296. ++mcdi->credits;
  297. spin_unlock_bh(&mcdi->iface_lock);
  298. netif_err(efx, hw, efx->net_dev,
  299. "MC command 0x%x inlen %d mode %d timed out\n",
  300. cmd, (int)inlen, mcdi->mode);
  301. } else {
  302. size_t resplen;
  303. /* At the very least we need a memory barrier here to ensure
  304. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  305. * a spurious efx_mcdi_ev_cpl() running concurrently by
  306. * acquiring the iface_lock. */
  307. spin_lock_bh(&mcdi->iface_lock);
  308. rc = -mcdi->resprc;
  309. resplen = mcdi->resplen;
  310. spin_unlock_bh(&mcdi->iface_lock);
  311. if (rc == 0) {
  312. efx_mcdi_copyout(efx, outbuf,
  313. min(outlen, mcdi->resplen + 3) & ~0x3);
  314. if (outlen_actual != NULL)
  315. *outlen_actual = resplen;
  316. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  317. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  318. else if (rc == -EIO || rc == -EINTR) {
  319. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  320. -rc);
  321. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  322. } else
  323. netif_dbg(efx, hw, efx->net_dev,
  324. "MC command 0x%x inlen %d failed rc=%d\n",
  325. cmd, (int)inlen, -rc);
  326. }
  327. efx_mcdi_release(mcdi);
  328. return rc;
  329. }
  330. void efx_mcdi_mode_poll(struct efx_nic *efx)
  331. {
  332. struct efx_mcdi_iface *mcdi;
  333. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  334. return;
  335. mcdi = efx_mcdi(efx);
  336. if (mcdi->mode == MCDI_MODE_POLL)
  337. return;
  338. /* We can switch from event completion to polled completion, because
  339. * mcdi requests are always completed in shared memory. We do this by
  340. * switching the mode to POLL'd then completing the request.
  341. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  342. *
  343. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  344. * which efx_mcdi_complete() provides for us.
  345. */
  346. mcdi->mode = MCDI_MODE_POLL;
  347. efx_mcdi_complete(mcdi);
  348. }
  349. void efx_mcdi_mode_event(struct efx_nic *efx)
  350. {
  351. struct efx_mcdi_iface *mcdi;
  352. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  353. return;
  354. mcdi = efx_mcdi(efx);
  355. if (mcdi->mode == MCDI_MODE_EVENTS)
  356. return;
  357. /* We can't switch from polled to event completion in the middle of a
  358. * request, because the completion method is specified in the request.
  359. * So acquire the interface to serialise the requestors. We don't need
  360. * to acquire the iface_lock to change the mode here, but we do need a
  361. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  362. * efx_mcdi_acquire() provides.
  363. */
  364. efx_mcdi_acquire(mcdi);
  365. mcdi->mode = MCDI_MODE_EVENTS;
  366. efx_mcdi_release(mcdi);
  367. }
  368. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  369. {
  370. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  371. /* If there is an outstanding MCDI request, it has been terminated
  372. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  373. * in polled mode, then do nothing because the MC reboot handler will
  374. * set the header correctly. However, if the mcdi interface is waiting
  375. * for a CMDDONE event it won't receive it [and since all MCDI events
  376. * are sent to the same queue, we can't be racing with
  377. * efx_mcdi_ev_cpl()]
  378. *
  379. * There's a race here with efx_mcdi_rpc(), because we might receive
  380. * a REBOOT event *before* the request has been copied out. In polled
  381. * mode (during startup) this is irrelevent, because efx_mcdi_complete()
  382. * is ignored. In event mode, this condition is just an edge-case of
  383. * receiving a REBOOT event after posting the MCDI request. Did the mc
  384. * reboot before or after the copyout? The best we can do always is
  385. * just return failure.
  386. */
  387. spin_lock(&mcdi->iface_lock);
  388. if (efx_mcdi_complete(mcdi)) {
  389. if (mcdi->mode == MCDI_MODE_EVENTS) {
  390. mcdi->resprc = rc;
  391. mcdi->resplen = 0;
  392. ++mcdi->credits;
  393. }
  394. } else
  395. /* Nobody was waiting for an MCDI request, so trigger a reset */
  396. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  397. spin_unlock(&mcdi->iface_lock);
  398. }
  399. static unsigned int efx_mcdi_event_link_speed[] = {
  400. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  401. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  402. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  403. };
  404. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  405. {
  406. u32 flags, fcntl, speed, lpa;
  407. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  408. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  409. speed = efx_mcdi_event_link_speed[speed];
  410. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  411. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  412. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  413. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  414. * which is only run after flushing the event queues. Therefore, it
  415. * is safe to modify the link state outside of the mac_lock here.
  416. */
  417. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  418. efx_mcdi_phy_check_fcntl(efx, lpa);
  419. efx_link_status_changed(efx);
  420. }
  421. static const char *sensor_names[] = {
  422. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  423. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  424. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  425. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  426. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  427. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  428. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  429. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  430. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  431. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  432. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  433. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  434. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  435. };
  436. static const char *sensor_status_names[] = {
  437. [MC_CMD_SENSOR_STATE_OK] = "OK",
  438. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  439. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  440. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  441. };
  442. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  443. {
  444. unsigned int monitor, state, value;
  445. const char *name, *state_txt;
  446. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  447. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  448. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  449. /* Deal gracefully with the board having more drivers than we
  450. * know about, but do not expect new sensor states. */
  451. name = (monitor >= ARRAY_SIZE(sensor_names))
  452. ? "No sensor name available" :
  453. sensor_names[monitor];
  454. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  455. state_txt = sensor_status_names[state];
  456. netif_err(efx, hw, efx->net_dev,
  457. "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  458. monitor, name, state_txt, value);
  459. }
  460. /* Called from falcon_process_eventq for MCDI events */
  461. void efx_mcdi_process_event(struct efx_channel *channel,
  462. efx_qword_t *event)
  463. {
  464. struct efx_nic *efx = channel->efx;
  465. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  466. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  467. switch (code) {
  468. case MCDI_EVENT_CODE_BADSSERT:
  469. netif_err(efx, hw, efx->net_dev,
  470. "MC watchdog or assertion failure at 0x%x\n", data);
  471. efx_mcdi_ev_death(efx, EINTR);
  472. break;
  473. case MCDI_EVENT_CODE_PMNOTICE:
  474. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  475. break;
  476. case MCDI_EVENT_CODE_CMDDONE:
  477. efx_mcdi_ev_cpl(efx,
  478. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  479. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  480. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  481. break;
  482. case MCDI_EVENT_CODE_LINKCHANGE:
  483. efx_mcdi_process_link_change(efx, event);
  484. break;
  485. case MCDI_EVENT_CODE_SENSOREVT:
  486. efx_mcdi_sensor_event(efx, event);
  487. break;
  488. case MCDI_EVENT_CODE_SCHEDERR:
  489. netif_info(efx, hw, efx->net_dev,
  490. "MC Scheduler error address=0x%x\n", data);
  491. break;
  492. case MCDI_EVENT_CODE_REBOOT:
  493. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  494. efx_mcdi_ev_death(efx, EIO);
  495. break;
  496. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  497. /* MAC stats are gather lazily. We can ignore this. */
  498. break;
  499. default:
  500. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  501. code);
  502. }
  503. }
  504. /**************************************************************************
  505. *
  506. * Specific request functions
  507. *
  508. **************************************************************************
  509. */
  510. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  511. {
  512. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  513. size_t outlength;
  514. const __le16 *ver_words;
  515. int rc;
  516. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  517. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  518. outbuf, sizeof(outbuf), &outlength);
  519. if (rc)
  520. goto fail;
  521. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  522. rc = -EIO;
  523. goto fail;
  524. }
  525. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  526. snprintf(buf, len, "%u.%u.%u.%u",
  527. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  528. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  529. return;
  530. fail:
  531. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  532. buf[0] = 0;
  533. }
  534. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  535. bool *was_attached)
  536. {
  537. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  538. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  539. size_t outlen;
  540. int rc;
  541. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  542. driver_operating ? 1 : 0);
  543. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  544. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  545. outbuf, sizeof(outbuf), &outlen);
  546. if (rc)
  547. goto fail;
  548. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  549. rc = -EIO;
  550. goto fail;
  551. }
  552. if (was_attached != NULL)
  553. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  554. return 0;
  555. fail:
  556. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  557. return rc;
  558. }
  559. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  560. u16 *fw_subtype_list)
  561. {
  562. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  563. size_t outlen;
  564. int port_num = efx_port_num(efx);
  565. int offset;
  566. int rc;
  567. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  568. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  569. outbuf, sizeof(outbuf), &outlen);
  570. if (rc)
  571. goto fail;
  572. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  573. rc = -EIO;
  574. goto fail;
  575. }
  576. offset = (port_num)
  577. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  578. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  579. if (mac_address)
  580. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  581. if (fw_subtype_list)
  582. memcpy(fw_subtype_list,
  583. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  584. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  585. return 0;
  586. fail:
  587. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  588. __func__, rc, (int)outlen);
  589. return rc;
  590. }
  591. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  592. {
  593. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  594. u32 dest = 0;
  595. int rc;
  596. if (uart)
  597. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  598. if (evq)
  599. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  600. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  601. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  602. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  603. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  604. NULL, 0, NULL);
  605. if (rc)
  606. goto fail;
  607. return 0;
  608. fail:
  609. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  610. return rc;
  611. }
  612. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  613. {
  614. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  615. size_t outlen;
  616. int rc;
  617. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  618. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  619. outbuf, sizeof(outbuf), &outlen);
  620. if (rc)
  621. goto fail;
  622. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  623. rc = -EIO;
  624. goto fail;
  625. }
  626. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  627. return 0;
  628. fail:
  629. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  630. __func__, rc);
  631. return rc;
  632. }
  633. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  634. size_t *size_out, size_t *erase_size_out,
  635. bool *protected_out)
  636. {
  637. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  638. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  639. size_t outlen;
  640. int rc;
  641. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  642. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  643. outbuf, sizeof(outbuf), &outlen);
  644. if (rc)
  645. goto fail;
  646. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  647. rc = -EIO;
  648. goto fail;
  649. }
  650. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  651. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  652. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  653. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  654. return 0;
  655. fail:
  656. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  657. return rc;
  658. }
  659. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  660. {
  661. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  662. int rc;
  663. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  664. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  665. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  666. NULL, 0, NULL);
  667. if (rc)
  668. goto fail;
  669. return 0;
  670. fail:
  671. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  672. return rc;
  673. }
  674. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  675. loff_t offset, u8 *buffer, size_t length)
  676. {
  677. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  678. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  679. size_t outlen;
  680. int rc;
  681. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  682. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  683. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  684. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  685. outbuf, sizeof(outbuf), &outlen);
  686. if (rc)
  687. goto fail;
  688. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  689. return 0;
  690. fail:
  691. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  692. return rc;
  693. }
  694. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  695. loff_t offset, const u8 *buffer, size_t length)
  696. {
  697. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  698. int rc;
  699. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  700. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  701. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  702. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  703. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  704. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  705. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  706. NULL, 0, NULL);
  707. if (rc)
  708. goto fail;
  709. return 0;
  710. fail:
  711. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  712. return rc;
  713. }
  714. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  715. loff_t offset, size_t length)
  716. {
  717. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  718. int rc;
  719. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  720. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  721. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  722. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  723. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  724. NULL, 0, NULL);
  725. if (rc)
  726. goto fail;
  727. return 0;
  728. fail:
  729. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  730. return rc;
  731. }
  732. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  733. {
  734. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  735. int rc;
  736. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  737. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  738. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  739. NULL, 0, NULL);
  740. if (rc)
  741. goto fail;
  742. return 0;
  743. fail:
  744. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  745. return rc;
  746. }
  747. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  748. {
  749. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  750. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  751. int rc;
  752. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  753. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  754. outbuf, sizeof(outbuf), NULL);
  755. if (rc)
  756. return rc;
  757. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  758. case MC_CMD_NVRAM_TEST_PASS:
  759. case MC_CMD_NVRAM_TEST_NOTSUPP:
  760. return 0;
  761. default:
  762. return -EIO;
  763. }
  764. }
  765. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  766. {
  767. u32 nvram_types;
  768. unsigned int type;
  769. int rc;
  770. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  771. if (rc)
  772. goto fail1;
  773. type = 0;
  774. while (nvram_types != 0) {
  775. if (nvram_types & 1) {
  776. rc = efx_mcdi_nvram_test(efx, type);
  777. if (rc)
  778. goto fail2;
  779. }
  780. type++;
  781. nvram_types >>= 1;
  782. }
  783. return 0;
  784. fail2:
  785. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  786. __func__, type);
  787. fail1:
  788. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  789. return rc;
  790. }
  791. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  792. {
  793. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  794. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  795. unsigned int flags, index, ofst;
  796. const char *reason;
  797. size_t outlen;
  798. int retry;
  799. int rc;
  800. /* Attempt to read any stored assertion state before we reboot
  801. * the mcfw out of the assertion handler. Retry twice, once
  802. * because a boot-time assertion might cause this command to fail
  803. * with EINTR. And once again because GET_ASSERTS can race with
  804. * MC_CMD_REBOOT running on the other port. */
  805. retry = 2;
  806. do {
  807. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  808. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  809. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  810. outbuf, sizeof(outbuf), &outlen);
  811. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  812. if (rc)
  813. return rc;
  814. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  815. return -EIO;
  816. /* Print out any recorded assertion state */
  817. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  818. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  819. return 0;
  820. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  821. ? "system-level assertion"
  822. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  823. ? "thread-level assertion"
  824. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  825. ? "watchdog reset"
  826. : "unknown assertion";
  827. netif_err(efx, hw, efx->net_dev,
  828. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  829. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  830. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  831. /* Print out the registers */
  832. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  833. for (index = 1; index < 32; index++) {
  834. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  835. MCDI_DWORD2(outbuf, ofst));
  836. ofst += sizeof(efx_dword_t);
  837. }
  838. return 0;
  839. }
  840. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  841. {
  842. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  843. /* Atomically reboot the mcfw out of the assertion handler */
  844. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  845. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  846. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  847. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  848. NULL, 0, NULL);
  849. }
  850. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  851. {
  852. int rc;
  853. rc = efx_mcdi_read_assertion(efx);
  854. if (rc)
  855. return rc;
  856. efx_mcdi_exit_assertion(efx);
  857. return 0;
  858. }
  859. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  860. {
  861. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  862. int rc;
  863. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  864. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  865. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  866. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  867. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  868. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  869. NULL, 0, NULL);
  870. if (rc)
  871. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  872. __func__, rc);
  873. }
  874. int efx_mcdi_reset_port(struct efx_nic *efx)
  875. {
  876. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  877. if (rc)
  878. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  879. __func__, rc);
  880. return rc;
  881. }
  882. int efx_mcdi_reset_mc(struct efx_nic *efx)
  883. {
  884. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  885. int rc;
  886. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  887. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  888. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  889. NULL, 0, NULL);
  890. /* White is black, and up is down */
  891. if (rc == -EIO)
  892. return 0;
  893. if (rc == 0)
  894. rc = -EIO;
  895. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  896. return rc;
  897. }
  898. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  899. const u8 *mac, int *id_out)
  900. {
  901. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  902. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  903. size_t outlen;
  904. int rc;
  905. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  906. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  907. MC_CMD_FILTER_MODE_SIMPLE);
  908. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  909. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  910. outbuf, sizeof(outbuf), &outlen);
  911. if (rc)
  912. goto fail;
  913. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  914. rc = -EIO;
  915. goto fail;
  916. }
  917. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  918. return 0;
  919. fail:
  920. *id_out = -1;
  921. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  922. return rc;
  923. }
  924. int
  925. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  926. {
  927. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  928. }
  929. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  930. {
  931. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  932. size_t outlen;
  933. int rc;
  934. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  935. outbuf, sizeof(outbuf), &outlen);
  936. if (rc)
  937. goto fail;
  938. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  939. rc = -EIO;
  940. goto fail;
  941. }
  942. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  943. return 0;
  944. fail:
  945. *id_out = -1;
  946. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  947. return rc;
  948. }
  949. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  950. {
  951. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  952. int rc;
  953. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  954. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  955. NULL, 0, NULL);
  956. if (rc)
  957. goto fail;
  958. return 0;
  959. fail:
  960. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  961. return rc;
  962. }
  963. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  964. {
  965. int rc;
  966. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  967. if (rc)
  968. goto fail;
  969. return 0;
  970. fail:
  971. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  972. return rc;
  973. }