icplus.c 4.2 KB

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  1. /*
  2. * Driver for ICPlus PHYs
  3. *
  4. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/string.h>
  14. #include <linux/errno.h>
  15. #include <linux/unistd.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <linux/mii.h>
  26. #include <linux/ethtool.h>
  27. #include <linux/phy.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/uaccess.h>
  31. MODULE_DESCRIPTION("ICPlus IP175C/IC1001 PHY drivers");
  32. MODULE_AUTHOR("Michael Barkowski");
  33. MODULE_LICENSE("GPL");
  34. static int ip175c_config_init(struct phy_device *phydev)
  35. {
  36. int err, i;
  37. static int full_reset_performed = 0;
  38. if (full_reset_performed == 0) {
  39. /* master reset */
  40. err = phydev->bus->write(phydev->bus, 30, 0, 0x175c);
  41. if (err < 0)
  42. return err;
  43. /* ensure no bus delays overlap reset period */
  44. err = phydev->bus->read(phydev->bus, 30, 0);
  45. /* data sheet specifies reset period is 2 msec */
  46. mdelay(2);
  47. /* enable IP175C mode */
  48. err = phydev->bus->write(phydev->bus, 29, 31, 0x175c);
  49. if (err < 0)
  50. return err;
  51. /* Set MII0 speed and duplex (in PHY mode) */
  52. err = phydev->bus->write(phydev->bus, 29, 22, 0x420);
  53. if (err < 0)
  54. return err;
  55. /* reset switch ports */
  56. for (i = 0; i < 5; i++) {
  57. err = phydev->bus->write(phydev->bus, i,
  58. MII_BMCR, BMCR_RESET);
  59. if (err < 0)
  60. return err;
  61. }
  62. for (i = 0; i < 5; i++)
  63. err = phydev->bus->read(phydev->bus, i, MII_BMCR);
  64. mdelay(2);
  65. full_reset_performed = 1;
  66. }
  67. if (phydev->addr != 4) {
  68. phydev->state = PHY_RUNNING;
  69. phydev->speed = SPEED_100;
  70. phydev->duplex = DUPLEX_FULL;
  71. phydev->link = 1;
  72. netif_carrier_on(phydev->attached_dev);
  73. }
  74. return 0;
  75. }
  76. static int ip1001_config_init(struct phy_device *phydev)
  77. {
  78. int err, value;
  79. /* Software Reset PHY */
  80. value = phy_read(phydev, MII_BMCR);
  81. value |= BMCR_RESET;
  82. err = phy_write(phydev, MII_BMCR, value);
  83. if (err < 0)
  84. return err;
  85. do {
  86. value = phy_read(phydev, MII_BMCR);
  87. } while (value & BMCR_RESET);
  88. /* Additional delay (2ns) used to adjust RX clock phase
  89. * at GMII/ RGMII interface */
  90. value = phy_read(phydev, 16);
  91. value |= 0x3;
  92. err = phy_write(phydev, 16, value);
  93. if (err < 0)
  94. return err;
  95. return err;
  96. }
  97. static int ip175c_read_status(struct phy_device *phydev)
  98. {
  99. if (phydev->addr == 4) /* WAN port */
  100. genphy_read_status(phydev);
  101. else
  102. /* Don't need to read status for switch ports */
  103. phydev->irq = PHY_IGNORE_INTERRUPT;
  104. return 0;
  105. }
  106. static int ip175c_config_aneg(struct phy_device *phydev)
  107. {
  108. if (phydev->addr == 4) /* WAN port */
  109. genphy_config_aneg(phydev);
  110. return 0;
  111. }
  112. static struct phy_driver ip175c_driver = {
  113. .phy_id = 0x02430d80,
  114. .name = "ICPlus IP175C",
  115. .phy_id_mask = 0x0ffffff0,
  116. .features = PHY_BASIC_FEATURES,
  117. .config_init = &ip175c_config_init,
  118. .config_aneg = &ip175c_config_aneg,
  119. .read_status = &ip175c_read_status,
  120. .suspend = genphy_suspend,
  121. .resume = genphy_resume,
  122. .driver = { .owner = THIS_MODULE,},
  123. };
  124. static struct phy_driver ip1001_driver = {
  125. .phy_id = 0x02430d90,
  126. .name = "ICPlus IP1001",
  127. .phy_id_mask = 0x0ffffff0,
  128. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
  129. SUPPORTED_Asym_Pause,
  130. .config_init = &ip1001_config_init,
  131. .config_aneg = &genphy_config_aneg,
  132. .read_status = &genphy_read_status,
  133. .suspend = genphy_suspend,
  134. .resume = genphy_resume,
  135. .driver = { .owner = THIS_MODULE,},
  136. };
  137. static int __init icplus_init(void)
  138. {
  139. int ret = 0;
  140. ret = phy_driver_register(&ip1001_driver);
  141. if (ret < 0)
  142. return -ENODEV;
  143. return phy_driver_register(&ip175c_driver);
  144. }
  145. static void __exit icplus_exit(void)
  146. {
  147. phy_driver_unregister(&ip1001_driver);
  148. phy_driver_unregister(&ip175c_driver);
  149. }
  150. module_init(icplus_init);
  151. module_exit(icplus_exit);
  152. static struct mdio_device_id __maybe_unused icplus_tbl[] = {
  153. { 0x02430d80, 0x0ffffff0 },
  154. { 0x02430d90, 0x0ffffff0 },
  155. { }
  156. };
  157. MODULE_DEVICE_TABLE(mdio, icplus_tbl);