cnic.c 139 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  55. static LIST_HEAD(cnic_dev_list);
  56. static LIST_HEAD(cnic_udev_list);
  57. static DEFINE_RWLOCK(cnic_dev_lock);
  58. static DEFINE_MUTEX(cnic_lock);
  59. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  60. /* helper function, assuming cnic_lock is held */
  61. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  62. {
  63. return rcu_dereference_protected(cnic_ulp_tbl[type],
  64. lockdep_is_held(&cnic_lock));
  65. }
  66. static int cnic_service_bnx2(void *, void *);
  67. static int cnic_service_bnx2x(void *, void *);
  68. static int cnic_ctl(void *, struct cnic_ctl_info *);
  69. static struct cnic_ops cnic_bnx2_ops = {
  70. .cnic_owner = THIS_MODULE,
  71. .cnic_handler = cnic_service_bnx2,
  72. .cnic_ctl = cnic_ctl,
  73. };
  74. static struct cnic_ops cnic_bnx2x_ops = {
  75. .cnic_owner = THIS_MODULE,
  76. .cnic_handler = cnic_service_bnx2x,
  77. .cnic_ctl = cnic_ctl,
  78. };
  79. static struct workqueue_struct *cnic_wq;
  80. static void cnic_shutdown_rings(struct cnic_dev *);
  81. static void cnic_init_rings(struct cnic_dev *);
  82. static int cnic_cm_set_pg(struct cnic_sock *);
  83. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  84. {
  85. struct cnic_uio_dev *udev = uinfo->priv;
  86. struct cnic_dev *dev;
  87. if (!capable(CAP_NET_ADMIN))
  88. return -EPERM;
  89. if (udev->uio_dev != -1)
  90. return -EBUSY;
  91. rtnl_lock();
  92. dev = udev->dev;
  93. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  94. rtnl_unlock();
  95. return -ENODEV;
  96. }
  97. udev->uio_dev = iminor(inode);
  98. cnic_shutdown_rings(dev);
  99. cnic_init_rings(dev);
  100. rtnl_unlock();
  101. return 0;
  102. }
  103. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  104. {
  105. struct cnic_uio_dev *udev = uinfo->priv;
  106. udev->uio_dev = -1;
  107. return 0;
  108. }
  109. static inline void cnic_hold(struct cnic_dev *dev)
  110. {
  111. atomic_inc(&dev->ref_count);
  112. }
  113. static inline void cnic_put(struct cnic_dev *dev)
  114. {
  115. atomic_dec(&dev->ref_count);
  116. }
  117. static inline void csk_hold(struct cnic_sock *csk)
  118. {
  119. atomic_inc(&csk->ref_count);
  120. }
  121. static inline void csk_put(struct cnic_sock *csk)
  122. {
  123. atomic_dec(&csk->ref_count);
  124. }
  125. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  126. {
  127. struct cnic_dev *cdev;
  128. read_lock(&cnic_dev_lock);
  129. list_for_each_entry(cdev, &cnic_dev_list, list) {
  130. if (netdev == cdev->netdev) {
  131. cnic_hold(cdev);
  132. read_unlock(&cnic_dev_lock);
  133. return cdev;
  134. }
  135. }
  136. read_unlock(&cnic_dev_lock);
  137. return NULL;
  138. }
  139. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  140. {
  141. atomic_inc(&ulp_ops->ref_count);
  142. }
  143. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  144. {
  145. atomic_dec(&ulp_ops->ref_count);
  146. }
  147. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  148. {
  149. struct cnic_local *cp = dev->cnic_priv;
  150. struct cnic_eth_dev *ethdev = cp->ethdev;
  151. struct drv_ctl_info info;
  152. struct drv_ctl_io *io = &info.data.io;
  153. info.cmd = DRV_CTL_CTX_WR_CMD;
  154. io->cid_addr = cid_addr;
  155. io->offset = off;
  156. io->data = val;
  157. ethdev->drv_ctl(dev->netdev, &info);
  158. }
  159. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  160. {
  161. struct cnic_local *cp = dev->cnic_priv;
  162. struct cnic_eth_dev *ethdev = cp->ethdev;
  163. struct drv_ctl_info info;
  164. struct drv_ctl_io *io = &info.data.io;
  165. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  166. io->offset = off;
  167. io->dma_addr = addr;
  168. ethdev->drv_ctl(dev->netdev, &info);
  169. }
  170. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  171. {
  172. struct cnic_local *cp = dev->cnic_priv;
  173. struct cnic_eth_dev *ethdev = cp->ethdev;
  174. struct drv_ctl_info info;
  175. struct drv_ctl_l2_ring *ring = &info.data.ring;
  176. if (start)
  177. info.cmd = DRV_CTL_START_L2_CMD;
  178. else
  179. info.cmd = DRV_CTL_STOP_L2_CMD;
  180. ring->cid = cid;
  181. ring->client_id = cl_id;
  182. ethdev->drv_ctl(dev->netdev, &info);
  183. }
  184. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  185. {
  186. struct cnic_local *cp = dev->cnic_priv;
  187. struct cnic_eth_dev *ethdev = cp->ethdev;
  188. struct drv_ctl_info info;
  189. struct drv_ctl_io *io = &info.data.io;
  190. info.cmd = DRV_CTL_IO_WR_CMD;
  191. io->offset = off;
  192. io->data = val;
  193. ethdev->drv_ctl(dev->netdev, &info);
  194. }
  195. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  196. {
  197. struct cnic_local *cp = dev->cnic_priv;
  198. struct cnic_eth_dev *ethdev = cp->ethdev;
  199. struct drv_ctl_info info;
  200. struct drv_ctl_io *io = &info.data.io;
  201. info.cmd = DRV_CTL_IO_RD_CMD;
  202. io->offset = off;
  203. ethdev->drv_ctl(dev->netdev, &info);
  204. return io->data;
  205. }
  206. static int cnic_in_use(struct cnic_sock *csk)
  207. {
  208. return test_bit(SK_F_INUSE, &csk->flags);
  209. }
  210. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  211. {
  212. struct cnic_local *cp = dev->cnic_priv;
  213. struct cnic_eth_dev *ethdev = cp->ethdev;
  214. struct drv_ctl_info info;
  215. info.cmd = cmd;
  216. info.data.credit.credit_count = count;
  217. ethdev->drv_ctl(dev->netdev, &info);
  218. }
  219. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  220. {
  221. u32 i;
  222. for (i = 0; i < cp->max_cid_space; i++) {
  223. if (cp->ctx_tbl[i].cid == cid) {
  224. *l5_cid = i;
  225. return 0;
  226. }
  227. }
  228. return -EINVAL;
  229. }
  230. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  231. struct cnic_sock *csk)
  232. {
  233. struct iscsi_path path_req;
  234. char *buf = NULL;
  235. u16 len = 0;
  236. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  237. struct cnic_ulp_ops *ulp_ops;
  238. struct cnic_uio_dev *udev = cp->udev;
  239. int rc = 0, retry = 0;
  240. if (!udev || udev->uio_dev == -1)
  241. return -ENODEV;
  242. if (csk) {
  243. len = sizeof(path_req);
  244. buf = (char *) &path_req;
  245. memset(&path_req, 0, len);
  246. msg_type = ISCSI_KEVENT_PATH_REQ;
  247. path_req.handle = (u64) csk->l5_cid;
  248. if (test_bit(SK_F_IPV6, &csk->flags)) {
  249. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  250. sizeof(struct in6_addr));
  251. path_req.ip_addr_len = 16;
  252. } else {
  253. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  254. sizeof(struct in_addr));
  255. path_req.ip_addr_len = 4;
  256. }
  257. path_req.vlan_id = csk->vlan_id;
  258. path_req.pmtu = csk->mtu;
  259. }
  260. while (retry < 3) {
  261. rc = 0;
  262. rcu_read_lock();
  263. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  264. if (ulp_ops)
  265. rc = ulp_ops->iscsi_nl_send_msg(
  266. cp->ulp_handle[CNIC_ULP_ISCSI],
  267. msg_type, buf, len);
  268. rcu_read_unlock();
  269. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  270. break;
  271. msleep(100);
  272. retry++;
  273. }
  274. return 0;
  275. }
  276. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  277. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  278. char *buf, u16 len)
  279. {
  280. int rc = -EINVAL;
  281. switch (msg_type) {
  282. case ISCSI_UEVENT_PATH_UPDATE: {
  283. struct cnic_local *cp;
  284. u32 l5_cid;
  285. struct cnic_sock *csk;
  286. struct iscsi_path *path_resp;
  287. if (len < sizeof(*path_resp))
  288. break;
  289. path_resp = (struct iscsi_path *) buf;
  290. cp = dev->cnic_priv;
  291. l5_cid = (u32) path_resp->handle;
  292. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  293. break;
  294. rcu_read_lock();
  295. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  296. rc = -ENODEV;
  297. rcu_read_unlock();
  298. break;
  299. }
  300. csk = &cp->csk_tbl[l5_cid];
  301. csk_hold(csk);
  302. if (cnic_in_use(csk) &&
  303. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  304. memcpy(csk->ha, path_resp->mac_addr, 6);
  305. if (test_bit(SK_F_IPV6, &csk->flags))
  306. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  307. sizeof(struct in6_addr));
  308. else
  309. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  310. sizeof(struct in_addr));
  311. if (is_valid_ether_addr(csk->ha)) {
  312. cnic_cm_set_pg(csk);
  313. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  314. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  315. cnic_cm_upcall(cp, csk,
  316. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  317. clear_bit(SK_F_CONNECT_START, &csk->flags);
  318. }
  319. }
  320. csk_put(csk);
  321. rcu_read_unlock();
  322. rc = 0;
  323. }
  324. }
  325. return rc;
  326. }
  327. static int cnic_offld_prep(struct cnic_sock *csk)
  328. {
  329. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  330. return 0;
  331. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  332. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  333. return 0;
  334. }
  335. return 1;
  336. }
  337. static int cnic_close_prep(struct cnic_sock *csk)
  338. {
  339. clear_bit(SK_F_CONNECT_START, &csk->flags);
  340. smp_mb__after_clear_bit();
  341. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  342. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  343. msleep(1);
  344. return 1;
  345. }
  346. return 0;
  347. }
  348. static int cnic_abort_prep(struct cnic_sock *csk)
  349. {
  350. clear_bit(SK_F_CONNECT_START, &csk->flags);
  351. smp_mb__after_clear_bit();
  352. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  353. msleep(1);
  354. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  355. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  356. return 1;
  357. }
  358. return 0;
  359. }
  360. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  361. {
  362. struct cnic_dev *dev;
  363. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  364. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  365. return -EINVAL;
  366. }
  367. mutex_lock(&cnic_lock);
  368. if (cnic_ulp_tbl_prot(ulp_type)) {
  369. pr_err("%s: Type %d has already been registered\n",
  370. __func__, ulp_type);
  371. mutex_unlock(&cnic_lock);
  372. return -EBUSY;
  373. }
  374. read_lock(&cnic_dev_lock);
  375. list_for_each_entry(dev, &cnic_dev_list, list) {
  376. struct cnic_local *cp = dev->cnic_priv;
  377. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  378. }
  379. read_unlock(&cnic_dev_lock);
  380. atomic_set(&ulp_ops->ref_count, 0);
  381. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  382. mutex_unlock(&cnic_lock);
  383. /* Prevent race conditions with netdev_event */
  384. rtnl_lock();
  385. list_for_each_entry(dev, &cnic_dev_list, list) {
  386. struct cnic_local *cp = dev->cnic_priv;
  387. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  388. ulp_ops->cnic_init(dev);
  389. }
  390. rtnl_unlock();
  391. return 0;
  392. }
  393. int cnic_unregister_driver(int ulp_type)
  394. {
  395. struct cnic_dev *dev;
  396. struct cnic_ulp_ops *ulp_ops;
  397. int i = 0;
  398. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  399. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  400. return -EINVAL;
  401. }
  402. mutex_lock(&cnic_lock);
  403. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  404. if (!ulp_ops) {
  405. pr_err("%s: Type %d has not been registered\n",
  406. __func__, ulp_type);
  407. goto out_unlock;
  408. }
  409. read_lock(&cnic_dev_lock);
  410. list_for_each_entry(dev, &cnic_dev_list, list) {
  411. struct cnic_local *cp = dev->cnic_priv;
  412. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  413. pr_err("%s: Type %d still has devices registered\n",
  414. __func__, ulp_type);
  415. read_unlock(&cnic_dev_lock);
  416. goto out_unlock;
  417. }
  418. }
  419. read_unlock(&cnic_dev_lock);
  420. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  421. mutex_unlock(&cnic_lock);
  422. synchronize_rcu();
  423. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  424. msleep(100);
  425. i++;
  426. }
  427. if (atomic_read(&ulp_ops->ref_count) != 0)
  428. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  429. return 0;
  430. out_unlock:
  431. mutex_unlock(&cnic_lock);
  432. return -EINVAL;
  433. }
  434. static int cnic_start_hw(struct cnic_dev *);
  435. static void cnic_stop_hw(struct cnic_dev *);
  436. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  437. void *ulp_ctx)
  438. {
  439. struct cnic_local *cp = dev->cnic_priv;
  440. struct cnic_ulp_ops *ulp_ops;
  441. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  442. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  443. return -EINVAL;
  444. }
  445. mutex_lock(&cnic_lock);
  446. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  447. pr_err("%s: Driver with type %d has not been registered\n",
  448. __func__, ulp_type);
  449. mutex_unlock(&cnic_lock);
  450. return -EAGAIN;
  451. }
  452. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  453. pr_err("%s: Type %d has already been registered to this device\n",
  454. __func__, ulp_type);
  455. mutex_unlock(&cnic_lock);
  456. return -EBUSY;
  457. }
  458. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  459. cp->ulp_handle[ulp_type] = ulp_ctx;
  460. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  461. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  462. cnic_hold(dev);
  463. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  464. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  465. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  466. mutex_unlock(&cnic_lock);
  467. return 0;
  468. }
  469. EXPORT_SYMBOL(cnic_register_driver);
  470. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  471. {
  472. struct cnic_local *cp = dev->cnic_priv;
  473. int i = 0;
  474. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  475. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  476. return -EINVAL;
  477. }
  478. mutex_lock(&cnic_lock);
  479. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  480. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  481. cnic_put(dev);
  482. } else {
  483. pr_err("%s: device not registered to this ulp type %d\n",
  484. __func__, ulp_type);
  485. mutex_unlock(&cnic_lock);
  486. return -EINVAL;
  487. }
  488. mutex_unlock(&cnic_lock);
  489. if (ulp_type == CNIC_ULP_ISCSI)
  490. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  491. synchronize_rcu();
  492. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  493. i < 20) {
  494. msleep(100);
  495. i++;
  496. }
  497. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  498. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  499. return 0;
  500. }
  501. EXPORT_SYMBOL(cnic_unregister_driver);
  502. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  503. {
  504. id_tbl->start = start_id;
  505. id_tbl->max = size;
  506. id_tbl->next = 0;
  507. spin_lock_init(&id_tbl->lock);
  508. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  509. if (!id_tbl->table)
  510. return -ENOMEM;
  511. return 0;
  512. }
  513. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  514. {
  515. kfree(id_tbl->table);
  516. id_tbl->table = NULL;
  517. }
  518. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  519. {
  520. int ret = -1;
  521. id -= id_tbl->start;
  522. if (id >= id_tbl->max)
  523. return ret;
  524. spin_lock(&id_tbl->lock);
  525. if (!test_bit(id, id_tbl->table)) {
  526. set_bit(id, id_tbl->table);
  527. ret = 0;
  528. }
  529. spin_unlock(&id_tbl->lock);
  530. return ret;
  531. }
  532. /* Returns -1 if not successful */
  533. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  534. {
  535. u32 id;
  536. spin_lock(&id_tbl->lock);
  537. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  538. if (id >= id_tbl->max) {
  539. id = -1;
  540. if (id_tbl->next != 0) {
  541. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  542. if (id >= id_tbl->next)
  543. id = -1;
  544. }
  545. }
  546. if (id < id_tbl->max) {
  547. set_bit(id, id_tbl->table);
  548. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  549. id += id_tbl->start;
  550. }
  551. spin_unlock(&id_tbl->lock);
  552. return id;
  553. }
  554. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  555. {
  556. if (id == -1)
  557. return;
  558. id -= id_tbl->start;
  559. if (id >= id_tbl->max)
  560. return;
  561. clear_bit(id, id_tbl->table);
  562. }
  563. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  564. {
  565. int i;
  566. if (!dma->pg_arr)
  567. return;
  568. for (i = 0; i < dma->num_pages; i++) {
  569. if (dma->pg_arr[i]) {
  570. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  571. dma->pg_arr[i], dma->pg_map_arr[i]);
  572. dma->pg_arr[i] = NULL;
  573. }
  574. }
  575. if (dma->pgtbl) {
  576. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  577. dma->pgtbl, dma->pgtbl_map);
  578. dma->pgtbl = NULL;
  579. }
  580. kfree(dma->pg_arr);
  581. dma->pg_arr = NULL;
  582. dma->num_pages = 0;
  583. }
  584. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  585. {
  586. int i;
  587. __le32 *page_table = (__le32 *) dma->pgtbl;
  588. for (i = 0; i < dma->num_pages; i++) {
  589. /* Each entry needs to be in big endian format. */
  590. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  591. page_table++;
  592. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  593. page_table++;
  594. }
  595. }
  596. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  597. {
  598. int i;
  599. __le32 *page_table = (__le32 *) dma->pgtbl;
  600. for (i = 0; i < dma->num_pages; i++) {
  601. /* Each entry needs to be in little endian format. */
  602. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  603. page_table++;
  604. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  605. page_table++;
  606. }
  607. }
  608. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  609. int pages, int use_pg_tbl)
  610. {
  611. int i, size;
  612. struct cnic_local *cp = dev->cnic_priv;
  613. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  614. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  615. if (dma->pg_arr == NULL)
  616. return -ENOMEM;
  617. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  618. dma->num_pages = pages;
  619. for (i = 0; i < pages; i++) {
  620. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  621. BCM_PAGE_SIZE,
  622. &dma->pg_map_arr[i],
  623. GFP_ATOMIC);
  624. if (dma->pg_arr[i] == NULL)
  625. goto error;
  626. }
  627. if (!use_pg_tbl)
  628. return 0;
  629. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  630. ~(BCM_PAGE_SIZE - 1);
  631. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  632. &dma->pgtbl_map, GFP_ATOMIC);
  633. if (dma->pgtbl == NULL)
  634. goto error;
  635. cp->setup_pgtbl(dev, dma);
  636. return 0;
  637. error:
  638. cnic_free_dma(dev, dma);
  639. return -ENOMEM;
  640. }
  641. static void cnic_free_context(struct cnic_dev *dev)
  642. {
  643. struct cnic_local *cp = dev->cnic_priv;
  644. int i;
  645. for (i = 0; i < cp->ctx_blks; i++) {
  646. if (cp->ctx_arr[i].ctx) {
  647. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  648. cp->ctx_arr[i].ctx,
  649. cp->ctx_arr[i].mapping);
  650. cp->ctx_arr[i].ctx = NULL;
  651. }
  652. }
  653. }
  654. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  655. {
  656. uio_unregister_device(&udev->cnic_uinfo);
  657. if (udev->l2_buf) {
  658. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  659. udev->l2_buf, udev->l2_buf_map);
  660. udev->l2_buf = NULL;
  661. }
  662. if (udev->l2_ring) {
  663. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  664. udev->l2_ring, udev->l2_ring_map);
  665. udev->l2_ring = NULL;
  666. }
  667. pci_dev_put(udev->pdev);
  668. kfree(udev);
  669. }
  670. static void cnic_free_uio(struct cnic_uio_dev *udev)
  671. {
  672. if (!udev)
  673. return;
  674. write_lock(&cnic_dev_lock);
  675. list_del_init(&udev->list);
  676. write_unlock(&cnic_dev_lock);
  677. __cnic_free_uio(udev);
  678. }
  679. static void cnic_free_resc(struct cnic_dev *dev)
  680. {
  681. struct cnic_local *cp = dev->cnic_priv;
  682. struct cnic_uio_dev *udev = cp->udev;
  683. if (udev) {
  684. udev->dev = NULL;
  685. cp->udev = NULL;
  686. }
  687. cnic_free_context(dev);
  688. kfree(cp->ctx_arr);
  689. cp->ctx_arr = NULL;
  690. cp->ctx_blks = 0;
  691. cnic_free_dma(dev, &cp->gbl_buf_info);
  692. cnic_free_dma(dev, &cp->conn_buf_info);
  693. cnic_free_dma(dev, &cp->kwq_info);
  694. cnic_free_dma(dev, &cp->kwq_16_data_info);
  695. cnic_free_dma(dev, &cp->kcq2.dma);
  696. cnic_free_dma(dev, &cp->kcq1.dma);
  697. kfree(cp->iscsi_tbl);
  698. cp->iscsi_tbl = NULL;
  699. kfree(cp->ctx_tbl);
  700. cp->ctx_tbl = NULL;
  701. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  702. cnic_free_id_tbl(&cp->cid_tbl);
  703. }
  704. static int cnic_alloc_context(struct cnic_dev *dev)
  705. {
  706. struct cnic_local *cp = dev->cnic_priv;
  707. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  708. int i, k, arr_size;
  709. cp->ctx_blk_size = BCM_PAGE_SIZE;
  710. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  711. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  712. sizeof(struct cnic_ctx);
  713. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  714. if (cp->ctx_arr == NULL)
  715. return -ENOMEM;
  716. k = 0;
  717. for (i = 0; i < 2; i++) {
  718. u32 j, reg, off, lo, hi;
  719. if (i == 0)
  720. off = BNX2_PG_CTX_MAP;
  721. else
  722. off = BNX2_ISCSI_CTX_MAP;
  723. reg = cnic_reg_rd_ind(dev, off);
  724. lo = reg >> 16;
  725. hi = reg & 0xffff;
  726. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  727. cp->ctx_arr[k].cid = j;
  728. }
  729. cp->ctx_blks = k;
  730. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  731. cp->ctx_blks = 0;
  732. return -ENOMEM;
  733. }
  734. for (i = 0; i < cp->ctx_blks; i++) {
  735. cp->ctx_arr[i].ctx =
  736. dma_alloc_coherent(&dev->pcidev->dev,
  737. BCM_PAGE_SIZE,
  738. &cp->ctx_arr[i].mapping,
  739. GFP_KERNEL);
  740. if (cp->ctx_arr[i].ctx == NULL)
  741. return -ENOMEM;
  742. }
  743. }
  744. return 0;
  745. }
  746. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  747. {
  748. int err, i, is_bnx2 = 0;
  749. struct kcqe **kcq;
  750. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  751. is_bnx2 = 1;
  752. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  753. if (err)
  754. return err;
  755. kcq = (struct kcqe **) info->dma.pg_arr;
  756. info->kcq = kcq;
  757. if (is_bnx2)
  758. return 0;
  759. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  760. struct bnx2x_bd_chain_next *next =
  761. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  762. int j = i + 1;
  763. if (j >= KCQ_PAGE_CNT)
  764. j = 0;
  765. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  766. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  767. }
  768. return 0;
  769. }
  770. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  771. {
  772. struct cnic_local *cp = dev->cnic_priv;
  773. struct cnic_uio_dev *udev;
  774. read_lock(&cnic_dev_lock);
  775. list_for_each_entry(udev, &cnic_udev_list, list) {
  776. if (udev->pdev == dev->pcidev) {
  777. udev->dev = dev;
  778. cp->udev = udev;
  779. read_unlock(&cnic_dev_lock);
  780. return 0;
  781. }
  782. }
  783. read_unlock(&cnic_dev_lock);
  784. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  785. if (!udev)
  786. return -ENOMEM;
  787. udev->uio_dev = -1;
  788. udev->dev = dev;
  789. udev->pdev = dev->pcidev;
  790. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  791. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  792. &udev->l2_ring_map,
  793. GFP_KERNEL | __GFP_COMP);
  794. if (!udev->l2_ring)
  795. goto err_udev;
  796. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  797. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  798. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  799. &udev->l2_buf_map,
  800. GFP_KERNEL | __GFP_COMP);
  801. if (!udev->l2_buf)
  802. goto err_dma;
  803. write_lock(&cnic_dev_lock);
  804. list_add(&udev->list, &cnic_udev_list);
  805. write_unlock(&cnic_dev_lock);
  806. pci_dev_get(udev->pdev);
  807. cp->udev = udev;
  808. return 0;
  809. err_dma:
  810. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  811. udev->l2_ring, udev->l2_ring_map);
  812. err_udev:
  813. kfree(udev);
  814. return -ENOMEM;
  815. }
  816. static int cnic_init_uio(struct cnic_dev *dev)
  817. {
  818. struct cnic_local *cp = dev->cnic_priv;
  819. struct cnic_uio_dev *udev = cp->udev;
  820. struct uio_info *uinfo;
  821. int ret = 0;
  822. if (!udev)
  823. return -ENOMEM;
  824. uinfo = &udev->cnic_uinfo;
  825. uinfo->mem[0].addr = dev->netdev->base_addr;
  826. uinfo->mem[0].internal_addr = dev->regview;
  827. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  828. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  829. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  830. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  831. PAGE_MASK;
  832. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  833. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  834. else
  835. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  836. uinfo->name = "bnx2_cnic";
  837. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  838. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  839. PAGE_MASK;
  840. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  841. uinfo->name = "bnx2x_cnic";
  842. }
  843. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  844. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  845. uinfo->mem[2].size = udev->l2_ring_size;
  846. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  847. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  848. uinfo->mem[3].size = udev->l2_buf_size;
  849. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  850. uinfo->version = CNIC_MODULE_VERSION;
  851. uinfo->irq = UIO_IRQ_CUSTOM;
  852. uinfo->open = cnic_uio_open;
  853. uinfo->release = cnic_uio_close;
  854. if (udev->uio_dev == -1) {
  855. if (!uinfo->priv) {
  856. uinfo->priv = udev;
  857. ret = uio_register_device(&udev->pdev->dev, uinfo);
  858. }
  859. } else {
  860. cnic_init_rings(dev);
  861. }
  862. return ret;
  863. }
  864. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  865. {
  866. struct cnic_local *cp = dev->cnic_priv;
  867. int ret;
  868. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  869. if (ret)
  870. goto error;
  871. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  872. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  873. if (ret)
  874. goto error;
  875. ret = cnic_alloc_context(dev);
  876. if (ret)
  877. goto error;
  878. ret = cnic_alloc_uio_rings(dev, 2);
  879. if (ret)
  880. goto error;
  881. ret = cnic_init_uio(dev);
  882. if (ret)
  883. goto error;
  884. return 0;
  885. error:
  886. cnic_free_resc(dev);
  887. return ret;
  888. }
  889. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  890. {
  891. struct cnic_local *cp = dev->cnic_priv;
  892. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  893. int total_mem, blks, i;
  894. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  895. blks = total_mem / ctx_blk_size;
  896. if (total_mem % ctx_blk_size)
  897. blks++;
  898. if (blks > cp->ethdev->ctx_tbl_len)
  899. return -ENOMEM;
  900. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  901. if (cp->ctx_arr == NULL)
  902. return -ENOMEM;
  903. cp->ctx_blks = blks;
  904. cp->ctx_blk_size = ctx_blk_size;
  905. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  906. cp->ctx_align = 0;
  907. else
  908. cp->ctx_align = ctx_blk_size;
  909. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  910. for (i = 0; i < blks; i++) {
  911. cp->ctx_arr[i].ctx =
  912. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  913. &cp->ctx_arr[i].mapping,
  914. GFP_KERNEL);
  915. if (cp->ctx_arr[i].ctx == NULL)
  916. return -ENOMEM;
  917. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  918. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  919. cnic_free_context(dev);
  920. cp->ctx_blk_size += cp->ctx_align;
  921. i = -1;
  922. continue;
  923. }
  924. }
  925. }
  926. return 0;
  927. }
  928. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  929. {
  930. struct cnic_local *cp = dev->cnic_priv;
  931. struct cnic_eth_dev *ethdev = cp->ethdev;
  932. u32 start_cid = ethdev->starting_cid;
  933. int i, j, n, ret, pages;
  934. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  935. cp->iro_arr = ethdev->iro_arr;
  936. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  937. cp->iscsi_start_cid = start_cid;
  938. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  939. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  940. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  941. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  942. if (!cp->fcoe_init_cid)
  943. cp->fcoe_init_cid = 0x10;
  944. }
  945. if (start_cid < BNX2X_ISCSI_START_CID) {
  946. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  947. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  948. cp->fcoe_start_cid += delta;
  949. cp->max_cid_space += delta;
  950. }
  951. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  952. GFP_KERNEL);
  953. if (!cp->iscsi_tbl)
  954. goto error;
  955. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  956. cp->max_cid_space, GFP_KERNEL);
  957. if (!cp->ctx_tbl)
  958. goto error;
  959. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  960. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  961. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  962. }
  963. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  964. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  965. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  966. PAGE_SIZE;
  967. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  968. if (ret)
  969. return -ENOMEM;
  970. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  971. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  972. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  973. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  974. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  975. off;
  976. if ((i % n) == (n - 1))
  977. j++;
  978. }
  979. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  980. if (ret)
  981. goto error;
  982. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  983. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  984. if (ret)
  985. goto error;
  986. }
  987. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  988. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  989. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  990. if (ret)
  991. goto error;
  992. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  993. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  994. if (ret)
  995. goto error;
  996. ret = cnic_alloc_bnx2x_context(dev);
  997. if (ret)
  998. goto error;
  999. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1000. cp->l2_rx_ring_size = 15;
  1001. ret = cnic_alloc_uio_rings(dev, 4);
  1002. if (ret)
  1003. goto error;
  1004. ret = cnic_init_uio(dev);
  1005. if (ret)
  1006. goto error;
  1007. return 0;
  1008. error:
  1009. cnic_free_resc(dev);
  1010. return -ENOMEM;
  1011. }
  1012. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1013. {
  1014. return cp->max_kwq_idx -
  1015. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1016. }
  1017. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1018. u32 num_wqes)
  1019. {
  1020. struct cnic_local *cp = dev->cnic_priv;
  1021. struct kwqe *prod_qe;
  1022. u16 prod, sw_prod, i;
  1023. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1024. return -EAGAIN; /* bnx2 is down */
  1025. spin_lock_bh(&cp->cnic_ulp_lock);
  1026. if (num_wqes > cnic_kwq_avail(cp) &&
  1027. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1028. spin_unlock_bh(&cp->cnic_ulp_lock);
  1029. return -EAGAIN;
  1030. }
  1031. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1032. prod = cp->kwq_prod_idx;
  1033. sw_prod = prod & MAX_KWQ_IDX;
  1034. for (i = 0; i < num_wqes; i++) {
  1035. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1036. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1037. prod++;
  1038. sw_prod = prod & MAX_KWQ_IDX;
  1039. }
  1040. cp->kwq_prod_idx = prod;
  1041. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1042. spin_unlock_bh(&cp->cnic_ulp_lock);
  1043. return 0;
  1044. }
  1045. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1046. union l5cm_specific_data *l5_data)
  1047. {
  1048. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1049. dma_addr_t map;
  1050. map = ctx->kwqe_data_mapping;
  1051. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1052. l5_data->phy_address.hi = (u64) map >> 32;
  1053. return ctx->kwqe_data;
  1054. }
  1055. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1056. u32 type, union l5cm_specific_data *l5_data)
  1057. {
  1058. struct cnic_local *cp = dev->cnic_priv;
  1059. struct l5cm_spe kwqe;
  1060. struct kwqe_16 *kwq[1];
  1061. u16 type_16;
  1062. int ret;
  1063. kwqe.hdr.conn_and_cmd_data =
  1064. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1065. BNX2X_HW_CID(cp, cid)));
  1066. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1067. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1068. SPE_HDR_FUNCTION_ID;
  1069. kwqe.hdr.type = cpu_to_le16(type_16);
  1070. kwqe.hdr.reserved1 = 0;
  1071. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1072. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1073. kwq[0] = (struct kwqe_16 *) &kwqe;
  1074. spin_lock_bh(&cp->cnic_ulp_lock);
  1075. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1076. spin_unlock_bh(&cp->cnic_ulp_lock);
  1077. if (ret == 1)
  1078. return 0;
  1079. return -EBUSY;
  1080. }
  1081. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1082. struct kcqe *cqes[], u32 num_cqes)
  1083. {
  1084. struct cnic_local *cp = dev->cnic_priv;
  1085. struct cnic_ulp_ops *ulp_ops;
  1086. rcu_read_lock();
  1087. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1088. if (likely(ulp_ops)) {
  1089. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1090. cqes, num_cqes);
  1091. }
  1092. rcu_read_unlock();
  1093. }
  1094. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1095. {
  1096. struct cnic_local *cp = dev->cnic_priv;
  1097. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1098. int hq_bds, pages;
  1099. u32 pfid = cp->pfid;
  1100. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1101. cp->num_ccells = req1->num_ccells_per_conn;
  1102. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1103. cp->num_iscsi_tasks;
  1104. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1105. BNX2X_ISCSI_R2TQE_SIZE;
  1106. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1107. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1108. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1109. cp->num_cqs = req1->num_cqs;
  1110. if (!dev->max_iscsi_conn)
  1111. return 0;
  1112. /* init Tstorm RAM */
  1113. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1114. req1->rq_num_wqes);
  1115. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1116. PAGE_SIZE);
  1117. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1118. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1119. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1120. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1121. req1->num_tasks_per_conn);
  1122. /* init Ustorm RAM */
  1123. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1124. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1125. req1->rq_buffer_size);
  1126. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1127. PAGE_SIZE);
  1128. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1129. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1130. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1131. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1132. req1->num_tasks_per_conn);
  1133. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1134. req1->rq_num_wqes);
  1135. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1136. req1->cq_num_wqes);
  1137. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1138. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1139. /* init Xstorm RAM */
  1140. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1141. PAGE_SIZE);
  1142. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1143. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1144. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1145. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1146. req1->num_tasks_per_conn);
  1147. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1148. hq_bds);
  1149. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1150. req1->num_tasks_per_conn);
  1151. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1152. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1153. /* init Cstorm RAM */
  1154. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1155. PAGE_SIZE);
  1156. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1157. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1158. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1159. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1160. req1->num_tasks_per_conn);
  1161. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1162. req1->cq_num_wqes);
  1163. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1164. hq_bds);
  1165. return 0;
  1166. }
  1167. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1168. {
  1169. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1170. struct cnic_local *cp = dev->cnic_priv;
  1171. u32 pfid = cp->pfid;
  1172. struct iscsi_kcqe kcqe;
  1173. struct kcqe *cqes[1];
  1174. memset(&kcqe, 0, sizeof(kcqe));
  1175. if (!dev->max_iscsi_conn) {
  1176. kcqe.completion_status =
  1177. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1178. goto done;
  1179. }
  1180. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1181. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1182. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1183. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1184. req2->error_bit_map[1]);
  1185. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1186. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1187. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1188. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1189. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1190. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1191. req2->error_bit_map[1]);
  1192. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1193. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1194. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1195. done:
  1196. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1197. cqes[0] = (struct kcqe *) &kcqe;
  1198. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1199. return 0;
  1200. }
  1201. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1202. {
  1203. struct cnic_local *cp = dev->cnic_priv;
  1204. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1205. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1206. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1207. cnic_free_dma(dev, &iscsi->hq_info);
  1208. cnic_free_dma(dev, &iscsi->r2tq_info);
  1209. cnic_free_dma(dev, &iscsi->task_array_info);
  1210. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1211. } else {
  1212. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1213. }
  1214. ctx->cid = 0;
  1215. }
  1216. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1217. {
  1218. u32 cid;
  1219. int ret, pages;
  1220. struct cnic_local *cp = dev->cnic_priv;
  1221. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1222. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1223. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1224. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1225. if (cid == -1) {
  1226. ret = -ENOMEM;
  1227. goto error;
  1228. }
  1229. ctx->cid = cid;
  1230. return 0;
  1231. }
  1232. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1233. if (cid == -1) {
  1234. ret = -ENOMEM;
  1235. goto error;
  1236. }
  1237. ctx->cid = cid;
  1238. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1239. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1240. if (ret)
  1241. goto error;
  1242. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1243. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1244. if (ret)
  1245. goto error;
  1246. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1247. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1248. if (ret)
  1249. goto error;
  1250. return 0;
  1251. error:
  1252. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1253. return ret;
  1254. }
  1255. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1256. struct regpair *ctx_addr)
  1257. {
  1258. struct cnic_local *cp = dev->cnic_priv;
  1259. struct cnic_eth_dev *ethdev = cp->ethdev;
  1260. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1261. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1262. unsigned long align_off = 0;
  1263. dma_addr_t ctx_map;
  1264. void *ctx;
  1265. if (cp->ctx_align) {
  1266. unsigned long mask = cp->ctx_align - 1;
  1267. if (cp->ctx_arr[blk].mapping & mask)
  1268. align_off = cp->ctx_align -
  1269. (cp->ctx_arr[blk].mapping & mask);
  1270. }
  1271. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1272. (off * BNX2X_CONTEXT_MEM_SIZE);
  1273. ctx = cp->ctx_arr[blk].ctx + align_off +
  1274. (off * BNX2X_CONTEXT_MEM_SIZE);
  1275. if (init)
  1276. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1277. ctx_addr->lo = ctx_map & 0xffffffff;
  1278. ctx_addr->hi = (u64) ctx_map >> 32;
  1279. return ctx;
  1280. }
  1281. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1282. u32 num)
  1283. {
  1284. struct cnic_local *cp = dev->cnic_priv;
  1285. struct iscsi_kwqe_conn_offload1 *req1 =
  1286. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1287. struct iscsi_kwqe_conn_offload2 *req2 =
  1288. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1289. struct iscsi_kwqe_conn_offload3 *req3;
  1290. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1291. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1292. u32 cid = ctx->cid;
  1293. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1294. struct iscsi_context *ictx;
  1295. struct regpair context_addr;
  1296. int i, j, n = 2, n_max;
  1297. ctx->ctx_flags = 0;
  1298. if (!req2->num_additional_wqes)
  1299. return -EINVAL;
  1300. n_max = req2->num_additional_wqes + 2;
  1301. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1302. if (ictx == NULL)
  1303. return -ENOMEM;
  1304. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1305. ictx->xstorm_ag_context.hq_prod = 1;
  1306. ictx->xstorm_st_context.iscsi.first_burst_length =
  1307. ISCSI_DEF_FIRST_BURST_LEN;
  1308. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1309. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1310. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1311. req1->sq_page_table_addr_lo;
  1312. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1313. req1->sq_page_table_addr_hi;
  1314. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1315. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1316. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1317. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1318. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1319. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1320. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1321. iscsi->hq_info.pgtbl[0];
  1322. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1323. iscsi->hq_info.pgtbl[1];
  1324. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1325. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1326. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1327. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1328. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1329. iscsi->r2tq_info.pgtbl[0];
  1330. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1331. iscsi->r2tq_info.pgtbl[1];
  1332. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1333. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1334. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1335. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1336. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1337. BNX2X_ISCSI_PBL_NOT_CACHED;
  1338. ictx->xstorm_st_context.iscsi.flags.flags |=
  1339. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1340. ictx->xstorm_st_context.iscsi.flags.flags |=
  1341. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1342. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1343. /* TSTORM requires the base address of RQ DB & not PTE */
  1344. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1345. req2->rq_page_table_addr_lo & PAGE_MASK;
  1346. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1347. req2->rq_page_table_addr_hi;
  1348. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1349. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1350. ictx->tstorm_st_context.tcp.flags2 |=
  1351. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1352. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1353. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1354. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1355. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1356. req2->rq_page_table_addr_lo;
  1357. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1358. req2->rq_page_table_addr_hi;
  1359. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1360. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1361. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1362. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1363. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1364. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1365. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1366. iscsi->r2tq_info.pgtbl[0];
  1367. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1368. iscsi->r2tq_info.pgtbl[1];
  1369. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1370. req1->cq_page_table_addr_lo;
  1371. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1372. req1->cq_page_table_addr_hi;
  1373. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1374. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1375. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1376. ictx->ustorm_st_context.task_pbe_cache_index =
  1377. BNX2X_ISCSI_PBL_NOT_CACHED;
  1378. ictx->ustorm_st_context.task_pdu_cache_index =
  1379. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1380. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1381. if (j == 3) {
  1382. if (n >= n_max)
  1383. break;
  1384. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1385. j = 0;
  1386. }
  1387. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1388. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1389. req3->qp_first_pte[j].hi;
  1390. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1391. req3->qp_first_pte[j].lo;
  1392. }
  1393. ictx->ustorm_st_context.task_pbl_base.lo =
  1394. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1395. ictx->ustorm_st_context.task_pbl_base.hi =
  1396. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1397. ictx->ustorm_st_context.tce_phy_addr.lo =
  1398. iscsi->task_array_info.pgtbl[0];
  1399. ictx->ustorm_st_context.tce_phy_addr.hi =
  1400. iscsi->task_array_info.pgtbl[1];
  1401. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1402. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1403. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1404. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1405. ISCSI_DEF_MAX_BURST_LEN;
  1406. ictx->ustorm_st_context.negotiated_rx |=
  1407. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1408. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1409. ictx->cstorm_st_context.hq_pbl_base.lo =
  1410. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1411. ictx->cstorm_st_context.hq_pbl_base.hi =
  1412. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1413. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1414. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1415. ictx->cstorm_st_context.task_pbl_base.lo =
  1416. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1417. ictx->cstorm_st_context.task_pbl_base.hi =
  1418. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1419. /* CSTORM and USTORM initialization is different, CSTORM requires
  1420. * CQ DB base & not PTE addr */
  1421. ictx->cstorm_st_context.cq_db_base.lo =
  1422. req1->cq_page_table_addr_lo & PAGE_MASK;
  1423. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1424. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1425. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1426. for (i = 0; i < cp->num_cqs; i++) {
  1427. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1428. ISCSI_INITIAL_SN;
  1429. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1430. ISCSI_INITIAL_SN;
  1431. }
  1432. ictx->xstorm_ag_context.cdu_reserved =
  1433. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1434. ISCSI_CONNECTION_TYPE);
  1435. ictx->ustorm_ag_context.cdu_usage =
  1436. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1437. ISCSI_CONNECTION_TYPE);
  1438. return 0;
  1439. }
  1440. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1441. u32 num, int *work)
  1442. {
  1443. struct iscsi_kwqe_conn_offload1 *req1;
  1444. struct iscsi_kwqe_conn_offload2 *req2;
  1445. struct cnic_local *cp = dev->cnic_priv;
  1446. struct cnic_context *ctx;
  1447. struct iscsi_kcqe kcqe;
  1448. struct kcqe *cqes[1];
  1449. u32 l5_cid;
  1450. int ret = 0;
  1451. if (num < 2) {
  1452. *work = num;
  1453. return -EINVAL;
  1454. }
  1455. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1456. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1457. if ((num - 2) < req2->num_additional_wqes) {
  1458. *work = num;
  1459. return -EINVAL;
  1460. }
  1461. *work = 2 + req2->num_additional_wqes;
  1462. l5_cid = req1->iscsi_conn_id;
  1463. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1464. return -EINVAL;
  1465. memset(&kcqe, 0, sizeof(kcqe));
  1466. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1467. kcqe.iscsi_conn_id = l5_cid;
  1468. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1469. ctx = &cp->ctx_tbl[l5_cid];
  1470. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1471. kcqe.completion_status =
  1472. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1473. goto done;
  1474. }
  1475. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1476. atomic_dec(&cp->iscsi_conn);
  1477. goto done;
  1478. }
  1479. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1480. if (ret) {
  1481. atomic_dec(&cp->iscsi_conn);
  1482. ret = 0;
  1483. goto done;
  1484. }
  1485. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1486. if (ret < 0) {
  1487. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1488. atomic_dec(&cp->iscsi_conn);
  1489. goto done;
  1490. }
  1491. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1492. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1493. done:
  1494. cqes[0] = (struct kcqe *) &kcqe;
  1495. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1496. return ret;
  1497. }
  1498. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1499. {
  1500. struct cnic_local *cp = dev->cnic_priv;
  1501. struct iscsi_kwqe_conn_update *req =
  1502. (struct iscsi_kwqe_conn_update *) kwqe;
  1503. void *data;
  1504. union l5cm_specific_data l5_data;
  1505. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1506. int ret;
  1507. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1508. return -EINVAL;
  1509. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1510. if (!data)
  1511. return -ENOMEM;
  1512. memcpy(data, kwqe, sizeof(struct kwqe));
  1513. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1514. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1515. return ret;
  1516. }
  1517. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1518. {
  1519. struct cnic_local *cp = dev->cnic_priv;
  1520. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1521. union l5cm_specific_data l5_data;
  1522. int ret;
  1523. u32 hw_cid;
  1524. init_waitqueue_head(&ctx->waitq);
  1525. ctx->wait_cond = 0;
  1526. memset(&l5_data, 0, sizeof(l5_data));
  1527. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1528. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1529. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1530. if (ret == 0)
  1531. wait_event(ctx->waitq, ctx->wait_cond);
  1532. return ret;
  1533. }
  1534. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1535. {
  1536. struct cnic_local *cp = dev->cnic_priv;
  1537. struct iscsi_kwqe_conn_destroy *req =
  1538. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1539. u32 l5_cid = req->reserved0;
  1540. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1541. int ret = 0;
  1542. struct iscsi_kcqe kcqe;
  1543. struct kcqe *cqes[1];
  1544. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1545. goto skip_cfc_delete;
  1546. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1547. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1548. if (delta > (2 * HZ))
  1549. delta = 0;
  1550. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1551. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1552. goto destroy_reply;
  1553. }
  1554. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1555. skip_cfc_delete:
  1556. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1557. atomic_dec(&cp->iscsi_conn);
  1558. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1559. destroy_reply:
  1560. memset(&kcqe, 0, sizeof(kcqe));
  1561. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1562. kcqe.iscsi_conn_id = l5_cid;
  1563. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1564. kcqe.iscsi_conn_context_id = req->context_id;
  1565. cqes[0] = (struct kcqe *) &kcqe;
  1566. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1567. return ret;
  1568. }
  1569. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1570. struct l4_kwq_connect_req1 *kwqe1,
  1571. struct l4_kwq_connect_req3 *kwqe3,
  1572. struct l5cm_active_conn_buffer *conn_buf)
  1573. {
  1574. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1575. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1576. &conn_buf->xstorm_conn_buffer;
  1577. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1578. &conn_buf->tstorm_conn_buffer;
  1579. struct regpair context_addr;
  1580. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1581. struct in6_addr src_ip, dst_ip;
  1582. int i;
  1583. u32 *addrp;
  1584. addrp = (u32 *) &conn_addr->local_ip_addr;
  1585. for (i = 0; i < 4; i++, addrp++)
  1586. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1587. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1588. for (i = 0; i < 4; i++, addrp++)
  1589. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1590. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1591. xstorm_buf->context_addr.hi = context_addr.hi;
  1592. xstorm_buf->context_addr.lo = context_addr.lo;
  1593. xstorm_buf->mss = 0xffff;
  1594. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1595. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1596. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1597. xstorm_buf->pseudo_header_checksum =
  1598. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1599. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1600. tstorm_buf->params |=
  1601. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1602. if (kwqe3->ka_timeout) {
  1603. tstorm_buf->ka_enable = 1;
  1604. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1605. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1606. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1607. }
  1608. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1609. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1610. tstorm_buf->max_rt_time = 0xffffffff;
  1611. }
  1612. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1613. {
  1614. struct cnic_local *cp = dev->cnic_priv;
  1615. u32 pfid = cp->pfid;
  1616. u8 *mac = dev->mac_addr;
  1617. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1618. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1619. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1620. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1621. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1622. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1623. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1624. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1625. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1626. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1627. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1628. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1629. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1630. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1631. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1632. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1633. mac[4]);
  1634. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1635. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1636. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1637. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1638. mac[2]);
  1639. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1640. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1641. mac[1]);
  1642. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1643. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1644. mac[0]);
  1645. }
  1646. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1647. {
  1648. struct cnic_local *cp = dev->cnic_priv;
  1649. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1650. u16 tstorm_flags = 0;
  1651. if (tcp_ts) {
  1652. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1653. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1654. }
  1655. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1656. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1657. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1658. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1659. }
  1660. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1661. u32 num, int *work)
  1662. {
  1663. struct cnic_local *cp = dev->cnic_priv;
  1664. struct l4_kwq_connect_req1 *kwqe1 =
  1665. (struct l4_kwq_connect_req1 *) wqes[0];
  1666. struct l4_kwq_connect_req3 *kwqe3;
  1667. struct l5cm_active_conn_buffer *conn_buf;
  1668. struct l5cm_conn_addr_params *conn_addr;
  1669. union l5cm_specific_data l5_data;
  1670. u32 l5_cid = kwqe1->pg_cid;
  1671. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1672. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1673. int ret;
  1674. if (num < 2) {
  1675. *work = num;
  1676. return -EINVAL;
  1677. }
  1678. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1679. *work = 3;
  1680. else
  1681. *work = 2;
  1682. if (num < *work) {
  1683. *work = num;
  1684. return -EINVAL;
  1685. }
  1686. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1687. netdev_err(dev->netdev, "conn_buf size too big\n");
  1688. return -ENOMEM;
  1689. }
  1690. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1691. if (!conn_buf)
  1692. return -ENOMEM;
  1693. memset(conn_buf, 0, sizeof(*conn_buf));
  1694. conn_addr = &conn_buf->conn_addr_buf;
  1695. conn_addr->remote_addr_0 = csk->ha[0];
  1696. conn_addr->remote_addr_1 = csk->ha[1];
  1697. conn_addr->remote_addr_2 = csk->ha[2];
  1698. conn_addr->remote_addr_3 = csk->ha[3];
  1699. conn_addr->remote_addr_4 = csk->ha[4];
  1700. conn_addr->remote_addr_5 = csk->ha[5];
  1701. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1702. struct l4_kwq_connect_req2 *kwqe2 =
  1703. (struct l4_kwq_connect_req2 *) wqes[1];
  1704. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1705. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1706. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1707. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1708. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1709. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1710. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1711. }
  1712. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1713. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1714. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1715. conn_addr->local_tcp_port = kwqe1->src_port;
  1716. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1717. conn_addr->pmtu = kwqe3->pmtu;
  1718. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1719. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1720. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1721. cnic_bnx2x_set_tcp_timestamp(dev,
  1722. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1723. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1724. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1725. if (!ret)
  1726. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1727. return ret;
  1728. }
  1729. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1730. {
  1731. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1732. union l5cm_specific_data l5_data;
  1733. int ret;
  1734. memset(&l5_data, 0, sizeof(l5_data));
  1735. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1736. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1737. return ret;
  1738. }
  1739. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1740. {
  1741. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1742. union l5cm_specific_data l5_data;
  1743. int ret;
  1744. memset(&l5_data, 0, sizeof(l5_data));
  1745. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1746. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1747. return ret;
  1748. }
  1749. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1750. {
  1751. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1752. struct l4_kcq kcqe;
  1753. struct kcqe *cqes[1];
  1754. memset(&kcqe, 0, sizeof(kcqe));
  1755. kcqe.pg_host_opaque = req->host_opaque;
  1756. kcqe.pg_cid = req->host_opaque;
  1757. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1758. cqes[0] = (struct kcqe *) &kcqe;
  1759. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1760. return 0;
  1761. }
  1762. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1763. {
  1764. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1765. struct l4_kcq kcqe;
  1766. struct kcqe *cqes[1];
  1767. memset(&kcqe, 0, sizeof(kcqe));
  1768. kcqe.pg_host_opaque = req->pg_host_opaque;
  1769. kcqe.pg_cid = req->pg_cid;
  1770. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1771. cqes[0] = (struct kcqe *) &kcqe;
  1772. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1773. return 0;
  1774. }
  1775. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1776. {
  1777. struct fcoe_kwqe_stat *req;
  1778. struct fcoe_stat_ramrod_params *fcoe_stat;
  1779. union l5cm_specific_data l5_data;
  1780. struct cnic_local *cp = dev->cnic_priv;
  1781. int ret;
  1782. u32 cid;
  1783. req = (struct fcoe_kwqe_stat *) kwqe;
  1784. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1785. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1786. if (!fcoe_stat)
  1787. return -ENOMEM;
  1788. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1789. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1790. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1791. FCOE_CONNECTION_TYPE, &l5_data);
  1792. return ret;
  1793. }
  1794. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1795. u32 num, int *work)
  1796. {
  1797. int ret;
  1798. struct cnic_local *cp = dev->cnic_priv;
  1799. u32 cid;
  1800. struct fcoe_init_ramrod_params *fcoe_init;
  1801. struct fcoe_kwqe_init1 *req1;
  1802. struct fcoe_kwqe_init2 *req2;
  1803. struct fcoe_kwqe_init3 *req3;
  1804. union l5cm_specific_data l5_data;
  1805. if (num < 3) {
  1806. *work = num;
  1807. return -EINVAL;
  1808. }
  1809. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1810. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1811. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1812. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1813. *work = 1;
  1814. return -EINVAL;
  1815. }
  1816. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1817. *work = 2;
  1818. return -EINVAL;
  1819. }
  1820. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1821. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1822. return -ENOMEM;
  1823. }
  1824. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1825. if (!fcoe_init)
  1826. return -ENOMEM;
  1827. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1828. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1829. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1830. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1831. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1832. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1833. fcoe_init->eq_next_page_addr.lo =
  1834. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1835. fcoe_init->eq_next_page_addr.hi =
  1836. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1837. fcoe_init->sb_num = cp->status_blk_num;
  1838. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1839. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1840. cp->kcq2.sw_prod_idx = 0;
  1841. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1842. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1843. FCOE_CONNECTION_TYPE, &l5_data);
  1844. *work = 3;
  1845. return ret;
  1846. }
  1847. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1848. u32 num, int *work)
  1849. {
  1850. int ret = 0;
  1851. u32 cid = -1, l5_cid;
  1852. struct cnic_local *cp = dev->cnic_priv;
  1853. struct fcoe_kwqe_conn_offload1 *req1;
  1854. struct fcoe_kwqe_conn_offload2 *req2;
  1855. struct fcoe_kwqe_conn_offload3 *req3;
  1856. struct fcoe_kwqe_conn_offload4 *req4;
  1857. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1858. struct cnic_context *ctx;
  1859. struct fcoe_context *fctx;
  1860. struct regpair ctx_addr;
  1861. union l5cm_specific_data l5_data;
  1862. struct fcoe_kcqe kcqe;
  1863. struct kcqe *cqes[1];
  1864. if (num < 4) {
  1865. *work = num;
  1866. return -EINVAL;
  1867. }
  1868. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1869. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1870. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1871. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1872. *work = 4;
  1873. l5_cid = req1->fcoe_conn_id;
  1874. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1875. goto err_reply;
  1876. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1877. ctx = &cp->ctx_tbl[l5_cid];
  1878. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1879. goto err_reply;
  1880. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1881. if (ret) {
  1882. ret = 0;
  1883. goto err_reply;
  1884. }
  1885. cid = ctx->cid;
  1886. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1887. if (fctx) {
  1888. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1889. u32 val;
  1890. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1891. FCOE_CONNECTION_TYPE);
  1892. fctx->xstorm_ag_context.cdu_reserved = val;
  1893. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1894. FCOE_CONNECTION_TYPE);
  1895. fctx->ustorm_ag_context.cdu_usage = val;
  1896. }
  1897. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1898. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1899. goto err_reply;
  1900. }
  1901. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1902. if (!fcoe_offload)
  1903. goto err_reply;
  1904. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1905. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1906. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1907. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1908. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1909. cid = BNX2X_HW_CID(cp, cid);
  1910. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1911. FCOE_CONNECTION_TYPE, &l5_data);
  1912. if (!ret)
  1913. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1914. return ret;
  1915. err_reply:
  1916. if (cid != -1)
  1917. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1918. memset(&kcqe, 0, sizeof(kcqe));
  1919. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1920. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1921. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1922. cqes[0] = (struct kcqe *) &kcqe;
  1923. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1924. return ret;
  1925. }
  1926. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1927. {
  1928. struct fcoe_kwqe_conn_enable_disable *req;
  1929. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1930. union l5cm_specific_data l5_data;
  1931. int ret;
  1932. u32 cid, l5_cid;
  1933. struct cnic_local *cp = dev->cnic_priv;
  1934. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1935. cid = req->context_id;
  1936. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1937. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1938. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1939. return -ENOMEM;
  1940. }
  1941. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1942. if (!fcoe_enable)
  1943. return -ENOMEM;
  1944. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1945. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1946. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1947. FCOE_CONNECTION_TYPE, &l5_data);
  1948. return ret;
  1949. }
  1950. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1951. {
  1952. struct fcoe_kwqe_conn_enable_disable *req;
  1953. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1954. union l5cm_specific_data l5_data;
  1955. int ret;
  1956. u32 cid, l5_cid;
  1957. struct cnic_local *cp = dev->cnic_priv;
  1958. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1959. cid = req->context_id;
  1960. l5_cid = req->conn_id;
  1961. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1962. return -EINVAL;
  1963. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1964. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1965. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1966. return -ENOMEM;
  1967. }
  1968. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1969. if (!fcoe_disable)
  1970. return -ENOMEM;
  1971. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1972. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  1973. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  1974. FCOE_CONNECTION_TYPE, &l5_data);
  1975. return ret;
  1976. }
  1977. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1978. {
  1979. struct fcoe_kwqe_conn_destroy *req;
  1980. union l5cm_specific_data l5_data;
  1981. int ret;
  1982. u32 cid, l5_cid;
  1983. struct cnic_local *cp = dev->cnic_priv;
  1984. struct cnic_context *ctx;
  1985. struct fcoe_kcqe kcqe;
  1986. struct kcqe *cqes[1];
  1987. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  1988. cid = req->context_id;
  1989. l5_cid = req->conn_id;
  1990. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1991. return -EINVAL;
  1992. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1993. ctx = &cp->ctx_tbl[l5_cid];
  1994. init_waitqueue_head(&ctx->waitq);
  1995. ctx->wait_cond = 0;
  1996. memset(&l5_data, 0, sizeof(l5_data));
  1997. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  1998. FCOE_CONNECTION_TYPE, &l5_data);
  1999. if (ret == 0) {
  2000. wait_event(ctx->waitq, ctx->wait_cond);
  2001. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2002. queue_delayed_work(cnic_wq, &cp->delete_task,
  2003. msecs_to_jiffies(2000));
  2004. }
  2005. memset(&kcqe, 0, sizeof(kcqe));
  2006. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2007. kcqe.fcoe_conn_id = req->conn_id;
  2008. kcqe.fcoe_conn_context_id = cid;
  2009. cqes[0] = (struct kcqe *) &kcqe;
  2010. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2011. return ret;
  2012. }
  2013. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2014. {
  2015. struct fcoe_kwqe_destroy *req;
  2016. union l5cm_specific_data l5_data;
  2017. struct cnic_local *cp = dev->cnic_priv;
  2018. int ret;
  2019. u32 cid;
  2020. req = (struct fcoe_kwqe_destroy *) kwqe;
  2021. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2022. memset(&l5_data, 0, sizeof(l5_data));
  2023. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2024. FCOE_CONNECTION_TYPE, &l5_data);
  2025. return ret;
  2026. }
  2027. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2028. struct kwqe *wqes[], u32 num_wqes)
  2029. {
  2030. int i, work, ret;
  2031. u32 opcode;
  2032. struct kwqe *kwqe;
  2033. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2034. return -EAGAIN; /* bnx2 is down */
  2035. for (i = 0; i < num_wqes; ) {
  2036. kwqe = wqes[i];
  2037. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2038. work = 1;
  2039. switch (opcode) {
  2040. case ISCSI_KWQE_OPCODE_INIT1:
  2041. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2042. break;
  2043. case ISCSI_KWQE_OPCODE_INIT2:
  2044. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2045. break;
  2046. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2047. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2048. num_wqes - i, &work);
  2049. break;
  2050. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2051. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2052. break;
  2053. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2054. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2055. break;
  2056. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2057. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2058. &work);
  2059. break;
  2060. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2061. ret = cnic_bnx2x_close(dev, kwqe);
  2062. break;
  2063. case L4_KWQE_OPCODE_VALUE_RESET:
  2064. ret = cnic_bnx2x_reset(dev, kwqe);
  2065. break;
  2066. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2067. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2068. break;
  2069. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2070. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2071. break;
  2072. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2073. ret = 0;
  2074. break;
  2075. default:
  2076. ret = 0;
  2077. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2078. opcode);
  2079. break;
  2080. }
  2081. if (ret < 0)
  2082. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2083. opcode);
  2084. i += work;
  2085. }
  2086. return 0;
  2087. }
  2088. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2089. struct kwqe *wqes[], u32 num_wqes)
  2090. {
  2091. struct cnic_local *cp = dev->cnic_priv;
  2092. int i, work, ret;
  2093. u32 opcode;
  2094. struct kwqe *kwqe;
  2095. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2096. return -EAGAIN; /* bnx2 is down */
  2097. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2098. return -EINVAL;
  2099. for (i = 0; i < num_wqes; ) {
  2100. kwqe = wqes[i];
  2101. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2102. work = 1;
  2103. switch (opcode) {
  2104. case FCOE_KWQE_OPCODE_INIT1:
  2105. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2106. num_wqes - i, &work);
  2107. break;
  2108. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2109. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2110. num_wqes - i, &work);
  2111. break;
  2112. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2113. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2114. break;
  2115. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2116. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2117. break;
  2118. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2119. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2120. break;
  2121. case FCOE_KWQE_OPCODE_DESTROY:
  2122. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2123. break;
  2124. case FCOE_KWQE_OPCODE_STAT:
  2125. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2126. break;
  2127. default:
  2128. ret = 0;
  2129. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2130. opcode);
  2131. break;
  2132. }
  2133. if (ret < 0)
  2134. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2135. opcode);
  2136. i += work;
  2137. }
  2138. return 0;
  2139. }
  2140. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2141. u32 num_wqes)
  2142. {
  2143. int ret = -EINVAL;
  2144. u32 layer_code;
  2145. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2146. return -EAGAIN; /* bnx2x is down */
  2147. if (!num_wqes)
  2148. return 0;
  2149. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2150. switch (layer_code) {
  2151. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2152. case KWQE_FLAGS_LAYER_MASK_L4:
  2153. case KWQE_FLAGS_LAYER_MASK_L2:
  2154. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2155. break;
  2156. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2157. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2158. break;
  2159. }
  2160. return ret;
  2161. }
  2162. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2163. {
  2164. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2165. return KCQE_FLAGS_LAYER_MASK_L4;
  2166. return opflag & KCQE_FLAGS_LAYER_MASK;
  2167. }
  2168. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2169. {
  2170. struct cnic_local *cp = dev->cnic_priv;
  2171. int i, j, comp = 0;
  2172. i = 0;
  2173. j = 1;
  2174. while (num_cqes) {
  2175. struct cnic_ulp_ops *ulp_ops;
  2176. int ulp_type;
  2177. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2178. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2179. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2180. comp++;
  2181. while (j < num_cqes) {
  2182. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2183. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2184. break;
  2185. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2186. comp++;
  2187. j++;
  2188. }
  2189. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2190. ulp_type = CNIC_ULP_RDMA;
  2191. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2192. ulp_type = CNIC_ULP_ISCSI;
  2193. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2194. ulp_type = CNIC_ULP_FCOE;
  2195. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2196. ulp_type = CNIC_ULP_L4;
  2197. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2198. goto end;
  2199. else {
  2200. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2201. kcqe_op_flag);
  2202. goto end;
  2203. }
  2204. rcu_read_lock();
  2205. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2206. if (likely(ulp_ops)) {
  2207. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2208. cp->completed_kcq + i, j);
  2209. }
  2210. rcu_read_unlock();
  2211. end:
  2212. num_cqes -= j;
  2213. i += j;
  2214. j = 1;
  2215. }
  2216. if (unlikely(comp))
  2217. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2218. }
  2219. static u16 cnic_bnx2_next_idx(u16 idx)
  2220. {
  2221. return idx + 1;
  2222. }
  2223. static u16 cnic_bnx2_hw_idx(u16 idx)
  2224. {
  2225. return idx;
  2226. }
  2227. static u16 cnic_bnx2x_next_idx(u16 idx)
  2228. {
  2229. idx++;
  2230. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2231. idx++;
  2232. return idx;
  2233. }
  2234. static u16 cnic_bnx2x_hw_idx(u16 idx)
  2235. {
  2236. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2237. idx++;
  2238. return idx;
  2239. }
  2240. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2241. {
  2242. struct cnic_local *cp = dev->cnic_priv;
  2243. u16 i, ri, hw_prod, last;
  2244. struct kcqe *kcqe;
  2245. int kcqe_cnt = 0, last_cnt = 0;
  2246. i = ri = last = info->sw_prod_idx;
  2247. ri &= MAX_KCQ_IDX;
  2248. hw_prod = *info->hw_prod_idx_ptr;
  2249. hw_prod = cp->hw_idx(hw_prod);
  2250. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2251. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2252. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2253. i = cp->next_idx(i);
  2254. ri = i & MAX_KCQ_IDX;
  2255. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2256. last_cnt = kcqe_cnt;
  2257. last = i;
  2258. }
  2259. }
  2260. info->sw_prod_idx = last;
  2261. return last_cnt;
  2262. }
  2263. static int cnic_l2_completion(struct cnic_local *cp)
  2264. {
  2265. u16 hw_cons, sw_cons;
  2266. struct cnic_uio_dev *udev = cp->udev;
  2267. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2268. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2269. u32 cmd;
  2270. int comp = 0;
  2271. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2272. return 0;
  2273. hw_cons = *cp->rx_cons_ptr;
  2274. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2275. hw_cons++;
  2276. sw_cons = cp->rx_cons;
  2277. while (sw_cons != hw_cons) {
  2278. u8 cqe_fp_flags;
  2279. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2280. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2281. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2282. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2283. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2284. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2285. cmd == RAMROD_CMD_ID_ETH_HALT)
  2286. comp++;
  2287. }
  2288. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2289. }
  2290. return comp;
  2291. }
  2292. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2293. {
  2294. u16 rx_cons, tx_cons;
  2295. int comp = 0;
  2296. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2297. return;
  2298. rx_cons = *cp->rx_cons_ptr;
  2299. tx_cons = *cp->tx_cons_ptr;
  2300. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2301. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2302. comp = cnic_l2_completion(cp);
  2303. cp->tx_cons = tx_cons;
  2304. cp->rx_cons = rx_cons;
  2305. if (cp->udev)
  2306. uio_event_notify(&cp->udev->cnic_uinfo);
  2307. }
  2308. if (comp)
  2309. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2310. }
  2311. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2312. {
  2313. struct cnic_local *cp = dev->cnic_priv;
  2314. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2315. int kcqe_cnt;
  2316. /* status block index must be read before reading other fields */
  2317. rmb();
  2318. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2319. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2320. service_kcqes(dev, kcqe_cnt);
  2321. /* Tell compiler that status_blk fields can change. */
  2322. barrier();
  2323. if (status_idx != *cp->kcq1.status_idx_ptr) {
  2324. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2325. /* status block index must be read first */
  2326. rmb();
  2327. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2328. } else
  2329. break;
  2330. }
  2331. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2332. cnic_chk_pkt_rings(cp);
  2333. return status_idx;
  2334. }
  2335. static int cnic_service_bnx2(void *data, void *status_blk)
  2336. {
  2337. struct cnic_dev *dev = data;
  2338. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2339. struct status_block *sblk = status_blk;
  2340. return sblk->status_idx;
  2341. }
  2342. return cnic_service_bnx2_queues(dev);
  2343. }
  2344. static void cnic_service_bnx2_msix(unsigned long data)
  2345. {
  2346. struct cnic_dev *dev = (struct cnic_dev *) data;
  2347. struct cnic_local *cp = dev->cnic_priv;
  2348. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2349. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2350. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2351. }
  2352. static void cnic_doirq(struct cnic_dev *dev)
  2353. {
  2354. struct cnic_local *cp = dev->cnic_priv;
  2355. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2356. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2357. prefetch(cp->status_blk.gen);
  2358. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2359. tasklet_schedule(&cp->cnic_irq_task);
  2360. }
  2361. }
  2362. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2363. {
  2364. struct cnic_dev *dev = dev_instance;
  2365. struct cnic_local *cp = dev->cnic_priv;
  2366. if (cp->ack_int)
  2367. cp->ack_int(dev);
  2368. cnic_doirq(dev);
  2369. return IRQ_HANDLED;
  2370. }
  2371. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2372. u16 index, u8 op, u8 update)
  2373. {
  2374. struct cnic_local *cp = dev->cnic_priv;
  2375. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2376. COMMAND_REG_INT_ACK);
  2377. struct igu_ack_register igu_ack;
  2378. igu_ack.status_block_index = index;
  2379. igu_ack.sb_id_and_flags =
  2380. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2381. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2382. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2383. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2384. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2385. }
  2386. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2387. u16 index, u8 op, u8 update)
  2388. {
  2389. struct igu_regular cmd_data;
  2390. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2391. cmd_data.sb_id_and_flags =
  2392. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2393. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2394. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2395. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2396. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2397. }
  2398. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2399. {
  2400. struct cnic_local *cp = dev->cnic_priv;
  2401. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2402. IGU_INT_DISABLE, 0);
  2403. }
  2404. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2405. {
  2406. struct cnic_local *cp = dev->cnic_priv;
  2407. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2408. IGU_INT_DISABLE, 0);
  2409. }
  2410. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2411. {
  2412. u32 last_status = *info->status_idx_ptr;
  2413. int kcqe_cnt;
  2414. /* status block index must be read before reading the KCQ */
  2415. rmb();
  2416. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2417. service_kcqes(dev, kcqe_cnt);
  2418. /* Tell compiler that sblk fields can change. */
  2419. barrier();
  2420. if (last_status == *info->status_idx_ptr)
  2421. break;
  2422. last_status = *info->status_idx_ptr;
  2423. /* status block index must be read before reading the KCQ */
  2424. rmb();
  2425. }
  2426. return last_status;
  2427. }
  2428. static void cnic_service_bnx2x_bh(unsigned long data)
  2429. {
  2430. struct cnic_dev *dev = (struct cnic_dev *) data;
  2431. struct cnic_local *cp = dev->cnic_priv;
  2432. u32 status_idx, new_status_idx;
  2433. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2434. return;
  2435. while (1) {
  2436. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2437. CNIC_WR16(dev, cp->kcq1.io_addr,
  2438. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2439. if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2440. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2441. status_idx, IGU_INT_ENABLE, 1);
  2442. break;
  2443. }
  2444. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2445. if (new_status_idx != status_idx)
  2446. continue;
  2447. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2448. MAX_KCQ_IDX);
  2449. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2450. status_idx, IGU_INT_ENABLE, 1);
  2451. break;
  2452. }
  2453. }
  2454. static int cnic_service_bnx2x(void *data, void *status_blk)
  2455. {
  2456. struct cnic_dev *dev = data;
  2457. struct cnic_local *cp = dev->cnic_priv;
  2458. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2459. cnic_doirq(dev);
  2460. cnic_chk_pkt_rings(cp);
  2461. return 0;
  2462. }
  2463. static void cnic_ulp_stop(struct cnic_dev *dev)
  2464. {
  2465. struct cnic_local *cp = dev->cnic_priv;
  2466. int if_type;
  2467. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2468. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2469. struct cnic_ulp_ops *ulp_ops;
  2470. mutex_lock(&cnic_lock);
  2471. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2472. lockdep_is_held(&cnic_lock));
  2473. if (!ulp_ops) {
  2474. mutex_unlock(&cnic_lock);
  2475. continue;
  2476. }
  2477. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2478. mutex_unlock(&cnic_lock);
  2479. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2480. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2481. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2482. }
  2483. }
  2484. static void cnic_ulp_start(struct cnic_dev *dev)
  2485. {
  2486. struct cnic_local *cp = dev->cnic_priv;
  2487. int if_type;
  2488. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2489. struct cnic_ulp_ops *ulp_ops;
  2490. mutex_lock(&cnic_lock);
  2491. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2492. lockdep_is_held(&cnic_lock));
  2493. if (!ulp_ops || !ulp_ops->cnic_start) {
  2494. mutex_unlock(&cnic_lock);
  2495. continue;
  2496. }
  2497. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2498. mutex_unlock(&cnic_lock);
  2499. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2500. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2501. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2502. }
  2503. }
  2504. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2505. {
  2506. struct cnic_dev *dev = data;
  2507. switch (info->cmd) {
  2508. case CNIC_CTL_STOP_CMD:
  2509. cnic_hold(dev);
  2510. cnic_ulp_stop(dev);
  2511. cnic_stop_hw(dev);
  2512. cnic_put(dev);
  2513. break;
  2514. case CNIC_CTL_START_CMD:
  2515. cnic_hold(dev);
  2516. if (!cnic_start_hw(dev))
  2517. cnic_ulp_start(dev);
  2518. cnic_put(dev);
  2519. break;
  2520. case CNIC_CTL_COMPLETION_CMD: {
  2521. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2522. u32 l5_cid;
  2523. struct cnic_local *cp = dev->cnic_priv;
  2524. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2525. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2526. ctx->wait_cond = 1;
  2527. wake_up(&ctx->waitq);
  2528. }
  2529. break;
  2530. }
  2531. default:
  2532. return -EINVAL;
  2533. }
  2534. return 0;
  2535. }
  2536. static void cnic_ulp_init(struct cnic_dev *dev)
  2537. {
  2538. int i;
  2539. struct cnic_local *cp = dev->cnic_priv;
  2540. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2541. struct cnic_ulp_ops *ulp_ops;
  2542. mutex_lock(&cnic_lock);
  2543. ulp_ops = cnic_ulp_tbl_prot(i);
  2544. if (!ulp_ops || !ulp_ops->cnic_init) {
  2545. mutex_unlock(&cnic_lock);
  2546. continue;
  2547. }
  2548. ulp_get(ulp_ops);
  2549. mutex_unlock(&cnic_lock);
  2550. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2551. ulp_ops->cnic_init(dev);
  2552. ulp_put(ulp_ops);
  2553. }
  2554. }
  2555. static void cnic_ulp_exit(struct cnic_dev *dev)
  2556. {
  2557. int i;
  2558. struct cnic_local *cp = dev->cnic_priv;
  2559. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2560. struct cnic_ulp_ops *ulp_ops;
  2561. mutex_lock(&cnic_lock);
  2562. ulp_ops = cnic_ulp_tbl_prot(i);
  2563. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2564. mutex_unlock(&cnic_lock);
  2565. continue;
  2566. }
  2567. ulp_get(ulp_ops);
  2568. mutex_unlock(&cnic_lock);
  2569. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2570. ulp_ops->cnic_exit(dev);
  2571. ulp_put(ulp_ops);
  2572. }
  2573. }
  2574. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2575. {
  2576. struct cnic_dev *dev = csk->dev;
  2577. struct l4_kwq_offload_pg *l4kwqe;
  2578. struct kwqe *wqes[1];
  2579. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2580. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2581. wqes[0] = (struct kwqe *) l4kwqe;
  2582. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2583. l4kwqe->flags =
  2584. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2585. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2586. l4kwqe->da0 = csk->ha[0];
  2587. l4kwqe->da1 = csk->ha[1];
  2588. l4kwqe->da2 = csk->ha[2];
  2589. l4kwqe->da3 = csk->ha[3];
  2590. l4kwqe->da4 = csk->ha[4];
  2591. l4kwqe->da5 = csk->ha[5];
  2592. l4kwqe->sa0 = dev->mac_addr[0];
  2593. l4kwqe->sa1 = dev->mac_addr[1];
  2594. l4kwqe->sa2 = dev->mac_addr[2];
  2595. l4kwqe->sa3 = dev->mac_addr[3];
  2596. l4kwqe->sa4 = dev->mac_addr[4];
  2597. l4kwqe->sa5 = dev->mac_addr[5];
  2598. l4kwqe->etype = ETH_P_IP;
  2599. l4kwqe->ipid_start = DEF_IPID_START;
  2600. l4kwqe->host_opaque = csk->l5_cid;
  2601. if (csk->vlan_id) {
  2602. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2603. l4kwqe->vlan_tag = csk->vlan_id;
  2604. l4kwqe->l2hdr_nbytes += 4;
  2605. }
  2606. return dev->submit_kwqes(dev, wqes, 1);
  2607. }
  2608. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2609. {
  2610. struct cnic_dev *dev = csk->dev;
  2611. struct l4_kwq_update_pg *l4kwqe;
  2612. struct kwqe *wqes[1];
  2613. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2614. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2615. wqes[0] = (struct kwqe *) l4kwqe;
  2616. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2617. l4kwqe->flags =
  2618. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2619. l4kwqe->pg_cid = csk->pg_cid;
  2620. l4kwqe->da0 = csk->ha[0];
  2621. l4kwqe->da1 = csk->ha[1];
  2622. l4kwqe->da2 = csk->ha[2];
  2623. l4kwqe->da3 = csk->ha[3];
  2624. l4kwqe->da4 = csk->ha[4];
  2625. l4kwqe->da5 = csk->ha[5];
  2626. l4kwqe->pg_host_opaque = csk->l5_cid;
  2627. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2628. return dev->submit_kwqes(dev, wqes, 1);
  2629. }
  2630. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2631. {
  2632. struct cnic_dev *dev = csk->dev;
  2633. struct l4_kwq_upload *l4kwqe;
  2634. struct kwqe *wqes[1];
  2635. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2636. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2637. wqes[0] = (struct kwqe *) l4kwqe;
  2638. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2639. l4kwqe->flags =
  2640. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2641. l4kwqe->cid = csk->pg_cid;
  2642. return dev->submit_kwqes(dev, wqes, 1);
  2643. }
  2644. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2645. {
  2646. struct cnic_dev *dev = csk->dev;
  2647. struct l4_kwq_connect_req1 *l4kwqe1;
  2648. struct l4_kwq_connect_req2 *l4kwqe2;
  2649. struct l4_kwq_connect_req3 *l4kwqe3;
  2650. struct kwqe *wqes[3];
  2651. u8 tcp_flags = 0;
  2652. int num_wqes = 2;
  2653. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2654. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2655. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2656. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2657. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2658. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2659. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2660. l4kwqe3->flags =
  2661. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2662. l4kwqe3->ka_timeout = csk->ka_timeout;
  2663. l4kwqe3->ka_interval = csk->ka_interval;
  2664. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2665. l4kwqe3->tos = csk->tos;
  2666. l4kwqe3->ttl = csk->ttl;
  2667. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2668. l4kwqe3->pmtu = csk->mtu;
  2669. l4kwqe3->rcv_buf = csk->rcv_buf;
  2670. l4kwqe3->snd_buf = csk->snd_buf;
  2671. l4kwqe3->seed = csk->seed;
  2672. wqes[0] = (struct kwqe *) l4kwqe1;
  2673. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2674. wqes[1] = (struct kwqe *) l4kwqe2;
  2675. wqes[2] = (struct kwqe *) l4kwqe3;
  2676. num_wqes = 3;
  2677. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2678. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2679. l4kwqe2->flags =
  2680. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2681. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2682. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2683. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2684. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2685. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2686. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2687. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2688. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2689. sizeof(struct tcphdr);
  2690. } else {
  2691. wqes[1] = (struct kwqe *) l4kwqe3;
  2692. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2693. sizeof(struct tcphdr);
  2694. }
  2695. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2696. l4kwqe1->flags =
  2697. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2698. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2699. l4kwqe1->cid = csk->cid;
  2700. l4kwqe1->pg_cid = csk->pg_cid;
  2701. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2702. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2703. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2704. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2705. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2706. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2707. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2708. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2709. if (csk->tcp_flags & SK_TCP_NAGLE)
  2710. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2711. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2712. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2713. if (csk->tcp_flags & SK_TCP_SACK)
  2714. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2715. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2716. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2717. l4kwqe1->tcp_flags = tcp_flags;
  2718. return dev->submit_kwqes(dev, wqes, num_wqes);
  2719. }
  2720. static int cnic_cm_close_req(struct cnic_sock *csk)
  2721. {
  2722. struct cnic_dev *dev = csk->dev;
  2723. struct l4_kwq_close_req *l4kwqe;
  2724. struct kwqe *wqes[1];
  2725. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2726. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2727. wqes[0] = (struct kwqe *) l4kwqe;
  2728. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2729. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2730. l4kwqe->cid = csk->cid;
  2731. return dev->submit_kwqes(dev, wqes, 1);
  2732. }
  2733. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2734. {
  2735. struct cnic_dev *dev = csk->dev;
  2736. struct l4_kwq_reset_req *l4kwqe;
  2737. struct kwqe *wqes[1];
  2738. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2739. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2740. wqes[0] = (struct kwqe *) l4kwqe;
  2741. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2742. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2743. l4kwqe->cid = csk->cid;
  2744. return dev->submit_kwqes(dev, wqes, 1);
  2745. }
  2746. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2747. u32 l5_cid, struct cnic_sock **csk, void *context)
  2748. {
  2749. struct cnic_local *cp = dev->cnic_priv;
  2750. struct cnic_sock *csk1;
  2751. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2752. return -EINVAL;
  2753. if (cp->ctx_tbl) {
  2754. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2755. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2756. return -EAGAIN;
  2757. }
  2758. csk1 = &cp->csk_tbl[l5_cid];
  2759. if (atomic_read(&csk1->ref_count))
  2760. return -EAGAIN;
  2761. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2762. return -EBUSY;
  2763. csk1->dev = dev;
  2764. csk1->cid = cid;
  2765. csk1->l5_cid = l5_cid;
  2766. csk1->ulp_type = ulp_type;
  2767. csk1->context = context;
  2768. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2769. csk1->ka_interval = DEF_KA_INTERVAL;
  2770. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2771. csk1->tos = DEF_TOS;
  2772. csk1->ttl = DEF_TTL;
  2773. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2774. csk1->rcv_buf = DEF_RCV_BUF;
  2775. csk1->snd_buf = DEF_SND_BUF;
  2776. csk1->seed = DEF_SEED;
  2777. *csk = csk1;
  2778. return 0;
  2779. }
  2780. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2781. {
  2782. if (csk->src_port) {
  2783. struct cnic_dev *dev = csk->dev;
  2784. struct cnic_local *cp = dev->cnic_priv;
  2785. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2786. csk->src_port = 0;
  2787. }
  2788. }
  2789. static void cnic_close_conn(struct cnic_sock *csk)
  2790. {
  2791. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2792. cnic_cm_upload_pg(csk);
  2793. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2794. }
  2795. cnic_cm_cleanup(csk);
  2796. }
  2797. static int cnic_cm_destroy(struct cnic_sock *csk)
  2798. {
  2799. if (!cnic_in_use(csk))
  2800. return -EINVAL;
  2801. csk_hold(csk);
  2802. clear_bit(SK_F_INUSE, &csk->flags);
  2803. smp_mb__after_clear_bit();
  2804. while (atomic_read(&csk->ref_count) != 1)
  2805. msleep(1);
  2806. cnic_cm_cleanup(csk);
  2807. csk->flags = 0;
  2808. csk_put(csk);
  2809. return 0;
  2810. }
  2811. static inline u16 cnic_get_vlan(struct net_device *dev,
  2812. struct net_device **vlan_dev)
  2813. {
  2814. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2815. *vlan_dev = vlan_dev_real_dev(dev);
  2816. return vlan_dev_vlan_id(dev);
  2817. }
  2818. *vlan_dev = dev;
  2819. return 0;
  2820. }
  2821. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2822. struct dst_entry **dst)
  2823. {
  2824. #if defined(CONFIG_INET)
  2825. struct rtable *rt;
  2826. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2827. if (!IS_ERR(rt)) {
  2828. *dst = &rt->dst;
  2829. return 0;
  2830. }
  2831. return PTR_ERR(rt);
  2832. #else
  2833. return -ENETUNREACH;
  2834. #endif
  2835. }
  2836. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2837. struct dst_entry **dst)
  2838. {
  2839. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2840. struct flowi6 fl6;
  2841. memset(&fl6, 0, sizeof(fl6));
  2842. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2843. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2844. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2845. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2846. if (*dst)
  2847. return 0;
  2848. #endif
  2849. return -ENETUNREACH;
  2850. }
  2851. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2852. int ulp_type)
  2853. {
  2854. struct cnic_dev *dev = NULL;
  2855. struct dst_entry *dst;
  2856. struct net_device *netdev = NULL;
  2857. int err = -ENETUNREACH;
  2858. if (dst_addr->sin_family == AF_INET)
  2859. err = cnic_get_v4_route(dst_addr, &dst);
  2860. else if (dst_addr->sin_family == AF_INET6) {
  2861. struct sockaddr_in6 *dst_addr6 =
  2862. (struct sockaddr_in6 *) dst_addr;
  2863. err = cnic_get_v6_route(dst_addr6, &dst);
  2864. } else
  2865. return NULL;
  2866. if (err)
  2867. return NULL;
  2868. if (!dst->dev)
  2869. goto done;
  2870. cnic_get_vlan(dst->dev, &netdev);
  2871. dev = cnic_from_netdev(netdev);
  2872. done:
  2873. dst_release(dst);
  2874. if (dev)
  2875. cnic_put(dev);
  2876. return dev;
  2877. }
  2878. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2879. {
  2880. struct cnic_dev *dev = csk->dev;
  2881. struct cnic_local *cp = dev->cnic_priv;
  2882. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2883. }
  2884. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2885. {
  2886. struct cnic_dev *dev = csk->dev;
  2887. struct cnic_local *cp = dev->cnic_priv;
  2888. int is_v6, rc = 0;
  2889. struct dst_entry *dst = NULL;
  2890. struct net_device *realdev;
  2891. __be16 local_port;
  2892. u32 port_id;
  2893. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2894. saddr->remote.v6.sin6_family == AF_INET6)
  2895. is_v6 = 1;
  2896. else if (saddr->local.v4.sin_family == AF_INET &&
  2897. saddr->remote.v4.sin_family == AF_INET)
  2898. is_v6 = 0;
  2899. else
  2900. return -EINVAL;
  2901. clear_bit(SK_F_IPV6, &csk->flags);
  2902. if (is_v6) {
  2903. set_bit(SK_F_IPV6, &csk->flags);
  2904. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2905. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2906. sizeof(struct in6_addr));
  2907. csk->dst_port = saddr->remote.v6.sin6_port;
  2908. local_port = saddr->local.v6.sin6_port;
  2909. } else {
  2910. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2911. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2912. csk->dst_port = saddr->remote.v4.sin_port;
  2913. local_port = saddr->local.v4.sin_port;
  2914. }
  2915. csk->vlan_id = 0;
  2916. csk->mtu = dev->netdev->mtu;
  2917. if (dst && dst->dev) {
  2918. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2919. if (realdev == dev->netdev) {
  2920. csk->vlan_id = vlan;
  2921. csk->mtu = dst_mtu(dst);
  2922. }
  2923. }
  2924. port_id = be16_to_cpu(local_port);
  2925. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2926. port_id < CNIC_LOCAL_PORT_MAX) {
  2927. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2928. port_id = 0;
  2929. } else
  2930. port_id = 0;
  2931. if (!port_id) {
  2932. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2933. if (port_id == -1) {
  2934. rc = -ENOMEM;
  2935. goto err_out;
  2936. }
  2937. local_port = cpu_to_be16(port_id);
  2938. }
  2939. csk->src_port = local_port;
  2940. err_out:
  2941. dst_release(dst);
  2942. return rc;
  2943. }
  2944. static void cnic_init_csk_state(struct cnic_sock *csk)
  2945. {
  2946. csk->state = 0;
  2947. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2948. clear_bit(SK_F_CLOSING, &csk->flags);
  2949. }
  2950. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2951. {
  2952. int err = 0;
  2953. if (!cnic_in_use(csk))
  2954. return -EINVAL;
  2955. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2956. return -EINVAL;
  2957. cnic_init_csk_state(csk);
  2958. err = cnic_get_route(csk, saddr);
  2959. if (err)
  2960. goto err_out;
  2961. err = cnic_resolve_addr(csk, saddr);
  2962. if (!err)
  2963. return 0;
  2964. err_out:
  2965. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2966. return err;
  2967. }
  2968. static int cnic_cm_abort(struct cnic_sock *csk)
  2969. {
  2970. struct cnic_local *cp = csk->dev->cnic_priv;
  2971. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2972. if (!cnic_in_use(csk))
  2973. return -EINVAL;
  2974. if (cnic_abort_prep(csk))
  2975. return cnic_cm_abort_req(csk);
  2976. /* Getting here means that we haven't started connect, or
  2977. * connect was not successful.
  2978. */
  2979. cp->close_conn(csk, opcode);
  2980. if (csk->state != opcode)
  2981. return -EALREADY;
  2982. return 0;
  2983. }
  2984. static int cnic_cm_close(struct cnic_sock *csk)
  2985. {
  2986. if (!cnic_in_use(csk))
  2987. return -EINVAL;
  2988. if (cnic_close_prep(csk)) {
  2989. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2990. return cnic_cm_close_req(csk);
  2991. } else {
  2992. return -EALREADY;
  2993. }
  2994. return 0;
  2995. }
  2996. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2997. u8 opcode)
  2998. {
  2999. struct cnic_ulp_ops *ulp_ops;
  3000. int ulp_type = csk->ulp_type;
  3001. rcu_read_lock();
  3002. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3003. if (ulp_ops) {
  3004. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3005. ulp_ops->cm_connect_complete(csk);
  3006. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3007. ulp_ops->cm_close_complete(csk);
  3008. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3009. ulp_ops->cm_remote_abort(csk);
  3010. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3011. ulp_ops->cm_abort_complete(csk);
  3012. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3013. ulp_ops->cm_remote_close(csk);
  3014. }
  3015. rcu_read_unlock();
  3016. }
  3017. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3018. {
  3019. if (cnic_offld_prep(csk)) {
  3020. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3021. cnic_cm_update_pg(csk);
  3022. else
  3023. cnic_cm_offload_pg(csk);
  3024. }
  3025. return 0;
  3026. }
  3027. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3028. {
  3029. struct cnic_local *cp = dev->cnic_priv;
  3030. u32 l5_cid = kcqe->pg_host_opaque;
  3031. u8 opcode = kcqe->op_code;
  3032. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3033. csk_hold(csk);
  3034. if (!cnic_in_use(csk))
  3035. goto done;
  3036. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3037. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3038. goto done;
  3039. }
  3040. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3041. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3042. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3043. cnic_cm_upcall(cp, csk,
  3044. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3045. goto done;
  3046. }
  3047. csk->pg_cid = kcqe->pg_cid;
  3048. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3049. cnic_cm_conn_req(csk);
  3050. done:
  3051. csk_put(csk);
  3052. }
  3053. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3054. {
  3055. struct cnic_local *cp = dev->cnic_priv;
  3056. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3057. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3058. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3059. ctx->timestamp = jiffies;
  3060. ctx->wait_cond = 1;
  3061. wake_up(&ctx->waitq);
  3062. }
  3063. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3064. {
  3065. struct cnic_local *cp = dev->cnic_priv;
  3066. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3067. u8 opcode = l4kcqe->op_code;
  3068. u32 l5_cid;
  3069. struct cnic_sock *csk;
  3070. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3071. cnic_process_fcoe_term_conn(dev, kcqe);
  3072. return;
  3073. }
  3074. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3075. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3076. cnic_cm_process_offld_pg(dev, l4kcqe);
  3077. return;
  3078. }
  3079. l5_cid = l4kcqe->conn_id;
  3080. if (opcode & 0x80)
  3081. l5_cid = l4kcqe->cid;
  3082. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3083. return;
  3084. csk = &cp->csk_tbl[l5_cid];
  3085. csk_hold(csk);
  3086. if (!cnic_in_use(csk)) {
  3087. csk_put(csk);
  3088. return;
  3089. }
  3090. switch (opcode) {
  3091. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3092. if (l4kcqe->status != 0) {
  3093. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3094. cnic_cm_upcall(cp, csk,
  3095. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3096. }
  3097. break;
  3098. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3099. if (l4kcqe->status == 0)
  3100. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3101. smp_mb__before_clear_bit();
  3102. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3103. cnic_cm_upcall(cp, csk, opcode);
  3104. break;
  3105. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3106. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3107. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3108. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3109. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3110. cp->close_conn(csk, opcode);
  3111. break;
  3112. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3113. cnic_cm_upcall(cp, csk, opcode);
  3114. break;
  3115. }
  3116. csk_put(csk);
  3117. }
  3118. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3119. {
  3120. struct cnic_dev *dev = data;
  3121. int i;
  3122. for (i = 0; i < num; i++)
  3123. cnic_cm_process_kcqe(dev, kcqe[i]);
  3124. }
  3125. static struct cnic_ulp_ops cm_ulp_ops = {
  3126. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3127. };
  3128. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3129. {
  3130. struct cnic_local *cp = dev->cnic_priv;
  3131. kfree(cp->csk_tbl);
  3132. cp->csk_tbl = NULL;
  3133. cnic_free_id_tbl(&cp->csk_port_tbl);
  3134. }
  3135. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3136. {
  3137. struct cnic_local *cp = dev->cnic_priv;
  3138. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3139. GFP_KERNEL);
  3140. if (!cp->csk_tbl)
  3141. return -ENOMEM;
  3142. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3143. CNIC_LOCAL_PORT_MIN)) {
  3144. cnic_cm_free_mem(dev);
  3145. return -ENOMEM;
  3146. }
  3147. return 0;
  3148. }
  3149. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3150. {
  3151. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3152. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3153. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3154. csk->state = opcode;
  3155. }
  3156. /* 1. If event opcode matches the expected event in csk->state
  3157. * 2. If the expected event is CLOSE_COMP, we accept any event
  3158. * 3. If the expected event is 0, meaning the connection was never
  3159. * never established, we accept the opcode from cm_abort.
  3160. */
  3161. if (opcode == csk->state || csk->state == 0 ||
  3162. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  3163. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3164. if (csk->state == 0)
  3165. csk->state = opcode;
  3166. return 1;
  3167. }
  3168. }
  3169. return 0;
  3170. }
  3171. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3172. {
  3173. struct cnic_dev *dev = csk->dev;
  3174. struct cnic_local *cp = dev->cnic_priv;
  3175. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3176. cnic_cm_upcall(cp, csk, opcode);
  3177. return;
  3178. }
  3179. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3180. cnic_close_conn(csk);
  3181. csk->state = opcode;
  3182. cnic_cm_upcall(cp, csk, opcode);
  3183. }
  3184. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3185. {
  3186. }
  3187. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3188. {
  3189. u32 seed;
  3190. get_random_bytes(&seed, 4);
  3191. cnic_ctx_wr(dev, 45, 0, seed);
  3192. return 0;
  3193. }
  3194. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3195. {
  3196. struct cnic_dev *dev = csk->dev;
  3197. struct cnic_local *cp = dev->cnic_priv;
  3198. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3199. union l5cm_specific_data l5_data;
  3200. u32 cmd = 0;
  3201. int close_complete = 0;
  3202. switch (opcode) {
  3203. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3204. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3205. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3206. if (cnic_ready_to_close(csk, opcode)) {
  3207. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3208. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3209. else
  3210. close_complete = 1;
  3211. }
  3212. break;
  3213. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3214. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3215. break;
  3216. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3217. close_complete = 1;
  3218. break;
  3219. }
  3220. if (cmd) {
  3221. memset(&l5_data, 0, sizeof(l5_data));
  3222. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3223. &l5_data);
  3224. } else if (close_complete) {
  3225. ctx->timestamp = jiffies;
  3226. cnic_close_conn(csk);
  3227. cnic_cm_upcall(cp, csk, csk->state);
  3228. }
  3229. }
  3230. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3231. {
  3232. struct cnic_local *cp = dev->cnic_priv;
  3233. int i;
  3234. if (!cp->ctx_tbl)
  3235. return;
  3236. if (!netif_running(dev->netdev))
  3237. return;
  3238. for (i = 0; i < cp->max_cid_space; i++) {
  3239. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3240. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3241. msleep(10);
  3242. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3243. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3244. ctx->cid);
  3245. }
  3246. cancel_delayed_work(&cp->delete_task);
  3247. flush_workqueue(cnic_wq);
  3248. if (atomic_read(&cp->iscsi_conn) != 0)
  3249. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3250. atomic_read(&cp->iscsi_conn));
  3251. }
  3252. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3253. {
  3254. struct cnic_local *cp = dev->cnic_priv;
  3255. u32 pfid = cp->pfid;
  3256. u32 port = CNIC_PORT(cp);
  3257. cnic_init_bnx2x_mac(dev);
  3258. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3259. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3260. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3261. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3262. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3263. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3264. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3265. DEF_MAX_DA_COUNT);
  3266. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3267. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3268. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3269. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3270. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3271. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3272. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3273. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3274. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3275. DEF_MAX_CWND);
  3276. return 0;
  3277. }
  3278. static void cnic_delete_task(struct work_struct *work)
  3279. {
  3280. struct cnic_local *cp;
  3281. struct cnic_dev *dev;
  3282. u32 i;
  3283. int need_resched = 0;
  3284. cp = container_of(work, struct cnic_local, delete_task.work);
  3285. dev = cp->dev;
  3286. for (i = 0; i < cp->max_cid_space; i++) {
  3287. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3288. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3289. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3290. continue;
  3291. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3292. need_resched = 1;
  3293. continue;
  3294. }
  3295. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3296. continue;
  3297. cnic_bnx2x_destroy_ramrod(dev, i);
  3298. cnic_free_bnx2x_conn_resc(dev, i);
  3299. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3300. atomic_dec(&cp->iscsi_conn);
  3301. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3302. }
  3303. if (need_resched)
  3304. queue_delayed_work(cnic_wq, &cp->delete_task,
  3305. msecs_to_jiffies(10));
  3306. }
  3307. static int cnic_cm_open(struct cnic_dev *dev)
  3308. {
  3309. struct cnic_local *cp = dev->cnic_priv;
  3310. int err;
  3311. err = cnic_cm_alloc_mem(dev);
  3312. if (err)
  3313. return err;
  3314. err = cp->start_cm(dev);
  3315. if (err)
  3316. goto err_out;
  3317. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3318. dev->cm_create = cnic_cm_create;
  3319. dev->cm_destroy = cnic_cm_destroy;
  3320. dev->cm_connect = cnic_cm_connect;
  3321. dev->cm_abort = cnic_cm_abort;
  3322. dev->cm_close = cnic_cm_close;
  3323. dev->cm_select_dev = cnic_cm_select_dev;
  3324. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3325. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3326. return 0;
  3327. err_out:
  3328. cnic_cm_free_mem(dev);
  3329. return err;
  3330. }
  3331. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3332. {
  3333. struct cnic_local *cp = dev->cnic_priv;
  3334. int i;
  3335. cp->stop_cm(dev);
  3336. if (!cp->csk_tbl)
  3337. return 0;
  3338. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3339. struct cnic_sock *csk = &cp->csk_tbl[i];
  3340. clear_bit(SK_F_INUSE, &csk->flags);
  3341. cnic_cm_cleanup(csk);
  3342. }
  3343. cnic_cm_free_mem(dev);
  3344. return 0;
  3345. }
  3346. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3347. {
  3348. u32 cid_addr;
  3349. int i;
  3350. cid_addr = GET_CID_ADDR(cid);
  3351. for (i = 0; i < CTX_SIZE; i += 4)
  3352. cnic_ctx_wr(dev, cid_addr, i, 0);
  3353. }
  3354. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3355. {
  3356. struct cnic_local *cp = dev->cnic_priv;
  3357. int ret = 0, i;
  3358. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3359. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3360. return 0;
  3361. for (i = 0; i < cp->ctx_blks; i++) {
  3362. int j;
  3363. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3364. u32 val;
  3365. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3366. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3367. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3368. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3369. (u64) cp->ctx_arr[i].mapping >> 32);
  3370. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3371. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3372. for (j = 0; j < 10; j++) {
  3373. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3374. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3375. break;
  3376. udelay(5);
  3377. }
  3378. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3379. ret = -EBUSY;
  3380. break;
  3381. }
  3382. }
  3383. return ret;
  3384. }
  3385. static void cnic_free_irq(struct cnic_dev *dev)
  3386. {
  3387. struct cnic_local *cp = dev->cnic_priv;
  3388. struct cnic_eth_dev *ethdev = cp->ethdev;
  3389. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3390. cp->disable_int_sync(dev);
  3391. tasklet_kill(&cp->cnic_irq_task);
  3392. free_irq(ethdev->irq_arr[0].vector, dev);
  3393. }
  3394. }
  3395. static int cnic_request_irq(struct cnic_dev *dev)
  3396. {
  3397. struct cnic_local *cp = dev->cnic_priv;
  3398. struct cnic_eth_dev *ethdev = cp->ethdev;
  3399. int err;
  3400. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3401. if (err)
  3402. tasklet_disable(&cp->cnic_irq_task);
  3403. return err;
  3404. }
  3405. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3406. {
  3407. struct cnic_local *cp = dev->cnic_priv;
  3408. struct cnic_eth_dev *ethdev = cp->ethdev;
  3409. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3410. int err, i = 0;
  3411. int sblk_num = cp->status_blk_num;
  3412. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3413. BNX2_HC_SB_CONFIG_1;
  3414. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3415. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3416. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3417. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3418. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3419. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3420. (unsigned long) dev);
  3421. err = cnic_request_irq(dev);
  3422. if (err)
  3423. return err;
  3424. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3425. i < 10) {
  3426. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3427. 1 << (11 + sblk_num));
  3428. udelay(10);
  3429. i++;
  3430. barrier();
  3431. }
  3432. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3433. cnic_free_irq(dev);
  3434. goto failed;
  3435. }
  3436. } else {
  3437. struct status_block *sblk = cp->status_blk.gen;
  3438. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3439. int i = 0;
  3440. while (sblk->status_completion_producer_index && i < 10) {
  3441. CNIC_WR(dev, BNX2_HC_COMMAND,
  3442. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3443. udelay(10);
  3444. i++;
  3445. barrier();
  3446. }
  3447. if (sblk->status_completion_producer_index)
  3448. goto failed;
  3449. }
  3450. return 0;
  3451. failed:
  3452. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3453. return -EBUSY;
  3454. }
  3455. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3456. {
  3457. struct cnic_local *cp = dev->cnic_priv;
  3458. struct cnic_eth_dev *ethdev = cp->ethdev;
  3459. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3460. return;
  3461. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3462. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3463. }
  3464. static void cnic_get_bnx2_iscsi_info(struct cnic_dev *dev)
  3465. {
  3466. u32 max_conn;
  3467. max_conn = cnic_reg_rd_ind(dev, BNX2_FW_MAX_ISCSI_CONN);
  3468. dev->max_iscsi_conn = max_conn;
  3469. }
  3470. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3471. {
  3472. struct cnic_local *cp = dev->cnic_priv;
  3473. struct cnic_eth_dev *ethdev = cp->ethdev;
  3474. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3475. return;
  3476. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3477. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3478. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3479. synchronize_irq(ethdev->irq_arr[0].vector);
  3480. }
  3481. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3482. {
  3483. struct cnic_local *cp = dev->cnic_priv;
  3484. struct cnic_eth_dev *ethdev = cp->ethdev;
  3485. struct cnic_uio_dev *udev = cp->udev;
  3486. u32 cid_addr, tx_cid, sb_id;
  3487. u32 val, offset0, offset1, offset2, offset3;
  3488. int i;
  3489. struct tx_bd *txbd;
  3490. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3491. struct status_block *s_blk = cp->status_blk.gen;
  3492. sb_id = cp->status_blk_num;
  3493. tx_cid = 20;
  3494. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3495. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3496. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3497. tx_cid = TX_TSS_CID + sb_id - 1;
  3498. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3499. (TX_TSS_CID << 7));
  3500. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3501. }
  3502. cp->tx_cons = *cp->tx_cons_ptr;
  3503. cid_addr = GET_CID_ADDR(tx_cid);
  3504. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3505. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3506. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3507. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3508. offset0 = BNX2_L2CTX_TYPE_XI;
  3509. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3510. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3511. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3512. } else {
  3513. cnic_init_context(dev, tx_cid);
  3514. cnic_init_context(dev, tx_cid + 1);
  3515. offset0 = BNX2_L2CTX_TYPE;
  3516. offset1 = BNX2_L2CTX_CMD_TYPE;
  3517. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3518. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3519. }
  3520. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3521. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3522. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3523. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3524. txbd = (struct tx_bd *) udev->l2_ring;
  3525. buf_map = udev->l2_buf_map;
  3526. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3527. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3528. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3529. }
  3530. val = (u64) ring_map >> 32;
  3531. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3532. txbd->tx_bd_haddr_hi = val;
  3533. val = (u64) ring_map & 0xffffffff;
  3534. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3535. txbd->tx_bd_haddr_lo = val;
  3536. }
  3537. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3538. {
  3539. struct cnic_local *cp = dev->cnic_priv;
  3540. struct cnic_eth_dev *ethdev = cp->ethdev;
  3541. struct cnic_uio_dev *udev = cp->udev;
  3542. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3543. int i;
  3544. struct rx_bd *rxbd;
  3545. struct status_block *s_blk = cp->status_blk.gen;
  3546. dma_addr_t ring_map = udev->l2_ring_map;
  3547. sb_id = cp->status_blk_num;
  3548. cnic_init_context(dev, 2);
  3549. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3550. coal_reg = BNX2_HC_COMMAND;
  3551. coal_val = CNIC_RD(dev, coal_reg);
  3552. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3553. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3554. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3555. coal_reg = BNX2_HC_COALESCE_NOW;
  3556. coal_val = 1 << (11 + sb_id);
  3557. }
  3558. i = 0;
  3559. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3560. CNIC_WR(dev, coal_reg, coal_val);
  3561. udelay(10);
  3562. i++;
  3563. barrier();
  3564. }
  3565. cp->rx_cons = *cp->rx_cons_ptr;
  3566. cid_addr = GET_CID_ADDR(2);
  3567. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3568. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3569. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3570. if (sb_id == 0)
  3571. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3572. else
  3573. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3574. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3575. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3576. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3577. dma_addr_t buf_map;
  3578. int n = (i % cp->l2_rx_ring_size) + 1;
  3579. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3580. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3581. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3582. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3583. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3584. }
  3585. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3586. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3587. rxbd->rx_bd_haddr_hi = val;
  3588. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3589. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3590. rxbd->rx_bd_haddr_lo = val;
  3591. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3592. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3593. }
  3594. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3595. {
  3596. struct kwqe *wqes[1], l2kwqe;
  3597. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3598. wqes[0] = &l2kwqe;
  3599. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3600. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3601. KWQE_OPCODE_SHIFT) | 2;
  3602. dev->submit_kwqes(dev, wqes, 1);
  3603. }
  3604. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3605. {
  3606. struct cnic_local *cp = dev->cnic_priv;
  3607. u32 val;
  3608. val = cp->func << 2;
  3609. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3610. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3611. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3612. dev->mac_addr[0] = (u8) (val >> 8);
  3613. dev->mac_addr[1] = (u8) val;
  3614. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3615. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3616. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3617. dev->mac_addr[2] = (u8) (val >> 24);
  3618. dev->mac_addr[3] = (u8) (val >> 16);
  3619. dev->mac_addr[4] = (u8) (val >> 8);
  3620. dev->mac_addr[5] = (u8) val;
  3621. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3622. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3623. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3624. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3625. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3626. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3627. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3628. }
  3629. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3630. {
  3631. struct cnic_local *cp = dev->cnic_priv;
  3632. struct cnic_eth_dev *ethdev = cp->ethdev;
  3633. struct status_block *sblk = cp->status_blk.gen;
  3634. u32 val, kcq_cid_addr, kwq_cid_addr;
  3635. int err;
  3636. cnic_set_bnx2_mac(dev);
  3637. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3638. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3639. if (BCM_PAGE_BITS > 12)
  3640. val |= (12 - 8) << 4;
  3641. else
  3642. val |= (BCM_PAGE_BITS - 8) << 4;
  3643. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3644. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3645. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3646. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3647. err = cnic_setup_5709_context(dev, 1);
  3648. if (err)
  3649. return err;
  3650. cnic_init_context(dev, KWQ_CID);
  3651. cnic_init_context(dev, KCQ_CID);
  3652. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3653. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3654. cp->max_kwq_idx = MAX_KWQ_IDX;
  3655. cp->kwq_prod_idx = 0;
  3656. cp->kwq_con_idx = 0;
  3657. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3658. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3659. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3660. else
  3661. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3662. /* Initialize the kernel work queue context. */
  3663. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3664. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3665. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3666. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3667. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3668. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3669. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3670. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3671. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3672. val = (u32) cp->kwq_info.pgtbl_map;
  3673. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3674. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3675. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3676. cp->kcq1.sw_prod_idx = 0;
  3677. cp->kcq1.hw_prod_idx_ptr =
  3678. (u16 *) &sblk->status_completion_producer_index;
  3679. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3680. /* Initialize the kernel complete queue context. */
  3681. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3682. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3683. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3684. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3685. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3686. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3687. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3688. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3689. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3690. val = (u32) cp->kcq1.dma.pgtbl_map;
  3691. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3692. cp->int_num = 0;
  3693. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3694. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3695. u32 sb_id = cp->status_blk_num;
  3696. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3697. cp->kcq1.hw_prod_idx_ptr =
  3698. (u16 *) &msblk->status_completion_producer_index;
  3699. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3700. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3701. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3702. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3703. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3704. }
  3705. /* Enable Commnad Scheduler notification when we write to the
  3706. * host producer index of the kernel contexts. */
  3707. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3708. /* Enable Command Scheduler notification when we write to either
  3709. * the Send Queue or Receive Queue producer indexes of the kernel
  3710. * bypass contexts. */
  3711. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3712. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3713. /* Notify COM when the driver post an application buffer. */
  3714. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3715. /* Set the CP and COM doorbells. These two processors polls the
  3716. * doorbell for a non zero value before running. This must be done
  3717. * after setting up the kernel queue contexts. */
  3718. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3719. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3720. cnic_init_bnx2_tx_ring(dev);
  3721. cnic_init_bnx2_rx_ring(dev);
  3722. err = cnic_init_bnx2_irq(dev);
  3723. if (err) {
  3724. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3725. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3726. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3727. return err;
  3728. }
  3729. cnic_get_bnx2_iscsi_info(dev);
  3730. return 0;
  3731. }
  3732. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3733. {
  3734. struct cnic_local *cp = dev->cnic_priv;
  3735. struct cnic_eth_dev *ethdev = cp->ethdev;
  3736. u32 start_offset = ethdev->ctx_tbl_offset;
  3737. int i;
  3738. for (i = 0; i < cp->ctx_blks; i++) {
  3739. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3740. dma_addr_t map = ctx->mapping;
  3741. if (cp->ctx_align) {
  3742. unsigned long mask = cp->ctx_align - 1;
  3743. map = (map + mask) & ~mask;
  3744. }
  3745. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3746. }
  3747. }
  3748. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3749. {
  3750. struct cnic_local *cp = dev->cnic_priv;
  3751. struct cnic_eth_dev *ethdev = cp->ethdev;
  3752. int err = 0;
  3753. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3754. (unsigned long) dev);
  3755. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3756. err = cnic_request_irq(dev);
  3757. return err;
  3758. }
  3759. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3760. u16 sb_id, u8 sb_index,
  3761. u8 disable)
  3762. {
  3763. u32 addr = BAR_CSTRORM_INTMEM +
  3764. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3765. offsetof(struct hc_status_block_data_e1x, index_data) +
  3766. sizeof(struct hc_index_data)*sb_index +
  3767. offsetof(struct hc_index_data, flags);
  3768. u16 flags = CNIC_RD16(dev, addr);
  3769. /* clear and set */
  3770. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3771. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3772. HC_INDEX_DATA_HC_ENABLED);
  3773. CNIC_WR16(dev, addr, flags);
  3774. }
  3775. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3776. {
  3777. struct cnic_local *cp = dev->cnic_priv;
  3778. u8 sb_id = cp->status_blk_num;
  3779. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3780. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3781. offsetof(struct hc_status_block_data_e1x, index_data) +
  3782. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3783. offsetof(struct hc_index_data, timeout), 64 / 12);
  3784. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3785. }
  3786. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3787. {
  3788. }
  3789. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3790. struct client_init_ramrod_data *data)
  3791. {
  3792. struct cnic_local *cp = dev->cnic_priv;
  3793. struct cnic_uio_dev *udev = cp->udev;
  3794. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3795. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3796. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3797. int port = CNIC_PORT(cp);
  3798. int i;
  3799. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3800. u32 val;
  3801. memset(txbd, 0, BCM_PAGE_SIZE);
  3802. buf_map = udev->l2_buf_map;
  3803. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3804. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3805. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3806. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3807. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3808. reg_bd->addr_hi = start_bd->addr_hi;
  3809. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3810. start_bd->nbytes = cpu_to_le16(0x10);
  3811. start_bd->nbd = cpu_to_le16(3);
  3812. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3813. start_bd->general_data = (UNICAST_ADDRESS <<
  3814. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3815. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3816. }
  3817. val = (u64) ring_map >> 32;
  3818. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3819. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3820. val = (u64) ring_map & 0xffffffff;
  3821. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3822. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3823. /* Other ramrod params */
  3824. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3825. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3826. /* reset xstorm per client statistics */
  3827. if (cli < MAX_STAT_COUNTER_ID) {
  3828. val = BAR_XSTRORM_INTMEM +
  3829. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3830. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3831. CNIC_WR(dev, val + i * 4, 0);
  3832. }
  3833. cp->tx_cons_ptr =
  3834. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3835. }
  3836. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3837. struct client_init_ramrod_data *data)
  3838. {
  3839. struct cnic_local *cp = dev->cnic_priv;
  3840. struct cnic_uio_dev *udev = cp->udev;
  3841. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3842. BCM_PAGE_SIZE);
  3843. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3844. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3845. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3846. int i;
  3847. int port = CNIC_PORT(cp);
  3848. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3849. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3850. u32 val;
  3851. dma_addr_t ring_map = udev->l2_ring_map;
  3852. /* General data */
  3853. data->general.client_id = cli;
  3854. data->general.statistics_en_flg = 1;
  3855. data->general.statistics_counter_id = cli;
  3856. data->general.activate_flg = 1;
  3857. data->general.sp_client_id = cli;
  3858. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3859. dma_addr_t buf_map;
  3860. int n = (i % cp->l2_rx_ring_size) + 1;
  3861. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3862. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3863. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3864. }
  3865. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3866. rxbd->addr_hi = cpu_to_le32(val);
  3867. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3868. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3869. rxbd->addr_lo = cpu_to_le32(val);
  3870. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3871. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3872. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3873. rxcqe->addr_hi = cpu_to_le32(val);
  3874. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3875. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3876. rxcqe->addr_lo = cpu_to_le32(val);
  3877. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3878. /* Other ramrod params */
  3879. data->rx.client_qzone_id = cl_qzone_id;
  3880. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3881. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3882. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3883. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3884. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3885. data->rx.outer_vlan_removal_enable_flg = 1;
  3886. /* reset tstorm and ustorm per client statistics */
  3887. if (cli < MAX_STAT_COUNTER_ID) {
  3888. val = BAR_TSTRORM_INTMEM +
  3889. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3890. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3891. CNIC_WR(dev, val + i * 4, 0);
  3892. val = BAR_USTRORM_INTMEM +
  3893. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3894. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3895. CNIC_WR(dev, val + i * 4, 0);
  3896. }
  3897. cp->rx_cons_ptr =
  3898. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3899. cp->rx_cons = *cp->rx_cons_ptr;
  3900. }
  3901. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3902. {
  3903. struct cnic_local *cp = dev->cnic_priv;
  3904. u32 pfid = cp->pfid;
  3905. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3906. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3907. cp->kcq1.sw_prod_idx = 0;
  3908. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3909. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3910. cp->kcq1.hw_prod_idx_ptr =
  3911. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3912. cp->kcq1.status_idx_ptr =
  3913. &sb->sb.running_index[SM_RX_ID];
  3914. } else {
  3915. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3916. cp->kcq1.hw_prod_idx_ptr =
  3917. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3918. cp->kcq1.status_idx_ptr =
  3919. &sb->sb.running_index[SM_RX_ID];
  3920. }
  3921. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3922. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3923. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3924. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3925. cp->kcq2.sw_prod_idx = 0;
  3926. cp->kcq2.hw_prod_idx_ptr =
  3927. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3928. cp->kcq2.status_idx_ptr =
  3929. &sb->sb.running_index[SM_RX_ID];
  3930. }
  3931. }
  3932. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3933. {
  3934. struct cnic_local *cp = dev->cnic_priv;
  3935. struct cnic_eth_dev *ethdev = cp->ethdev;
  3936. int func = CNIC_FUNC(cp), ret, i;
  3937. u32 pfid;
  3938. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3939. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3940. if (!(val & 1))
  3941. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3942. else
  3943. val = (val >> 1) & 1;
  3944. if (val)
  3945. cp->pfid = func >> 1;
  3946. else
  3947. cp->pfid = func & 0x6;
  3948. } else {
  3949. cp->pfid = func;
  3950. }
  3951. pfid = cp->pfid;
  3952. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3953. cp->iscsi_start_cid);
  3954. if (ret)
  3955. return -ENOMEM;
  3956. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3957. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3958. BNX2X_FCOE_NUM_CONNECTIONS,
  3959. cp->fcoe_start_cid);
  3960. if (ret)
  3961. return -ENOMEM;
  3962. }
  3963. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3964. cnic_init_bnx2x_kcq(dev);
  3965. /* Only 1 EQ */
  3966. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3967. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3968. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3969. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3970. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3971. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3972. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3973. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3974. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3975. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3976. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3977. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3978. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3979. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3980. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3981. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3982. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3983. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3984. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3985. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3986. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3987. HC_INDEX_ISCSI_EQ_CONS);
  3988. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3989. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3990. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3991. cp->conn_buf_info.pgtbl[2 * i]);
  3992. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3993. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3994. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3995. }
  3996. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3997. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3998. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3999. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4000. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4001. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4002. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4003. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4004. cnic_setup_bnx2x_context(dev);
  4005. ret = cnic_init_bnx2x_irq(dev);
  4006. if (ret)
  4007. return ret;
  4008. return 0;
  4009. }
  4010. static void cnic_init_rings(struct cnic_dev *dev)
  4011. {
  4012. struct cnic_local *cp = dev->cnic_priv;
  4013. struct cnic_uio_dev *udev = cp->udev;
  4014. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4015. return;
  4016. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4017. cnic_init_bnx2_tx_ring(dev);
  4018. cnic_init_bnx2_rx_ring(dev);
  4019. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4020. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4021. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4022. u32 cid = cp->ethdev->iscsi_l2_cid;
  4023. u32 cl_qzone_id;
  4024. struct client_init_ramrod_data *data;
  4025. union l5cm_specific_data l5_data;
  4026. struct ustorm_eth_rx_producers rx_prods = {0};
  4027. u32 off, i;
  4028. rx_prods.bd_prod = 0;
  4029. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4030. barrier();
  4031. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4032. off = BAR_USTRORM_INTMEM +
  4033. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4034. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4035. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4036. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4037. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4038. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4039. data = udev->l2_buf;
  4040. memset(data, 0, sizeof(*data));
  4041. cnic_init_bnx2x_tx_ring(dev, data);
  4042. cnic_init_bnx2x_rx_ring(dev, data);
  4043. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4044. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4045. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4046. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4047. cid, ETH_CONNECTION_TYPE, &l5_data);
  4048. i = 0;
  4049. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4050. ++i < 10)
  4051. msleep(1);
  4052. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4053. netdev_err(dev->netdev,
  4054. "iSCSI CLIENT_SETUP did not complete\n");
  4055. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4056. cnic_ring_ctl(dev, cid, cli, 1);
  4057. }
  4058. }
  4059. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4060. {
  4061. struct cnic_local *cp = dev->cnic_priv;
  4062. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4063. return;
  4064. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4065. cnic_shutdown_bnx2_rx_ring(dev);
  4066. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4067. struct cnic_local *cp = dev->cnic_priv;
  4068. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4069. u32 cid = cp->ethdev->iscsi_l2_cid;
  4070. union l5cm_specific_data l5_data;
  4071. int i;
  4072. cnic_ring_ctl(dev, cid, cli, 0);
  4073. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4074. l5_data.phy_address.lo = cli;
  4075. l5_data.phy_address.hi = 0;
  4076. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4077. cid, ETH_CONNECTION_TYPE, &l5_data);
  4078. i = 0;
  4079. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4080. ++i < 10)
  4081. msleep(1);
  4082. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4083. netdev_err(dev->netdev,
  4084. "iSCSI CLIENT_HALT did not complete\n");
  4085. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4086. memset(&l5_data, 0, sizeof(l5_data));
  4087. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4088. cid, NONE_CONNECTION_TYPE, &l5_data);
  4089. msleep(10);
  4090. }
  4091. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4092. }
  4093. static int cnic_register_netdev(struct cnic_dev *dev)
  4094. {
  4095. struct cnic_local *cp = dev->cnic_priv;
  4096. struct cnic_eth_dev *ethdev = cp->ethdev;
  4097. int err;
  4098. if (!ethdev)
  4099. return -ENODEV;
  4100. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4101. return 0;
  4102. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4103. if (err)
  4104. netdev_err(dev->netdev, "register_cnic failed\n");
  4105. return err;
  4106. }
  4107. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4108. {
  4109. struct cnic_local *cp = dev->cnic_priv;
  4110. struct cnic_eth_dev *ethdev = cp->ethdev;
  4111. if (!ethdev)
  4112. return;
  4113. ethdev->drv_unregister_cnic(dev->netdev);
  4114. }
  4115. static int cnic_start_hw(struct cnic_dev *dev)
  4116. {
  4117. struct cnic_local *cp = dev->cnic_priv;
  4118. struct cnic_eth_dev *ethdev = cp->ethdev;
  4119. int err;
  4120. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4121. return -EALREADY;
  4122. dev->regview = ethdev->io_base;
  4123. pci_dev_get(dev->pcidev);
  4124. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4125. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4126. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4127. err = cp->alloc_resc(dev);
  4128. if (err) {
  4129. netdev_err(dev->netdev, "allocate resource failure\n");
  4130. goto err1;
  4131. }
  4132. err = cp->start_hw(dev);
  4133. if (err)
  4134. goto err1;
  4135. err = cnic_cm_open(dev);
  4136. if (err)
  4137. goto err1;
  4138. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4139. cp->enable_int(dev);
  4140. return 0;
  4141. err1:
  4142. cp->free_resc(dev);
  4143. pci_dev_put(dev->pcidev);
  4144. return err;
  4145. }
  4146. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4147. {
  4148. cnic_disable_bnx2_int_sync(dev);
  4149. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4150. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4151. cnic_init_context(dev, KWQ_CID);
  4152. cnic_init_context(dev, KCQ_CID);
  4153. cnic_setup_5709_context(dev, 0);
  4154. cnic_free_irq(dev);
  4155. cnic_free_resc(dev);
  4156. }
  4157. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4158. {
  4159. struct cnic_local *cp = dev->cnic_priv;
  4160. cnic_free_irq(dev);
  4161. *cp->kcq1.hw_prod_idx_ptr = 0;
  4162. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4163. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4164. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4165. cnic_free_resc(dev);
  4166. }
  4167. static void cnic_stop_hw(struct cnic_dev *dev)
  4168. {
  4169. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4170. struct cnic_local *cp = dev->cnic_priv;
  4171. int i = 0;
  4172. /* Need to wait for the ring shutdown event to complete
  4173. * before clearing the CNIC_UP flag.
  4174. */
  4175. while (cp->udev->uio_dev != -1 && i < 15) {
  4176. msleep(100);
  4177. i++;
  4178. }
  4179. cnic_shutdown_rings(dev);
  4180. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4181. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4182. synchronize_rcu();
  4183. cnic_cm_shutdown(dev);
  4184. cp->stop_hw(dev);
  4185. pci_dev_put(dev->pcidev);
  4186. }
  4187. }
  4188. static void cnic_free_dev(struct cnic_dev *dev)
  4189. {
  4190. int i = 0;
  4191. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4192. msleep(100);
  4193. i++;
  4194. }
  4195. if (atomic_read(&dev->ref_count) != 0)
  4196. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4197. netdev_info(dev->netdev, "Removed CNIC device\n");
  4198. dev_put(dev->netdev);
  4199. kfree(dev);
  4200. }
  4201. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4202. struct pci_dev *pdev)
  4203. {
  4204. struct cnic_dev *cdev;
  4205. struct cnic_local *cp;
  4206. int alloc_size;
  4207. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4208. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4209. if (cdev == NULL) {
  4210. netdev_err(dev, "allocate dev struct failure\n");
  4211. return NULL;
  4212. }
  4213. cdev->netdev = dev;
  4214. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4215. cdev->register_device = cnic_register_device;
  4216. cdev->unregister_device = cnic_unregister_device;
  4217. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4218. cp = cdev->cnic_priv;
  4219. cp->dev = cdev;
  4220. cp->l2_single_buf_size = 0x400;
  4221. cp->l2_rx_ring_size = 3;
  4222. spin_lock_init(&cp->cnic_ulp_lock);
  4223. netdev_info(dev, "Added CNIC device\n");
  4224. return cdev;
  4225. }
  4226. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4227. {
  4228. struct pci_dev *pdev;
  4229. struct cnic_dev *cdev;
  4230. struct cnic_local *cp;
  4231. struct cnic_eth_dev *ethdev = NULL;
  4232. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4233. probe = symbol_get(bnx2_cnic_probe);
  4234. if (probe) {
  4235. ethdev = (*probe)(dev);
  4236. symbol_put(bnx2_cnic_probe);
  4237. }
  4238. if (!ethdev)
  4239. return NULL;
  4240. pdev = ethdev->pdev;
  4241. if (!pdev)
  4242. return NULL;
  4243. dev_hold(dev);
  4244. pci_dev_get(pdev);
  4245. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4246. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4247. (pdev->revision < 0x10)) {
  4248. pci_dev_put(pdev);
  4249. goto cnic_err;
  4250. }
  4251. pci_dev_put(pdev);
  4252. cdev = cnic_alloc_dev(dev, pdev);
  4253. if (cdev == NULL)
  4254. goto cnic_err;
  4255. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4256. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4257. cp = cdev->cnic_priv;
  4258. cp->ethdev = ethdev;
  4259. cdev->pcidev = pdev;
  4260. cp->chip_id = ethdev->chip_id;
  4261. cp->cnic_ops = &cnic_bnx2_ops;
  4262. cp->start_hw = cnic_start_bnx2_hw;
  4263. cp->stop_hw = cnic_stop_bnx2_hw;
  4264. cp->setup_pgtbl = cnic_setup_page_tbl;
  4265. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4266. cp->free_resc = cnic_free_resc;
  4267. cp->start_cm = cnic_cm_init_bnx2_hw;
  4268. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4269. cp->enable_int = cnic_enable_bnx2_int;
  4270. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4271. cp->close_conn = cnic_close_bnx2_conn;
  4272. cp->next_idx = cnic_bnx2_next_idx;
  4273. cp->hw_idx = cnic_bnx2_hw_idx;
  4274. return cdev;
  4275. cnic_err:
  4276. dev_put(dev);
  4277. return NULL;
  4278. }
  4279. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4280. {
  4281. struct pci_dev *pdev;
  4282. struct cnic_dev *cdev;
  4283. struct cnic_local *cp;
  4284. struct cnic_eth_dev *ethdev = NULL;
  4285. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4286. probe = symbol_get(bnx2x_cnic_probe);
  4287. if (probe) {
  4288. ethdev = (*probe)(dev);
  4289. symbol_put(bnx2x_cnic_probe);
  4290. }
  4291. if (!ethdev)
  4292. return NULL;
  4293. pdev = ethdev->pdev;
  4294. if (!pdev)
  4295. return NULL;
  4296. dev_hold(dev);
  4297. cdev = cnic_alloc_dev(dev, pdev);
  4298. if (cdev == NULL) {
  4299. dev_put(dev);
  4300. return NULL;
  4301. }
  4302. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4303. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4304. cp = cdev->cnic_priv;
  4305. cp->ethdev = ethdev;
  4306. cdev->pcidev = pdev;
  4307. cp->chip_id = ethdev->chip_id;
  4308. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4309. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4310. if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
  4311. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4312. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4313. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4314. cp->cnic_ops = &cnic_bnx2x_ops;
  4315. cp->start_hw = cnic_start_bnx2x_hw;
  4316. cp->stop_hw = cnic_stop_bnx2x_hw;
  4317. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4318. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4319. cp->free_resc = cnic_free_resc;
  4320. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4321. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4322. cp->enable_int = cnic_enable_bnx2x_int;
  4323. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4324. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  4325. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4326. else
  4327. cp->ack_int = cnic_ack_bnx2x_msix;
  4328. cp->close_conn = cnic_close_bnx2x_conn;
  4329. cp->next_idx = cnic_bnx2x_next_idx;
  4330. cp->hw_idx = cnic_bnx2x_hw_idx;
  4331. return cdev;
  4332. }
  4333. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4334. {
  4335. struct ethtool_drvinfo drvinfo;
  4336. struct cnic_dev *cdev = NULL;
  4337. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4338. memset(&drvinfo, 0, sizeof(drvinfo));
  4339. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4340. if (!strcmp(drvinfo.driver, "bnx2"))
  4341. cdev = init_bnx2_cnic(dev);
  4342. if (!strcmp(drvinfo.driver, "bnx2x"))
  4343. cdev = init_bnx2x_cnic(dev);
  4344. if (cdev) {
  4345. write_lock(&cnic_dev_lock);
  4346. list_add(&cdev->list, &cnic_dev_list);
  4347. write_unlock(&cnic_dev_lock);
  4348. }
  4349. }
  4350. return cdev;
  4351. }
  4352. /**
  4353. * netdev event handler
  4354. */
  4355. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4356. void *ptr)
  4357. {
  4358. struct net_device *netdev = ptr;
  4359. struct cnic_dev *dev;
  4360. int if_type;
  4361. int new_dev = 0;
  4362. dev = cnic_from_netdev(netdev);
  4363. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  4364. /* Check for the hot-plug device */
  4365. dev = is_cnic_dev(netdev);
  4366. if (dev) {
  4367. new_dev = 1;
  4368. cnic_hold(dev);
  4369. }
  4370. }
  4371. if (dev) {
  4372. struct cnic_local *cp = dev->cnic_priv;
  4373. if (new_dev)
  4374. cnic_ulp_init(dev);
  4375. else if (event == NETDEV_UNREGISTER)
  4376. cnic_ulp_exit(dev);
  4377. if (event == NETDEV_UP) {
  4378. if (cnic_register_netdev(dev) != 0) {
  4379. cnic_put(dev);
  4380. goto done;
  4381. }
  4382. if (!cnic_start_hw(dev))
  4383. cnic_ulp_start(dev);
  4384. }
  4385. rcu_read_lock();
  4386. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4387. struct cnic_ulp_ops *ulp_ops;
  4388. void *ctx;
  4389. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4390. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4391. continue;
  4392. ctx = cp->ulp_handle[if_type];
  4393. ulp_ops->indicate_netevent(ctx, event);
  4394. }
  4395. rcu_read_unlock();
  4396. if (event == NETDEV_GOING_DOWN) {
  4397. cnic_ulp_stop(dev);
  4398. cnic_stop_hw(dev);
  4399. cnic_unregister_netdev(dev);
  4400. } else if (event == NETDEV_UNREGISTER) {
  4401. write_lock(&cnic_dev_lock);
  4402. list_del_init(&dev->list);
  4403. write_unlock(&cnic_dev_lock);
  4404. cnic_put(dev);
  4405. cnic_free_dev(dev);
  4406. goto done;
  4407. }
  4408. cnic_put(dev);
  4409. }
  4410. done:
  4411. return NOTIFY_DONE;
  4412. }
  4413. static struct notifier_block cnic_netdev_notifier = {
  4414. .notifier_call = cnic_netdev_event
  4415. };
  4416. static void cnic_release(void)
  4417. {
  4418. struct cnic_dev *dev;
  4419. struct cnic_uio_dev *udev;
  4420. while (!list_empty(&cnic_dev_list)) {
  4421. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4422. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4423. cnic_ulp_stop(dev);
  4424. cnic_stop_hw(dev);
  4425. }
  4426. cnic_ulp_exit(dev);
  4427. cnic_unregister_netdev(dev);
  4428. list_del_init(&dev->list);
  4429. cnic_free_dev(dev);
  4430. }
  4431. while (!list_empty(&cnic_udev_list)) {
  4432. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4433. list);
  4434. cnic_free_uio(udev);
  4435. }
  4436. }
  4437. static int __init cnic_init(void)
  4438. {
  4439. int rc = 0;
  4440. pr_info("%s", version);
  4441. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4442. if (rc) {
  4443. cnic_release();
  4444. return rc;
  4445. }
  4446. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4447. if (!cnic_wq) {
  4448. cnic_release();
  4449. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4450. return -ENOMEM;
  4451. }
  4452. return 0;
  4453. }
  4454. static void __exit cnic_exit(void)
  4455. {
  4456. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4457. cnic_release();
  4458. destroy_workqueue(cnic_wq);
  4459. }
  4460. module_init(cnic_init);
  4461. module_exit(cnic_exit);