main.c 54 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_update_txpow(struct ath_softc *sc)
  20. {
  21. struct ath_hw *ah = sc->sc_ah;
  22. if (sc->curtxpow != sc->config.txpowlimit) {
  23. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
  24. /* read back in case value is clamped */
  25. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  26. }
  27. }
  28. static u8 parse_mpdudensity(u8 mpdudensity)
  29. {
  30. /*
  31. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  32. * 0 for no restriction
  33. * 1 for 1/4 us
  34. * 2 for 1/2 us
  35. * 3 for 1 us
  36. * 4 for 2 us
  37. * 5 for 4 us
  38. * 6 for 8 us
  39. * 7 for 16 us
  40. */
  41. switch (mpdudensity) {
  42. case 0:
  43. return 0;
  44. case 1:
  45. case 2:
  46. case 3:
  47. /* Our lower layer calculations limit our precision to
  48. 1 microsecond */
  49. return 1;
  50. case 4:
  51. return 2;
  52. case 5:
  53. return 4;
  54. case 6:
  55. return 8;
  56. case 7:
  57. return 16;
  58. default:
  59. return 0;
  60. }
  61. }
  62. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  63. struct ieee80211_hw *hw)
  64. {
  65. struct ieee80211_channel *curchan = hw->conf.channel;
  66. struct ath9k_channel *channel;
  67. u8 chan_idx;
  68. chan_idx = curchan->hw_value;
  69. channel = &sc->sc_ah->channels[chan_idx];
  70. ath9k_update_ichannel(sc, hw, channel);
  71. return channel;
  72. }
  73. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  74. {
  75. unsigned long flags;
  76. bool ret;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  79. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  80. return ret;
  81. }
  82. void ath9k_ps_wakeup(struct ath_softc *sc)
  83. {
  84. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  85. unsigned long flags;
  86. enum ath9k_power_mode power_mode;
  87. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  88. if (++sc->ps_usecount != 1)
  89. goto unlock;
  90. power_mode = sc->sc_ah->power_mode;
  91. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  92. /*
  93. * While the hardware is asleep, the cycle counters contain no
  94. * useful data. Better clear them now so that they don't mess up
  95. * survey data results.
  96. */
  97. if (power_mode != ATH9K_PM_AWAKE) {
  98. spin_lock(&common->cc_lock);
  99. ath_hw_cycle_counters_update(common);
  100. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  101. spin_unlock(&common->cc_lock);
  102. }
  103. unlock:
  104. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  105. }
  106. void ath9k_ps_restore(struct ath_softc *sc)
  107. {
  108. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  109. unsigned long flags;
  110. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  111. if (--sc->ps_usecount != 0)
  112. goto unlock;
  113. spin_lock(&common->cc_lock);
  114. ath_hw_cycle_counters_update(common);
  115. spin_unlock(&common->cc_lock);
  116. if (sc->ps_idle)
  117. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  118. else if (sc->ps_enabled &&
  119. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  120. PS_WAIT_FOR_CAB |
  121. PS_WAIT_FOR_PSPOLL_DATA |
  122. PS_WAIT_FOR_TX_ACK)))
  123. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  124. unlock:
  125. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  126. }
  127. static void ath_start_ani(struct ath_common *common)
  128. {
  129. struct ath_hw *ah = common->ah;
  130. unsigned long timestamp = jiffies_to_msecs(jiffies);
  131. struct ath_softc *sc = (struct ath_softc *) common->priv;
  132. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  133. return;
  134. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  135. return;
  136. common->ani.longcal_timer = timestamp;
  137. common->ani.shortcal_timer = timestamp;
  138. common->ani.checkani_timer = timestamp;
  139. mod_timer(&common->ani.timer,
  140. jiffies +
  141. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  142. }
  143. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  144. {
  145. struct ath_hw *ah = sc->sc_ah;
  146. struct ath9k_channel *chan = &ah->channels[channel];
  147. struct survey_info *survey = &sc->survey[channel];
  148. if (chan->noisefloor) {
  149. survey->filled |= SURVEY_INFO_NOISE_DBM;
  150. survey->noise = chan->noisefloor;
  151. }
  152. }
  153. static void ath_update_survey_stats(struct ath_softc *sc)
  154. {
  155. struct ath_hw *ah = sc->sc_ah;
  156. struct ath_common *common = ath9k_hw_common(ah);
  157. int pos = ah->curchan - &ah->channels[0];
  158. struct survey_info *survey = &sc->survey[pos];
  159. struct ath_cycle_counters *cc = &common->cc_survey;
  160. unsigned int div = common->clockrate * 1000;
  161. if (!ah->curchan)
  162. return;
  163. if (ah->power_mode == ATH9K_PM_AWAKE)
  164. ath_hw_cycle_counters_update(common);
  165. if (cc->cycles > 0) {
  166. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  167. SURVEY_INFO_CHANNEL_TIME_BUSY |
  168. SURVEY_INFO_CHANNEL_TIME_RX |
  169. SURVEY_INFO_CHANNEL_TIME_TX;
  170. survey->channel_time += cc->cycles / div;
  171. survey->channel_time_busy += cc->rx_busy / div;
  172. survey->channel_time_rx += cc->rx_frame / div;
  173. survey->channel_time_tx += cc->tx_frame / div;
  174. }
  175. memset(cc, 0, sizeof(*cc));
  176. ath_update_survey_nf(sc, pos);
  177. }
  178. /*
  179. * Set/change channels. If the channel is really being changed, it's done
  180. * by reseting the chip. To accomplish this we must first cleanup any pending
  181. * DMA, then restart stuff.
  182. */
  183. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  184. struct ath9k_channel *hchan)
  185. {
  186. struct ath_hw *ah = sc->sc_ah;
  187. struct ath_common *common = ath9k_hw_common(ah);
  188. struct ieee80211_conf *conf = &common->hw->conf;
  189. bool fastcc = true, stopped;
  190. struct ieee80211_channel *channel = hw->conf.channel;
  191. struct ath9k_hw_cal_data *caldata = NULL;
  192. int r;
  193. if (sc->sc_flags & SC_OP_INVALID)
  194. return -EIO;
  195. del_timer_sync(&common->ani.timer);
  196. cancel_work_sync(&sc->paprd_work);
  197. cancel_work_sync(&sc->hw_check_work);
  198. cancel_delayed_work_sync(&sc->tx_complete_work);
  199. ath9k_ps_wakeup(sc);
  200. spin_lock_bh(&sc->sc_pcu_lock);
  201. /*
  202. * This is only performed if the channel settings have
  203. * actually changed.
  204. *
  205. * To switch channels clear any pending DMA operations;
  206. * wait long enough for the RX fifo to drain, reset the
  207. * hardware at the new frequency, and then re-enable
  208. * the relevant bits of the h/w.
  209. */
  210. ath9k_hw_disable_interrupts(ah);
  211. stopped = ath_drain_all_txq(sc, false);
  212. if (!ath_stoprecv(sc))
  213. stopped = false;
  214. if (!ath9k_hw_check_alive(ah))
  215. stopped = false;
  216. /* XXX: do not flush receive queue here. We don't want
  217. * to flush data frames already in queue because of
  218. * changing channel. */
  219. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  220. fastcc = false;
  221. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  222. caldata = &sc->caldata;
  223. ath_dbg(common, ATH_DBG_CONFIG,
  224. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  225. sc->sc_ah->curchan->channel,
  226. channel->center_freq, conf_is_ht40(conf),
  227. fastcc);
  228. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  229. if (r) {
  230. ath_err(common,
  231. "Unable to reset channel (%u MHz), reset status %d\n",
  232. channel->center_freq, r);
  233. goto ps_restore;
  234. }
  235. if (ath_startrecv(sc) != 0) {
  236. ath_err(common, "Unable to restart recv logic\n");
  237. r = -EIO;
  238. goto ps_restore;
  239. }
  240. ath_update_txpow(sc);
  241. ath9k_hw_set_interrupts(ah, ah->imask);
  242. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  243. if (sc->sc_flags & SC_OP_BEACONS)
  244. ath_beacon_config(sc, NULL);
  245. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  246. ath_start_ani(common);
  247. }
  248. ps_restore:
  249. ieee80211_wake_queues(hw);
  250. spin_unlock_bh(&sc->sc_pcu_lock);
  251. ath9k_ps_restore(sc);
  252. return r;
  253. }
  254. static void ath_paprd_activate(struct ath_softc *sc)
  255. {
  256. struct ath_hw *ah = sc->sc_ah;
  257. struct ath9k_hw_cal_data *caldata = ah->caldata;
  258. struct ath_common *common = ath9k_hw_common(ah);
  259. int chain;
  260. if (!caldata || !caldata->paprd_done)
  261. return;
  262. ath9k_ps_wakeup(sc);
  263. ar9003_paprd_enable(ah, false);
  264. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  265. if (!(common->tx_chainmask & BIT(chain)))
  266. continue;
  267. ar9003_paprd_populate_single_table(ah, caldata, chain);
  268. }
  269. ar9003_paprd_enable(ah, true);
  270. ath9k_ps_restore(sc);
  271. }
  272. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  273. {
  274. struct ieee80211_hw *hw = sc->hw;
  275. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  276. struct ath_tx_control txctl;
  277. int time_left;
  278. memset(&txctl, 0, sizeof(txctl));
  279. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  280. memset(tx_info, 0, sizeof(*tx_info));
  281. tx_info->band = hw->conf.channel->band;
  282. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  283. tx_info->control.rates[0].idx = 0;
  284. tx_info->control.rates[0].count = 1;
  285. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  286. tx_info->control.rates[1].idx = -1;
  287. init_completion(&sc->paprd_complete);
  288. sc->paprd_pending = true;
  289. txctl.paprd = BIT(chain);
  290. if (ath_tx_start(hw, skb, &txctl) != 0)
  291. return false;
  292. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  293. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  294. sc->paprd_pending = false;
  295. if (!time_left)
  296. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
  297. "Timeout waiting for paprd training on TX chain %d\n",
  298. chain);
  299. return !!time_left;
  300. }
  301. void ath_paprd_calibrate(struct work_struct *work)
  302. {
  303. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  304. struct ieee80211_hw *hw = sc->hw;
  305. struct ath_hw *ah = sc->sc_ah;
  306. struct ieee80211_hdr *hdr;
  307. struct sk_buff *skb = NULL;
  308. struct ath9k_hw_cal_data *caldata = ah->caldata;
  309. struct ath_common *common = ath9k_hw_common(ah);
  310. int ftype;
  311. int chain_ok = 0;
  312. int chain;
  313. int len = 1800;
  314. if (!caldata)
  315. return;
  316. if (ar9003_paprd_init_table(ah) < 0)
  317. return;
  318. skb = alloc_skb(len, GFP_KERNEL);
  319. if (!skb)
  320. return;
  321. skb_put(skb, len);
  322. memset(skb->data, 0, len);
  323. hdr = (struct ieee80211_hdr *)skb->data;
  324. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  325. hdr->frame_control = cpu_to_le16(ftype);
  326. hdr->duration_id = cpu_to_le16(10);
  327. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  328. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  329. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  330. ath9k_ps_wakeup(sc);
  331. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  332. if (!(common->tx_chainmask & BIT(chain)))
  333. continue;
  334. chain_ok = 0;
  335. ath_dbg(common, ATH_DBG_CALIBRATE,
  336. "Sending PAPRD frame for thermal measurement "
  337. "on chain %d\n", chain);
  338. if (!ath_paprd_send_frame(sc, skb, chain))
  339. goto fail_paprd;
  340. ar9003_paprd_setup_gain_table(ah, chain);
  341. ath_dbg(common, ATH_DBG_CALIBRATE,
  342. "Sending PAPRD training frame on chain %d\n", chain);
  343. if (!ath_paprd_send_frame(sc, skb, chain))
  344. goto fail_paprd;
  345. if (!ar9003_paprd_is_done(ah))
  346. break;
  347. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  348. break;
  349. chain_ok = 1;
  350. }
  351. kfree_skb(skb);
  352. if (chain_ok) {
  353. caldata->paprd_done = true;
  354. ath_paprd_activate(sc);
  355. }
  356. fail_paprd:
  357. ath9k_ps_restore(sc);
  358. }
  359. /*
  360. * This routine performs the periodic noise floor calibration function
  361. * that is used to adjust and optimize the chip performance. This
  362. * takes environmental changes (location, temperature) into account.
  363. * When the task is complete, it reschedules itself depending on the
  364. * appropriate interval that was calculated.
  365. */
  366. void ath_ani_calibrate(unsigned long data)
  367. {
  368. struct ath_softc *sc = (struct ath_softc *)data;
  369. struct ath_hw *ah = sc->sc_ah;
  370. struct ath_common *common = ath9k_hw_common(ah);
  371. bool longcal = false;
  372. bool shortcal = false;
  373. bool aniflag = false;
  374. unsigned int timestamp = jiffies_to_msecs(jiffies);
  375. u32 cal_interval, short_cal_interval, long_cal_interval;
  376. unsigned long flags;
  377. if (ah->caldata && ah->caldata->nfcal_interference)
  378. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  379. else
  380. long_cal_interval = ATH_LONG_CALINTERVAL;
  381. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  382. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  383. /* Only calibrate if awake */
  384. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  385. goto set_timer;
  386. ath9k_ps_wakeup(sc);
  387. /* Long calibration runs independently of short calibration. */
  388. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  389. longcal = true;
  390. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  391. common->ani.longcal_timer = timestamp;
  392. }
  393. /* Short calibration applies only while caldone is false */
  394. if (!common->ani.caldone) {
  395. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  396. shortcal = true;
  397. ath_dbg(common, ATH_DBG_ANI,
  398. "shortcal @%lu\n", jiffies);
  399. common->ani.shortcal_timer = timestamp;
  400. common->ani.resetcal_timer = timestamp;
  401. }
  402. } else {
  403. if ((timestamp - common->ani.resetcal_timer) >=
  404. ATH_RESTART_CALINTERVAL) {
  405. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  406. if (common->ani.caldone)
  407. common->ani.resetcal_timer = timestamp;
  408. }
  409. }
  410. /* Verify whether we must check ANI */
  411. if ((timestamp - common->ani.checkani_timer) >=
  412. ah->config.ani_poll_interval) {
  413. aniflag = true;
  414. common->ani.checkani_timer = timestamp;
  415. }
  416. /* Skip all processing if there's nothing to do. */
  417. if (longcal || shortcal || aniflag) {
  418. /* Call ANI routine if necessary */
  419. if (aniflag) {
  420. spin_lock_irqsave(&common->cc_lock, flags);
  421. ath9k_hw_ani_monitor(ah, ah->curchan);
  422. ath_update_survey_stats(sc);
  423. spin_unlock_irqrestore(&common->cc_lock, flags);
  424. }
  425. /* Perform calibration if necessary */
  426. if (longcal || shortcal) {
  427. common->ani.caldone =
  428. ath9k_hw_calibrate(ah,
  429. ah->curchan,
  430. common->rx_chainmask,
  431. longcal);
  432. }
  433. }
  434. ath9k_ps_restore(sc);
  435. set_timer:
  436. /*
  437. * Set timer interval based on previous results.
  438. * The interval must be the shortest necessary to satisfy ANI,
  439. * short calibration and long calibration.
  440. */
  441. cal_interval = ATH_LONG_CALINTERVAL;
  442. if (sc->sc_ah->config.enable_ani)
  443. cal_interval = min(cal_interval,
  444. (u32)ah->config.ani_poll_interval);
  445. if (!common->ani.caldone)
  446. cal_interval = min(cal_interval, (u32)short_cal_interval);
  447. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  448. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  449. if (!ah->caldata->paprd_done)
  450. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  451. else if (!ah->paprd_table_write_done)
  452. ath_paprd_activate(sc);
  453. }
  454. }
  455. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  456. {
  457. struct ath_node *an;
  458. struct ath_hw *ah = sc->sc_ah;
  459. an = (struct ath_node *)sta->drv_priv;
  460. #ifdef CONFIG_ATH9K_DEBUGFS
  461. spin_lock(&sc->nodes_lock);
  462. list_add(&an->list, &sc->nodes);
  463. spin_unlock(&sc->nodes_lock);
  464. an->sta = sta;
  465. #endif
  466. if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
  467. sc->sc_flags |= SC_OP_ENABLE_APM;
  468. if (sc->sc_flags & SC_OP_TXAGGR) {
  469. ath_tx_node_init(sc, an);
  470. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  471. sta->ht_cap.ampdu_factor);
  472. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  473. }
  474. }
  475. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  476. {
  477. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  478. #ifdef CONFIG_ATH9K_DEBUGFS
  479. spin_lock(&sc->nodes_lock);
  480. list_del(&an->list);
  481. spin_unlock(&sc->nodes_lock);
  482. an->sta = NULL;
  483. #endif
  484. if (sc->sc_flags & SC_OP_TXAGGR)
  485. ath_tx_node_cleanup(sc, an);
  486. }
  487. void ath_hw_check(struct work_struct *work)
  488. {
  489. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  490. int i;
  491. ath9k_ps_wakeup(sc);
  492. for (i = 0; i < 3; i++) {
  493. if (ath9k_hw_check_alive(sc->sc_ah))
  494. goto out;
  495. msleep(1);
  496. }
  497. ath_reset(sc, true);
  498. out:
  499. ath9k_ps_restore(sc);
  500. }
  501. void ath9k_tasklet(unsigned long data)
  502. {
  503. struct ath_softc *sc = (struct ath_softc *)data;
  504. struct ath_hw *ah = sc->sc_ah;
  505. struct ath_common *common = ath9k_hw_common(ah);
  506. u32 status = sc->intrstatus;
  507. u32 rxmask;
  508. ath9k_ps_wakeup(sc);
  509. if (status & ATH9K_INT_FATAL) {
  510. ath_reset(sc, true);
  511. ath9k_ps_restore(sc);
  512. return;
  513. }
  514. spin_lock(&sc->sc_pcu_lock);
  515. /*
  516. * Only run the baseband hang check if beacons stop working in AP or
  517. * IBSS mode, because it has a high false positive rate. For station
  518. * mode it should not be necessary, since the upper layers will detect
  519. * this through a beacon miss automatically and the following channel
  520. * change will trigger a hardware reset anyway
  521. */
  522. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  523. !ath9k_hw_check_alive(ah))
  524. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  525. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  526. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  527. ATH9K_INT_RXORN);
  528. else
  529. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  530. if (status & rxmask) {
  531. /* Check for high priority Rx first */
  532. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  533. (status & ATH9K_INT_RXHP))
  534. ath_rx_tasklet(sc, 0, true);
  535. ath_rx_tasklet(sc, 0, false);
  536. }
  537. if (status & ATH9K_INT_TX) {
  538. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  539. ath_tx_edma_tasklet(sc);
  540. else
  541. ath_tx_tasklet(sc);
  542. }
  543. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  544. /*
  545. * TSF sync does not look correct; remain awake to sync with
  546. * the next Beacon.
  547. */
  548. ath_dbg(common, ATH_DBG_PS,
  549. "TSFOOR - Sync with next Beacon\n");
  550. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  551. }
  552. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  553. if (status & ATH9K_INT_GENTIMER)
  554. ath_gen_timer_isr(sc->sc_ah);
  555. /* re-enable hardware interrupt */
  556. ath9k_hw_enable_interrupts(ah);
  557. spin_unlock(&sc->sc_pcu_lock);
  558. ath9k_ps_restore(sc);
  559. }
  560. irqreturn_t ath_isr(int irq, void *dev)
  561. {
  562. #define SCHED_INTR ( \
  563. ATH9K_INT_FATAL | \
  564. ATH9K_INT_RXORN | \
  565. ATH9K_INT_RXEOL | \
  566. ATH9K_INT_RX | \
  567. ATH9K_INT_RXLP | \
  568. ATH9K_INT_RXHP | \
  569. ATH9K_INT_TX | \
  570. ATH9K_INT_BMISS | \
  571. ATH9K_INT_CST | \
  572. ATH9K_INT_TSFOOR | \
  573. ATH9K_INT_GENTIMER)
  574. struct ath_softc *sc = dev;
  575. struct ath_hw *ah = sc->sc_ah;
  576. struct ath_common *common = ath9k_hw_common(ah);
  577. enum ath9k_int status;
  578. bool sched = false;
  579. /*
  580. * The hardware is not ready/present, don't
  581. * touch anything. Note this can happen early
  582. * on if the IRQ is shared.
  583. */
  584. if (sc->sc_flags & SC_OP_INVALID)
  585. return IRQ_NONE;
  586. /* shared irq, not for us */
  587. if (!ath9k_hw_intrpend(ah))
  588. return IRQ_NONE;
  589. /*
  590. * Figure out the reason(s) for the interrupt. Note
  591. * that the hal returns a pseudo-ISR that may include
  592. * bits we haven't explicitly enabled so we mask the
  593. * value to insure we only process bits we requested.
  594. */
  595. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  596. status &= ah->imask; /* discard unasked-for bits */
  597. /*
  598. * If there are no status bits set, then this interrupt was not
  599. * for me (should have been caught above).
  600. */
  601. if (!status)
  602. return IRQ_NONE;
  603. /* Cache the status */
  604. sc->intrstatus = status;
  605. if (status & SCHED_INTR)
  606. sched = true;
  607. /*
  608. * If a FATAL or RXORN interrupt is received, we have to reset the
  609. * chip immediately.
  610. */
  611. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  612. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  613. goto chip_reset;
  614. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  615. (status & ATH9K_INT_BB_WATCHDOG)) {
  616. spin_lock(&common->cc_lock);
  617. ath_hw_cycle_counters_update(common);
  618. ar9003_hw_bb_watchdog_dbg_info(ah);
  619. spin_unlock(&common->cc_lock);
  620. goto chip_reset;
  621. }
  622. if (status & ATH9K_INT_SWBA)
  623. tasklet_schedule(&sc->bcon_tasklet);
  624. if (status & ATH9K_INT_TXURN)
  625. ath9k_hw_updatetxtriglevel(ah, true);
  626. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  627. if (status & ATH9K_INT_RXEOL) {
  628. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  629. ath9k_hw_set_interrupts(ah, ah->imask);
  630. }
  631. }
  632. if (status & ATH9K_INT_MIB) {
  633. /*
  634. * Disable interrupts until we service the MIB
  635. * interrupt; otherwise it will continue to
  636. * fire.
  637. */
  638. ath9k_hw_disable_interrupts(ah);
  639. /*
  640. * Let the hal handle the event. We assume
  641. * it will clear whatever condition caused
  642. * the interrupt.
  643. */
  644. spin_lock(&common->cc_lock);
  645. ath9k_hw_proc_mib_event(ah);
  646. spin_unlock(&common->cc_lock);
  647. ath9k_hw_enable_interrupts(ah);
  648. }
  649. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  650. if (status & ATH9K_INT_TIM_TIMER) {
  651. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  652. goto chip_reset;
  653. /* Clear RxAbort bit so that we can
  654. * receive frames */
  655. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  656. ath9k_hw_setrxabort(sc->sc_ah, 0);
  657. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  658. }
  659. chip_reset:
  660. ath_debug_stat_interrupt(sc, status);
  661. if (sched) {
  662. /* turn off every interrupt */
  663. ath9k_hw_disable_interrupts(ah);
  664. tasklet_schedule(&sc->intr_tq);
  665. }
  666. return IRQ_HANDLED;
  667. #undef SCHED_INTR
  668. }
  669. static u32 ath_get_extchanmode(struct ath_softc *sc,
  670. struct ieee80211_channel *chan,
  671. enum nl80211_channel_type channel_type)
  672. {
  673. u32 chanmode = 0;
  674. switch (chan->band) {
  675. case IEEE80211_BAND_2GHZ:
  676. switch(channel_type) {
  677. case NL80211_CHAN_NO_HT:
  678. case NL80211_CHAN_HT20:
  679. chanmode = CHANNEL_G_HT20;
  680. break;
  681. case NL80211_CHAN_HT40PLUS:
  682. chanmode = CHANNEL_G_HT40PLUS;
  683. break;
  684. case NL80211_CHAN_HT40MINUS:
  685. chanmode = CHANNEL_G_HT40MINUS;
  686. break;
  687. }
  688. break;
  689. case IEEE80211_BAND_5GHZ:
  690. switch(channel_type) {
  691. case NL80211_CHAN_NO_HT:
  692. case NL80211_CHAN_HT20:
  693. chanmode = CHANNEL_A_HT20;
  694. break;
  695. case NL80211_CHAN_HT40PLUS:
  696. chanmode = CHANNEL_A_HT40PLUS;
  697. break;
  698. case NL80211_CHAN_HT40MINUS:
  699. chanmode = CHANNEL_A_HT40MINUS;
  700. break;
  701. }
  702. break;
  703. default:
  704. break;
  705. }
  706. return chanmode;
  707. }
  708. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  709. struct ieee80211_hw *hw,
  710. struct ieee80211_vif *vif,
  711. struct ieee80211_bss_conf *bss_conf)
  712. {
  713. struct ath_hw *ah = sc->sc_ah;
  714. struct ath_common *common = ath9k_hw_common(ah);
  715. if (bss_conf->assoc) {
  716. ath_dbg(common, ATH_DBG_CONFIG,
  717. "Bss Info ASSOC %d, bssid: %pM\n",
  718. bss_conf->aid, common->curbssid);
  719. /* New association, store aid */
  720. common->curaid = bss_conf->aid;
  721. ath9k_hw_write_associd(ah);
  722. /*
  723. * Request a re-configuration of Beacon related timers
  724. * on the receipt of the first Beacon frame (i.e.,
  725. * after time sync with the AP).
  726. */
  727. sc->ps_flags |= PS_BEACON_SYNC;
  728. /* Configure the beacon */
  729. ath_beacon_config(sc, vif);
  730. /* Reset rssi stats */
  731. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  732. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  733. sc->sc_flags |= SC_OP_ANI_RUN;
  734. ath_start_ani(common);
  735. } else {
  736. ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  737. common->curaid = 0;
  738. /* Stop ANI */
  739. sc->sc_flags &= ~SC_OP_ANI_RUN;
  740. del_timer_sync(&common->ani.timer);
  741. }
  742. }
  743. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  744. {
  745. struct ath_hw *ah = sc->sc_ah;
  746. struct ath_common *common = ath9k_hw_common(ah);
  747. struct ieee80211_channel *channel = hw->conf.channel;
  748. int r;
  749. ath9k_ps_wakeup(sc);
  750. spin_lock_bh(&sc->sc_pcu_lock);
  751. ath9k_hw_configpcipowersave(ah, 0, 0);
  752. if (!ah->curchan)
  753. ah->curchan = ath_get_curchannel(sc, sc->hw);
  754. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  755. if (r) {
  756. ath_err(common,
  757. "Unable to reset channel (%u MHz), reset status %d\n",
  758. channel->center_freq, r);
  759. }
  760. ath_update_txpow(sc);
  761. if (ath_startrecv(sc) != 0) {
  762. ath_err(common, "Unable to restart recv logic\n");
  763. goto out;
  764. }
  765. if (sc->sc_flags & SC_OP_BEACONS)
  766. ath_beacon_config(sc, NULL); /* restart beacons */
  767. /* Re-Enable interrupts */
  768. ath9k_hw_set_interrupts(ah, ah->imask);
  769. /* Enable LED */
  770. ath9k_hw_cfg_output(ah, ah->led_pin,
  771. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  772. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  773. ieee80211_wake_queues(hw);
  774. out:
  775. spin_unlock_bh(&sc->sc_pcu_lock);
  776. ath9k_ps_restore(sc);
  777. }
  778. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  779. {
  780. struct ath_hw *ah = sc->sc_ah;
  781. struct ieee80211_channel *channel = hw->conf.channel;
  782. int r;
  783. ath9k_ps_wakeup(sc);
  784. spin_lock_bh(&sc->sc_pcu_lock);
  785. ieee80211_stop_queues(hw);
  786. /*
  787. * Keep the LED on when the radio is disabled
  788. * during idle unassociated state.
  789. */
  790. if (!sc->ps_idle) {
  791. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  792. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  793. }
  794. /* Disable interrupts */
  795. ath9k_hw_disable_interrupts(ah);
  796. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  797. ath_stoprecv(sc); /* turn off frame recv */
  798. ath_flushrecv(sc); /* flush recv queue */
  799. if (!ah->curchan)
  800. ah->curchan = ath_get_curchannel(sc, hw);
  801. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  802. if (r) {
  803. ath_err(ath9k_hw_common(sc->sc_ah),
  804. "Unable to reset channel (%u MHz), reset status %d\n",
  805. channel->center_freq, r);
  806. }
  807. ath9k_hw_phy_disable(ah);
  808. ath9k_hw_configpcipowersave(ah, 1, 1);
  809. spin_unlock_bh(&sc->sc_pcu_lock);
  810. ath9k_ps_restore(sc);
  811. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  812. }
  813. int ath_reset(struct ath_softc *sc, bool retry_tx)
  814. {
  815. struct ath_hw *ah = sc->sc_ah;
  816. struct ath_common *common = ath9k_hw_common(ah);
  817. struct ieee80211_hw *hw = sc->hw;
  818. int r;
  819. /* Stop ANI */
  820. del_timer_sync(&common->ani.timer);
  821. spin_lock_bh(&sc->sc_pcu_lock);
  822. ieee80211_stop_queues(hw);
  823. ath9k_hw_disable_interrupts(ah);
  824. ath_drain_all_txq(sc, retry_tx);
  825. ath_stoprecv(sc);
  826. ath_flushrecv(sc);
  827. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  828. if (r)
  829. ath_err(common,
  830. "Unable to reset hardware; reset status %d\n", r);
  831. if (ath_startrecv(sc) != 0)
  832. ath_err(common, "Unable to start recv logic\n");
  833. /*
  834. * We may be doing a reset in response to a request
  835. * that changes the channel so update any state that
  836. * might change as a result.
  837. */
  838. ath_update_txpow(sc);
  839. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  840. ath_beacon_config(sc, NULL); /* restart beacons */
  841. ath9k_hw_set_interrupts(ah, ah->imask);
  842. if (retry_tx) {
  843. int i;
  844. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  845. if (ATH_TXQ_SETUP(sc, i)) {
  846. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  847. ath_txq_schedule(sc, &sc->tx.txq[i]);
  848. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  849. }
  850. }
  851. }
  852. ieee80211_wake_queues(hw);
  853. spin_unlock_bh(&sc->sc_pcu_lock);
  854. /* Start ANI */
  855. ath_start_ani(common);
  856. return r;
  857. }
  858. /* XXX: Remove me once we don't depend on ath9k_channel for all
  859. * this redundant data */
  860. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  861. struct ath9k_channel *ichan)
  862. {
  863. struct ieee80211_channel *chan = hw->conf.channel;
  864. struct ieee80211_conf *conf = &hw->conf;
  865. ichan->channel = chan->center_freq;
  866. ichan->chan = chan;
  867. if (chan->band == IEEE80211_BAND_2GHZ) {
  868. ichan->chanmode = CHANNEL_G;
  869. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  870. } else {
  871. ichan->chanmode = CHANNEL_A;
  872. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  873. }
  874. if (conf_is_ht(conf))
  875. ichan->chanmode = ath_get_extchanmode(sc, chan,
  876. conf->channel_type);
  877. }
  878. /**********************/
  879. /* mac80211 callbacks */
  880. /**********************/
  881. static int ath9k_start(struct ieee80211_hw *hw)
  882. {
  883. struct ath_softc *sc = hw->priv;
  884. struct ath_hw *ah = sc->sc_ah;
  885. struct ath_common *common = ath9k_hw_common(ah);
  886. struct ieee80211_channel *curchan = hw->conf.channel;
  887. struct ath9k_channel *init_channel;
  888. int r;
  889. ath_dbg(common, ATH_DBG_CONFIG,
  890. "Starting driver with initial channel: %d MHz\n",
  891. curchan->center_freq);
  892. mutex_lock(&sc->mutex);
  893. /* setup initial channel */
  894. sc->chan_idx = curchan->hw_value;
  895. init_channel = ath_get_curchannel(sc, hw);
  896. /* Reset SERDES registers */
  897. ath9k_hw_configpcipowersave(ah, 0, 0);
  898. /*
  899. * The basic interface to setting the hardware in a good
  900. * state is ``reset''. On return the hardware is known to
  901. * be powered up and with interrupts disabled. This must
  902. * be followed by initialization of the appropriate bits
  903. * and then setup of the interrupt mask.
  904. */
  905. spin_lock_bh(&sc->sc_pcu_lock);
  906. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  907. if (r) {
  908. ath_err(common,
  909. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  910. r, curchan->center_freq);
  911. spin_unlock_bh(&sc->sc_pcu_lock);
  912. goto mutex_unlock;
  913. }
  914. /*
  915. * This is needed only to setup initial state
  916. * but it's best done after a reset.
  917. */
  918. ath_update_txpow(sc);
  919. /*
  920. * Setup the hardware after reset:
  921. * The receive engine is set going.
  922. * Frame transmit is handled entirely
  923. * in the frame output path; there's nothing to do
  924. * here except setup the interrupt mask.
  925. */
  926. if (ath_startrecv(sc) != 0) {
  927. ath_err(common, "Unable to start recv logic\n");
  928. r = -EIO;
  929. spin_unlock_bh(&sc->sc_pcu_lock);
  930. goto mutex_unlock;
  931. }
  932. spin_unlock_bh(&sc->sc_pcu_lock);
  933. /* Setup our intr mask. */
  934. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  935. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  936. ATH9K_INT_GLOBAL;
  937. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  938. ah->imask |= ATH9K_INT_RXHP |
  939. ATH9K_INT_RXLP |
  940. ATH9K_INT_BB_WATCHDOG;
  941. else
  942. ah->imask |= ATH9K_INT_RX;
  943. ah->imask |= ATH9K_INT_GTT;
  944. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  945. ah->imask |= ATH9K_INT_CST;
  946. sc->sc_flags &= ~SC_OP_INVALID;
  947. sc->sc_ah->is_monitoring = false;
  948. /* Disable BMISS interrupt when we're not associated */
  949. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  950. ath9k_hw_set_interrupts(ah, ah->imask);
  951. ieee80211_wake_queues(hw);
  952. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  953. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  954. !ah->btcoex_hw.enabled) {
  955. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  956. AR_STOMP_LOW_WLAN_WGHT);
  957. ath9k_hw_btcoex_enable(ah);
  958. if (common->bus_ops->bt_coex_prep)
  959. common->bus_ops->bt_coex_prep(common);
  960. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  961. ath9k_btcoex_timer_resume(sc);
  962. }
  963. /* User has the option to provide pm-qos value as a module
  964. * parameter rather than using the default value of
  965. * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
  966. */
  967. pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
  968. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  969. common->bus_ops->extn_synch_en(common);
  970. mutex_unlock:
  971. mutex_unlock(&sc->mutex);
  972. return r;
  973. }
  974. static int ath9k_tx(struct ieee80211_hw *hw,
  975. struct sk_buff *skb)
  976. {
  977. struct ath_softc *sc = hw->priv;
  978. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  979. struct ath_tx_control txctl;
  980. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  981. if (sc->ps_enabled) {
  982. /*
  983. * mac80211 does not set PM field for normal data frames, so we
  984. * need to update that based on the current PS mode.
  985. */
  986. if (ieee80211_is_data(hdr->frame_control) &&
  987. !ieee80211_is_nullfunc(hdr->frame_control) &&
  988. !ieee80211_has_pm(hdr->frame_control)) {
  989. ath_dbg(common, ATH_DBG_PS,
  990. "Add PM=1 for a TX frame while in PS mode\n");
  991. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  992. }
  993. }
  994. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  995. /*
  996. * We are using PS-Poll and mac80211 can request TX while in
  997. * power save mode. Need to wake up hardware for the TX to be
  998. * completed and if needed, also for RX of buffered frames.
  999. */
  1000. ath9k_ps_wakeup(sc);
  1001. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  1002. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1003. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1004. ath_dbg(common, ATH_DBG_PS,
  1005. "Sending PS-Poll to pick a buffered frame\n");
  1006. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1007. } else {
  1008. ath_dbg(common, ATH_DBG_PS,
  1009. "Wake up to complete TX\n");
  1010. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1011. }
  1012. /*
  1013. * The actual restore operation will happen only after
  1014. * the sc_flags bit is cleared. We are just dropping
  1015. * the ps_usecount here.
  1016. */
  1017. ath9k_ps_restore(sc);
  1018. }
  1019. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1020. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  1021. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1022. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1023. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  1024. goto exit;
  1025. }
  1026. return 0;
  1027. exit:
  1028. dev_kfree_skb_any(skb);
  1029. return 0;
  1030. }
  1031. static void ath9k_stop(struct ieee80211_hw *hw)
  1032. {
  1033. struct ath_softc *sc = hw->priv;
  1034. struct ath_hw *ah = sc->sc_ah;
  1035. struct ath_common *common = ath9k_hw_common(ah);
  1036. mutex_lock(&sc->mutex);
  1037. if (led_blink)
  1038. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1039. cancel_delayed_work_sync(&sc->tx_complete_work);
  1040. cancel_work_sync(&sc->paprd_work);
  1041. cancel_work_sync(&sc->hw_check_work);
  1042. if (sc->sc_flags & SC_OP_INVALID) {
  1043. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  1044. mutex_unlock(&sc->mutex);
  1045. return;
  1046. }
  1047. /* Ensure HW is awake when we try to shut it down. */
  1048. ath9k_ps_wakeup(sc);
  1049. if (ah->btcoex_hw.enabled) {
  1050. ath9k_hw_btcoex_disable(ah);
  1051. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1052. ath9k_btcoex_timer_pause(sc);
  1053. }
  1054. spin_lock_bh(&sc->sc_pcu_lock);
  1055. /* make sure h/w will not generate any interrupt
  1056. * before setting the invalid flag. */
  1057. ath9k_hw_disable_interrupts(ah);
  1058. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1059. ath_drain_all_txq(sc, false);
  1060. ath_stoprecv(sc);
  1061. ath9k_hw_phy_disable(ah);
  1062. } else
  1063. sc->rx.rxlink = NULL;
  1064. if (sc->rx.frag) {
  1065. dev_kfree_skb_any(sc->rx.frag);
  1066. sc->rx.frag = NULL;
  1067. }
  1068. /* disable HAL and put h/w to sleep */
  1069. ath9k_hw_disable(ah);
  1070. ath9k_hw_configpcipowersave(ah, 1, 1);
  1071. spin_unlock_bh(&sc->sc_pcu_lock);
  1072. ath9k_ps_restore(sc);
  1073. sc->ps_idle = true;
  1074. ath_radio_disable(sc, hw);
  1075. sc->sc_flags |= SC_OP_INVALID;
  1076. pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
  1077. mutex_unlock(&sc->mutex);
  1078. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1079. }
  1080. bool ath9k_uses_beacons(int type)
  1081. {
  1082. switch (type) {
  1083. case NL80211_IFTYPE_AP:
  1084. case NL80211_IFTYPE_ADHOC:
  1085. case NL80211_IFTYPE_MESH_POINT:
  1086. return true;
  1087. default:
  1088. return false;
  1089. }
  1090. }
  1091. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1092. struct ieee80211_vif *vif)
  1093. {
  1094. struct ath_vif *avp = (void *)vif->drv_priv;
  1095. /* Disable SWBA interrupt */
  1096. sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
  1097. ath9k_ps_wakeup(sc);
  1098. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1099. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1100. tasklet_kill(&sc->bcon_tasklet);
  1101. ath9k_ps_restore(sc);
  1102. ath_beacon_return(sc, avp);
  1103. sc->sc_flags &= ~SC_OP_BEACONS;
  1104. if (sc->nbcnvifs > 0) {
  1105. /* Re-enable beaconing */
  1106. sc->sc_ah->imask |= ATH9K_INT_SWBA;
  1107. ath9k_ps_wakeup(sc);
  1108. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1109. ath9k_ps_restore(sc);
  1110. }
  1111. }
  1112. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1113. {
  1114. struct ath9k_vif_iter_data *iter_data = data;
  1115. int i;
  1116. if (iter_data->hw_macaddr)
  1117. for (i = 0; i < ETH_ALEN; i++)
  1118. iter_data->mask[i] &=
  1119. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1120. switch (vif->type) {
  1121. case NL80211_IFTYPE_AP:
  1122. iter_data->naps++;
  1123. break;
  1124. case NL80211_IFTYPE_STATION:
  1125. iter_data->nstations++;
  1126. break;
  1127. case NL80211_IFTYPE_ADHOC:
  1128. iter_data->nadhocs++;
  1129. break;
  1130. case NL80211_IFTYPE_MESH_POINT:
  1131. iter_data->nmeshes++;
  1132. break;
  1133. case NL80211_IFTYPE_WDS:
  1134. iter_data->nwds++;
  1135. break;
  1136. default:
  1137. iter_data->nothers++;
  1138. break;
  1139. }
  1140. }
  1141. /* Called with sc->mutex held. */
  1142. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1143. struct ieee80211_vif *vif,
  1144. struct ath9k_vif_iter_data *iter_data)
  1145. {
  1146. struct ath_softc *sc = hw->priv;
  1147. struct ath_hw *ah = sc->sc_ah;
  1148. struct ath_common *common = ath9k_hw_common(ah);
  1149. /*
  1150. * Use the hardware MAC address as reference, the hardware uses it
  1151. * together with the BSSID mask when matching addresses.
  1152. */
  1153. memset(iter_data, 0, sizeof(*iter_data));
  1154. iter_data->hw_macaddr = common->macaddr;
  1155. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1156. if (vif)
  1157. ath9k_vif_iter(iter_data, vif->addr, vif);
  1158. /* Get list of all active MAC addresses */
  1159. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1160. iter_data);
  1161. }
  1162. /* Called with sc->mutex held. */
  1163. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1164. struct ieee80211_vif *vif)
  1165. {
  1166. struct ath_softc *sc = hw->priv;
  1167. struct ath_hw *ah = sc->sc_ah;
  1168. struct ath_common *common = ath9k_hw_common(ah);
  1169. struct ath9k_vif_iter_data iter_data;
  1170. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1171. /* Set BSSID mask. */
  1172. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1173. ath_hw_setbssidmask(common);
  1174. /* Set op-mode & TSF */
  1175. if (iter_data.naps > 0) {
  1176. ath9k_hw_set_tsfadjust(ah, 1);
  1177. sc->sc_flags |= SC_OP_TSF_RESET;
  1178. ah->opmode = NL80211_IFTYPE_AP;
  1179. } else {
  1180. ath9k_hw_set_tsfadjust(ah, 0);
  1181. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1182. if (iter_data.nwds + iter_data.nmeshes)
  1183. ah->opmode = NL80211_IFTYPE_AP;
  1184. else if (iter_data.nadhocs)
  1185. ah->opmode = NL80211_IFTYPE_ADHOC;
  1186. else
  1187. ah->opmode = NL80211_IFTYPE_STATION;
  1188. }
  1189. /*
  1190. * Enable MIB interrupts when there are hardware phy counters.
  1191. */
  1192. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1193. if (ah->config.enable_ani)
  1194. ah->imask |= ATH9K_INT_MIB;
  1195. ah->imask |= ATH9K_INT_TSFOOR;
  1196. } else {
  1197. ah->imask &= ~ATH9K_INT_MIB;
  1198. ah->imask &= ~ATH9K_INT_TSFOOR;
  1199. }
  1200. ath9k_hw_set_interrupts(ah, ah->imask);
  1201. /* Set up ANI */
  1202. if ((iter_data.naps + iter_data.nadhocs) > 0) {
  1203. sc->sc_flags |= SC_OP_ANI_RUN;
  1204. ath_start_ani(common);
  1205. } else {
  1206. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1207. del_timer_sync(&common->ani.timer);
  1208. }
  1209. }
  1210. /* Called with sc->mutex held, vif counts set up properly. */
  1211. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1212. struct ieee80211_vif *vif)
  1213. {
  1214. struct ath_softc *sc = hw->priv;
  1215. ath9k_calculate_summary_state(hw, vif);
  1216. if (ath9k_uses_beacons(vif->type)) {
  1217. int error;
  1218. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1219. /* This may fail because upper levels do not have beacons
  1220. * properly configured yet. That's OK, we assume it
  1221. * will be properly configured and then we will be notified
  1222. * in the info_changed method and set up beacons properly
  1223. * there.
  1224. */
  1225. error = ath_beacon_alloc(sc, vif);
  1226. if (error)
  1227. ath9k_reclaim_beacon(sc, vif);
  1228. else
  1229. ath_beacon_config(sc, vif);
  1230. }
  1231. }
  1232. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1233. struct ieee80211_vif *vif)
  1234. {
  1235. struct ath_softc *sc = hw->priv;
  1236. struct ath_hw *ah = sc->sc_ah;
  1237. struct ath_common *common = ath9k_hw_common(ah);
  1238. struct ath_vif *avp = (void *)vif->drv_priv;
  1239. int ret = 0;
  1240. mutex_lock(&sc->mutex);
  1241. switch (vif->type) {
  1242. case NL80211_IFTYPE_STATION:
  1243. case NL80211_IFTYPE_WDS:
  1244. case NL80211_IFTYPE_ADHOC:
  1245. case NL80211_IFTYPE_AP:
  1246. case NL80211_IFTYPE_MESH_POINT:
  1247. break;
  1248. default:
  1249. ath_err(common, "Interface type %d not yet supported\n",
  1250. vif->type);
  1251. ret = -EOPNOTSUPP;
  1252. goto out;
  1253. }
  1254. if (ath9k_uses_beacons(vif->type)) {
  1255. if (sc->nbcnvifs >= ATH_BCBUF) {
  1256. ath_err(common, "Not enough beacon buffers when adding"
  1257. " new interface of type: %i\n",
  1258. vif->type);
  1259. ret = -ENOBUFS;
  1260. goto out;
  1261. }
  1262. }
  1263. if ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1264. sc->nvifs > 0) {
  1265. ath_err(common, "Cannot create ADHOC interface when other"
  1266. " interfaces already exist.\n");
  1267. ret = -EINVAL;
  1268. goto out;
  1269. }
  1270. ath_dbg(common, ATH_DBG_CONFIG,
  1271. "Attach a VIF of type: %d\n", vif->type);
  1272. /* Set the VIF opmode */
  1273. avp->av_opmode = vif->type;
  1274. avp->av_bslot = -1;
  1275. sc->nvifs++;
  1276. ath9k_do_vif_add_setup(hw, vif);
  1277. out:
  1278. mutex_unlock(&sc->mutex);
  1279. return ret;
  1280. }
  1281. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1282. struct ieee80211_vif *vif,
  1283. enum nl80211_iftype new_type,
  1284. bool p2p)
  1285. {
  1286. struct ath_softc *sc = hw->priv;
  1287. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1288. int ret = 0;
  1289. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1290. mutex_lock(&sc->mutex);
  1291. /* See if new interface type is valid. */
  1292. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1293. (sc->nvifs > 1)) {
  1294. ath_err(common, "When using ADHOC, it must be the only"
  1295. " interface.\n");
  1296. ret = -EINVAL;
  1297. goto out;
  1298. }
  1299. if (ath9k_uses_beacons(new_type) &&
  1300. !ath9k_uses_beacons(vif->type)) {
  1301. if (sc->nbcnvifs >= ATH_BCBUF) {
  1302. ath_err(common, "No beacon slot available\n");
  1303. ret = -ENOBUFS;
  1304. goto out;
  1305. }
  1306. }
  1307. /* Clean up old vif stuff */
  1308. if (ath9k_uses_beacons(vif->type))
  1309. ath9k_reclaim_beacon(sc, vif);
  1310. /* Add new settings */
  1311. vif->type = new_type;
  1312. vif->p2p = p2p;
  1313. ath9k_do_vif_add_setup(hw, vif);
  1314. out:
  1315. mutex_unlock(&sc->mutex);
  1316. return ret;
  1317. }
  1318. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1319. struct ieee80211_vif *vif)
  1320. {
  1321. struct ath_softc *sc = hw->priv;
  1322. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1323. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1324. mutex_lock(&sc->mutex);
  1325. sc->nvifs--;
  1326. /* Reclaim beacon resources */
  1327. if (ath9k_uses_beacons(vif->type))
  1328. ath9k_reclaim_beacon(sc, vif);
  1329. ath9k_calculate_summary_state(hw, NULL);
  1330. mutex_unlock(&sc->mutex);
  1331. }
  1332. static void ath9k_enable_ps(struct ath_softc *sc)
  1333. {
  1334. struct ath_hw *ah = sc->sc_ah;
  1335. sc->ps_enabled = true;
  1336. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1337. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1338. ah->imask |= ATH9K_INT_TIM_TIMER;
  1339. ath9k_hw_set_interrupts(ah, ah->imask);
  1340. }
  1341. ath9k_hw_setrxabort(ah, 1);
  1342. }
  1343. }
  1344. static void ath9k_disable_ps(struct ath_softc *sc)
  1345. {
  1346. struct ath_hw *ah = sc->sc_ah;
  1347. sc->ps_enabled = false;
  1348. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1349. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1350. ath9k_hw_setrxabort(ah, 0);
  1351. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1352. PS_WAIT_FOR_CAB |
  1353. PS_WAIT_FOR_PSPOLL_DATA |
  1354. PS_WAIT_FOR_TX_ACK);
  1355. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1356. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1357. ath9k_hw_set_interrupts(ah, ah->imask);
  1358. }
  1359. }
  1360. }
  1361. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1362. {
  1363. struct ath_softc *sc = hw->priv;
  1364. struct ath_hw *ah = sc->sc_ah;
  1365. struct ath_common *common = ath9k_hw_common(ah);
  1366. struct ieee80211_conf *conf = &hw->conf;
  1367. bool disable_radio = false;
  1368. mutex_lock(&sc->mutex);
  1369. /*
  1370. * Leave this as the first check because we need to turn on the
  1371. * radio if it was disabled before prior to processing the rest
  1372. * of the changes. Likewise we must only disable the radio towards
  1373. * the end.
  1374. */
  1375. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1376. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1377. if (!sc->ps_idle) {
  1378. ath_radio_enable(sc, hw);
  1379. ath_dbg(common, ATH_DBG_CONFIG,
  1380. "not-idle: enabling radio\n");
  1381. } else {
  1382. disable_radio = true;
  1383. }
  1384. }
  1385. /*
  1386. * We just prepare to enable PS. We have to wait until our AP has
  1387. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1388. * those ACKs and end up retransmitting the same null data frames.
  1389. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1390. */
  1391. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1392. unsigned long flags;
  1393. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1394. if (conf->flags & IEEE80211_CONF_PS)
  1395. ath9k_enable_ps(sc);
  1396. else
  1397. ath9k_disable_ps(sc);
  1398. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1399. }
  1400. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1401. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1402. ath_dbg(common, ATH_DBG_CONFIG,
  1403. "Monitor mode is enabled\n");
  1404. sc->sc_ah->is_monitoring = true;
  1405. } else {
  1406. ath_dbg(common, ATH_DBG_CONFIG,
  1407. "Monitor mode is disabled\n");
  1408. sc->sc_ah->is_monitoring = false;
  1409. }
  1410. }
  1411. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1412. struct ieee80211_channel *curchan = hw->conf.channel;
  1413. int pos = curchan->hw_value;
  1414. int old_pos = -1;
  1415. unsigned long flags;
  1416. if (ah->curchan)
  1417. old_pos = ah->curchan - &ah->channels[0];
  1418. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1419. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1420. else
  1421. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1422. ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1423. curchan->center_freq);
  1424. /* XXX: remove me eventualy */
  1425. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1426. /* update survey stats for the old channel before switching */
  1427. spin_lock_irqsave(&common->cc_lock, flags);
  1428. ath_update_survey_stats(sc);
  1429. spin_unlock_irqrestore(&common->cc_lock, flags);
  1430. /*
  1431. * If the operating channel changes, change the survey in-use flags
  1432. * along with it.
  1433. * Reset the survey data for the new channel, unless we're switching
  1434. * back to the operating channel from an off-channel operation.
  1435. */
  1436. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1437. sc->cur_survey != &sc->survey[pos]) {
  1438. if (sc->cur_survey)
  1439. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1440. sc->cur_survey = &sc->survey[pos];
  1441. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1442. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1443. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1444. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1445. }
  1446. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1447. ath_err(common, "Unable to set channel\n");
  1448. mutex_unlock(&sc->mutex);
  1449. return -EINVAL;
  1450. }
  1451. /*
  1452. * The most recent snapshot of channel->noisefloor for the old
  1453. * channel is only available after the hardware reset. Copy it to
  1454. * the survey stats now.
  1455. */
  1456. if (old_pos >= 0)
  1457. ath_update_survey_nf(sc, old_pos);
  1458. }
  1459. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1460. sc->config.txpowlimit = 2 * conf->power_level;
  1461. ath_update_txpow(sc);
  1462. }
  1463. if (disable_radio) {
  1464. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1465. ath_radio_disable(sc, hw);
  1466. }
  1467. mutex_unlock(&sc->mutex);
  1468. return 0;
  1469. }
  1470. #define SUPPORTED_FILTERS \
  1471. (FIF_PROMISC_IN_BSS | \
  1472. FIF_ALLMULTI | \
  1473. FIF_CONTROL | \
  1474. FIF_PSPOLL | \
  1475. FIF_OTHER_BSS | \
  1476. FIF_BCN_PRBRESP_PROMISC | \
  1477. FIF_PROBE_REQ | \
  1478. FIF_FCSFAIL)
  1479. /* FIXME: sc->sc_full_reset ? */
  1480. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1481. unsigned int changed_flags,
  1482. unsigned int *total_flags,
  1483. u64 multicast)
  1484. {
  1485. struct ath_softc *sc = hw->priv;
  1486. u32 rfilt;
  1487. changed_flags &= SUPPORTED_FILTERS;
  1488. *total_flags &= SUPPORTED_FILTERS;
  1489. sc->rx.rxfilter = *total_flags;
  1490. ath9k_ps_wakeup(sc);
  1491. rfilt = ath_calcrxfilter(sc);
  1492. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1493. ath9k_ps_restore(sc);
  1494. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1495. "Set HW RX filter: 0x%x\n", rfilt);
  1496. }
  1497. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1498. struct ieee80211_vif *vif,
  1499. struct ieee80211_sta *sta)
  1500. {
  1501. struct ath_softc *sc = hw->priv;
  1502. ath_node_attach(sc, sta);
  1503. return 0;
  1504. }
  1505. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1506. struct ieee80211_vif *vif,
  1507. struct ieee80211_sta *sta)
  1508. {
  1509. struct ath_softc *sc = hw->priv;
  1510. ath_node_detach(sc, sta);
  1511. return 0;
  1512. }
  1513. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1514. const struct ieee80211_tx_queue_params *params)
  1515. {
  1516. struct ath_softc *sc = hw->priv;
  1517. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1518. struct ath_txq *txq;
  1519. struct ath9k_tx_queue_info qi;
  1520. int ret = 0;
  1521. if (queue >= WME_NUM_AC)
  1522. return 0;
  1523. txq = sc->tx.txq_map[queue];
  1524. mutex_lock(&sc->mutex);
  1525. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1526. qi.tqi_aifs = params->aifs;
  1527. qi.tqi_cwmin = params->cw_min;
  1528. qi.tqi_cwmax = params->cw_max;
  1529. qi.tqi_burstTime = params->txop;
  1530. ath_dbg(common, ATH_DBG_CONFIG,
  1531. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1532. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1533. params->cw_max, params->txop);
  1534. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1535. if (ret)
  1536. ath_err(common, "TXQ Update failed\n");
  1537. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1538. if (queue == WME_AC_BE && !ret)
  1539. ath_beaconq_config(sc);
  1540. mutex_unlock(&sc->mutex);
  1541. return ret;
  1542. }
  1543. static int ath9k_set_key(struct ieee80211_hw *hw,
  1544. enum set_key_cmd cmd,
  1545. struct ieee80211_vif *vif,
  1546. struct ieee80211_sta *sta,
  1547. struct ieee80211_key_conf *key)
  1548. {
  1549. struct ath_softc *sc = hw->priv;
  1550. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1551. int ret = 0;
  1552. if (ath9k_modparam_nohwcrypt)
  1553. return -ENOSPC;
  1554. mutex_lock(&sc->mutex);
  1555. ath9k_ps_wakeup(sc);
  1556. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1557. switch (cmd) {
  1558. case SET_KEY:
  1559. ret = ath_key_config(common, vif, sta, key);
  1560. if (ret >= 0) {
  1561. key->hw_key_idx = ret;
  1562. /* push IV and Michael MIC generation to stack */
  1563. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1564. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1565. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1566. if (sc->sc_ah->sw_mgmt_crypto &&
  1567. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1568. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1569. ret = 0;
  1570. }
  1571. break;
  1572. case DISABLE_KEY:
  1573. ath_key_delete(common, key);
  1574. break;
  1575. default:
  1576. ret = -EINVAL;
  1577. }
  1578. ath9k_ps_restore(sc);
  1579. mutex_unlock(&sc->mutex);
  1580. return ret;
  1581. }
  1582. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1583. struct ieee80211_vif *vif,
  1584. struct ieee80211_bss_conf *bss_conf,
  1585. u32 changed)
  1586. {
  1587. struct ath_softc *sc = hw->priv;
  1588. struct ath_hw *ah = sc->sc_ah;
  1589. struct ath_common *common = ath9k_hw_common(ah);
  1590. struct ath_vif *avp = (void *)vif->drv_priv;
  1591. int slottime;
  1592. int error;
  1593. mutex_lock(&sc->mutex);
  1594. if (changed & BSS_CHANGED_BSSID) {
  1595. /* Set BSSID */
  1596. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1597. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1598. common->curaid = 0;
  1599. ath9k_hw_write_associd(ah);
  1600. /* Set aggregation protection mode parameters */
  1601. sc->config.ath_aggr_prot = 0;
  1602. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1603. common->curbssid, common->curaid);
  1604. /* need to reconfigure the beacon */
  1605. sc->sc_flags &= ~SC_OP_BEACONS ;
  1606. }
  1607. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1608. if ((changed & BSS_CHANGED_BEACON) ||
  1609. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1610. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1611. error = ath_beacon_alloc(sc, vif);
  1612. if (!error)
  1613. ath_beacon_config(sc, vif);
  1614. }
  1615. if (changed & BSS_CHANGED_ERP_SLOT) {
  1616. if (bss_conf->use_short_slot)
  1617. slottime = 9;
  1618. else
  1619. slottime = 20;
  1620. if (vif->type == NL80211_IFTYPE_AP) {
  1621. /*
  1622. * Defer update, so that connected stations can adjust
  1623. * their settings at the same time.
  1624. * See beacon.c for more details
  1625. */
  1626. sc->beacon.slottime = slottime;
  1627. sc->beacon.updateslot = UPDATE;
  1628. } else {
  1629. ah->slottime = slottime;
  1630. ath9k_hw_init_global_settings(ah);
  1631. }
  1632. }
  1633. /* Disable transmission of beacons */
  1634. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1635. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1636. if (changed & BSS_CHANGED_BEACON_INT) {
  1637. sc->beacon_interval = bss_conf->beacon_int;
  1638. /*
  1639. * In case of AP mode, the HW TSF has to be reset
  1640. * when the beacon interval changes.
  1641. */
  1642. if (vif->type == NL80211_IFTYPE_AP) {
  1643. sc->sc_flags |= SC_OP_TSF_RESET;
  1644. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1645. error = ath_beacon_alloc(sc, vif);
  1646. if (!error)
  1647. ath_beacon_config(sc, vif);
  1648. } else {
  1649. ath_beacon_config(sc, vif);
  1650. }
  1651. }
  1652. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1653. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1654. bss_conf->use_short_preamble);
  1655. if (bss_conf->use_short_preamble)
  1656. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1657. else
  1658. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1659. }
  1660. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1661. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1662. bss_conf->use_cts_prot);
  1663. if (bss_conf->use_cts_prot &&
  1664. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1665. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1666. else
  1667. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1668. }
  1669. if (changed & BSS_CHANGED_ASSOC) {
  1670. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1671. bss_conf->assoc);
  1672. ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
  1673. }
  1674. mutex_unlock(&sc->mutex);
  1675. }
  1676. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1677. {
  1678. struct ath_softc *sc = hw->priv;
  1679. u64 tsf;
  1680. mutex_lock(&sc->mutex);
  1681. ath9k_ps_wakeup(sc);
  1682. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1683. ath9k_ps_restore(sc);
  1684. mutex_unlock(&sc->mutex);
  1685. return tsf;
  1686. }
  1687. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1688. {
  1689. struct ath_softc *sc = hw->priv;
  1690. mutex_lock(&sc->mutex);
  1691. ath9k_ps_wakeup(sc);
  1692. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1693. ath9k_ps_restore(sc);
  1694. mutex_unlock(&sc->mutex);
  1695. }
  1696. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1697. {
  1698. struct ath_softc *sc = hw->priv;
  1699. mutex_lock(&sc->mutex);
  1700. ath9k_ps_wakeup(sc);
  1701. ath9k_hw_reset_tsf(sc->sc_ah);
  1702. ath9k_ps_restore(sc);
  1703. mutex_unlock(&sc->mutex);
  1704. }
  1705. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1706. struct ieee80211_vif *vif,
  1707. enum ieee80211_ampdu_mlme_action action,
  1708. struct ieee80211_sta *sta,
  1709. u16 tid, u16 *ssn, u8 buf_size)
  1710. {
  1711. struct ath_softc *sc = hw->priv;
  1712. int ret = 0;
  1713. local_bh_disable();
  1714. switch (action) {
  1715. case IEEE80211_AMPDU_RX_START:
  1716. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1717. ret = -ENOTSUPP;
  1718. break;
  1719. case IEEE80211_AMPDU_RX_STOP:
  1720. break;
  1721. case IEEE80211_AMPDU_TX_START:
  1722. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1723. return -EOPNOTSUPP;
  1724. ath9k_ps_wakeup(sc);
  1725. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1726. if (!ret)
  1727. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1728. ath9k_ps_restore(sc);
  1729. break;
  1730. case IEEE80211_AMPDU_TX_STOP:
  1731. ath9k_ps_wakeup(sc);
  1732. ath_tx_aggr_stop(sc, sta, tid);
  1733. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1734. ath9k_ps_restore(sc);
  1735. break;
  1736. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1737. ath9k_ps_wakeup(sc);
  1738. ath_tx_aggr_resume(sc, sta, tid);
  1739. ath9k_ps_restore(sc);
  1740. break;
  1741. default:
  1742. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1743. }
  1744. local_bh_enable();
  1745. return ret;
  1746. }
  1747. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1748. struct survey_info *survey)
  1749. {
  1750. struct ath_softc *sc = hw->priv;
  1751. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1752. struct ieee80211_supported_band *sband;
  1753. struct ieee80211_channel *chan;
  1754. unsigned long flags;
  1755. int pos;
  1756. spin_lock_irqsave(&common->cc_lock, flags);
  1757. if (idx == 0)
  1758. ath_update_survey_stats(sc);
  1759. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1760. if (sband && idx >= sband->n_channels) {
  1761. idx -= sband->n_channels;
  1762. sband = NULL;
  1763. }
  1764. if (!sband)
  1765. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1766. if (!sband || idx >= sband->n_channels) {
  1767. spin_unlock_irqrestore(&common->cc_lock, flags);
  1768. return -ENOENT;
  1769. }
  1770. chan = &sband->channels[idx];
  1771. pos = chan->hw_value;
  1772. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1773. survey->channel = chan;
  1774. spin_unlock_irqrestore(&common->cc_lock, flags);
  1775. return 0;
  1776. }
  1777. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1778. {
  1779. struct ath_softc *sc = hw->priv;
  1780. struct ath_hw *ah = sc->sc_ah;
  1781. mutex_lock(&sc->mutex);
  1782. ah->coverage_class = coverage_class;
  1783. ath9k_hw_init_global_settings(ah);
  1784. mutex_unlock(&sc->mutex);
  1785. }
  1786. struct ieee80211_ops ath9k_ops = {
  1787. .tx = ath9k_tx,
  1788. .start = ath9k_start,
  1789. .stop = ath9k_stop,
  1790. .add_interface = ath9k_add_interface,
  1791. .change_interface = ath9k_change_interface,
  1792. .remove_interface = ath9k_remove_interface,
  1793. .config = ath9k_config,
  1794. .configure_filter = ath9k_configure_filter,
  1795. .sta_add = ath9k_sta_add,
  1796. .sta_remove = ath9k_sta_remove,
  1797. .conf_tx = ath9k_conf_tx,
  1798. .bss_info_changed = ath9k_bss_info_changed,
  1799. .set_key = ath9k_set_key,
  1800. .get_tsf = ath9k_get_tsf,
  1801. .set_tsf = ath9k_set_tsf,
  1802. .reset_tsf = ath9k_reset_tsf,
  1803. .ampdu_action = ath9k_ampdu_action,
  1804. .get_survey = ath9k_get_survey,
  1805. .rfkill_poll = ath9k_rfkill_poll_state,
  1806. .set_coverage_class = ath9k_set_coverage_class,
  1807. };