platform.c 11 KB

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  1. /*
  2. * Platform device support for Au1x00 SoCs.
  3. *
  4. * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  5. *
  6. * (C) Copyright Embedded Alley Solutions, Inc 2005
  7. * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/dma-mapping.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/serial_8250.h>
  16. #include <linux/init.h>
  17. #include <asm/mach-au1x00/au1xxx.h>
  18. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  19. #include <asm/mach-au1x00/au1100_mmc.h>
  20. #include <asm/mach-au1x00/au1xxx_eth.h>
  21. #define PORT(_base, _irq) \
  22. { \
  23. .mapbase = _base, \
  24. .irq = _irq, \
  25. .regshift = 2, \
  26. .iotype = UPIO_AU, \
  27. .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
  28. UPF_FIXED_TYPE, \
  29. .type = PORT_16550A, \
  30. }
  31. static struct plat_serial8250_port au1x00_uart_data[] = {
  32. #if defined(CONFIG_SERIAL_8250_AU1X00)
  33. #if defined(CONFIG_SOC_AU1000)
  34. PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
  35. PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
  36. PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
  37. PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
  38. #elif defined(CONFIG_SOC_AU1500)
  39. PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
  40. PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
  41. #elif defined(CONFIG_SOC_AU1100)
  42. PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
  43. PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
  44. PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
  45. #elif defined(CONFIG_SOC_AU1550)
  46. PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
  47. PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
  48. PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
  49. #elif defined(CONFIG_SOC_AU1200)
  50. PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
  51. PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
  52. #endif
  53. #endif /* CONFIG_SERIAL_8250_AU1X00 */
  54. { },
  55. };
  56. static struct platform_device au1xx0_uart_device = {
  57. .name = "serial8250",
  58. .id = PLAT8250_DEV_AU1X00,
  59. .dev = {
  60. .platform_data = au1x00_uart_data,
  61. },
  62. };
  63. /* OHCI (USB full speed host controller) */
  64. static struct resource au1xxx_usb_ohci_resources[] = {
  65. [0] = {
  66. .start = USB_OHCI_BASE,
  67. .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
  68. .flags = IORESOURCE_MEM,
  69. },
  70. [1] = {
  71. .start = FOR_PLATFORM_C_USB_HOST_INT,
  72. .end = FOR_PLATFORM_C_USB_HOST_INT,
  73. .flags = IORESOURCE_IRQ,
  74. },
  75. };
  76. /* The dmamask must be set for OHCI to work */
  77. static u64 ohci_dmamask = DMA_BIT_MASK(32);
  78. static struct platform_device au1xxx_usb_ohci_device = {
  79. .name = "au1xxx-ohci",
  80. .id = 0,
  81. .dev = {
  82. .dma_mask = &ohci_dmamask,
  83. .coherent_dma_mask = DMA_BIT_MASK(32),
  84. },
  85. .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
  86. .resource = au1xxx_usb_ohci_resources,
  87. };
  88. /*** AU1100 LCD controller ***/
  89. #ifdef CONFIG_FB_AU1100
  90. static struct resource au1100_lcd_resources[] = {
  91. [0] = {
  92. .start = LCD_PHYS_ADDR,
  93. .end = LCD_PHYS_ADDR + 0x800 - 1,
  94. .flags = IORESOURCE_MEM,
  95. },
  96. [1] = {
  97. .start = AU1100_LCD_INT,
  98. .end = AU1100_LCD_INT,
  99. .flags = IORESOURCE_IRQ,
  100. }
  101. };
  102. static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
  103. static struct platform_device au1100_lcd_device = {
  104. .name = "au1100-lcd",
  105. .id = 0,
  106. .dev = {
  107. .dma_mask = &au1100_lcd_dmamask,
  108. .coherent_dma_mask = DMA_BIT_MASK(32),
  109. },
  110. .num_resources = ARRAY_SIZE(au1100_lcd_resources),
  111. .resource = au1100_lcd_resources,
  112. };
  113. #endif
  114. #ifdef CONFIG_SOC_AU1200
  115. /* EHCI (USB high speed host controller) */
  116. static struct resource au1xxx_usb_ehci_resources[] = {
  117. [0] = {
  118. .start = USB_EHCI_BASE,
  119. .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
  120. .flags = IORESOURCE_MEM,
  121. },
  122. [1] = {
  123. .start = AU1200_USB_INT,
  124. .end = AU1200_USB_INT,
  125. .flags = IORESOURCE_IRQ,
  126. },
  127. };
  128. static u64 ehci_dmamask = DMA_BIT_MASK(32);
  129. static struct platform_device au1xxx_usb_ehci_device = {
  130. .name = "au1xxx-ehci",
  131. .id = 0,
  132. .dev = {
  133. .dma_mask = &ehci_dmamask,
  134. .coherent_dma_mask = DMA_BIT_MASK(32),
  135. },
  136. .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
  137. .resource = au1xxx_usb_ehci_resources,
  138. };
  139. /* Au1200 UDC (USB gadget controller) */
  140. static struct resource au1xxx_usb_gdt_resources[] = {
  141. [0] = {
  142. .start = USB_UDC_BASE,
  143. .end = USB_UDC_BASE + USB_UDC_LEN - 1,
  144. .flags = IORESOURCE_MEM,
  145. },
  146. [1] = {
  147. .start = AU1200_USB_INT,
  148. .end = AU1200_USB_INT,
  149. .flags = IORESOURCE_IRQ,
  150. },
  151. };
  152. static u64 udc_dmamask = DMA_BIT_MASK(32);
  153. static struct platform_device au1xxx_usb_gdt_device = {
  154. .name = "au1xxx-udc",
  155. .id = 0,
  156. .dev = {
  157. .dma_mask = &udc_dmamask,
  158. .coherent_dma_mask = DMA_BIT_MASK(32),
  159. },
  160. .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
  161. .resource = au1xxx_usb_gdt_resources,
  162. };
  163. /* Au1200 UOC (USB OTG controller) */
  164. static struct resource au1xxx_usb_otg_resources[] = {
  165. [0] = {
  166. .start = USB_UOC_BASE,
  167. .end = USB_UOC_BASE + USB_UOC_LEN - 1,
  168. .flags = IORESOURCE_MEM,
  169. },
  170. [1] = {
  171. .start = AU1200_USB_INT,
  172. .end = AU1200_USB_INT,
  173. .flags = IORESOURCE_IRQ,
  174. },
  175. };
  176. static u64 uoc_dmamask = DMA_BIT_MASK(32);
  177. static struct platform_device au1xxx_usb_otg_device = {
  178. .name = "au1xxx-uoc",
  179. .id = 0,
  180. .dev = {
  181. .dma_mask = &uoc_dmamask,
  182. .coherent_dma_mask = DMA_BIT_MASK(32),
  183. },
  184. .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
  185. .resource = au1xxx_usb_otg_resources,
  186. };
  187. static struct resource au1200_lcd_resources[] = {
  188. [0] = {
  189. .start = LCD_PHYS_ADDR,
  190. .end = LCD_PHYS_ADDR + 0x800 - 1,
  191. .flags = IORESOURCE_MEM,
  192. },
  193. [1] = {
  194. .start = AU1200_LCD_INT,
  195. .end = AU1200_LCD_INT,
  196. .flags = IORESOURCE_IRQ,
  197. }
  198. };
  199. static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
  200. static struct platform_device au1200_lcd_device = {
  201. .name = "au1200-lcd",
  202. .id = 0,
  203. .dev = {
  204. .dma_mask = &au1200_lcd_dmamask,
  205. .coherent_dma_mask = DMA_BIT_MASK(32),
  206. },
  207. .num_resources = ARRAY_SIZE(au1200_lcd_resources),
  208. .resource = au1200_lcd_resources,
  209. };
  210. static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
  211. extern struct au1xmmc_platform_data au1xmmc_platdata[2];
  212. static struct resource au1200_mmc0_resources[] = {
  213. [0] = {
  214. .start = SD0_PHYS_ADDR,
  215. .end = SD0_PHYS_ADDR + 0x7ffff,
  216. .flags = IORESOURCE_MEM,
  217. },
  218. [1] = {
  219. .start = AU1200_SD_INT,
  220. .end = AU1200_SD_INT,
  221. .flags = IORESOURCE_IRQ,
  222. },
  223. [2] = {
  224. .start = DSCR_CMD0_SDMS_TX0,
  225. .end = DSCR_CMD0_SDMS_TX0,
  226. .flags = IORESOURCE_DMA,
  227. },
  228. [3] = {
  229. .start = DSCR_CMD0_SDMS_RX0,
  230. .end = DSCR_CMD0_SDMS_RX0,
  231. .flags = IORESOURCE_DMA,
  232. }
  233. };
  234. static struct platform_device au1200_mmc0_device = {
  235. .name = "au1xxx-mmc",
  236. .id = 0,
  237. .dev = {
  238. .dma_mask = &au1xxx_mmc_dmamask,
  239. .coherent_dma_mask = DMA_BIT_MASK(32),
  240. .platform_data = &au1xmmc_platdata[0],
  241. },
  242. .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
  243. .resource = au1200_mmc0_resources,
  244. };
  245. #ifndef CONFIG_MIPS_DB1200
  246. static struct resource au1200_mmc1_resources[] = {
  247. [0] = {
  248. .start = SD1_PHYS_ADDR,
  249. .end = SD1_PHYS_ADDR + 0x7ffff,
  250. .flags = IORESOURCE_MEM,
  251. },
  252. [1] = {
  253. .start = AU1200_SD_INT,
  254. .end = AU1200_SD_INT,
  255. .flags = IORESOURCE_IRQ,
  256. },
  257. [2] = {
  258. .start = DSCR_CMD0_SDMS_TX1,
  259. .end = DSCR_CMD0_SDMS_TX1,
  260. .flags = IORESOURCE_DMA,
  261. },
  262. [3] = {
  263. .start = DSCR_CMD0_SDMS_RX1,
  264. .end = DSCR_CMD0_SDMS_RX1,
  265. .flags = IORESOURCE_DMA,
  266. }
  267. };
  268. static struct platform_device au1200_mmc1_device = {
  269. .name = "au1xxx-mmc",
  270. .id = 1,
  271. .dev = {
  272. .dma_mask = &au1xxx_mmc_dmamask,
  273. .coherent_dma_mask = DMA_BIT_MASK(32),
  274. .platform_data = &au1xmmc_platdata[1],
  275. },
  276. .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
  277. .resource = au1200_mmc1_resources,
  278. };
  279. #endif /* #ifndef CONFIG_MIPS_DB1200 */
  280. #endif /* #ifdef CONFIG_SOC_AU1200 */
  281. /* All Alchemy demoboards with I2C have this #define in their headers */
  282. #ifdef SMBUS_PSC_BASE
  283. static struct resource pbdb_smbus_resources[] = {
  284. {
  285. .start = CPHYSADDR(SMBUS_PSC_BASE),
  286. .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
  287. .flags = IORESOURCE_MEM,
  288. },
  289. };
  290. static struct platform_device pbdb_smbus_device = {
  291. .name = "au1xpsc_smbus",
  292. .id = 0, /* bus number */
  293. .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
  294. .resource = pbdb_smbus_resources,
  295. };
  296. #endif
  297. /* Macro to help defining the Ethernet MAC resources */
  298. #define MAC_RES(_base, _enable, _irq) \
  299. { \
  300. .start = CPHYSADDR(_base), \
  301. .end = CPHYSADDR(_base + 0xffff), \
  302. .flags = IORESOURCE_MEM, \
  303. }, \
  304. { \
  305. .start = CPHYSADDR(_enable), \
  306. .end = CPHYSADDR(_enable + 0x3), \
  307. .flags = IORESOURCE_MEM, \
  308. }, \
  309. { \
  310. .start = _irq, \
  311. .end = _irq, \
  312. .flags = IORESOURCE_IRQ \
  313. }
  314. static struct resource au1xxx_eth0_resources[] = {
  315. #if defined(CONFIG_SOC_AU1000)
  316. MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
  317. #elif defined(CONFIG_SOC_AU1100)
  318. MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
  319. #elif defined(CONFIG_SOC_AU1550)
  320. MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
  321. #elif defined(CONFIG_SOC_AU1500)
  322. MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
  323. #endif
  324. };
  325. static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
  326. .phy1_search_mac0 = 1,
  327. };
  328. static struct platform_device au1xxx_eth0_device = {
  329. .name = "au1000-eth",
  330. .id = 0,
  331. .num_resources = ARRAY_SIZE(au1xxx_eth0_resources),
  332. .resource = au1xxx_eth0_resources,
  333. .dev.platform_data = &au1xxx_eth0_platform_data,
  334. };
  335. #ifndef CONFIG_SOC_AU1100
  336. static struct resource au1xxx_eth1_resources[] = {
  337. #if defined(CONFIG_SOC_AU1000)
  338. MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
  339. #elif defined(CONFIG_SOC_AU1550)
  340. MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
  341. #elif defined(CONFIG_SOC_AU1500)
  342. MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
  343. #endif
  344. };
  345. static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
  346. .phy1_search_mac0 = 1,
  347. };
  348. static struct platform_device au1xxx_eth1_device = {
  349. .name = "au1000-eth",
  350. .id = 1,
  351. .num_resources = ARRAY_SIZE(au1xxx_eth1_resources),
  352. .resource = au1xxx_eth1_resources,
  353. .dev.platform_data = &au1xxx_eth1_platform_data,
  354. };
  355. #endif
  356. void __init au1xxx_override_eth_cfg(unsigned int port,
  357. struct au1000_eth_platform_data *eth_data)
  358. {
  359. if (!eth_data || port > 1)
  360. return;
  361. if (port == 0)
  362. memcpy(&au1xxx_eth0_platform_data, eth_data,
  363. sizeof(struct au1000_eth_platform_data));
  364. #ifndef CONFIG_SOC_AU1100
  365. else
  366. memcpy(&au1xxx_eth1_platform_data, eth_data,
  367. sizeof(struct au1000_eth_platform_data));
  368. #endif
  369. }
  370. static struct platform_device *au1xxx_platform_devices[] __initdata = {
  371. &au1xx0_uart_device,
  372. &au1xxx_usb_ohci_device,
  373. #ifdef CONFIG_FB_AU1100
  374. &au1100_lcd_device,
  375. #endif
  376. #ifdef CONFIG_SOC_AU1200
  377. &au1xxx_usb_ehci_device,
  378. &au1xxx_usb_gdt_device,
  379. &au1xxx_usb_otg_device,
  380. &au1200_lcd_device,
  381. &au1200_mmc0_device,
  382. #ifndef CONFIG_MIPS_DB1200
  383. &au1200_mmc1_device,
  384. #endif
  385. #endif
  386. #ifdef SMBUS_PSC_BASE
  387. &pbdb_smbus_device,
  388. #endif
  389. &au1xxx_eth0_device,
  390. };
  391. static int __init au1xxx_platform_init(void)
  392. {
  393. unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
  394. int err, i;
  395. /* Fill up uartclk. */
  396. for (i = 0; au1x00_uart_data[i].flags; i++)
  397. au1x00_uart_data[i].uartclk = uartclk;
  398. err = platform_add_devices(au1xxx_platform_devices,
  399. ARRAY_SIZE(au1xxx_platform_devices));
  400. #ifndef CONFIG_SOC_AU1100
  401. /* Register second MAC if enabled in pinfunc */
  402. if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
  403. platform_device_register(&au1xxx_eth1_device);
  404. #endif
  405. return err;
  406. }
  407. arch_initcall(au1xxx_platform_init);