config.c 6.3 KB

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  1. /***************************************************************************/
  2. /*
  3. * linux/arch/m68knommu/platform/520x/config.c
  4. *
  5. * Copyright (C) 2005, Freescale (www.freescale.com)
  6. * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
  7. * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
  8. * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  9. */
  10. /***************************************************************************/
  11. #include <linux/kernel.h>
  12. #include <linux/param.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/gpio.h>
  17. #include <asm/machdep.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/mcfuart.h>
  21. #include <asm/mcfqspi.h>
  22. /***************************************************************************/
  23. static struct resource m520x_fec_resources[] = {
  24. {
  25. .start = MCFFEC_BASE,
  26. .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
  27. .flags = IORESOURCE_MEM,
  28. },
  29. {
  30. .start = 64 + 36,
  31. .end = 64 + 36,
  32. .flags = IORESOURCE_IRQ,
  33. },
  34. {
  35. .start = 64 + 40,
  36. .end = 64 + 40,
  37. .flags = IORESOURCE_IRQ,
  38. },
  39. {
  40. .start = 64 + 42,
  41. .end = 64 + 42,
  42. .flags = IORESOURCE_IRQ,
  43. },
  44. };
  45. static struct platform_device m520x_fec = {
  46. .name = "fec",
  47. .id = 0,
  48. .num_resources = ARRAY_SIZE(m520x_fec_resources),
  49. .resource = m520x_fec_resources,
  50. };
  51. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  52. static struct resource m520x_qspi_resources[] = {
  53. {
  54. .start = MCFQSPI_IOBASE,
  55. .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
  56. .flags = IORESOURCE_MEM,
  57. },
  58. {
  59. .start = MCFINT_VECBASE + MCFINT_QSPI,
  60. .end = MCFINT_VECBASE + MCFINT_QSPI,
  61. .flags = IORESOURCE_IRQ,
  62. },
  63. };
  64. #define MCFQSPI_CS0 46
  65. #define MCFQSPI_CS1 47
  66. #define MCFQSPI_CS2 27
  67. static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
  68. {
  69. int status;
  70. status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
  71. if (status) {
  72. pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
  73. goto fail0;
  74. }
  75. status = gpio_direction_output(MCFQSPI_CS0, 1);
  76. if (status) {
  77. pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
  78. goto fail1;
  79. }
  80. status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
  81. if (status) {
  82. pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
  83. goto fail1;
  84. }
  85. status = gpio_direction_output(MCFQSPI_CS1, 1);
  86. if (status) {
  87. pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
  88. goto fail2;
  89. }
  90. status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
  91. if (status) {
  92. pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
  93. goto fail2;
  94. }
  95. status = gpio_direction_output(MCFQSPI_CS2, 1);
  96. if (status) {
  97. pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
  98. goto fail3;
  99. }
  100. return 0;
  101. fail3:
  102. gpio_free(MCFQSPI_CS2);
  103. fail2:
  104. gpio_free(MCFQSPI_CS1);
  105. fail1:
  106. gpio_free(MCFQSPI_CS0);
  107. fail0:
  108. return status;
  109. }
  110. static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
  111. {
  112. gpio_free(MCFQSPI_CS2);
  113. gpio_free(MCFQSPI_CS1);
  114. gpio_free(MCFQSPI_CS0);
  115. }
  116. static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
  117. u8 chip_select, bool cs_high)
  118. {
  119. switch (chip_select) {
  120. case 0:
  121. gpio_set_value(MCFQSPI_CS0, cs_high);
  122. break;
  123. case 1:
  124. gpio_set_value(MCFQSPI_CS1, cs_high);
  125. break;
  126. case 2:
  127. gpio_set_value(MCFQSPI_CS2, cs_high);
  128. break;
  129. }
  130. }
  131. static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
  132. u8 chip_select, bool cs_high)
  133. {
  134. switch (chip_select) {
  135. case 0:
  136. gpio_set_value(MCFQSPI_CS0, !cs_high);
  137. break;
  138. case 1:
  139. gpio_set_value(MCFQSPI_CS1, !cs_high);
  140. break;
  141. case 2:
  142. gpio_set_value(MCFQSPI_CS2, !cs_high);
  143. break;
  144. }
  145. }
  146. static struct mcfqspi_cs_control m520x_cs_control = {
  147. .setup = m520x_cs_setup,
  148. .teardown = m520x_cs_teardown,
  149. .select = m520x_cs_select,
  150. .deselect = m520x_cs_deselect,
  151. };
  152. static struct mcfqspi_platform_data m520x_qspi_data = {
  153. .bus_num = 0,
  154. .num_chipselect = 3,
  155. .cs_control = &m520x_cs_control,
  156. };
  157. static struct platform_device m520x_qspi = {
  158. .name = "mcfqspi",
  159. .id = 0,
  160. .num_resources = ARRAY_SIZE(m520x_qspi_resources),
  161. .resource = m520x_qspi_resources,
  162. .dev.platform_data = &m520x_qspi_data,
  163. };
  164. static void __init m520x_qspi_init(void)
  165. {
  166. u16 par;
  167. /* setup Port QS for QSPI with gpio CS control */
  168. writeb(0x3f, MCF_GPIO_PAR_QSPI);
  169. /* make U1CTS and U2RTS gpio for cs_control */
  170. par = readw(MCF_GPIO_PAR_UART);
  171. par &= 0x00ff;
  172. writew(par, MCF_GPIO_PAR_UART);
  173. }
  174. #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
  175. static struct platform_device *m520x_devices[] __initdata = {
  176. &m520x_fec,
  177. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  178. &m520x_qspi,
  179. #endif
  180. };
  181. /***************************************************************************/
  182. static void __init m520x_uarts_init(void)
  183. {
  184. u16 par;
  185. u8 par2;
  186. /* UART0 and UART1 GPIO pin setup */
  187. par = readw(MCF_GPIO_PAR_UART);
  188. par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
  189. par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
  190. writew(par, MCF_GPIO_PAR_UART);
  191. /* UART1 GPIO pin setup */
  192. par2 = readb(MCF_GPIO_PAR_FECI2C);
  193. par2 &= ~0x0F;
  194. par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
  195. MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
  196. writeb(par2, MCF_GPIO_PAR_FECI2C);
  197. }
  198. /***************************************************************************/
  199. static void __init m520x_fec_init(void)
  200. {
  201. u8 v;
  202. /* Set multi-function pins to ethernet mode */
  203. v = readb(MCF_GPIO_PAR_FEC);
  204. writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
  205. v = readb(MCF_GPIO_PAR_FECI2C);
  206. writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
  207. }
  208. /***************************************************************************/
  209. static void m520x_cpu_reset(void)
  210. {
  211. local_irq_disable();
  212. __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
  213. }
  214. /***************************************************************************/
  215. void __init config_BSP(char *commandp, int size)
  216. {
  217. mach_reset = m520x_cpu_reset;
  218. mach_sched_init = hw_timer_init;
  219. m520x_uarts_init();
  220. m520x_fec_init();
  221. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  222. m520x_qspi_init();
  223. #endif
  224. }
  225. /***************************************************************************/
  226. static int __init init_BSP(void)
  227. {
  228. platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
  229. return 0;
  230. }
  231. arch_initcall(init_BSP);
  232. /***************************************************************************/