Kconfig 28 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config SYMBOL_PREFIX
  7. string
  8. default "_"
  9. config MMU
  10. def_bool n
  11. config FPU
  12. def_bool n
  13. config RWSEM_GENERIC_SPINLOCK
  14. def_bool y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. def_bool n
  17. config BLACKFIN
  18. def_bool y
  19. select HAVE_FUNCTION_GRAPH_TRACER
  20. select HAVE_FUNCTION_TRACER
  21. select HAVE_IDE
  22. select HAVE_KERNEL_GZIP
  23. select HAVE_KERNEL_BZIP2
  24. select HAVE_KERNEL_LZMA
  25. select HAVE_OPROFILE
  26. select ARCH_WANT_OPTIONAL_GPIOLIB
  27. config GENERIC_CSUM
  28. def_bool y
  29. config GENERIC_BUG
  30. def_bool y
  31. depends on BUG
  32. config ZONE_DMA
  33. def_bool y
  34. config GENERIC_FIND_NEXT_BIT
  35. def_bool y
  36. config GENERIC_HARDIRQS
  37. def_bool y
  38. config GENERIC_IRQ_PROBE
  39. def_bool y
  40. config GENERIC_HARDIRQS_NO__DO_IRQ
  41. def_bool y
  42. config GENERIC_GPIO
  43. def_bool y
  44. config FORCE_MAX_ZONEORDER
  45. int
  46. default "14"
  47. config GENERIC_CALIBRATE_DELAY
  48. def_bool y
  49. config LOCKDEP_SUPPORT
  50. def_bool y
  51. config STACKTRACE_SUPPORT
  52. def_bool y
  53. config TRACE_IRQFLAGS_SUPPORT
  54. def_bool y
  55. source "init/Kconfig"
  56. source "kernel/Kconfig.preempt"
  57. source "kernel/Kconfig.freezer"
  58. menu "Blackfin Processor Options"
  59. comment "Processor and Board Settings"
  60. choice
  61. prompt "CPU"
  62. default BF533
  63. config BF512
  64. bool "BF512"
  65. help
  66. BF512 Processor Support.
  67. config BF514
  68. bool "BF514"
  69. help
  70. BF514 Processor Support.
  71. config BF516
  72. bool "BF516"
  73. help
  74. BF516 Processor Support.
  75. config BF518
  76. bool "BF518"
  77. help
  78. BF518 Processor Support.
  79. config BF522
  80. bool "BF522"
  81. help
  82. BF522 Processor Support.
  83. config BF523
  84. bool "BF523"
  85. help
  86. BF523 Processor Support.
  87. config BF524
  88. bool "BF524"
  89. help
  90. BF524 Processor Support.
  91. config BF525
  92. bool "BF525"
  93. help
  94. BF525 Processor Support.
  95. config BF526
  96. bool "BF526"
  97. help
  98. BF526 Processor Support.
  99. config BF527
  100. bool "BF527"
  101. help
  102. BF527 Processor Support.
  103. config BF531
  104. bool "BF531"
  105. help
  106. BF531 Processor Support.
  107. config BF532
  108. bool "BF532"
  109. help
  110. BF532 Processor Support.
  111. config BF533
  112. bool "BF533"
  113. help
  114. BF533 Processor Support.
  115. config BF534
  116. bool "BF534"
  117. help
  118. BF534 Processor Support.
  119. config BF536
  120. bool "BF536"
  121. help
  122. BF536 Processor Support.
  123. config BF537
  124. bool "BF537"
  125. help
  126. BF537 Processor Support.
  127. config BF538
  128. bool "BF538"
  129. help
  130. BF538 Processor Support.
  131. config BF539
  132. bool "BF539"
  133. help
  134. BF539 Processor Support.
  135. config BF542_std
  136. bool "BF542"
  137. help
  138. BF542 Processor Support.
  139. config BF542M
  140. bool "BF542m"
  141. help
  142. BF542 Processor Support.
  143. config BF544_std
  144. bool "BF544"
  145. help
  146. BF544 Processor Support.
  147. config BF544M
  148. bool "BF544m"
  149. help
  150. BF544 Processor Support.
  151. config BF547_std
  152. bool "BF547"
  153. help
  154. BF547 Processor Support.
  155. config BF547M
  156. bool "BF547m"
  157. help
  158. BF547 Processor Support.
  159. config BF548_std
  160. bool "BF548"
  161. help
  162. BF548 Processor Support.
  163. config BF548M
  164. bool "BF548m"
  165. help
  166. BF548 Processor Support.
  167. config BF549_std
  168. bool "BF549"
  169. help
  170. BF549 Processor Support.
  171. config BF549M
  172. bool "BF549m"
  173. help
  174. BF549 Processor Support.
  175. config BF561
  176. bool "BF561"
  177. help
  178. BF561 Processor Support.
  179. endchoice
  180. config SMP
  181. depends on BF561
  182. select TICKSOURCE_CORETMR
  183. bool "Symmetric multi-processing support"
  184. ---help---
  185. This enables support for systems with more than one CPU,
  186. like the dual core BF561. If you have a system with only one
  187. CPU, say N. If you have a system with more than one CPU, say Y.
  188. If you don't know what to do here, say N.
  189. config NR_CPUS
  190. int
  191. depends on SMP
  192. default 2 if BF561
  193. config IRQ_PER_CPU
  194. bool
  195. depends on SMP
  196. default y
  197. config HAVE_LEGACY_PER_CPU_AREA
  198. def_bool y
  199. depends on SMP
  200. config BF_REV_MIN
  201. int
  202. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  203. default 2 if (BF537 || BF536 || BF534)
  204. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  205. default 4 if (BF538 || BF539)
  206. config BF_REV_MAX
  207. int
  208. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  209. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  210. default 5 if (BF561 || BF538 || BF539)
  211. default 6 if (BF533 || BF532 || BF531)
  212. choice
  213. prompt "Silicon Rev"
  214. default BF_REV_0_0 if (BF51x || BF52x)
  215. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  216. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  217. config BF_REV_0_0
  218. bool "0.0"
  219. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  220. config BF_REV_0_1
  221. bool "0.1"
  222. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  223. config BF_REV_0_2
  224. bool "0.2"
  225. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  226. config BF_REV_0_3
  227. bool "0.3"
  228. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  229. config BF_REV_0_4
  230. bool "0.4"
  231. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  232. config BF_REV_0_5
  233. bool "0.5"
  234. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  235. config BF_REV_0_6
  236. bool "0.6"
  237. depends on (BF533 || BF532 || BF531)
  238. config BF_REV_ANY
  239. bool "any"
  240. config BF_REV_NONE
  241. bool "none"
  242. endchoice
  243. config BF53x
  244. bool
  245. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  246. default y
  247. config MEM_GENERIC_BOARD
  248. bool
  249. depends on GENERIC_BOARD
  250. default y
  251. config MEM_MT48LC64M4A2FB_7E
  252. bool
  253. depends on (BFIN533_STAMP)
  254. default y
  255. config MEM_MT48LC16M16A2TG_75
  256. bool
  257. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  258. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  259. || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  260. || BFIN527_BLUETECHNIX_CM)
  261. default y
  262. config MEM_MT48LC32M8A2_75
  263. bool
  264. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  265. default y
  266. config MEM_MT48LC8M32B2B5_7
  267. bool
  268. depends on (BFIN561_BLUETECHNIX_CM)
  269. default y
  270. config MEM_MT48LC32M16A2TG_75
  271. bool
  272. depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
  273. default y
  274. config MEM_MT48LC32M8A2_75
  275. bool
  276. depends on (BFIN518F_EZBRD)
  277. default y
  278. config MEM_MT48H32M16LFCJ_75
  279. bool
  280. depends on (BFIN526_EZBRD)
  281. default y
  282. source "arch/blackfin/mach-bf518/Kconfig"
  283. source "arch/blackfin/mach-bf527/Kconfig"
  284. source "arch/blackfin/mach-bf533/Kconfig"
  285. source "arch/blackfin/mach-bf561/Kconfig"
  286. source "arch/blackfin/mach-bf537/Kconfig"
  287. source "arch/blackfin/mach-bf538/Kconfig"
  288. source "arch/blackfin/mach-bf548/Kconfig"
  289. menu "Board customizations"
  290. config CMDLINE_BOOL
  291. bool "Default bootloader kernel arguments"
  292. config CMDLINE
  293. string "Initial kernel command string"
  294. depends on CMDLINE_BOOL
  295. default "console=ttyBF0,57600"
  296. help
  297. If you don't have a boot loader capable of passing a command line string
  298. to the kernel, you may specify one here. As a minimum, you should specify
  299. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  300. config BOOT_LOAD
  301. hex "Kernel load address for booting"
  302. default "0x1000"
  303. range 0x1000 0x20000000
  304. help
  305. This option allows you to set the load address of the kernel.
  306. This can be useful if you are on a board which has a small amount
  307. of memory or you wish to reserve some memory at the beginning of
  308. the address space.
  309. Note that you need to keep this value above 4k (0x1000) as this
  310. memory region is used to capture NULL pointer references as well
  311. as some core kernel functions.
  312. config ROM_BASE
  313. hex "Kernel ROM Base"
  314. depends on ROMKERNEL
  315. default "0x20040000"
  316. range 0x20000000 0x20400000 if !(BF54x || BF561)
  317. range 0x20000000 0x30000000 if (BF54x || BF561)
  318. help
  319. comment "Clock/PLL Setup"
  320. config CLKIN_HZ
  321. int "Frequency of the crystal on the board in Hz"
  322. default "10000000" if BFIN532_IP0X
  323. default "11059200" if BFIN533_STAMP
  324. default "24576000" if PNAV10
  325. default "25000000" # most people use this
  326. default "27000000" if BFIN533_EZKIT
  327. default "30000000" if BFIN561_EZKIT
  328. help
  329. The frequency of CLKIN crystal oscillator on the board in Hz.
  330. Warning: This value should match the crystal on the board. Otherwise,
  331. peripherals won't work properly.
  332. config BFIN_KERNEL_CLOCK
  333. bool "Re-program Clocks while Kernel boots?"
  334. default n
  335. help
  336. This option decides if kernel clocks are re-programed from the
  337. bootloader settings. If the clocks are not set, the SDRAM settings
  338. are also not changed, and the Bootloader does 100% of the hardware
  339. configuration.
  340. config PLL_BYPASS
  341. bool "Bypass PLL"
  342. depends on BFIN_KERNEL_CLOCK
  343. default n
  344. config CLKIN_HALF
  345. bool "Half Clock In"
  346. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  347. default n
  348. help
  349. If this is set the clock will be divided by 2, before it goes to the PLL.
  350. config VCO_MULT
  351. int "VCO Multiplier"
  352. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  353. range 1 64
  354. default "22" if BFIN533_EZKIT
  355. default "45" if BFIN533_STAMP
  356. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  357. default "22" if BFIN533_BLUETECHNIX_CM
  358. default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  359. default "20" if BFIN561_EZKIT
  360. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  361. help
  362. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  363. PLL Frequency = (Crystal Frequency) * (this setting)
  364. choice
  365. prompt "Core Clock Divider"
  366. depends on BFIN_KERNEL_CLOCK
  367. default CCLK_DIV_1
  368. help
  369. This sets the frequency of the core. It can be 1, 2, 4 or 8
  370. Core Frequency = (PLL frequency) / (this setting)
  371. config CCLK_DIV_1
  372. bool "1"
  373. config CCLK_DIV_2
  374. bool "2"
  375. config CCLK_DIV_4
  376. bool "4"
  377. config CCLK_DIV_8
  378. bool "8"
  379. endchoice
  380. config SCLK_DIV
  381. int "System Clock Divider"
  382. depends on BFIN_KERNEL_CLOCK
  383. range 1 15
  384. default 5
  385. help
  386. This sets the frequency of the system clock (including SDRAM or DDR).
  387. This can be between 1 and 15
  388. System Clock = (PLL frequency) / (this setting)
  389. choice
  390. prompt "DDR SDRAM Chip Type"
  391. depends on BFIN_KERNEL_CLOCK
  392. depends on BF54x
  393. default MEM_MT46V32M16_5B
  394. config MEM_MT46V32M16_6T
  395. bool "MT46V32M16_6T"
  396. config MEM_MT46V32M16_5B
  397. bool "MT46V32M16_5B"
  398. endchoice
  399. choice
  400. prompt "DDR/SDRAM Timing"
  401. depends on BFIN_KERNEL_CLOCK
  402. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  403. help
  404. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  405. The calculated SDRAM timing parameters may not be 100%
  406. accurate - This option is therefore marked experimental.
  407. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  408. bool "Calculate Timings (EXPERIMENTAL)"
  409. depends on EXPERIMENTAL
  410. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  411. bool "Provide accurate Timings based on target SCLK"
  412. help
  413. Please consult the Blackfin Hardware Reference Manuals as well
  414. as the memory device datasheet.
  415. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  416. endchoice
  417. menu "Memory Init Control"
  418. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  419. config MEM_DDRCTL0
  420. depends on BF54x
  421. hex "DDRCTL0"
  422. default 0x0
  423. config MEM_DDRCTL1
  424. depends on BF54x
  425. hex "DDRCTL1"
  426. default 0x0
  427. config MEM_DDRCTL2
  428. depends on BF54x
  429. hex "DDRCTL2"
  430. default 0x0
  431. config MEM_EBIU_DDRQUE
  432. depends on BF54x
  433. hex "DDRQUE"
  434. default 0x0
  435. config MEM_SDRRC
  436. depends on !BF54x
  437. hex "SDRRC"
  438. default 0x0
  439. config MEM_SDGCTL
  440. depends on !BF54x
  441. hex "SDGCTL"
  442. default 0x0
  443. endmenu
  444. #
  445. # Max & Min Speeds for various Chips
  446. #
  447. config MAX_VCO_HZ
  448. int
  449. default 400000000 if BF512
  450. default 400000000 if BF514
  451. default 400000000 if BF516
  452. default 400000000 if BF518
  453. default 400000000 if BF522
  454. default 600000000 if BF523
  455. default 400000000 if BF524
  456. default 600000000 if BF525
  457. default 400000000 if BF526
  458. default 600000000 if BF527
  459. default 400000000 if BF531
  460. default 400000000 if BF532
  461. default 750000000 if BF533
  462. default 500000000 if BF534
  463. default 400000000 if BF536
  464. default 600000000 if BF537
  465. default 533333333 if BF538
  466. default 533333333 if BF539
  467. default 600000000 if BF542
  468. default 533333333 if BF544
  469. default 600000000 if BF547
  470. default 600000000 if BF548
  471. default 533333333 if BF549
  472. default 600000000 if BF561
  473. config MIN_VCO_HZ
  474. int
  475. default 50000000
  476. config MAX_SCLK_HZ
  477. int
  478. default 133333333
  479. config MIN_SCLK_HZ
  480. int
  481. default 27000000
  482. comment "Kernel Timer/Scheduler"
  483. source kernel/Kconfig.hz
  484. config GENERIC_TIME
  485. def_bool y
  486. config GENERIC_CLOCKEVENTS
  487. bool "Generic clock events"
  488. default y
  489. menu "Clock event device"
  490. depends on GENERIC_CLOCKEVENTS
  491. config TICKSOURCE_GPTMR0
  492. bool "GPTimer0"
  493. depends on !SMP
  494. select BFIN_GPTIMERS
  495. config TICKSOURCE_CORETMR
  496. bool "Core timer"
  497. default y
  498. endmenu
  499. menu "Clock souce"
  500. depends on GENERIC_CLOCKEVENTS
  501. config CYCLES_CLOCKSOURCE
  502. bool "CYCLES"
  503. default y
  504. depends on !BFIN_SCRATCH_REG_CYCLES
  505. depends on !SMP
  506. help
  507. If you say Y here, you will enable support for using the 'cycles'
  508. registers as a clock source. Doing so means you will be unable to
  509. safely write to the 'cycles' register during runtime. You will
  510. still be able to read it (such as for performance monitoring), but
  511. writing the registers will most likely crash the kernel.
  512. config GPTMR0_CLOCKSOURCE
  513. bool "GPTimer0"
  514. select BFIN_GPTIMERS
  515. depends on !TICKSOURCE_GPTMR0
  516. endmenu
  517. config ARCH_USES_GETTIMEOFFSET
  518. depends on !GENERIC_CLOCKEVENTS
  519. def_bool y
  520. source kernel/time/Kconfig
  521. comment "Misc"
  522. choice
  523. prompt "Blackfin Exception Scratch Register"
  524. default BFIN_SCRATCH_REG_RETN
  525. help
  526. Select the resource to reserve for the Exception handler:
  527. - RETN: Non-Maskable Interrupt (NMI)
  528. - RETE: Exception Return (JTAG/ICE)
  529. - CYCLES: Performance counter
  530. If you are unsure, please select "RETN".
  531. config BFIN_SCRATCH_REG_RETN
  532. bool "RETN"
  533. help
  534. Use the RETN register in the Blackfin exception handler
  535. as a stack scratch register. This means you cannot
  536. safely use NMI on the Blackfin while running Linux, but
  537. you can debug the system with a JTAG ICE and use the
  538. CYCLES performance registers.
  539. If you are unsure, please select "RETN".
  540. config BFIN_SCRATCH_REG_RETE
  541. bool "RETE"
  542. help
  543. Use the RETE register in the Blackfin exception handler
  544. as a stack scratch register. This means you cannot
  545. safely use a JTAG ICE while debugging a Blackfin board,
  546. but you can safely use the CYCLES performance registers
  547. and the NMI.
  548. If you are unsure, please select "RETN".
  549. config BFIN_SCRATCH_REG_CYCLES
  550. bool "CYCLES"
  551. help
  552. Use the CYCLES register in the Blackfin exception handler
  553. as a stack scratch register. This means you cannot
  554. safely use the CYCLES performance registers on a Blackfin
  555. board at anytime, but you can debug the system with a JTAG
  556. ICE and use the NMI.
  557. If you are unsure, please select "RETN".
  558. endchoice
  559. endmenu
  560. menu "Blackfin Kernel Optimizations"
  561. depends on !SMP
  562. comment "Memory Optimizations"
  563. config I_ENTRY_L1
  564. bool "Locate interrupt entry code in L1 Memory"
  565. default y
  566. help
  567. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  568. into L1 instruction memory. (less latency)
  569. config EXCPT_IRQ_SYSC_L1
  570. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  571. default y
  572. help
  573. If enabled, the entire ASM lowlevel exception and interrupt entry code
  574. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  575. (less latency)
  576. config DO_IRQ_L1
  577. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  578. default y
  579. help
  580. If enabled, the frequently called do_irq dispatcher function is linked
  581. into L1 instruction memory. (less latency)
  582. config CORE_TIMER_IRQ_L1
  583. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  584. default y
  585. help
  586. If enabled, the frequently called timer_interrupt() function is linked
  587. into L1 instruction memory. (less latency)
  588. config IDLE_L1
  589. bool "Locate frequently idle function in L1 Memory"
  590. default y
  591. help
  592. If enabled, the frequently called idle function is linked
  593. into L1 instruction memory. (less latency)
  594. config SCHEDULE_L1
  595. bool "Locate kernel schedule function in L1 Memory"
  596. default y
  597. help
  598. If enabled, the frequently called kernel schedule is linked
  599. into L1 instruction memory. (less latency)
  600. config ARITHMETIC_OPS_L1
  601. bool "Locate kernel owned arithmetic functions in L1 Memory"
  602. default y
  603. help
  604. If enabled, arithmetic functions are linked
  605. into L1 instruction memory. (less latency)
  606. config ACCESS_OK_L1
  607. bool "Locate access_ok function in L1 Memory"
  608. default y
  609. help
  610. If enabled, the access_ok function is linked
  611. into L1 instruction memory. (less latency)
  612. config MEMSET_L1
  613. bool "Locate memset function in L1 Memory"
  614. default y
  615. help
  616. If enabled, the memset function is linked
  617. into L1 instruction memory. (less latency)
  618. config MEMCPY_L1
  619. bool "Locate memcpy function in L1 Memory"
  620. default y
  621. help
  622. If enabled, the memcpy function is linked
  623. into L1 instruction memory. (less latency)
  624. config SYS_BFIN_SPINLOCK_L1
  625. bool "Locate sys_bfin_spinlock function in L1 Memory"
  626. default y
  627. help
  628. If enabled, sys_bfin_spinlock function is linked
  629. into L1 instruction memory. (less latency)
  630. config IP_CHECKSUM_L1
  631. bool "Locate IP Checksum function in L1 Memory"
  632. default n
  633. help
  634. If enabled, the IP Checksum function is linked
  635. into L1 instruction memory. (less latency)
  636. config CACHELINE_ALIGNED_L1
  637. bool "Locate cacheline_aligned data to L1 Data Memory"
  638. default y if !BF54x
  639. default n if BF54x
  640. depends on !BF531
  641. help
  642. If enabled, cacheline_aligned data is linked
  643. into L1 data memory. (less latency)
  644. config SYSCALL_TAB_L1
  645. bool "Locate Syscall Table L1 Data Memory"
  646. default n
  647. depends on !BF531
  648. help
  649. If enabled, the Syscall LUT is linked
  650. into L1 data memory. (less latency)
  651. config CPLB_SWITCH_TAB_L1
  652. bool "Locate CPLB Switch Tables L1 Data Memory"
  653. default n
  654. depends on !BF531
  655. help
  656. If enabled, the CPLB Switch Tables are linked
  657. into L1 data memory. (less latency)
  658. config APP_STACK_L1
  659. bool "Support locating application stack in L1 Scratch Memory"
  660. default y
  661. help
  662. If enabled the application stack can be located in L1
  663. scratch memory (less latency).
  664. Currently only works with FLAT binaries.
  665. config EXCEPTION_L1_SCRATCH
  666. bool "Locate exception stack in L1 Scratch Memory"
  667. default n
  668. depends on !APP_STACK_L1
  669. help
  670. Whenever an exception occurs, use the L1 Scratch memory for
  671. stack storage. You cannot place the stacks of FLAT binaries
  672. in L1 when using this option.
  673. If you don't use L1 Scratch, then you should say Y here.
  674. comment "Speed Optimizations"
  675. config BFIN_INS_LOWOVERHEAD
  676. bool "ins[bwl] low overhead, higher interrupt latency"
  677. default y
  678. help
  679. Reads on the Blackfin are speculative. In Blackfin terms, this means
  680. they can be interrupted at any time (even after they have been issued
  681. on to the external bus), and re-issued after the interrupt occurs.
  682. For memory - this is not a big deal, since memory does not change if
  683. it sees a read.
  684. If a FIFO is sitting on the end of the read, it will see two reads,
  685. when the core only sees one since the FIFO receives both the read
  686. which is cancelled (and not delivered to the core) and the one which
  687. is re-issued (which is delivered to the core).
  688. To solve this, interrupts are turned off before reads occur to
  689. I/O space. This option controls which the overhead/latency of
  690. controlling interrupts during this time
  691. "n" turns interrupts off every read
  692. (higher overhead, but lower interrupt latency)
  693. "y" turns interrupts off every loop
  694. (low overhead, but longer interrupt latency)
  695. default behavior is to leave this set to on (type "Y"). If you are experiencing
  696. interrupt latency issues, it is safe and OK to turn this off.
  697. endmenu
  698. choice
  699. prompt "Kernel executes from"
  700. help
  701. Choose the memory type that the kernel will be running in.
  702. config RAMKERNEL
  703. bool "RAM"
  704. help
  705. The kernel will be resident in RAM when running.
  706. config ROMKERNEL
  707. bool "ROM"
  708. help
  709. The kernel will be resident in FLASH/ROM when running.
  710. endchoice
  711. source "mm/Kconfig"
  712. config BFIN_GPTIMERS
  713. tristate "Enable Blackfin General Purpose Timers API"
  714. default n
  715. help
  716. Enable support for the General Purpose Timers API. If you
  717. are unsure, say N.
  718. To compile this driver as a module, choose M here: the module
  719. will be called gptimers.
  720. choice
  721. prompt "Uncached DMA region"
  722. default DMA_UNCACHED_1M
  723. config DMA_UNCACHED_4M
  724. bool "Enable 4M DMA region"
  725. config DMA_UNCACHED_2M
  726. bool "Enable 2M DMA region"
  727. config DMA_UNCACHED_1M
  728. bool "Enable 1M DMA region"
  729. config DMA_UNCACHED_512K
  730. bool "Enable 512K DMA region"
  731. config DMA_UNCACHED_256K
  732. bool "Enable 256K DMA region"
  733. config DMA_UNCACHED_128K
  734. bool "Enable 128K DMA region"
  735. config DMA_UNCACHED_NONE
  736. bool "Disable DMA region"
  737. endchoice
  738. comment "Cache Support"
  739. config BFIN_ICACHE
  740. bool "Enable ICACHE"
  741. default y
  742. config BFIN_EXTMEM_ICACHEABLE
  743. bool "Enable ICACHE for external memory"
  744. depends on BFIN_ICACHE
  745. default y
  746. config BFIN_L2_ICACHEABLE
  747. bool "Enable ICACHE for L2 SRAM"
  748. depends on BFIN_ICACHE
  749. depends on BF54x || BF561
  750. default n
  751. config BFIN_DCACHE
  752. bool "Enable DCACHE"
  753. default y
  754. config BFIN_DCACHE_BANKA
  755. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  756. depends on BFIN_DCACHE && !BF531
  757. default n
  758. config BFIN_EXTMEM_DCACHEABLE
  759. bool "Enable DCACHE for external memory"
  760. depends on BFIN_DCACHE
  761. default y
  762. choice
  763. prompt "External memory DCACHE policy"
  764. depends on BFIN_EXTMEM_DCACHEABLE
  765. default BFIN_EXTMEM_WRITEBACK if !SMP
  766. default BFIN_EXTMEM_WRITETHROUGH if SMP
  767. config BFIN_EXTMEM_WRITEBACK
  768. bool "Write back"
  769. depends on !SMP
  770. help
  771. Write Back Policy:
  772. Cached data will be written back to SDRAM only when needed.
  773. This can give a nice increase in performance, but beware of
  774. broken drivers that do not properly invalidate/flush their
  775. cache.
  776. Write Through Policy:
  777. Cached data will always be written back to SDRAM when the
  778. cache is updated. This is a completely safe setting, but
  779. performance is worse than Write Back.
  780. If you are unsure of the options and you want to be safe,
  781. then go with Write Through.
  782. config BFIN_EXTMEM_WRITETHROUGH
  783. bool "Write through"
  784. help
  785. Write Back Policy:
  786. Cached data will be written back to SDRAM only when needed.
  787. This can give a nice increase in performance, but beware of
  788. broken drivers that do not properly invalidate/flush their
  789. cache.
  790. Write Through Policy:
  791. Cached data will always be written back to SDRAM when the
  792. cache is updated. This is a completely safe setting, but
  793. performance is worse than Write Back.
  794. If you are unsure of the options and you want to be safe,
  795. then go with Write Through.
  796. endchoice
  797. config BFIN_L2_DCACHEABLE
  798. bool "Enable DCACHE for L2 SRAM"
  799. depends on BFIN_DCACHE
  800. depends on (BF54x || BF561) && !SMP
  801. default n
  802. choice
  803. prompt "L2 SRAM DCACHE policy"
  804. depends on BFIN_L2_DCACHEABLE
  805. default BFIN_L2_WRITEBACK
  806. config BFIN_L2_WRITEBACK
  807. bool "Write back"
  808. config BFIN_L2_WRITETHROUGH
  809. bool "Write through"
  810. endchoice
  811. comment "Memory Protection Unit"
  812. config MPU
  813. bool "Enable the memory protection unit (EXPERIMENTAL)"
  814. default n
  815. help
  816. Use the processor's MPU to protect applications from accessing
  817. memory they do not own. This comes at a performance penalty
  818. and is recommended only for debugging.
  819. comment "Asynchronous Memory Configuration"
  820. menu "EBIU_AMGCTL Global Control"
  821. config C_AMCKEN
  822. bool "Enable CLKOUT"
  823. default y
  824. config C_CDPRIO
  825. bool "DMA has priority over core for ext. accesses"
  826. default n
  827. config C_B0PEN
  828. depends on BF561
  829. bool "Bank 0 16 bit packing enable"
  830. default y
  831. config C_B1PEN
  832. depends on BF561
  833. bool "Bank 1 16 bit packing enable"
  834. default y
  835. config C_B2PEN
  836. depends on BF561
  837. bool "Bank 2 16 bit packing enable"
  838. default y
  839. config C_B3PEN
  840. depends on BF561
  841. bool "Bank 3 16 bit packing enable"
  842. default n
  843. choice
  844. prompt "Enable Asynchronous Memory Banks"
  845. default C_AMBEN_ALL
  846. config C_AMBEN
  847. bool "Disable All Banks"
  848. config C_AMBEN_B0
  849. bool "Enable Bank 0"
  850. config C_AMBEN_B0_B1
  851. bool "Enable Bank 0 & 1"
  852. config C_AMBEN_B0_B1_B2
  853. bool "Enable Bank 0 & 1 & 2"
  854. config C_AMBEN_ALL
  855. bool "Enable All Banks"
  856. endchoice
  857. endmenu
  858. menu "EBIU_AMBCTL Control"
  859. config BANK_0
  860. hex "Bank 0 (AMBCTL0.L)"
  861. default 0x7BB0
  862. help
  863. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  864. used to control the Asynchronous Memory Bank 0 settings.
  865. config BANK_1
  866. hex "Bank 1 (AMBCTL0.H)"
  867. default 0x7BB0
  868. default 0x5558 if BF54x
  869. help
  870. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  871. used to control the Asynchronous Memory Bank 1 settings.
  872. config BANK_2
  873. hex "Bank 2 (AMBCTL1.L)"
  874. default 0x7BB0
  875. help
  876. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  877. used to control the Asynchronous Memory Bank 2 settings.
  878. config BANK_3
  879. hex "Bank 3 (AMBCTL1.H)"
  880. default 0x99B3
  881. help
  882. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  883. used to control the Asynchronous Memory Bank 3 settings.
  884. endmenu
  885. config EBIU_MBSCTLVAL
  886. hex "EBIU Bank Select Control Register"
  887. depends on BF54x
  888. default 0
  889. config EBIU_MODEVAL
  890. hex "Flash Memory Mode Control Register"
  891. depends on BF54x
  892. default 1
  893. config EBIU_FCTLVAL
  894. hex "Flash Memory Bank Control Register"
  895. depends on BF54x
  896. default 6
  897. endmenu
  898. #############################################################################
  899. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  900. config PCI
  901. bool "PCI support"
  902. depends on BROKEN
  903. help
  904. Support for PCI bus.
  905. source "drivers/pci/Kconfig"
  906. source "drivers/pcmcia/Kconfig"
  907. source "drivers/pci/hotplug/Kconfig"
  908. endmenu
  909. menu "Executable file formats"
  910. source "fs/Kconfig.binfmt"
  911. endmenu
  912. menu "Power management options"
  913. depends on !SMP
  914. source "kernel/power/Kconfig"
  915. config ARCH_SUSPEND_POSSIBLE
  916. def_bool y
  917. choice
  918. prompt "Standby Power Saving Mode"
  919. depends on PM
  920. default PM_BFIN_SLEEP_DEEPER
  921. config PM_BFIN_SLEEP_DEEPER
  922. bool "Sleep Deeper"
  923. help
  924. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  925. power dissipation by disabling the clock to the processor core (CCLK).
  926. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  927. to 0.85 V to provide the greatest power savings, while preserving the
  928. processor state.
  929. The PLL and system clock (SCLK) continue to operate at a very low
  930. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  931. the SDRAM is put into Self Refresh Mode. Typically an external event
  932. such as GPIO interrupt or RTC activity wakes up the processor.
  933. Various Peripherals such as UART, SPORT, PPI may not function as
  934. normal during Sleep Deeper, due to the reduced SCLK frequency.
  935. When in the sleep mode, system DMA access to L1 memory is not supported.
  936. If unsure, select "Sleep Deeper".
  937. config PM_BFIN_SLEEP
  938. bool "Sleep"
  939. help
  940. Sleep Mode (High Power Savings) - The sleep mode reduces power
  941. dissipation by disabling the clock to the processor core (CCLK).
  942. The PLL and system clock (SCLK), however, continue to operate in
  943. this mode. Typically an external event or RTC activity will wake
  944. up the processor. When in the sleep mode, system DMA access to L1
  945. memory is not supported.
  946. If unsure, select "Sleep Deeper".
  947. endchoice
  948. config PM_WAKEUP_BY_GPIO
  949. bool "Allow Wakeup from Standby by GPIO"
  950. depends on PM && !BF54x
  951. config PM_WAKEUP_GPIO_NUMBER
  952. int "GPIO number"
  953. range 0 47
  954. depends on PM_WAKEUP_BY_GPIO
  955. default 2
  956. choice
  957. prompt "GPIO Polarity"
  958. depends on PM_WAKEUP_BY_GPIO
  959. default PM_WAKEUP_GPIO_POLAR_H
  960. config PM_WAKEUP_GPIO_POLAR_H
  961. bool "Active High"
  962. config PM_WAKEUP_GPIO_POLAR_L
  963. bool "Active Low"
  964. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  965. bool "Falling EDGE"
  966. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  967. bool "Rising EDGE"
  968. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  969. bool "Both EDGE"
  970. endchoice
  971. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  972. depends on PM
  973. config PM_BFIN_WAKE_PH6
  974. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  975. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  976. default n
  977. help
  978. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  979. config PM_BFIN_WAKE_GP
  980. bool "Allow Wake-Up from GPIOs"
  981. depends on PM && BF54x
  982. default n
  983. help
  984. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  985. (all processors, except ADSP-BF549). This option sets
  986. the general-purpose wake-up enable (GPWE) control bit to enable
  987. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  988. On ADSP-BF549 this option enables the the same functionality on the
  989. /MRXON pin also PH7.
  990. endmenu
  991. menu "CPU Frequency scaling"
  992. depends on !SMP
  993. source "drivers/cpufreq/Kconfig"
  994. config BFIN_CPU_FREQ
  995. bool
  996. depends on CPU_FREQ
  997. select CPU_FREQ_TABLE
  998. default y
  999. config CPU_VOLTAGE
  1000. bool "CPU Voltage scaling"
  1001. depends on EXPERIMENTAL
  1002. depends on CPU_FREQ
  1003. default n
  1004. help
  1005. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1006. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1007. manuals. There is a theoretical risk that during VDDINT transitions
  1008. the PLL may unlock.
  1009. endmenu
  1010. source "net/Kconfig"
  1011. source "drivers/Kconfig"
  1012. source "drivers/firmware/Kconfig"
  1013. source "fs/Kconfig"
  1014. source "arch/blackfin/Kconfig.debug"
  1015. source "security/Kconfig"
  1016. source "crypto/Kconfig"
  1017. source "lib/Kconfig"