i915_gem_context.c 18 KB

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  1. /*
  2. * Copyright © 2011-2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. /*
  28. * This file implements HW context support. On gen5+ a HW context consists of an
  29. * opaque GPU object which is referenced at times of context saves and restores.
  30. * With RC6 enabled, the context is also referenced as the GPU enters and exists
  31. * from RC6 (GPU has it's own internal power context, except on gen5). Though
  32. * something like a context does exist for the media ring, the code only
  33. * supports contexts for the render ring.
  34. *
  35. * In software, there is a distinction between contexts created by the user,
  36. * and the default HW context. The default HW context is used by GPU clients
  37. * that do not request setup of their own hardware context. The default
  38. * context's state is never restored to help prevent programming errors. This
  39. * would happen if a client ran and piggy-backed off another clients GPU state.
  40. * The default context only exists to give the GPU some offset to load as the
  41. * current to invoke a save of the context we actually care about. In fact, the
  42. * code could likely be constructed, albeit in a more complicated fashion, to
  43. * never use the default context, though that limits the driver's ability to
  44. * swap out, and/or destroy other contexts.
  45. *
  46. * All other contexts are created as a request by the GPU client. These contexts
  47. * store GPU state, and thus allow GPU clients to not re-emit state (and
  48. * potentially query certain state) at any time. The kernel driver makes
  49. * certain that the appropriate commands are inserted.
  50. *
  51. * The context life cycle is semi-complicated in that context BOs may live
  52. * longer than the context itself because of the way the hardware, and object
  53. * tracking works. Below is a very crude representation of the state machine
  54. * describing the context life.
  55. * refcount pincount active
  56. * S0: initial state 0 0 0
  57. * S1: context created 1 0 0
  58. * S2: context is currently running 2 1 X
  59. * S3: GPU referenced, but not current 2 0 1
  60. * S4: context is current, but destroyed 1 1 0
  61. * S5: like S3, but destroyed 1 0 1
  62. *
  63. * The most common (but not all) transitions:
  64. * S0->S1: client creates a context
  65. * S1->S2: client submits execbuf with context
  66. * S2->S3: other clients submits execbuf with context
  67. * S3->S1: context object was retired
  68. * S3->S2: clients submits another execbuf
  69. * S2->S4: context destroy called with current context
  70. * S3->S5->S0: destroy path
  71. * S4->S5->S0: destroy path on current context
  72. *
  73. * There are two confusing terms used above:
  74. * The "current context" means the context which is currently running on the
  75. * GPU. The GPU has loaded its state already and has stored away the gtt
  76. * offset of the BO. The GPU is not actively referencing the data at this
  77. * offset, but it will on the next context switch. The only way to avoid this
  78. * is to do a GPU reset.
  79. *
  80. * An "active context' is one which was previously the "current context" and is
  81. * on the active list waiting for the next context switch to occur. Until this
  82. * happens, the object must remain at the same gtt offset. It is therefore
  83. * possible to destroy a context, but it is still active.
  84. *
  85. */
  86. #include <drm/drmP.h>
  87. #include <drm/i915_drm.h>
  88. #include "i915_drv.h"
  89. /* This is a HW constraint. The value below is the largest known requirement
  90. * I've seen in a spec to date, and that was a workaround for a non-shipping
  91. * part. It should be safe to decrease this, but it's more future proof as is.
  92. */
  93. #define CONTEXT_ALIGN (64<<10)
  94. static struct i915_hw_context *
  95. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
  96. static int do_switch(struct i915_hw_context *to);
  97. static int get_context_size(struct drm_device *dev)
  98. {
  99. struct drm_i915_private *dev_priv = dev->dev_private;
  100. int ret;
  101. u32 reg;
  102. switch (INTEL_INFO(dev)->gen) {
  103. case 6:
  104. reg = I915_READ(CXT_SIZE);
  105. ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
  106. break;
  107. case 7:
  108. reg = I915_READ(GEN7_CXT_SIZE);
  109. if (IS_HASWELL(dev))
  110. ret = HSW_CXT_TOTAL_SIZE;
  111. else
  112. ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
  113. break;
  114. case 8:
  115. ret = GEN8_CXT_TOTAL_SIZE;
  116. break;
  117. default:
  118. BUG();
  119. }
  120. return ret;
  121. }
  122. void i915_gem_context_free(struct kref *ctx_ref)
  123. {
  124. struct i915_hw_context *ctx = container_of(ctx_ref,
  125. typeof(*ctx), ref);
  126. list_del(&ctx->link);
  127. drm_gem_object_unreference(&ctx->obj->base);
  128. kfree(ctx);
  129. }
  130. static struct i915_hw_context *
  131. create_hw_context(struct drm_device *dev,
  132. struct drm_i915_file_private *file_priv)
  133. {
  134. struct drm_i915_private *dev_priv = dev->dev_private;
  135. struct i915_hw_context *ctx;
  136. int ret;
  137. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  138. if (ctx == NULL)
  139. return ERR_PTR(-ENOMEM);
  140. kref_init(&ctx->ref);
  141. ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
  142. INIT_LIST_HEAD(&ctx->link);
  143. if (ctx->obj == NULL) {
  144. kfree(ctx);
  145. DRM_DEBUG_DRIVER("Context object allocated failed\n");
  146. return ERR_PTR(-ENOMEM);
  147. }
  148. if (INTEL_INFO(dev)->gen >= 7) {
  149. ret = i915_gem_object_set_cache_level(ctx->obj,
  150. I915_CACHE_L3_LLC);
  151. /* Failure shouldn't ever happen this early */
  152. if (WARN_ON(ret))
  153. goto err_out;
  154. }
  155. /* The ring associated with the context object is handled by the normal
  156. * object tracking code. We give an initial ring value simple to pass an
  157. * assertion in the context switch code.
  158. */
  159. ctx->ring = &dev_priv->ring[RCS];
  160. list_add_tail(&ctx->link, &dev_priv->context_list);
  161. /* Default context will never have a file_priv */
  162. if (file_priv == NULL)
  163. return ctx;
  164. ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0,
  165. GFP_KERNEL);
  166. if (ret < 0)
  167. goto err_out;
  168. ctx->file_priv = file_priv;
  169. ctx->id = ret;
  170. /* NB: Mark all slices as needing a remap so that when the context first
  171. * loads it will restore whatever remap state already exists. If there
  172. * is no remap info, it will be a NOP. */
  173. ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
  174. return ctx;
  175. err_out:
  176. i915_gem_context_unreference(ctx);
  177. return ERR_PTR(ret);
  178. }
  179. static inline bool is_default_context(struct i915_hw_context *ctx)
  180. {
  181. return (ctx == ctx->ring->default_context);
  182. }
  183. /**
  184. * The default context needs to exist per ring that uses contexts. It stores the
  185. * context state of the GPU for applications that don't utilize HW contexts, as
  186. * well as an idle case.
  187. */
  188. static int create_default_context(struct drm_i915_private *dev_priv)
  189. {
  190. struct i915_hw_context *ctx;
  191. int ret;
  192. BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  193. ctx = create_hw_context(dev_priv->dev, NULL);
  194. if (IS_ERR(ctx))
  195. return PTR_ERR(ctx);
  196. /* We may need to do things with the shrinker which require us to
  197. * immediately switch back to the default context. This can cause a
  198. * problem as pinning the default context also requires GTT space which
  199. * may not be available. To avoid this we always pin the
  200. * default context.
  201. */
  202. ret = i915_gem_obj_ggtt_pin(ctx->obj, CONTEXT_ALIGN, false, false);
  203. if (ret) {
  204. DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
  205. goto err_destroy;
  206. }
  207. ret = do_switch(ctx);
  208. if (ret) {
  209. DRM_DEBUG_DRIVER("Switch failed %d\n", ret);
  210. goto err_unpin;
  211. }
  212. dev_priv->ring[RCS].default_context = ctx;
  213. DRM_DEBUG_DRIVER("Default HW context loaded\n");
  214. return 0;
  215. err_unpin:
  216. i915_gem_object_unpin(ctx->obj);
  217. err_destroy:
  218. i915_gem_context_unreference(ctx);
  219. return ret;
  220. }
  221. void i915_gem_context_init(struct drm_device *dev)
  222. {
  223. struct drm_i915_private *dev_priv = dev->dev_private;
  224. if (!HAS_HW_CONTEXTS(dev)) {
  225. dev_priv->hw_contexts_disabled = true;
  226. DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
  227. return;
  228. }
  229. /* If called from reset, or thaw... we've been here already */
  230. if (dev_priv->hw_contexts_disabled ||
  231. dev_priv->ring[RCS].default_context)
  232. return;
  233. dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
  234. if (dev_priv->hw_context_size > (1<<20)) {
  235. dev_priv->hw_contexts_disabled = true;
  236. DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
  237. return;
  238. }
  239. if (create_default_context(dev_priv)) {
  240. dev_priv->hw_contexts_disabled = true;
  241. DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n");
  242. return;
  243. }
  244. DRM_DEBUG_DRIVER("HW context support initialized\n");
  245. }
  246. void i915_gem_context_fini(struct drm_device *dev)
  247. {
  248. struct drm_i915_private *dev_priv = dev->dev_private;
  249. struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
  250. if (dev_priv->hw_contexts_disabled)
  251. return;
  252. /* The only known way to stop the gpu from accessing the hw context is
  253. * to reset it. Do this as the very last operation to avoid confusing
  254. * other code, leading to spurious errors. */
  255. intel_gpu_reset(dev);
  256. /* When default context is created and switched to, base object refcount
  257. * will be 2 (+1 from object creation and +1 from do_switch()).
  258. * i915_gem_context_fini() will be called after gpu_idle() has switched
  259. * to default context. So we need to unreference the base object once
  260. * to offset the do_switch part, so that i915_gem_context_unreference()
  261. * can then free the base object correctly. */
  262. WARN_ON(!dev_priv->ring[RCS].last_context);
  263. if (dev_priv->ring[RCS].last_context == dctx) {
  264. /* Fake switch to NULL context */
  265. WARN_ON(dctx->obj->active);
  266. i915_gem_object_unpin(dctx->obj);
  267. i915_gem_context_unreference(dctx);
  268. }
  269. i915_gem_object_unpin(dctx->obj);
  270. i915_gem_context_unreference(dctx);
  271. dev_priv->ring[RCS].default_context = NULL;
  272. dev_priv->ring[RCS].last_context = NULL;
  273. }
  274. static int context_idr_cleanup(int id, void *p, void *data)
  275. {
  276. struct i915_hw_context *ctx = p;
  277. BUG_ON(id == DEFAULT_CONTEXT_ID);
  278. i915_gem_context_unreference(ctx);
  279. return 0;
  280. }
  281. struct i915_ctx_hang_stats *
  282. i915_gem_context_get_hang_stats(struct drm_device *dev,
  283. struct drm_file *file,
  284. u32 id)
  285. {
  286. struct drm_i915_private *dev_priv = dev->dev_private;
  287. struct drm_i915_file_private *file_priv = file->driver_priv;
  288. struct i915_hw_context *ctx;
  289. if (id == DEFAULT_CONTEXT_ID)
  290. return &file_priv->hang_stats;
  291. ctx = NULL;
  292. if (!dev_priv->hw_contexts_disabled)
  293. ctx = i915_gem_context_get(file->driver_priv, id);
  294. if (ctx == NULL)
  295. return ERR_PTR(-ENOENT);
  296. return &ctx->hang_stats;
  297. }
  298. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
  299. {
  300. struct drm_i915_file_private *file_priv = file->driver_priv;
  301. idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  302. idr_destroy(&file_priv->context_idr);
  303. }
  304. static struct i915_hw_context *
  305. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
  306. {
  307. return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
  308. }
  309. static inline int
  310. mi_set_context(struct intel_ring_buffer *ring,
  311. struct i915_hw_context *new_context,
  312. u32 hw_flags)
  313. {
  314. int ret;
  315. /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
  316. * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
  317. * explicitly, so we rely on the value at ring init, stored in
  318. * itlb_before_ctx_switch.
  319. */
  320. if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
  321. ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
  322. if (ret)
  323. return ret;
  324. }
  325. ret = intel_ring_begin(ring, 6);
  326. if (ret)
  327. return ret;
  328. /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
  329. if (IS_GEN7(ring->dev))
  330. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
  331. else
  332. intel_ring_emit(ring, MI_NOOP);
  333. intel_ring_emit(ring, MI_NOOP);
  334. intel_ring_emit(ring, MI_SET_CONTEXT);
  335. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
  336. MI_MM_SPACE_GTT |
  337. MI_SAVE_EXT_STATE_EN |
  338. MI_RESTORE_EXT_STATE_EN |
  339. hw_flags);
  340. /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
  341. intel_ring_emit(ring, MI_NOOP);
  342. if (IS_GEN7(ring->dev))
  343. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
  344. else
  345. intel_ring_emit(ring, MI_NOOP);
  346. intel_ring_advance(ring);
  347. return ret;
  348. }
  349. static int do_switch(struct i915_hw_context *to)
  350. {
  351. struct intel_ring_buffer *ring = to->ring;
  352. struct i915_hw_context *from = ring->last_context;
  353. u32 hw_flags = 0;
  354. int ret, i;
  355. BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
  356. if (from == to && !to->remap_slice)
  357. return 0;
  358. ret = i915_gem_obj_ggtt_pin(to->obj, CONTEXT_ALIGN, false, false);
  359. if (ret)
  360. return ret;
  361. /* Clear this page out of any CPU caches for coherent swap-in/out. Note
  362. * that thanks to write = false in this call and us not setting any gpu
  363. * write domains when putting a context object onto the active list
  364. * (when switching away from it), this won't block.
  365. * XXX: We need a real interface to do this instead of trickery. */
  366. ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
  367. if (ret) {
  368. i915_gem_object_unpin(to->obj);
  369. return ret;
  370. }
  371. if (!to->obj->has_global_gtt_mapping)
  372. i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
  373. if (!to->is_initialized || is_default_context(to))
  374. hw_flags |= MI_RESTORE_INHIBIT;
  375. ret = mi_set_context(ring, to, hw_flags);
  376. if (ret) {
  377. i915_gem_object_unpin(to->obj);
  378. return ret;
  379. }
  380. for (i = 0; i < MAX_L3_SLICES; i++) {
  381. if (!(to->remap_slice & (1<<i)))
  382. continue;
  383. ret = i915_gem_l3_remap(ring, i);
  384. /* If it failed, try again next round */
  385. if (ret)
  386. DRM_DEBUG_DRIVER("L3 remapping failed\n");
  387. else
  388. to->remap_slice &= ~(1<<i);
  389. }
  390. /* The backing object for the context is done after switching to the
  391. * *next* context. Therefore we cannot retire the previous context until
  392. * the next context has already started running. In fact, the below code
  393. * is a bit suboptimal because the retiring can occur simply after the
  394. * MI_SET_CONTEXT instead of when the next seqno has completed.
  395. */
  396. if (from != NULL) {
  397. from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
  398. i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
  399. /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
  400. * whole damn pipeline, we don't need to explicitly mark the
  401. * object dirty. The only exception is that the context must be
  402. * correct in case the object gets swapped out. Ideally we'd be
  403. * able to defer doing this until we know the object would be
  404. * swapped, but there is no way to do that yet.
  405. */
  406. from->obj->dirty = 1;
  407. BUG_ON(from->obj->ring != ring);
  408. /* obj is kept alive until the next request by its active ref */
  409. i915_gem_object_unpin(from->obj);
  410. i915_gem_context_unreference(from);
  411. }
  412. i915_gem_context_reference(to);
  413. ring->last_context = to;
  414. to->is_initialized = true;
  415. return 0;
  416. }
  417. /**
  418. * i915_switch_context() - perform a GPU context switch.
  419. * @ring: ring for which we'll execute the context switch
  420. * @file_priv: file_priv associated with the context, may be NULL
  421. * @id: context id number
  422. * @seqno: sequence number by which the new context will be switched to
  423. * @flags:
  424. *
  425. * The context life cycle is simple. The context refcount is incremented and
  426. * decremented by 1 and create and destroy. If the context is in use by the GPU,
  427. * it will have a refoucnt > 1. This allows us to destroy the context abstract
  428. * object while letting the normal object tracking destroy the backing BO.
  429. */
  430. int i915_switch_context(struct intel_ring_buffer *ring,
  431. struct drm_file *file,
  432. int to_id)
  433. {
  434. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  435. struct i915_hw_context *to;
  436. if (dev_priv->hw_contexts_disabled)
  437. return 0;
  438. WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  439. if (ring != &dev_priv->ring[RCS])
  440. return 0;
  441. if (to_id == DEFAULT_CONTEXT_ID) {
  442. to = ring->default_context;
  443. } else {
  444. if (file == NULL)
  445. return -EINVAL;
  446. to = i915_gem_context_get(file->driver_priv, to_id);
  447. if (to == NULL)
  448. return -ENOENT;
  449. }
  450. return do_switch(to);
  451. }
  452. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  453. struct drm_file *file)
  454. {
  455. struct drm_i915_private *dev_priv = dev->dev_private;
  456. struct drm_i915_gem_context_create *args = data;
  457. struct drm_i915_file_private *file_priv = file->driver_priv;
  458. struct i915_hw_context *ctx;
  459. int ret;
  460. if (!(dev->driver->driver_features & DRIVER_GEM))
  461. return -ENODEV;
  462. if (dev_priv->hw_contexts_disabled)
  463. return -ENODEV;
  464. ret = i915_mutex_lock_interruptible(dev);
  465. if (ret)
  466. return ret;
  467. ctx = create_hw_context(dev, file_priv);
  468. mutex_unlock(&dev->struct_mutex);
  469. if (IS_ERR(ctx))
  470. return PTR_ERR(ctx);
  471. args->ctx_id = ctx->id;
  472. DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
  473. return 0;
  474. }
  475. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  476. struct drm_file *file)
  477. {
  478. struct drm_i915_gem_context_destroy *args = data;
  479. struct drm_i915_file_private *file_priv = file->driver_priv;
  480. struct i915_hw_context *ctx;
  481. int ret;
  482. if (!(dev->driver->driver_features & DRIVER_GEM))
  483. return -ENODEV;
  484. ret = i915_mutex_lock_interruptible(dev);
  485. if (ret)
  486. return ret;
  487. ctx = i915_gem_context_get(file_priv, args->ctx_id);
  488. if (!ctx) {
  489. mutex_unlock(&dev->struct_mutex);
  490. return -ENOENT;
  491. }
  492. idr_remove(&ctx->file_priv->context_idr, ctx->id);
  493. i915_gem_context_unreference(ctx);
  494. mutex_unlock(&dev->struct_mutex);
  495. DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
  496. return 0;
  497. }