netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. unsigned long last_schedule_time;
  43. #define NETXEN_MAX_CRB_XFORM 60
  44. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  45. #define NETXEN_ADDR_ERROR (0xffffffff)
  46. #define crb_addr_transform(name) \
  47. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  48. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  49. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  50. static inline void
  51. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  52. unsigned long off, int *data)
  53. {
  54. void __iomem *addr = pci_base_offset(adapter, off);
  55. writel(*data, addr);
  56. }
  57. static void crb_addr_transform_setup(void)
  58. {
  59. crb_addr_transform(XDMA);
  60. crb_addr_transform(TIMR);
  61. crb_addr_transform(SRE);
  62. crb_addr_transform(SQN3);
  63. crb_addr_transform(SQN2);
  64. crb_addr_transform(SQN1);
  65. crb_addr_transform(SQN0);
  66. crb_addr_transform(SQS3);
  67. crb_addr_transform(SQS2);
  68. crb_addr_transform(SQS1);
  69. crb_addr_transform(SQS0);
  70. crb_addr_transform(RPMX7);
  71. crb_addr_transform(RPMX6);
  72. crb_addr_transform(RPMX5);
  73. crb_addr_transform(RPMX4);
  74. crb_addr_transform(RPMX3);
  75. crb_addr_transform(RPMX2);
  76. crb_addr_transform(RPMX1);
  77. crb_addr_transform(RPMX0);
  78. crb_addr_transform(ROMUSB);
  79. crb_addr_transform(SN);
  80. crb_addr_transform(QMN);
  81. crb_addr_transform(QMS);
  82. crb_addr_transform(PGNI);
  83. crb_addr_transform(PGND);
  84. crb_addr_transform(PGN3);
  85. crb_addr_transform(PGN2);
  86. crb_addr_transform(PGN1);
  87. crb_addr_transform(PGN0);
  88. crb_addr_transform(PGSI);
  89. crb_addr_transform(PGSD);
  90. crb_addr_transform(PGS3);
  91. crb_addr_transform(PGS2);
  92. crb_addr_transform(PGS1);
  93. crb_addr_transform(PGS0);
  94. crb_addr_transform(PS);
  95. crb_addr_transform(PH);
  96. crb_addr_transform(NIU);
  97. crb_addr_transform(I2Q);
  98. crb_addr_transform(EG);
  99. crb_addr_transform(MN);
  100. crb_addr_transform(MS);
  101. crb_addr_transform(CAS2);
  102. crb_addr_transform(CAS1);
  103. crb_addr_transform(CAS0);
  104. crb_addr_transform(CAM);
  105. crb_addr_transform(C2C1);
  106. crb_addr_transform(C2C0);
  107. crb_addr_transform(SMB);
  108. }
  109. int netxen_init_firmware(struct netxen_adapter *adapter)
  110. {
  111. u32 state = 0, loops = 0, err = 0;
  112. /* Window 1 call */
  113. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  114. if (state == PHAN_INITIALIZE_ACK)
  115. return 0;
  116. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  117. udelay(100);
  118. /* Window 1 call */
  119. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  120. loops++;
  121. }
  122. if (loops >= 2000) {
  123. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  124. state);
  125. err = -EIO;
  126. return err;
  127. }
  128. /* Window 1 call */
  129. writel(MPORT_MULTI_FUNCTION_MODE,
  130. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  131. writel(PHAN_INITIALIZE_ACK,
  132. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  133. return err;
  134. }
  135. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  136. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  137. struct pci_dev **used_dev)
  138. {
  139. void *addr;
  140. addr = pci_alloc_consistent(pdev, sz, ptr);
  141. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  142. *used_dev = pdev;
  143. return addr;
  144. }
  145. pci_free_consistent(pdev, sz, addr, *ptr);
  146. addr = pci_alloc_consistent(NULL, sz, ptr);
  147. *used_dev = NULL;
  148. return addr;
  149. }
  150. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  151. {
  152. int ctxid, ring;
  153. u32 i;
  154. u32 num_rx_bufs = 0;
  155. struct netxen_rcv_desc_ctx *rcv_desc;
  156. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  157. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  158. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  159. struct netxen_rx_buffer *rx_buf;
  160. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  161. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  162. rcv_desc->begin_alloc = 0;
  163. rx_buf = rcv_desc->rx_buf_arr;
  164. num_rx_bufs = rcv_desc->max_rx_desc_count;
  165. /*
  166. * Now go through all of them, set reference handles
  167. * and put them in the queues.
  168. */
  169. for (i = 0; i < num_rx_bufs; i++) {
  170. rx_buf->ref_handle = i;
  171. rx_buf->state = NETXEN_BUFFER_FREE;
  172. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  173. "%p\n", ctxid, i, rx_buf);
  174. rx_buf++;
  175. }
  176. }
  177. }
  178. }
  179. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  180. {
  181. int ports = 0;
  182. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  183. if (netxen_nic_get_board_info(adapter) != 0)
  184. printk("%s: Error getting board config info.\n",
  185. netxen_nic_driver_name);
  186. get_brd_port_by_type(board_info->board_type, &ports);
  187. if (ports == 0)
  188. printk(KERN_ERR "%s: Unknown board type\n",
  189. netxen_nic_driver_name);
  190. adapter->ahw.max_ports = ports;
  191. }
  192. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  193. {
  194. switch (adapter->ahw.board_type) {
  195. case NETXEN_NIC_GBE:
  196. adapter->enable_phy_interrupts =
  197. netxen_niu_gbe_enable_phy_interrupts;
  198. adapter->disable_phy_interrupts =
  199. netxen_niu_gbe_disable_phy_interrupts;
  200. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  201. adapter->macaddr_set = netxen_niu_macaddr_set;
  202. adapter->set_mtu = netxen_nic_set_mtu_gb;
  203. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  205. adapter->phy_read = netxen_niu_gbe_phy_read;
  206. adapter->phy_write = netxen_niu_gbe_phy_write;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. u32 netxen_decode_crb_addr(u32 addr)
  232. {
  233. int i;
  234. u32 base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 100;
  251. static long rom_lock_timeout = 10000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. if (jiffies > (last_schedule_time + (8 * HZ))) {
  365. last_schedule_time = jiffies;
  366. schedule();
  367. }
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  369. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  370. udelay(100); /* prevent bursting on CRB */
  371. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  372. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  373. if (netxen_wait_rom_done(adapter)) {
  374. printk("Error waiting for rom done\n");
  375. return -EIO;
  376. }
  377. /* reset abyte_cnt and dummy_byte_cnt */
  378. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  379. udelay(100); /* prevent bursting on CRB */
  380. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  381. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  382. return 0;
  383. }
  384. static inline int
  385. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  386. u8 *bytes, size_t size)
  387. {
  388. int addridx;
  389. int ret = 0;
  390. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  391. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  392. if (ret != 0)
  393. break;
  394. *(int *)bytes = cpu_to_le32(*(int *)bytes);
  395. bytes += 4;
  396. }
  397. return ret;
  398. }
  399. int
  400. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  401. u8 *bytes, size_t size)
  402. {
  403. int ret;
  404. ret = rom_lock(adapter);
  405. if (ret < 0)
  406. return ret;
  407. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  408. netxen_rom_unlock(adapter);
  409. return ret;
  410. }
  411. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  412. {
  413. int ret;
  414. if (rom_lock(adapter) != 0)
  415. return -EIO;
  416. ret = do_rom_fast_read(adapter, addr, valp);
  417. netxen_rom_unlock(adapter);
  418. return ret;
  419. }
  420. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  421. {
  422. int ret = 0;
  423. if (rom_lock(adapter) != 0) {
  424. return -1;
  425. }
  426. ret = do_rom_fast_write(adapter, addr, data);
  427. netxen_rom_unlock(adapter);
  428. return ret;
  429. }
  430. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  431. int addr, u8 *bytes, size_t size)
  432. {
  433. int addridx = addr;
  434. int ret = 0;
  435. while (addridx < (addr + size)) {
  436. int last_attempt = 0;
  437. int timeout = 0;
  438. int data;
  439. data = le32_to_cpu((*(u32*)bytes));
  440. ret = do_rom_fast_write(adapter, addridx, data);
  441. if (ret < 0)
  442. return ret;
  443. while(1) {
  444. int data1;
  445. ret = do_rom_fast_read(adapter, addridx, &data1);
  446. if (ret < 0)
  447. return ret;
  448. if (data1 == data)
  449. break;
  450. if (timeout++ >= rom_write_timeout) {
  451. if (last_attempt++ < 4) {
  452. ret = do_rom_fast_write(adapter,
  453. addridx, data);
  454. if (ret < 0)
  455. return ret;
  456. }
  457. else {
  458. printk(KERN_INFO "Data write did not "
  459. "succeed at address 0x%x\n", addridx);
  460. break;
  461. }
  462. }
  463. }
  464. bytes += 4;
  465. addridx += 4;
  466. }
  467. return ret;
  468. }
  469. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  470. u8 *bytes, size_t size)
  471. {
  472. int ret = 0;
  473. ret = rom_lock(adapter);
  474. if (ret < 0)
  475. return ret;
  476. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  477. netxen_rom_unlock(adapter);
  478. return ret;
  479. }
  480. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  481. {
  482. int ret;
  483. ret = netxen_rom_wren(adapter);
  484. if (ret < 0)
  485. return ret;
  486. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  487. netxen_crb_writelit_adapter(adapter,
  488. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  489. ret = netxen_wait_rom_done(adapter);
  490. if (ret < 0)
  491. return ret;
  492. return netxen_rom_wip_poll(adapter);
  493. }
  494. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  495. {
  496. int ret;
  497. ret = rom_lock(adapter);
  498. if (ret < 0)
  499. return ret;
  500. ret = netxen_do_rom_rdsr(adapter);
  501. netxen_rom_unlock(adapter);
  502. return ret;
  503. }
  504. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  505. {
  506. int ret = FLASH_SUCCESS;
  507. int val;
  508. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  509. if (!buffer)
  510. return -ENOMEM;
  511. /* unlock sector 63 */
  512. val = netxen_rom_rdsr(adapter);
  513. val = val & 0xe3;
  514. ret = netxen_rom_wrsr(adapter, val);
  515. if (ret != FLASH_SUCCESS)
  516. goto out_kfree;
  517. ret = netxen_rom_wip_poll(adapter);
  518. if (ret != FLASH_SUCCESS)
  519. goto out_kfree;
  520. /* copy sector 0 to sector 63 */
  521. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  522. buffer, NETXEN_FLASH_SECTOR_SIZE);
  523. if (ret != FLASH_SUCCESS)
  524. goto out_kfree;
  525. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  526. buffer, NETXEN_FLASH_SECTOR_SIZE);
  527. if (ret != FLASH_SUCCESS)
  528. goto out_kfree;
  529. /* lock sector 63 */
  530. val = netxen_rom_rdsr(adapter);
  531. if (!(val & 0x8)) {
  532. val |= (0x1 << 2);
  533. /* lock sector 63 */
  534. if (netxen_rom_wrsr(adapter, val) == 0) {
  535. ret = netxen_rom_wip_poll(adapter);
  536. if (ret != FLASH_SUCCESS)
  537. goto out_kfree;
  538. /* lock SR writes */
  539. ret = netxen_rom_wip_poll(adapter);
  540. if (ret != FLASH_SUCCESS)
  541. goto out_kfree;
  542. }
  543. }
  544. out_kfree:
  545. kfree(buffer);
  546. return ret;
  547. }
  548. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  549. {
  550. netxen_rom_wren(adapter);
  551. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  552. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  553. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  554. M25P_INSTR_SE);
  555. if (netxen_wait_rom_done(adapter)) {
  556. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  557. return -1;
  558. }
  559. return netxen_rom_wip_poll(adapter);
  560. }
  561. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  562. {
  563. int i;
  564. int val;
  565. int count = 0, erased_errors = 0;
  566. int range;
  567. range = (addr == NETXEN_USER_START) ?
  568. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  569. for (i = addr; i < range; i += 4) {
  570. netxen_rom_fast_read(adapter, i, &val);
  571. if (val != 0xffffffff)
  572. erased_errors++;
  573. count++;
  574. }
  575. if (erased_errors)
  576. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  577. "for sector address: %x\n", erased_errors, count, addr);
  578. }
  579. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  580. {
  581. int ret = 0;
  582. if (rom_lock(adapter) != 0) {
  583. return -1;
  584. }
  585. ret = netxen_do_rom_se(adapter, addr);
  586. netxen_rom_unlock(adapter);
  587. msleep(30);
  588. check_erased_flash(adapter, addr);
  589. return ret;
  590. }
  591. int
  592. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  593. {
  594. int ret = FLASH_SUCCESS;
  595. int i;
  596. for (i = start; i < end; i++) {
  597. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  598. if (ret)
  599. break;
  600. ret = netxen_rom_wip_poll(adapter);
  601. if (ret < 0)
  602. return ret;
  603. }
  604. return ret;
  605. }
  606. int
  607. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  608. {
  609. int ret = FLASH_SUCCESS;
  610. int start, end;
  611. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  612. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  613. ret = netxen_flash_erase_sections(adapter, start, end);
  614. return ret;
  615. }
  616. int
  617. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  618. {
  619. int ret = FLASH_SUCCESS;
  620. int start, end;
  621. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  622. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  623. ret = netxen_flash_erase_sections(adapter, start, end);
  624. return ret;
  625. }
  626. void netxen_halt_pegs(struct netxen_adapter *adapter)
  627. {
  628. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  629. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  630. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  631. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  632. }
  633. int netxen_flash_unlock(struct netxen_adapter *adapter)
  634. {
  635. int ret = 0;
  636. ret = netxen_rom_wrsr(adapter, 0);
  637. if (ret < 0)
  638. return ret;
  639. ret = netxen_rom_wren(adapter);
  640. if (ret < 0)
  641. return ret;
  642. return ret;
  643. }
  644. #define NETXEN_BOARDTYPE 0x4008
  645. #define NETXEN_BOARDNUM 0x400c
  646. #define NETXEN_CHIPNUM 0x4010
  647. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  648. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  649. #define NETXEN_ROM_FOUND_INIT 0x400
  650. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  651. {
  652. int addr, val, status;
  653. int n, i;
  654. int init_delay = 0;
  655. struct crb_addr_pair *buf;
  656. u32 off;
  657. /* resetall */
  658. status = netxen_nic_get_board_info(adapter);
  659. if (status)
  660. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  661. netxen_nic_driver_name);
  662. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  663. NETXEN_ROMBUS_RESET);
  664. if (verbose) {
  665. int val;
  666. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  667. printk("P2 ROM board type: 0x%08x\n", val);
  668. else
  669. printk("Could not read board type\n");
  670. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  671. printk("P2 ROM board num: 0x%08x\n", val);
  672. else
  673. printk("Could not read board number\n");
  674. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  675. printk("P2 ROM chip num: 0x%08x\n", val);
  676. else
  677. printk("Could not read chip number\n");
  678. }
  679. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  680. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  681. n &= ~NETXEN_ROM_ROUNDUP;
  682. if (n < NETXEN_ROM_FOUND_INIT) {
  683. if (verbose)
  684. printk("%s: %d CRB init values found"
  685. " in ROM.\n", netxen_nic_driver_name, n);
  686. } else {
  687. printk("%s:n=0x%x Error! NetXen card flash not"
  688. " initialized.\n", __FUNCTION__, n);
  689. return -EIO;
  690. }
  691. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  692. if (buf == NULL) {
  693. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  694. "memory.\n", netxen_nic_driver_name);
  695. return -ENOMEM;
  696. }
  697. for (i = 0; i < n; i++) {
  698. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  699. || netxen_rom_fast_read(adapter, 8 * i + 8,
  700. &addr) != 0)
  701. return -EIO;
  702. buf[i].addr = addr;
  703. buf[i].data = val;
  704. if (verbose)
  705. printk("%s: PCI: 0x%08x == 0x%08x\n",
  706. netxen_nic_driver_name, (unsigned int)
  707. netxen_decode_crb_addr(addr), val);
  708. }
  709. for (i = 0; i < n; i++) {
  710. off = netxen_decode_crb_addr(buf[i].addr);
  711. if (off == NETXEN_ADDR_ERROR) {
  712. printk(KERN_ERR"CRB init value out of range %x\n",
  713. buf[i].addr);
  714. continue;
  715. }
  716. off += NETXEN_PCI_CRBSPACE;
  717. /* skipping cold reboot MAGIC */
  718. if (off == NETXEN_CAM_RAM(0x1fc))
  719. continue;
  720. /* After writing this register, HW needs time for CRB */
  721. /* to quiet down (else crb_window returns 0xffffffff) */
  722. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  723. init_delay = 1;
  724. /* hold xdma in reset also */
  725. buf[i].data = NETXEN_NIC_XDMA_RESET;
  726. }
  727. if (ADDR_IN_WINDOW1(off)) {
  728. writel(buf[i].data,
  729. NETXEN_CRB_NORMALIZE(adapter, off));
  730. } else {
  731. netxen_nic_pci_change_crbwindow(adapter, 0);
  732. writel(buf[i].data,
  733. pci_base_offset(adapter, off));
  734. netxen_nic_pci_change_crbwindow(adapter, 1);
  735. }
  736. if (init_delay == 1) {
  737. ssleep(1);
  738. init_delay = 0;
  739. }
  740. msleep(1);
  741. }
  742. kfree(buf);
  743. /* disable_peg_cache_all */
  744. /* unreset_net_cache */
  745. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  746. 4);
  747. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  748. (val & 0xffffff0f));
  749. /* p2dn replyCount */
  750. netxen_crb_writelit_adapter(adapter,
  751. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  752. /* disable_peg_cache 0 */
  753. netxen_crb_writelit_adapter(adapter,
  754. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  755. /* disable_peg_cache 1 */
  756. netxen_crb_writelit_adapter(adapter,
  757. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  758. /* peg_clr_all */
  759. /* peg_clr 0 */
  760. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  761. 0);
  762. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  763. 0);
  764. /* peg_clr 1 */
  765. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  766. 0);
  767. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  768. 0);
  769. /* peg_clr 2 */
  770. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  771. 0);
  772. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  773. 0);
  774. /* peg_clr 3 */
  775. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  776. 0);
  777. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  778. 0);
  779. }
  780. return 0;
  781. }
  782. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  783. {
  784. uint64_t addr;
  785. uint32_t hi;
  786. uint32_t lo;
  787. adapter->dummy_dma.addr =
  788. pci_alloc_consistent(adapter->ahw.pdev,
  789. NETXEN_HOST_DUMMY_DMA_SIZE,
  790. &adapter->dummy_dma.phys_addr);
  791. if (adapter->dummy_dma.addr == NULL) {
  792. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  793. __FUNCTION__);
  794. return -ENOMEM;
  795. }
  796. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  797. hi = (addr >> 32) & 0xffffffff;
  798. lo = addr & 0xffffffff;
  799. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  800. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  801. return 0;
  802. }
  803. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  804. {
  805. if (adapter->dummy_dma.addr) {
  806. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  807. CRB_HOST_DUMMY_BUF_ADDR_HI));
  808. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  809. CRB_HOST_DUMMY_BUF_ADDR_LO));
  810. pci_free_consistent(adapter->ahw.pdev,
  811. NETXEN_HOST_DUMMY_DMA_SIZE,
  812. adapter->dummy_dma.addr,
  813. adapter->dummy_dma.phys_addr);
  814. adapter->dummy_dma.addr = NULL;
  815. }
  816. }
  817. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  818. {
  819. u32 val = 0;
  820. int loops = 0;
  821. if (!pegtune_val) {
  822. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  823. while (val != PHAN_INITIALIZE_COMPLETE &&
  824. val != PHAN_INITIALIZE_ACK && loops < 200000) {
  825. udelay(100);
  826. schedule();
  827. val =
  828. readl(NETXEN_CRB_NORMALIZE
  829. (adapter, CRB_CMDPEG_STATE));
  830. loops++;
  831. }
  832. if (val != PHAN_INITIALIZE_COMPLETE)
  833. printk("WARNING: Initial boot wait loop failed...\n");
  834. }
  835. }
  836. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  837. {
  838. int ctx;
  839. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  840. struct netxen_recv_context *recv_ctx =
  841. &(adapter->recv_ctx[ctx]);
  842. u32 consumer;
  843. struct status_desc *desc_head;
  844. struct status_desc *desc;
  845. consumer = recv_ctx->status_rx_consumer;
  846. desc_head = recv_ctx->rcv_status_desc_head;
  847. desc = &desc_head[consumer];
  848. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  849. return 1;
  850. }
  851. return 0;
  852. }
  853. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  854. {
  855. struct net_device *netdev = adapter->netdev;
  856. uint32_t temp, temp_state, temp_val;
  857. int rv = 0;
  858. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  859. temp_state = nx_get_temp_state(temp);
  860. temp_val = nx_get_temp_val(temp);
  861. if (temp_state == NX_TEMP_PANIC) {
  862. printk(KERN_ALERT
  863. "%s: Device temperature %d degrees C exceeds"
  864. " maximum allowed. Hardware has been shut down.\n",
  865. netxen_nic_driver_name, temp_val);
  866. netif_carrier_off(netdev);
  867. netif_stop_queue(netdev);
  868. rv = 1;
  869. } else if (temp_state == NX_TEMP_WARN) {
  870. if (adapter->temp == NX_TEMP_NORMAL) {
  871. printk(KERN_ALERT
  872. "%s: Device temperature %d degrees C "
  873. "exceeds operating range."
  874. " Immediate action needed.\n",
  875. netxen_nic_driver_name, temp_val);
  876. }
  877. } else {
  878. if (adapter->temp == NX_TEMP_WARN) {
  879. printk(KERN_INFO
  880. "%s: Device temperature is now %d degrees C"
  881. " in normal range.\n", netxen_nic_driver_name,
  882. temp_val);
  883. }
  884. }
  885. adapter->temp = temp_state;
  886. return rv;
  887. }
  888. void netxen_watchdog_task(struct work_struct *work)
  889. {
  890. struct net_device *netdev;
  891. struct netxen_adapter *adapter =
  892. container_of(work, struct netxen_adapter, watchdog_task);
  893. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  894. return;
  895. netdev = adapter->netdev;
  896. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  897. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  898. netxen_nic_driver_name, adapter->portnum, netdev->name);
  899. netif_carrier_on(netdev);
  900. }
  901. if (netif_queue_stopped(netdev))
  902. netif_wake_queue(netdev);
  903. if (adapter->handle_phy_intr)
  904. adapter->handle_phy_intr(adapter);
  905. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  906. }
  907. /*
  908. * netxen_process_rcv() send the received packet to the protocol stack.
  909. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  910. * invoke the routine to send more rx buffers to the Phantom...
  911. */
  912. void
  913. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  914. struct status_desc *desc)
  915. {
  916. struct pci_dev *pdev = adapter->pdev;
  917. struct net_device *netdev = adapter->netdev;
  918. int index = netxen_get_sts_refhandle(desc);
  919. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  920. struct netxen_rx_buffer *buffer;
  921. struct sk_buff *skb;
  922. u32 length = netxen_get_sts_totallength(desc);
  923. u32 desc_ctx;
  924. struct netxen_rcv_desc_ctx *rcv_desc;
  925. int ret;
  926. desc_ctx = netxen_get_sts_type(desc);
  927. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  928. printk("%s: %s Bad Rcv descriptor ring\n",
  929. netxen_nic_driver_name, netdev->name);
  930. return;
  931. }
  932. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  933. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  934. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  935. index, rcv_desc->max_rx_desc_count);
  936. return;
  937. }
  938. buffer = &rcv_desc->rx_buf_arr[index];
  939. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  940. buffer->lro_current_frags++;
  941. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  942. buffer->lro_expected_frags =
  943. netxen_get_sts_desc_lro_cnt(desc);
  944. buffer->lro_length = length;
  945. }
  946. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  947. if (buffer->lro_expected_frags != 0) {
  948. printk("LRO: (refhandle:%x) recv frag."
  949. "wait for last. flags: %x expected:%d"
  950. "have:%d\n", index,
  951. netxen_get_sts_desc_lro_last_frag(desc),
  952. buffer->lro_expected_frags,
  953. buffer->lro_current_frags);
  954. }
  955. return;
  956. }
  957. }
  958. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  959. PCI_DMA_FROMDEVICE);
  960. skb = (struct sk_buff *)buffer->skb;
  961. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  962. adapter->stats.csummed++;
  963. skb->ip_summed = CHECKSUM_UNNECESSARY;
  964. }
  965. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  966. /* True length was only available on the last pkt */
  967. skb_put(skb, buffer->lro_length);
  968. } else {
  969. skb_put(skb, length);
  970. }
  971. skb->protocol = eth_type_trans(skb, netdev);
  972. ret = netif_receive_skb(skb);
  973. /*
  974. * RH: Do we need these stats on a regular basis. Can we get it from
  975. * Linux stats.
  976. */
  977. switch (ret) {
  978. case NET_RX_SUCCESS:
  979. adapter->stats.uphappy++;
  980. break;
  981. case NET_RX_CN_LOW:
  982. adapter->stats.uplcong++;
  983. break;
  984. case NET_RX_CN_MOD:
  985. adapter->stats.upmcong++;
  986. break;
  987. case NET_RX_CN_HIGH:
  988. adapter->stats.uphcong++;
  989. break;
  990. case NET_RX_DROP:
  991. adapter->stats.updropped++;
  992. break;
  993. default:
  994. adapter->stats.updunno++;
  995. break;
  996. }
  997. netdev->last_rx = jiffies;
  998. rcv_desc->rcv_free++;
  999. rcv_desc->rcv_pending--;
  1000. /*
  1001. * We just consumed one buffer so post a buffer.
  1002. */
  1003. buffer->skb = NULL;
  1004. buffer->state = NETXEN_BUFFER_FREE;
  1005. buffer->lro_current_frags = 0;
  1006. buffer->lro_expected_frags = 0;
  1007. adapter->stats.no_rcv++;
  1008. adapter->stats.rxbytes += length;
  1009. }
  1010. /* Process Receive status ring */
  1011. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1012. {
  1013. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1014. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1015. struct status_desc *desc; /* used to read status desc here */
  1016. u32 consumer = recv_ctx->status_rx_consumer;
  1017. u32 producer = 0;
  1018. int count = 0, ring;
  1019. DPRINTK(INFO, "procesing receive\n");
  1020. /*
  1021. * we assume in this case that there is only one port and that is
  1022. * port #1...changes need to be done in firmware to indicate port
  1023. * number as part of the descriptor. This way we will be able to get
  1024. * the netdev which is associated with that device.
  1025. */
  1026. while (count < max) {
  1027. desc = &desc_head[consumer];
  1028. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1029. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1030. netxen_get_sts_owner(desc));
  1031. break;
  1032. }
  1033. netxen_process_rcv(adapter, ctxid, desc);
  1034. netxen_clear_sts_owner(desc);
  1035. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1036. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1037. count++;
  1038. }
  1039. if (count) {
  1040. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1041. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1042. }
  1043. }
  1044. /* update the consumer index in phantom */
  1045. if (count) {
  1046. recv_ctx->status_rx_consumer = consumer;
  1047. recv_ctx->status_rx_producer = producer;
  1048. /* Window = 1 */
  1049. writel(consumer,
  1050. NETXEN_CRB_NORMALIZE(adapter,
  1051. recv_crb_registers[adapter->portnum].
  1052. crb_rcv_status_consumer));
  1053. }
  1054. return count;
  1055. }
  1056. /* Process Command status ring */
  1057. int netxen_process_cmd_ring(unsigned long data)
  1058. {
  1059. u32 last_consumer;
  1060. u32 consumer;
  1061. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1062. int count1 = 0;
  1063. int count2 = 0;
  1064. struct netxen_cmd_buffer *buffer;
  1065. struct pci_dev *pdev;
  1066. struct netxen_skb_frag *frag;
  1067. u32 i;
  1068. struct sk_buff *skb = NULL;
  1069. int done;
  1070. spin_lock(&adapter->tx_lock);
  1071. last_consumer = adapter->last_cmd_consumer;
  1072. DPRINTK(INFO, "procesing xmit complete\n");
  1073. /* we assume in this case that there is only one port and that is
  1074. * port #1...changes need to be done in firmware to indicate port
  1075. * number as part of the descriptor. This way we will be able to get
  1076. * the netdev which is associated with that device.
  1077. */
  1078. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1079. if (last_consumer == consumer) { /* Ring is empty */
  1080. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1081. last_consumer, consumer);
  1082. spin_unlock(&adapter->tx_lock);
  1083. return 1;
  1084. }
  1085. adapter->proc_cmd_buf_counter++;
  1086. /*
  1087. * Not needed - does not seem to be used anywhere.
  1088. * adapter->cmd_consumer = consumer;
  1089. */
  1090. spin_unlock(&adapter->tx_lock);
  1091. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1092. buffer = &adapter->cmd_buf_arr[last_consumer];
  1093. pdev = adapter->pdev;
  1094. frag = &buffer->frag_array[0];
  1095. skb = buffer->skb;
  1096. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1097. pci_unmap_single(pdev, frag->dma, frag->length,
  1098. PCI_DMA_TODEVICE);
  1099. for (i = 1; i < buffer->frag_count; i++) {
  1100. DPRINTK(INFO, "getting fragment no %d\n", i);
  1101. frag++; /* Get the next frag */
  1102. pci_unmap_page(pdev, frag->dma, frag->length,
  1103. PCI_DMA_TODEVICE);
  1104. }
  1105. adapter->stats.skbfreed++;
  1106. dev_kfree_skb_any(skb);
  1107. skb = NULL;
  1108. } else if (adapter->proc_cmd_buf_counter == 1) {
  1109. adapter->stats.txnullskb++;
  1110. }
  1111. if (unlikely(netif_queue_stopped(adapter->netdev)
  1112. && netif_carrier_ok(adapter->netdev))
  1113. && ((jiffies - adapter->netdev->trans_start) >
  1114. adapter->netdev->watchdog_timeo)) {
  1115. SCHEDULE_WORK(&adapter->tx_timeout_task);
  1116. }
  1117. last_consumer = get_next_index(last_consumer,
  1118. adapter->max_tx_desc_count);
  1119. count1++;
  1120. }
  1121. count2 = 0;
  1122. spin_lock(&adapter->tx_lock);
  1123. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1124. adapter->last_cmd_consumer = last_consumer;
  1125. while ((adapter->last_cmd_consumer != consumer)
  1126. && (count2 < MAX_STATUS_HANDLE)) {
  1127. buffer =
  1128. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1129. count2++;
  1130. if (buffer->skb)
  1131. break;
  1132. else
  1133. adapter->last_cmd_consumer =
  1134. get_next_index(adapter->last_cmd_consumer,
  1135. adapter->max_tx_desc_count);
  1136. }
  1137. }
  1138. if (count1 || count2) {
  1139. if (netif_queue_stopped(adapter->netdev)
  1140. && (adapter->flags & NETXEN_NETDEV_STATUS)) {
  1141. netif_wake_queue(adapter->netdev);
  1142. adapter->flags &= ~NETXEN_NETDEV_STATUS;
  1143. }
  1144. }
  1145. /*
  1146. * If everything is freed up to consumer then check if the ring is full
  1147. * If the ring is full then check if more needs to be freed and
  1148. * schedule the call back again.
  1149. *
  1150. * This happens when there are 2 CPUs. One could be freeing and the
  1151. * other filling it. If the ring is full when we get out of here and
  1152. * the card has already interrupted the host then the host can miss the
  1153. * interrupt.
  1154. *
  1155. * There is still a possible race condition and the host could miss an
  1156. * interrupt. The card has to take care of this.
  1157. */
  1158. if (adapter->last_cmd_consumer == consumer &&
  1159. (((adapter->cmd_producer + 1) %
  1160. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1161. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1162. }
  1163. done = (adapter->last_cmd_consumer == consumer);
  1164. spin_unlock(&adapter->tx_lock);
  1165. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1166. __FUNCTION__);
  1167. return (done);
  1168. }
  1169. /*
  1170. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1171. */
  1172. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1173. {
  1174. struct pci_dev *pdev = adapter->ahw.pdev;
  1175. struct sk_buff *skb;
  1176. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1177. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1178. uint producer;
  1179. struct rcv_desc *pdesc;
  1180. struct netxen_rx_buffer *buffer;
  1181. int count = 0;
  1182. int index = 0;
  1183. netxen_ctx_msg msg = 0;
  1184. dma_addr_t dma;
  1185. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1186. producer = rcv_desc->producer;
  1187. index = rcv_desc->begin_alloc;
  1188. buffer = &rcv_desc->rx_buf_arr[index];
  1189. /* We can start writing rx descriptors into the phantom memory. */
  1190. while (buffer->state == NETXEN_BUFFER_FREE) {
  1191. skb = dev_alloc_skb(rcv_desc->skb_size);
  1192. if (unlikely(!skb)) {
  1193. /*
  1194. * TODO
  1195. * We need to schedule the posting of buffers to the pegs.
  1196. */
  1197. rcv_desc->begin_alloc = index;
  1198. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1199. " allocated only %d buffers\n", count);
  1200. break;
  1201. }
  1202. count++; /* now there should be no failure */
  1203. pdesc = &rcv_desc->desc_head[producer];
  1204. #if defined(XGB_DEBUG)
  1205. *(unsigned long *)(skb->head) = 0xc0debabe;
  1206. if (skb_is_nonlinear(skb)) {
  1207. printk("Allocated SKB @%p is nonlinear\n");
  1208. }
  1209. #endif
  1210. skb_reserve(skb, 2);
  1211. /* This will be setup when we receive the
  1212. * buffer after it has been filled FSL TBD TBD
  1213. * skb->dev = netdev;
  1214. */
  1215. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1216. PCI_DMA_FROMDEVICE);
  1217. pdesc->addr_buffer = cpu_to_le64(dma);
  1218. buffer->skb = skb;
  1219. buffer->state = NETXEN_BUFFER_BUSY;
  1220. buffer->dma = dma;
  1221. /* make a rcv descriptor */
  1222. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1223. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1224. DPRINTK(INFO, "done writing descripter\n");
  1225. producer =
  1226. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1227. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1228. buffer = &rcv_desc->rx_buf_arr[index];
  1229. }
  1230. /* if we did allocate buffers, then write the count to Phantom */
  1231. if (count) {
  1232. rcv_desc->begin_alloc = index;
  1233. rcv_desc->rcv_pending += count;
  1234. rcv_desc->producer = producer;
  1235. if (rcv_desc->rcv_free >= 32) {
  1236. rcv_desc->rcv_free = 0;
  1237. /* Window = 1 */
  1238. writel((producer - 1) &
  1239. (rcv_desc->max_rx_desc_count - 1),
  1240. NETXEN_CRB_NORMALIZE(adapter,
  1241. recv_crb_registers[
  1242. adapter->portnum].
  1243. rcv_desc_crb[ringid].
  1244. crb_rcv_producer_offset));
  1245. /*
  1246. * Write a doorbell msg to tell phanmon of change in
  1247. * receive ring producer
  1248. */
  1249. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1250. netxen_set_msg_privid(msg);
  1251. netxen_set_msg_count(msg,
  1252. ((producer -
  1253. 1) & (rcv_desc->
  1254. max_rx_desc_count - 1)));
  1255. netxen_set_msg_ctxid(msg, adapter->portnum);
  1256. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1257. writel(msg,
  1258. DB_NORMALIZE(adapter,
  1259. NETXEN_RCV_PRODUCER_OFFSET));
  1260. }
  1261. }
  1262. }
  1263. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1264. uint32_t ringid)
  1265. {
  1266. struct pci_dev *pdev = adapter->ahw.pdev;
  1267. struct sk_buff *skb;
  1268. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1269. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1270. u32 producer;
  1271. struct rcv_desc *pdesc;
  1272. struct netxen_rx_buffer *buffer;
  1273. int count = 0;
  1274. int index = 0;
  1275. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1276. producer = rcv_desc->producer;
  1277. index = rcv_desc->begin_alloc;
  1278. buffer = &rcv_desc->rx_buf_arr[index];
  1279. /* We can start writing rx descriptors into the phantom memory. */
  1280. while (buffer->state == NETXEN_BUFFER_FREE) {
  1281. skb = dev_alloc_skb(rcv_desc->skb_size);
  1282. if (unlikely(!skb)) {
  1283. /*
  1284. * We need to schedule the posting of buffers to the pegs.
  1285. */
  1286. rcv_desc->begin_alloc = index;
  1287. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1288. " allocated only %d buffers\n", count);
  1289. break;
  1290. }
  1291. count++; /* now there should be no failure */
  1292. pdesc = &rcv_desc->desc_head[producer];
  1293. skb_reserve(skb, 2);
  1294. /*
  1295. * This will be setup when we receive the
  1296. * buffer after it has been filled
  1297. * skb->dev = netdev;
  1298. */
  1299. buffer->skb = skb;
  1300. buffer->state = NETXEN_BUFFER_BUSY;
  1301. buffer->dma = pci_map_single(pdev, skb->data,
  1302. rcv_desc->dma_size,
  1303. PCI_DMA_FROMDEVICE);
  1304. /* make a rcv descriptor */
  1305. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1306. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1307. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1308. DPRINTK(INFO, "done writing descripter\n");
  1309. producer =
  1310. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1311. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1312. buffer = &rcv_desc->rx_buf_arr[index];
  1313. }
  1314. /* if we did allocate buffers, then write the count to Phantom */
  1315. if (count) {
  1316. rcv_desc->begin_alloc = index;
  1317. rcv_desc->rcv_pending += count;
  1318. rcv_desc->producer = producer;
  1319. if (rcv_desc->rcv_free >= 32) {
  1320. rcv_desc->rcv_free = 0;
  1321. /* Window = 1 */
  1322. writel((producer - 1) &
  1323. (rcv_desc->max_rx_desc_count - 1),
  1324. NETXEN_CRB_NORMALIZE(adapter,
  1325. recv_crb_registers[
  1326. adapter->portnum].
  1327. rcv_desc_crb[ringid].
  1328. crb_rcv_producer_offset));
  1329. wmb();
  1330. }
  1331. }
  1332. }
  1333. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1334. {
  1335. if (find_diff_among(adapter->last_cmd_consumer,
  1336. adapter->cmd_producer,
  1337. adapter->max_tx_desc_count) > 0)
  1338. return 1;
  1339. return 0;
  1340. }
  1341. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1342. {
  1343. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1344. return;
  1345. }