armada-370-rd.dts 2.0 KB

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  1. /*
  2. * Device Tree file for Marvell Armada 370 Reference Design board
  3. * (RD-88F6710-A1)
  4. *
  5. * Copied from arch/arm/boot/dts/armada-370-db.dts
  6. *
  7. * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. /dts-v1/;
  14. #include "armada-370.dtsi"
  15. / {
  16. model = "Marvell Armada 370 Reference Design";
  17. compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
  18. chosen {
  19. bootargs = "console=ttyS0,115200 earlyprintk";
  20. };
  21. memory {
  22. device_type = "memory";
  23. reg = <0x00000000 0x20000000>; /* 512 MB */
  24. };
  25. soc {
  26. ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
  27. MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
  28. internal-regs {
  29. serial@12000 {
  30. clock-frequency = <200000000>;
  31. status = "okay";
  32. };
  33. sata@a0000 {
  34. nr-ports = <2>;
  35. status = "okay";
  36. };
  37. mdio {
  38. phy0: ethernet-phy@0 {
  39. reg = <0>;
  40. };
  41. phy1: ethernet-phy@1 {
  42. reg = <1>;
  43. };
  44. };
  45. ethernet@70000 {
  46. status = "okay";
  47. phy = <&phy0>;
  48. phy-mode = "sgmii";
  49. };
  50. ethernet@74000 {
  51. status = "okay";
  52. phy = <&phy1>;
  53. phy-mode = "rgmii-id";
  54. };
  55. mvsdio@d4000 {
  56. pinctrl-0 = <&sdio_pins1>;
  57. pinctrl-names = "default";
  58. status = "okay";
  59. /* No CD or WP GPIOs */
  60. broken-cd;
  61. };
  62. usb@50000 {
  63. status = "okay";
  64. };
  65. usb@51000 {
  66. status = "okay";
  67. };
  68. gpio-keys {
  69. compatible = "gpio-keys";
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. button@1 {
  73. label = "Software Button";
  74. linux,code = <116>;
  75. gpios = <&gpio0 6 1>;
  76. };
  77. };
  78. pcie-controller {
  79. status = "okay";
  80. /* Internal mini-PCIe connector */
  81. pcie@1,0 {
  82. /* Port 0, Lane 0 */
  83. status = "okay";
  84. };
  85. /* Internal mini-PCIe connector */
  86. pcie@2,0 {
  87. /* Port 1, Lane 0 */
  88. status = "okay";
  89. };
  90. };
  91. };
  92. };
  93. };